Indication device

Abstract

The present invention provides a display device that can solve problems caused by moisture permeability paths and foreign matter in the organic optical layer and sealing layer, thereby extending the lifespan of the light-emitting element and the driving transistor and preventing a decrease in device performance. [Solution] A display device according to one embodiment of the present invention may include a substrate including a display area and a non-display area surrounding the display area, a plurality of pixels arranged in the display area, each of which includes a light-emitting element and a drive transistor, at least one dam arranged in the non-display area, an organic optical layer covering the plurality of pixels, and at least one cutoff pattern arranged in the non-display area and penetrating the organic optical layer.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device capable of improving reliability.

Background Art

[0002] Currently, with the advent of the full-fledged information age, the field of display devices for visually displaying electrical information signals has been rapidly developing, and research has been continuously conducted to improve performance such as thinning, weight reduction, and low power consumption for various display devices.

[0003] ]> Typical display devices include a liquid crystal display device (LCD), a field emission display device (FED), an electro-wetting display device (EWD), and an organic light emitting display device (OLED).

[0004] In particular, a CPL (Capping Layer) can be disposed on the OLED. It is located on the light-emitting layer to improve light efficiency, protect the organic layer from the external environment, and play a role in maintaining charge balance. The CPL reduces the reflection of internal light to enhance the light-emitting efficiency, protects the layer sensitive to moisture and oxygen, and strengthens the stability and durability.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a display device that can solve problems caused by moisture permeation paths and foreign matters that may occur in the organic optical layer and the encapsulation layer, extend the life of the light-emitting element and the driving transistor, and prevent deterioration of device performance.

[0006] Another problem that the present invention aims to solve is to provide a display device that maintains the performance of the drive circuit and light-emitting element and optimizes power consumption by ensuring uniformity of electrical signals and voltage stability through multiple wiring and interruption patterns.

[0007] The problems addressed by the present invention are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment of the present invention may include a substrate including a display area and a non-display area surrounding the display area, a plurality of pixels arranged in the display area, each of which includes a light-emitting element and a drive transistor, at least one dam arranged in the non-display area, an organic optical layer covering the plurality of pixels, and at least one cutoff pattern arranged in the non-display area and penetrating the organic optical layer.

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] This invention effectively blocks the penetration of external moisture and oxygen by the organic optical layer through a shielding pattern, thereby preventing performance degradation of the light-emitting element and the driving transistor, and improving the durability of the display device.

[0011] This invention aims to stabilize voltage through electrical connections between multiple wiring and interruption patterns, thereby suppressing electromagnetic interference (EMI) and maintaining stable screen output and high image quality.

[0012] The effects of the present invention are not limited to those exemplified above, and a wide variety of other effects are included within the present invention. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic plan view of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic plan view of a display device according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view along line III-III' shown in Figure 1. [Figure 4] This is a cross-sectional view along line IV-IV' shown in Figure 1. [Figure 5] This is a cross-sectional view of a display device according to another embodiment of the present invention. [Modes for carrying out the invention]

[0014] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but is embodied in a variety of different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform a person with ordinary skill in the art to which the present invention belongs, and the present invention is defined only by the scope of the claims.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings illustrating embodiments of the present invention are illustrative; therefore, the present invention is not limited to those illustrated. Throughout the specification, the same reference numerals refer to the same components. Furthermore, when describing the present invention, if it is determined that a specific description of related prior art would unnecessarily obscure the gist of the invention, such detailed description will be omitted. Where "includes," "has," "is made," etc., as mentioned in the present invention, other parts may be added unless "only" is used. When a component is expressed singly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0016] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0017] When explaining the positional relationship, for example, when the positional relationship between two parts is described as "above ~", "upper part of ~", "lower part of ~", "next to ~", etc., as long as "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0018] An element or layer being referred to as "on" another element or layer includes both cases where another layer or element is interposed immediately above or in the middle of the other element.

[0019] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical idea of the present invention.

[0020] [[ID=X]]Throughout the specification, the same reference numerals refer to the same components.

[0021] The area and thickness of each configuration shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the shown configuration.

[0022] The respective features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, enabling various interlocks and drives technically, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0023] Hereinafter, the present invention will be described with reference to the drawings.

[0024] FIG. 1 is a schematic plan view of a display device according to an embodiment of the present invention. In FIG. 1, for convenience of explanation, only the substrate 110, pads PAD, gate drive circuit GIP, a plurality of dams DAM1, DAM2, DAM3, and a plurality of blocking patterns CP1, CP2 among the various components of the display device 100 are shown. It should be noted that in the above translation, there is an error in the original text. The sentence "明細書全体にわたって、同じ参照符号は、同じ構成要素を指す。" has been translated as "Throughout the specification, the same reference numerals refer to the same components.", but the correct translation should be "Throughout the specification, the same reference numerals refer to the same components." It is recommended to correct the original text to avoid similar misunderstandings in the future.

[0025] Referring to FIG. 1, the display device 100 includes at least one display area A / A, and an array of pixels PX is formed in the display area A / A. A non-display area N / A may be arranged to surround the display area A / A. That is, the non-display area N / A may be adjacent to one or more sides of the display area A / A. In FIG. 1, the non-display area N / A surrounds the rectangular display area A / A. However, the form of the display area A / A and the form / arrangement of the non-display area N / A adjacent to the display area A / A are not limited to the example shown in FIG. 1.

[0026] Each pixel PX in the display area A / A may be associated with a pixel circuit. The pixel circuit can include one or more switching transistors and one or more driving transistors on a backplane. Each pixel circuit may be electrically connected to a gate line and a data line to communicate with one or more driving circuits such as a gate driving circuit GIP and a data driving circuit located in the non-display area N / A. Also, each pixel circuit may be connected to a power supply line located in the non-display area N / A to receive a voltage required for driving. As shown in FIG. 1, the driving circuit, the gate driving circuit GIP may be implemented by a TFT (thin film transistor) in the non-display area N / A. Such a gate driving circuit may be referred to as GIP (gate-in-panel). The gate driving circuit GIP may be arranged on at least one side of the left and right sides of the display area A / A. Also, some components such as a data driver IC are mounted on a separate printed circuit board and may be coupled to a plurality of pads PAD arranged in the non-display area N / A using a circuit film such as an FPCB (flexible printed circuit board), COF (chip-on-film), TCP (tape carrier-package), etc.,

[0027] Furthermore, the non-display area N / A may include a pad section, and the pad section may include multiple pads. Specifically, the multiple pads may include multiple common power supply pads, multiple data input pads, multiple power supply pads, multiple control signal input pads, and multiple touch drive pads, etc.

[0028] The display device 100 may further include various additional elements for generating various signals or driving pixels PX within the display area A / A. Additional elements for driving pixels PX may include inverter circuits, multiplexers, electrostatic discharge circuits, etc. The display device 100 may also include additional elements associated with functions other than pixel driving. For example, the display device 100 may include additional elements that provide touch sensing, user authentication (e.g., fingerprint recognition), multi-level pressure sensing, tactile feedback, etc. The aforementioned additional elements may be located in external circuits connected to the non-display area N / A and / or the linking interface.

[0029] Multiple dams DAM1, DAM2, and DAM3 are arranged so as to surround the display area A / A with a non-display area N / A. Multiple dams DAM1, DAM2, and DAM3 are arranged in the non-display area N / A, excluding the side where the pad PAD is located. That is, multiple dams DAM1, DAM2, and DAM3 can be arranged not only outside the gate drive circuit GIP, but also on the opposite side of the side where the pad PAD is located. Thus, multiple dams DAM1, DAM2, and DAM3 control the spread of the sealing layer in stages, and each dam DAM1, DAM2, and DAM3 plays a role in ensuring that the sealing layer does not go outside the restricted boundary.

[0030] Specifically, the first dam DAM1 is located on the outer perimeter of display area A / A and serves as the primary barrier to restrict the sealing layer to within display area A / A. The second dam DAM2 is located outside the first dam DAM1 and is positioned at a distance from it. The second dam DAM2 reinforces the boundary formed by the first dam DAM1 and further blocks the diffusion of the sealing layer over a wider area. The third dam DAM3 is located outside the second dam DAM2 and maintains a certain distance from it as well. The third dam DAM3 serves as the final line of defense, maximally limiting the diffusion of the sealing layer. These dams DAM1, DAM2, and DAM3 minimize the influence of the external environment on the display device and ensure the overall structural stability of the device.

[0031] Multiple blocking patterns CP1 and CP2 are positioned between multiple dams DAM1, DAM2, and DAM3, and serve to block moisture permeability pathways in the corresponding areas. By effectively blocking moisture permeability at these locations, the internal components of the display device are protected from moisture, contributing to improved overall durability.

[0032] Specifically, the multiple shut-off patterns CP1 and CP2 are located only on the side opposite to the side where the pad PAD is placed, and are not located outside the gate drive circuit GIP. The first shut-off pattern CP1 is located between the display area A / A and the first dam DAM1. The second shut-off pattern CP2 is located between the first dam DAM1 and the second dam DAM2.

[0033] One or more blocking patterns CP1 and CP2 extend from the first side of the display device 100 to the second side on the opposite side in the plan view of the display device 100. The length of one or more blocking patterns CP1 and CP2 is greater than the width of the display area A / A in the plan view of the display device 100.

[0034] Figure 2 is a schematic plan view of a display device according to one embodiment of the present invention. In Figure 2, for the sake of explanation, only the circuit board 110, touch sensing unit 150, touch routing wiring 155, and multiple touch pads TPAD are shown from among the various components of the display device 100.

[0035] In recent years, touch panel integrated display devices have been developed in which touch electrodes and the like are directly placed on the sealing layer of the display device in order to reduce the thickness of the display device and improve visibility. A display device 100 according to one embodiment of the present invention is a touch panel integrated display device in which a touch sensing part 150 can be formed on the sealing layer of the display device 100.

[0036] Referring to Figure 2, the display device 100 includes a touch sensing unit 150, a plurality of touch routing wires 155, and a plurality of touch pads TPAD. Here, the touch sensing unit 150 includes a plurality of first touch electrodes 151, a plurality of second touch electrodes 152, and touch connecting electrodes 153.

[0037] Multiple first touch electrodes 151 may be touch driving electrodes, and multiple second touch electrodes 152 may be touch sensing electrodes. Multiple first touch electrodes 151 can be connected in the row direction to form multiple electrode rows, and multiple second touch electrodes 152 can be connected vertically by touch connecting electrodes 153 to form multiple electrode rows.

[0038] The first touch electrode 151 and the second touch electrode 152 may be placed on the same layer. However, in the region where the first touch electrode 151 and the second touch electrode 152 intersect, the second touch electrode 152 may be placed separately, and the separated second touch electrodes 152 may be connected by a touch connecting electrode 153.

[0039] At this time, the first touch electrode 151, the second touch electrode 152, and the touch connecting electrode 153 are positioned in areas corresponding to the display areas A / A of the display device 100.

[0040] The external shapes of the first touch electrode 151 and the second touch electrode 152 can correspond to specific patterns. For example, as shown in Figure 2, the external shapes of the first touch electrode 151 and the second touch electrode 152 may have a mesh pattern containing a plurality of rhombic shapes. The first touch electrode 151 and the second touch electrode 152 may be made of a metal containing at least one of titanium (Ti), aluminum (Al), molybdenum (Mo), molybdenum titanium (MoTi), copper (Cu), and tantalum (Ta), and may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto. Light emitted from the display device 100 can be transmitted through the first touch electrode 151 and the second touch electrode 152 made of a transparent conductive material and emitted to the outside. However, without limiting thereto, light emitted from the display device 100 may also be emitted to the outside through a plurality of openings contained in the first touch electrode 151 and the second touch electrode 152.

[0041] The non-display area N / A is the area surrounding the display area A / A, and multiple touch routing wires 155 and multiple touchpads TPAD are arranged in the non-display area N / A.

[0042] Each of the multiple touch routing wires 155 electrically connects each of the multiple touch electrodes 151 and 152 located in the display area A / A to the touchpad TPAD in the non-display area N / A. For example, a touch drive signal can be applied to the first touch electrode 151 through the touch routing wire 155 connected to the first touch electrode 151, and a touch sensing signal can be transmitted to the second touch electrode 152 through the touch routing wire 155 connected to the second touch electrode 152.

[0043] Such touch routing wires 155 may be made of a low-resistance metallic material, or of a transparent conductive material such as ITO or IZO, but are not limited to these. For example, if multiple touch routing wires 155 are made of a low-resistance metallic material, the resistance may be reduced and the RC delay may decrease.

[0044] Multiple touchpads (TPADs) are connected at one end to a touch routing wire 155 and at the other end to an external circuit, such as a touch drive unit, which can receive touch signals from the external circuit or transmit touch sensing signals to the external circuit.

[0045] In this case, the multiple touch routing wires 155 and the multiple touchpads TPAD are arranged in the area corresponding to the non-display area N / A of the display device 100. In particular, the multiple touchpads TPAD can be connected to the pads PAD located in the non-display area N / A.

[0046] In the following, Figure 3 will be referenced for a more detailed explanation of the cross-sectional structure of the display area A / A of the display device 100.

[0047] Figure 3 is a cross-sectional view along line III-III' shown in Figure 1.

[0048] Figure 4 is a cross-sectional view along line IV-IV' shown in Figure 1.

[0049] Referring to Figure 3, the display area A / A of the display device according to one embodiment of the present invention may include a substrate 110, a buffer layer 111, a first drive transistor 120, a gate insulating layer 112, an interlayer insulating layer 113, a first planarization layer 114, an intermediate electrode 190, a second planarization layer 115, a bank 116, a light-emitting element 130, an organic optical layer 141, a sealing layer 142, a touch buffer layer 143, a touch insulating layer 145, a touch sensing unit 150, a cover layer 160, and a filling layer 170.

[0050] The substrate 110 can support various components of the display device 100. The substrate 110 may be made of glass or a flexible plastic material. If the substrate 110 is made of a plastic material, it may be made of polyimide (PI), for example.

[0051] The buffer layer 111 may be placed on the substrate 110. The buffer layer 111 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The buffer layer 111 can improve the adhesion between the layer formed on the buffer layer 111 and the substrate 110, and can also play a role in blocking alkaline components and the like from flowing out of the substrate 110.

[0052] The drive transistor 120 may be placed on the buffer layer 111. The drive transistor 120 may include an active layer 121, a gate electrode 124, a source electrode 122, and a drain electrode 123. Here, depending on the design of the pixel circuit, the source electrode 122 may become the drain electrode, and the drain electrode 123 may become the source electrode. The active layer 121 of the drive transistor 120 may be placed on the buffer layer 111.

[0053] The active layer 121 can be made of a variety of materials such as polysilicon, amorphous silicon, or oxide semiconductors. The active layer 121 may include a channel region where a channel is formed when the drive transistor 120 is driven, source regions on both sides of the channel region, and drain regions. The source region refers to the portion of the active layer 121 connected to the source electrode 122, and the drain region refers to the portion of the active layer 121 connected to the drain electrode 123.

[0054] A gate insulating layer 112 may be placed on the active layer 121 of the drive transistor 120. The gate insulating layer 112 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the gate insulating layer 112 so that the source electrode 122 and drain electrode 123 of the drive transistor 120 are connected to the source region and drain region of the active layer 121 of the drive transistor 120, respectively.

[0055] The gate electrode 124 of the drive transistor 120 may be positioned on the gate insulating layer 112. The gate electrode 124 may be formed as a single or multilayer of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The gate electrode 124 may be formed on the gate insulating layer 112 so as to overlap with the channel region of the active layer 121 of the drive transistor 120.

[0056] An interlayer insulating layer 113 may be disposed on the gate insulating layer 112 and the gate electrode 124. The interlayer insulating layer 113 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the interlayer insulating layer 113 to expose the source and drain regions of the active layer 121 of the drive transistor 120. The source electrode 122 and drain electrode 123 of the drive transistor 120 may be disposed on the interlayer insulating layer 113.

[0057] The source electrode 122 and drain electrode 123 of the drive transistor 120 can be connected to the active layer 121 of the drive transistor 120 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. Therefore, the source electrode 122 of the drive transistor 120 can be connected to the source region of the active layer 121 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. And the drain electrode 123 of the drive transistor 120 can be connected to the drain region of the active layer 121 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113.

[0058] The source electrode 122 and drain electrode 123 of the drive transistor 120 may be formed by the same process. Furthermore, the source electrode 122 and drain electrode 123 of the drive transistor 120 may be formed from the same material. The source electrode 122 and drain electrode 123 of the drive transistor 120 may be formed as a single layer or multiple layers of one of the following or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd).

[0059] The first planarization layer 114 may be positioned on the source electrode 122 and the drain electrode 123. As shown in Figure 3, the first planarization layer 114 may have contact holes to expose the drain electrode 123. The first planarization layer 114 may be an organic material layer for planarizing the top of the drive transistor 120. For example, the first planarization layer 114 may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, it is not limited to these, and the first planarization layer 114 may be an inorganic material layer for protecting the drive transistor 120. For example, it may be formed from an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The first planarization layer 114 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0060] The intermediate electrode 190 may be placed on the first planarization layer 114. The intermediate electrode 190 may be connected to the source electrode 122 of the drive transistor 120 through a contact hole in the first planarization layer 114. The intermediate electrode 190 can serve to electrically connect the drive transistor 120 and the light-emitting element 130. For example, the intermediate electrode 190 can serve to electrically connect the source electrode 122 of the drive transistor 120 and the first electrode 131 of the light-emitting element 130. The intermediate electrode 190 may be formed as a single or multilayer of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The intermediate electrode 190 may be formed from the same material as the source electrode 122 and drain electrode 123 of the drive transistor 120.

[0061] The second planarization layer 115 may be placed on the intermediate electrode 190 and the first planarization layer 114. As shown in Figure 3, the second planarization layer 115 may have contact holes to expose the intermediate electrode 190. The second planarization layer 115 may be an organic material layer for planarizing the top of the drive transistor 120. For example, the second planarization layer 115 may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0062] The light-emitting element 130 may be placed on the second planarization layer 115. The light-emitting element 130 may include a first electrode 131, a light-emitting structure 132, and a second electrode 133. The first electrode 131 of the light-emitting element 130 may be placed on the second planarization layer 115. The first electrode 131 may be electrically connected to the intermediate electrode 190 through a contact hole formed in the second planarization layer 115. Thus, the first electrode 131 of the light-emitting element 130 may be electrically connected to the drive transistor 120 by being connected to the intermediate electrode 190 through a contact hole formed in the second planarization layer 115.

[0063] The first electrode 131 can be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may be made of a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive film may be a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof. For example, the first electrode 131 can be formed as a structure in which a transparent conductive film, an opaque conductive film, and another transparent conductive film are sequentially laminated. However, it is not limited to this, and it can also be formed as a structure in which a transparent conductive film and an opaque conductive film are sequentially laminated.

[0064] In one embodiment of the present invention, the display device 100 is a top emission display device, so the first electrode 131 may be an anode electrode. If the display device 100 is bottom emission, the first electrode 131 arranged on the second planarization layer 115 may be a cathode electrode.

[0065] A bank 116 may be placed on the first electrode 131 and the second planarization layer 115. An opening may be formed in the bank 116 to expose the first electrode 131. The bank 116 can define the light-emitting area of ​​the display device 100, and can therefore be called a pixel-defining film.

[0066] A light-emitting structure 132, including a light-emitting layer, may be placed on the first electrode 131.

[0067] The light-emitting structure 132 of the light-emitting element 130 can be formed by stacking a hole layer, a light-emitting layer, and an electron layer on the first electrode 131 in either order or in reverse order. In addition, the light-emitting structure 132 may also comprise first and second light-emitting structures facing each other with a charge generation layer in between. In this case, one of the light-emitting layers of the first and second light-emitting structures may generate blue light, and the remaining light-emitting layer of the first and second light-emitting structures may generate yellow-green light, thereby generating white light through the first and second light-emitting structures. The white light generated by this light-emitting structure 132 can be incident on a color filter located above the light-emitting structure 132 to realize a color image. Alternatively, a color image can be realized by generating color light corresponding to each subpixel in each light-emitting structure 132 without a separate color filter. For example, the light-emitting structure 132 of the red (R) subpixel can generate red light, the light-emitting structure 132 of the green (G) subpixel can generate green light, and the light-emitting structure 132 of the blue (B) subpixel can generate blue light.

[0068] A second electrode 133 may be further arranged on the light-emitting structure 132. The second electrode 133 of the light-emitting element 130 may be arranged on the light-emitting structure 132 so as to face the first electrode 131 across the light-emitting structure 132. In one embodiment of the present invention, the display device 100 may be a cathode electrode.

[0069] An organic optical layer 141 may be placed on the light-emitting element 130. The organic optical layer 141 may be formed from an organic material such as polyimide or polycarbonate. The organic optical layer 141 has excellent transparency and thermal stability, and can minimize interface defects with the OLED element to achieve efficient light efficiency.

[0070] A sealing layer 142 that suppresses moisture penetration may be further disposed on the organic optical layer 141. The sealing layer 142 may include a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer. The first inorganic sealing layer of the sealing layer 142 may be disposed on the second electrode 133. The organic sealing layer may be disposed on the first inorganic sealing layer. The second inorganic sealing layer may be disposed on the organic sealing layer. The first and second inorganic sealing layers of the sealing layer 142 may be formed from inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). The organic sealing layer of the sealing layer 142 may be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0071] The second inorganic sealing layer can cover the upper and side surfaces of the first inorganic sealing layer and the organic sealing layer, respectively, and the second inorganic sealing layer minimizes or blocks the penetration of external moisture or oxygen into the first inorganic sealing layer and the organic sealing layer. In this case, the first inorganic sealing layer and the second inorganic sealing layer play a role in blocking the penetration of moisture and oxygen, and the organic sealing layer plays a role in flattening the upper surface of the first inorganic sealing layer. Thus, the sealing layer 142 can cover the gate drive circuit GIP and dam of the display area A / A and the non-display area N / A. However, the configuration of the sealing layer 142 is not limited thereto.

[0072] A touch buffer layer 143 may be placed on the sealing layer 142. The touch buffer layer 143 may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The touch buffer layer 143 can improve the adhesion of the touch sensing portion 150 formed on the touch buffer layer 143.

[0073] The touch sensing unit 150 may be placed on the touch buffer layer 143. The touch sensing unit 150 may include touch electrodes 151, 152 and touch connecting electrodes 153.

[0074] A touch connecting electrode 153 of the touch sensing unit 150 may be placed on the touch buffer layer 143. The touch connecting electrode 153 is positioned at the intersection of touch electrodes 151 and 152 arranged in different directions and is used to connect the touch electrodes 151 and 152 which are arranged in one of the directions. The touch connecting electrode 153 may consist of a transparent conductive layer, for example, a transparent conductive oxide such as ITO or IZO.

[0075] A touch insulating layer 145 may be placed on the touch buffer layer 143 and the touch connecting electrode 153. The touch insulating layer 145 can insulate the touch connecting electrode 153 from the touch electrodes 151 and 152. The touch insulating layer 145 may consist of an inorganic material layer or an organic material layer. If the touch insulating layer 145 is an inorganic material layer, it may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). If the touch insulating layer 145 is an organic material layer, it may be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Contact holes may be formed in the touch insulating layer 145 to expose the touch connecting electrode 153.

[0076] Multiple first touch electrodes 151 and multiple second touch electrodes 152 of the touch sensing unit 150 may be arranged on the touch insulating layer 145. Multiple second touch electrodes 152 may be connected to touch connecting electrodes 153 through contact holes in the touch insulating layer 145. Multiple second touch electrodes 152 may be connected to each other by the touch connecting electrodes 153.

[0077] The first touch electrode 151 and the second touch electrode 152 of the touch sensing section 150 may be formed of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, they are not limited to this, and the first touch electrode 151 and the second touch electrode 152 may be formed of an opaque conductive film having openings. If the first touch electrode 151 and the second touch electrode 152 consist of an opaque conductive film having openings, they may be formed as a single layer or multiple layers of one of the following or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0078] A cover layer 160 may be placed on the touch sensing portion 150 and the touch insulating layer 145. The cover layer 160 can flatten the touch sensing portion 150 and the touch insulating layer 145. The cover layer 160 can be made of polymer materials such as polyimide or epoxy, inorganic materials such as silicon oxide (SiO2) or aluminum oxide (Al2O3), or organic-inorganic composite materials. Such materials provide moisture and oxygen barrier, excellent adhesion, and high transparency, contributing to extending the stability and lifespan of the display device and maintaining optical performance.

[0079] A packing layer 170 may be placed on the cover layer 160. The packing layer 170 may consist of high-molecular-weight materials such as polyimide and polycarbonate or acrylic resin, or low-molecular-weight materials such as PMMA (Polymethyl Methacrylate) and epoxy resin. The packing layer 170 is used to maintain interlayer uniformity or fill structural gaps, thereby supporting device stability and efficiency.

[0080] Referring to Figures 3 and 4, the non-display area N / A of the display device 100 may contain a gate drive circuit GIP, multiple wirings DL1, DL2, DL3, a spacer 144, multiple dams DAM1, DAM2, DAM3, and multiple shut-off patterns CP1, CP2.

[0081] The gate driver circuit GIP receives a gate control signal input through the gate control line, generates a gate signal based on the gate control signal, and sequentially outputs the signal to the gate lines in the display area A / A. The gate driver circuit GIP can be arranged in the non-display area N / A of the substrate 110 in a GIP (gate driver in panel) configuration. The gate driver circuit GIP may include a plurality of gate transistors 180 having the same interlayer relationship as the drive transistor 120 or switching transistor arranged in the display area A / A.

[0082] That is, the gate transistor 180 may be placed on a buffer layer 111 that extends to a non-display area N / A. The gate transistor 180 may include an active layer 181, a gate electrode 184, a source electrode 182, and a drain electrode 183. Here, depending on the design of the pixel circuit, the source electrode 182 may become the drain electrode, and the drain electrode 183 may become the source electrode. The active layer 181 of the gate transistor 180 may be placed on the buffer layer 111.

[0083] The active layer 181 can be made of a variety of materials such as polysilicon, amorphous silicon, or oxide semiconductors. The active layer 181 may include a channel region where a channel is formed when the gate transistor 180 is driven, source regions on both sides of the channel region, and drain regions. The source region refers to the portion of the active layer 181 connected to the source electrode 182, and the drain region refers to the portion of the active layer 181 connected to the drain electrode 183.

[0084] A gate insulating layer 112 extending to a non-display area N / A may be placed on the active layer 181 of the gate transistor 180. Contact holes may be formed in the gate insulating layer 112 so that the source electrode 182 and drain electrode 183 of the gate transistor 180 are connected to the source region and drain region of the active layer 181 of the gate transistor 180, respectively.

[0085] The gate electrode 184 of the gate transistor 180 may be placed on the gate insulating layer 112. The gate electrode 184 may be formed on the gate insulating layer 112 so as to overlap with the channel region of the active layer 181 of the gate transistor 180.

[0086] An interlayer insulating layer 113 extending in a non-visible region N / A may be placed on the gate insulating layer 112 and the gate electrode 184. Contact holes may be formed in the interlayer insulating layer 113 to expose the source region and drain region of the active layer 181 of the gate transistor 180. The source electrode 182 and drain electrode 183 of the gate transistor 180 may be placed on the interlayer insulating layer 113.

[0087] The source electrode 182 and drain electrode 183 of the gate transistor 180 can be connected to the active layer 181 of the gate transistor 180 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. Thus, the source electrode 182 of the gate transistor 180 can be connected to the source region of the active layer 181 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. Furthermore, the drain electrode 183 of the gate transistor 180 can be connected to the drain region of the active layer 181 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. A first planarization layer 114 extending to a non-display area N / A may be placed on the source electrode 182 and the drain electrode 183.

[0088] A first wiring DL1 may be placed on the interlayer insulating layer 113 extending into the non-display region N / A. The first wiring DL1 may be formed from the same material as the source electrode 122 and drain electrode 123 of the drive transistor 120. That is, the first wiring DL1 may be formed by the same process as the source electrode 122 and drain electrode 123 of the drive transistor 120. Thus, the first wiring DL1 may be formed as a single or multilayer structure consisting of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd).

[0089] Then, a first planarization layer 114 extending to a non-display region N / A is placed on the first wiring DL1, and a second wiring DL2 may be placed on the first planarization layer 114. The second wiring DL2 may be formed from the same material as the intermediate electrode 190. That is, the second wiring DL2 may be formed by the same process as the intermediate electrode 190. Thus, the second wiring DL2 may be formed as a single layer or multiple layers consisting of one of the following or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd).

[0090] Then, a second planarization layer 115 extending to a non-display region N / A is placed on the second wiring DL2, and a third wiring DL3 may be placed on the second planarization layer 115. The third wiring DL3 may be formed from the same material as the first electrode 131. That is, the third wiring DL3 may be formed by the same process as the intermediate electrode 190. Thus, the third wiring DL3 may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may be made from a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive film may be a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof.

[0091] Furthermore, multiple wirings DL1, DL2, and DL3 may come into contact with each other in some areas of the non-display area N / A. For example, in Figure 4, the interlayer insulating layer 113, the first planarization layer 114, and the second planarization layer 115 may not be placed outside the gate drive circuit GIP, and multiple wirings DL1, DL2, and DL3 may come into contact with each other and be electrically connected. This has the advantage that the same voltage can be applied to multiple wirings DL1, DL2, and DL3, and the stability of the applied voltage can be improved.

[0092] Furthermore, spacers 144 may be positioned on the bank 116 extending into the non-display area N / A, so as to be separated from the light-emitting elements 130. The spacers 144 play a role in ensuring mechanical stability by maintaining appropriate spacing within the display device and distributing external pressure to prevent damage to the elements and deformation of the substrate. In addition, the spacers 144 improve optical performance and image quality by maintaining uniform thickness and spacing of the light-emitting structures 132. Polymeric materials such as polyimide or epoxy, or inorganic materials such as silica can be used as materials for the spacers 144, maintaining optical performance through their transparent properties.

[0093] A dam (DAM) may be placed on the non-display area N / A. The dam (DAM) is placed to control the spread of the organic sealing layer that forms the sealing layer 142, which is placed in the display area A / A and the non-display area N / A of the substrate 110. Multiple dams (DAM1, DAM2, DAM3) may include a first dam (DAM1), a second dam (DAM2), and a third dam (DAM3). The first dam (DAM1) may surround the display area A / A so as to be adjacent to it, the second dam (DAM2) may surround the outer casing of the first dam (DAM1), and the third dam (DAM3) may surround the outer casing of the second dam (DAM2).

[0094] Each of the multiple dams DAM1, DAM2, and DAM3 can be formed in multiple layers. Specifically, the first dam DAM1 may include a first layer 116a and a second layer 144a of the first dam DAM1, which are placed on the third wiring DL3. The first layer 116a of the first dam DAM1 may be made of the same material as the bank 116, and the second layer 144a of the first dam DAM1 may be made of the same material as the spacer 144.

[0095] Furthermore, the second dam DAM2 may include a first layer 115b, a second layer 116b, and a third layer 144b, which are arranged on the second wiring DL2. The first layer 115b of the second dam DAM2 may be formed in the same layer as the second flattening layer 115, the second layer 116b of the second dam DAM2 may be formed in the same material as the bank 116, and the third layer 144b of the second dam DAM2 may be formed in the same material as the spacer 144.

[0096] Furthermore, at least one of the organic optical layer 141, sealing layer 142, touch buffer layer 143, and touch insulating layer 145 may be arranged to cover at least one of the multiple dams DAM1, DAM2, and DAM3.

[0097] Specifically, the organic optical layer 141 may be formed to cover the first dam DAM1 and the second dam DAM2, while the remaining sealing layer 142, touch buffer layer 143, and touch insulating layer 145 may be formed to cover all of the dams DAM1, DAM2, and DAM3.

[0098] Furthermore, multiple blocking patterns CP1 and CP2 protect the display device from moisture and the external environment through a gradual arrangement within the non-display area N / A of the display device 100. The first blocking pattern CP1 is positioned between the display area A / A and the first dam DAM1, and the second blocking pattern CP2 is positioned between the first dam DAM1 and the second dam DAM2. The blocking patterns CP1 and CP2 are positioned to penetrate the organic optical layer 141, the sealing layer 142, the touch buffer layer 143, and the touch insulating layer 145.

[0099] Furthermore, the blocking patterns CP1 and CP2 can be formed from the same material as the touch electrodes 151 and 152 and the touch connecting electrode 153. Thus, the blocking patterns CP1 and CP2 can consist of transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO), or metallic materials such as molybdenum (Mo), copper (Cu), titanium (Ti), and aluminum (Al). Consequently, the blocking patterns CP1 and CP2 possess transparency and conductivity, providing moisture barrier protection and electrical stability.

[0100] Furthermore, in the cross-sectional view of the display device 100, the width of the first surface (i.e., the top surface) of one or more blocking patterns CP1 and CP2 is greater than the width of the second surface (i.e., the bottom surface) of one or more blocking patterns CP1 and CP2. Here, in the cross-sectional view, the first surface is located further away from the substrate 110 than the second surface.

[0101] On the other hand, the organic optical layer 141 of the present invention is a layer used to protect the light-emitting element 130 of the display device 100 and maintain optical efficiency, and is composed of a material with excellent transparency and thermal stability. However, during the manufacturing process, foreign matter may be mixed into the organic optical layer 141, or minute defects (e.g., pinholes, cracks, etc.) may occur due to external environmental factors. Such defects form moisture permeability pathways, allowing external moisture and oxygen to penetrate into the interior. Foreign matter and defects occurring in the organic optical layer 141 weaken the protective function of the sealing layer 142, allowing moisture and oxygen to penetrate into the light-emitting element 130 and the drive transistor 120, which are internal components of the display device. This can lead to a decrease in the performance of the device, such as a shortened lifespan of the light-emitting element 130, a decrease in luminous efficiency, and pixel defects. In particular, if the organic material inside the light-emitting element 130 reacts with moisture, its electrical properties will change, causing a phenomenon in which the luminous efficiency drops sharply.

[0102] Therefore, the multiple blocking patterns CP1 and CP2 of the display device 100 according to one embodiment of the present invention are arranged inside the organic optical layer 141 and the sealing layer 142 to effectively block the moisture permeability path. The blocking patterns CP1 and CP2 either physically block the moisture permeability path formed by defects occurring in the organic optical layer 141 or significantly reduce the rate at which moisture diffuses into the interior, blocking it before it reaches the light-emitting element 130. The first blocking pattern CP1 is arranged between the display area A / A and the first dam DAM1 and serves as a primary line of defense, and the second blocking pattern CP2 is arranged between the first dam DAM1 and the second dam DAM2 and serves as a secondary line of defense. Such a stepped blocking structure divides the moisture permeability path generated in the organic optical layer 141 into several sections and gradually blocks the diffusion of moisture into the interior.

[0103] Furthermore, the blocking patterns CP1 and CP2 work in cooperation with the organic and inorganic layers of the sealing layer 142 to minimize moisture permeability problems caused by defects in the organic optical layer 141. The inorganic sealing layer plays a physical blocking role, while the blocking patterns divide the moisture permeability path into smaller sections, helping moisture to dissipate before it penetrates the sealing layer. Through these functions, the blocking patterns CP1 and CP2 localize the impact of foreign matter and defects in the organic optical layer 141 on the entire display device, protecting internal components and contributing to increased reliability and durability of the display device. As a result, the blocking patterns play a crucial role in maintaining the long-term stability and performance of the display device.

[0104] Furthermore, the multiple cutoff patterns CP1 and CP2 of the display device according to one embodiment of the present invention, in addition to preventing the penetration of moisture and oxygen within the display device 100, also provide an important technical effect of electrically connecting with multiple wirings DL1, DL2, and DL3 to improve voltage stability.

[0105] Specifically, the electrical connections between the multiple wirings DL1, DL2, and DL3 and the shielding patterns CP1 and CP2 maintain a uniform voltage throughout the display device 100, thereby preventing performance degradation of the drive transistor 120 and the light-emitting element 130. In particular, voltage uniformity is ensured by minimizing signal delays and distortions that may occur when electrical signals are transmitted through long or complex wiring. Furthermore, the shielding patterns CP1 and CP2 disperse or shield noise through the wiring DL1, DL2, and DL3, suppressing external electromagnetic interference (EMI), thereby improving the electrical stability of the display device 100 and preventing image quality degradation.

[0106] In addition, the cutoff patterns CP1 and CP2 absorb or disperse voltage spikes and overvoltages that may occur around the gate drive circuit GIP and the light-emitting element 130, preventing device damage and improving durability. This minimizes power loss in the light-emitting element 130 and the drive transistor 120, reducing overall power consumption and contributing to improved power efficiency of the display device 100. Ensuring such electrical stability optimizes the driving environment of the light-emitting element 130, maintaining uniform luminous efficiency and high image quality, ultimately extending the device lifespan and providing a stable screen.

[0107] In conclusion, the shielding patterns CP1 and CP2 function as core elements that significantly improve the performance and reliability of the display device 100, not only by preventing moisture permeability but also by ensuring electrical stability. This plays a crucial role in optimizing the device's operating environment and providing users with a high-quality screen.

[0108] The following describes a display device according to another embodiment of the present invention. The only difference between the display device according to one embodiment of the present invention and the display device according to another embodiment of the present invention is the arrangement of the organic optical layer, so only this will be described.

[0109] Figure 5 is a cross-sectional view of a display device according to another embodiment of the present invention.

[0110] Referring to Figure 5, the organic optical layer 241 extends into the display area A / A and the non-display area N / A of the display device, but in the non-display area N / A, it extends only up to the spacer 144. This distinguishes it from one embodiment of the present invention in that the organic optical layer 241 is designed so as not to cover multiple dams DAM1, DAM2, and DAM3.

[0111] In other embodiments of the present invention, the reason why the organic optical layer 241 is positioned to extend only up to the spacer 144 is to optimize the structural design. By not covering the dams DAM1, DAM2, and DAM3 with the organic optical layer 241, the dams DAM1, DAM2, and DAM3 can independently maintain moisture resistance and the stability of the sealing layer 142. Furthermore, such a design has the advantage of reducing the amount of material used for the organic optical layer 241 and improving the efficiency of the manufacturing process.

[0112] In addition, by preventing interference between the organic optical layer 241 and the dams DAM1, DAM2, and DAM3, the main functions of the dams, such as controlling the spread of the sealing layer 142 and preventing moisture permeability, are not hindered. The organic optical layer 241 plays a role in improving and protecting the performance of the light-emitting element 130, while the dams DAM1, DAM2, and DAM3 independently perform the functions of boundary formation and moisture permeability prevention of the sealing layer 142.

[0113] Therefore, a design in which the organic optical layer 241 extends only up to the spacer 144 can optimize the independent function of each component and contribute to improving the structural stability of the display device and the efficiency of the manufacturing process.

[0114] Display devices according to various embodiments of the present invention can be described as follows.

[0115] A display device according to one embodiment of the present invention may include a substrate including a display area and a non-display area surrounding the display area, a plurality of pixels arranged in the display area, each of which includes a light-emitting element and a drive transistor, at least one dam arranged in the non-display area, an organic optical layer covering the plurality of pixels, and at least one blocking pattern arranged in the non-display area and penetrating the organic optical layer.

[0116] According to another feature of the present invention, the at least one blocking pattern may be located in at least one of the regions between the display region and the at least one dam and the regions between each of the at least one dam.

[0117] According to another feature of the present invention, the at least one dam located in the non-display area includes a first dam and a second dam located outside the first dam, and the at least one blocking pattern may include a first blocking pattern located between the display area and the first dam and a second blocking pattern located between the first dam and the second dam.

[0118] According to another feature of the present invention, the invention further includes at least one gate drive circuit located in the non-display area, wherein the at least one cutoff pattern does not need to be located outside the at least one gate drive circuit.

[0119] According to another feature of the present invention, the invention further includes a sealing layer disposed on the organic optical layer to seal the light-emitting element, wherein the at least one blocking pattern can penetrate the sealing layer.

[0120] According to another feature of the present invention, the invention further includes a touch buffer layer disposed on the sealing layer and a touch sensing portion disposed on the touch buffer layer, wherein the touch sensing portion includes a plurality of touch electrodes, touch connecting electrodes connecting the plurality of touch electrodes, and a touch insulating layer that insulates the plurality of touch electrodes from the touch connecting electrodes.

[0121] According to another feature of the present invention, the at least one blocking pattern may penetrate at least one of the touch buffer layer and the touch insulating layer.

[0122] According to another feature of the present invention, the at least one blocking pattern may be formed of the same material as any one of the plurality of touch electrodes and the touch connecting electrodes.

[0123] According to another feature of the present invention, each of the pixels further includes an intermediate electrode, which is positioned between the driving transistor and the light-emitting element and electrically connects the driving transistor and the light-emitting element, and the non-display region may include a first wiring formed of the same material as the source and drain electrodes of the driving transistor, a second wiring formed of the same material as the intermediate electrode, and a third wiring formed of the same material as the anode electrode of the light-emitting element.

[0124] According to another feature of the present invention, the at least one interruption pattern can be electrically connected to the first wiring, the second wiring, and the third wiring.

[0125] According to another feature of the present invention, the organic optical layer may extend to the non-display area so as to cover the at least one dam.

[0126] Although embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and non-limiting in all respects. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A substrate including a display area and a non-display area surrounding the display area, A plurality of pixels arranged in the display area, each of which includes a light-emitting element and a drive transistor, At least one dam located in the hidden area, The organic optical layer covering the plurality of pixels, and At least one blocking pattern arranged in the non-display region and penetrating the organic optical layer A display device, including a display device.

2. The display device according to claim 1, wherein the at least one blocking pattern is arranged in at least one of the following areas: the area between the display area and the first dam among the at least one dam, or the area between the first dam and the second dam among the at least one dam.

3. The at least one dam located in the non-display area includes a first dam and a second dam located outside the first dam. The display device according to claim 1, wherein the at least one blocking pattern includes a first blocking pattern and a second blocking pattern, the first blocking pattern is positioned between the display area and the first dam, and the second blocking pattern is positioned between the first dam and the second dam.

4. The system further includes at least one gate drive circuit located in the non-display area, The display device according to claim 1, wherein the at least one cutoff pattern is not arranged outside the at least one gate drive circuit.

5. The material further includes a sealing layer disposed on the organic optical layer and sealing the light-emitting element, The display device according to claim 1, wherein the at least one blocking pattern penetrates the sealing layer.

6. A touch buffer layer disposed on the sealing layer, and Touch sensing unit disposed on the touch buffer layer It further includes, The display device according to claim 5, wherein the touch sensing unit includes a plurality of touch electrodes, touch connecting electrodes connecting the plurality of touch electrodes, and a touch insulating layer that insulates the plurality of touch electrodes from the touch connecting electrodes.

7. The display device according to claim 6, wherein the at least one blocking pattern penetrates at least one of the touch buffer layer and the touch insulating layer.

8. The display device according to claim 6, wherein the at least one blocking pattern is formed of the same material as any one of the plurality of touch electrodes and the touch connecting electrodes.

9. Each of the aforementioned pixels further includes an intermediate electrode, which is positioned between the driving transistor and the light-emitting element, and electrically connects the driving transistor and the light-emitting element. The aforementioned hidden area includes: A first wiring harness formed from the same material as the source and drain electrodes of the aforementioned drive transistor, A second wiring, formed from the same material as the intermediate electrode, Third wiring formed from the same material as the anode electrode of the light-emitting element. The display device according to claim 1, which includes the following:

10. The display device according to claim 9, wherein the at least one interruption pattern is electrically connected to the first wiring, the second wiring, and the third wiring.

11. The display device according to claim 1, wherein the organic optical layer extends to the non-display area so as to cover the at least one dam.

12. A substrate including a display area and a non-display area surrounding the display area, A plurality of pixels arranged in the display area, each of which includes a light-emitting element, A data line, which is arranged in the non-display area, includes a metallic material, and supplies voltage to the pixel, At least one dam located in the hidden area, and At least one blocking pattern, which includes a conductive material, is arranged in the non-display area. Includes, The at least one interruption pattern is a display device directly connected to the data line.

13. An organic optical layer covering the plurality of pixels and extending to the non-display area, A sealing layer disposed on the organic optical layer and extending to the non-display region. It further includes, The display device according to claim 12, wherein the at least one blocking pattern penetrates the sealing layer and the organic optical layer and directly contacts the data line.

14. A touch buffer layer disposed on the sealing layer, and A touch sensing unit disposed in the display area on the touch buffer layer, the touch sensing unit including a touch insulating layer extending to the non-display area. It further includes, The display device according to claim 13, wherein the at least one blocking pattern further penetrates the touch insulating layer and the touch buffer layer.

15. An organic optical layer covering the plurality of pixels and extending to the non-display area, The present invention further includes a sealing layer disposed on the organic optical layer of the display region, extending to the non-display region and disposed on a portion of the organic optical layer of the non-display region, The display device according to claim 12, wherein the at least one blocking pattern penetrates the sealing layer and directly contacts the data line.

16. The system further includes a spacer positioned in the non-display area between the display area and the at least one blocking pattern, The organic optical layer extends to a portion of the non-display area between the display area and the spacer, The display device according to claim 15, wherein the organic optical layer does not extend to the other portion of the non-display area between the spacer and the at least one blocking pattern.

17. The at least one blocking pattern extends in a plan view from the first side of the display device to the second side which is opposite to the first side, The display device according to claim 12, wherein the length of the at least one blocking pattern is greater than the width of the display area in a plan view.

18. The width of the first surface of the at least one blocking pattern is greater than the width of the second surface of the at least one blocking pattern in the cross-sectional view of the display device. The display device according to claim 12, wherein in the cross-sectional view, the first surface is located further away from the substrate than the second surface.

19. The display device according to claim 12, wherein the at least one blocking pattern is arranged between the display area and the at least one dam.

20. The at least one interruption pattern includes a first interruption pattern and a second interruption pattern, The aforementioned at least one dam includes the first dam and the second dam, The first blocking pattern is positioned between the display area and the first dam. The display device according to claim 12, wherein the second shutoff pattern is positioned between the first dam and the second dam.

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