Load drive circuit, driver, and display device

Abstract

To provide a load drive circuit that can reduce the size of the device. [Solution] The device includes an external terminal tm1 for connecting a load, a transistor 24 whose drain is connected to the external terminal and whose gate receives a drive voltage and flows an output current corresponding to the drive voltage between the drain and source, a differential amplifier 22 that supplies a drive voltage to the gate, a first resistor Roff with one end connected to the source, a second resistor R with one end connected to the other end of the first resistor and a ground voltage applied to the other end, a selector 21 that supplies a first voltage Von to the non-inverting input terminal of the differential amplifier when the load is driven, and a second voltage Voff lower than the first voltage when the load is not driven, and switch circuits SW1, SW2, SW3 that short-circuit both ends of the first resistor and connect one end of the second resistor to the inverting input terminal of the differential amplifier when the load is driven, and connect one end of the first resistor to the inverting input terminal of the differential amplifier when the load is not driven.

Description

Technical Field

[0001] The present disclosure relates to a load driving circuit, a driver, and a display device.

Background Art

[0002] In recent years, a liquid crystal display device using a group of LEDs (Light Emitting Diodes) connected in series as a backlight source has been commercialized.

[0003] In addition, a device has been proposed that obtains a target brightness by PWM (Pulse Width Modulation) driving such a group of LEDs (for example, see Patent Document 1). This device includes a power supply circuit that applies a DC voltage for lighting the LEDs to the anode of one of the LEDs in the group of LEDs, and a transistor connected to the cathode of the other LED in the group of LEDs. In this device, the transistor is switched and driven, that is, on / off controlled, at a dimming duty ratio to PWM drive the group of LEDs.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] By the way, in order to drive and light a group of LEDs as the load as described above, it is necessary to apply a high voltage represented by at least N·VF (N: the number of LEDs connected in series, VF: the forward voltage of the LEDs) to the anode of one of the LEDs in the group of LEDs.

[0006] In this case, in the apparatus described in Patent Document 1, while the transistor is in the ON state, the voltage applied to the transistor is low, but when it is in the OFF state, a high voltage (N × VF) or higher is applied. Therefore, according to the apparatus described in Patent Document 1, it is necessary to use a high-voltage transistor, and there is a problem that the overall size of the apparatus becomes larger due to the increase in size associated with the higher voltage of the transistor.

[0007] The load drive circuit according to this disclosure includes an external terminal for connecting a load, a transistor whose drain is connected to the external terminal and which receives a drive voltage at its gate and flows an output current corresponding to the drive voltage between its drain and source, a differential amplifier that generates the drive voltage and supplies it to the gate of the transistor, a first resistor whose one end is connected to the source of the transistor, a second resistor whose one end is connected to the other end of the first resistor and which has a ground voltage applied to its other end, a selector that receives a first voltage and a second voltage lower than the first voltage, and supplies the first voltage to the non-inverting input terminal of the differential amplifier when the load is driven, and supplies the second voltage to the non-inverting input terminal of the differential amplifier when the load is not driven, and a switch circuit that short-circuits both ends of the first resistor and connects one end of the second resistor to the inverting input terminal of the differential amplifier when the load is driven, and connects one end of the first resistor to the inverting input terminal of the differential amplifier when the load is not driven. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram shows the schematic configuration of the display device 100. [Figure 2] This is a circuit diagram showing the internal configuration of the multiple light-emitting diodes included in the backlight panel 13 and the LED driver 20. [Figure 3] This is a circuit diagram showing the internal configuration of drive circuit 20_1. [Figure 4] This is a timing chart showing the operation of drive circuit 20_1. [Figure 5A]This is a circuit diagram showing the state of the drive circuit 20_1 when the light is on. [Figure 5B] This is a circuit diagram showing the state of drive circuit 20_1 when the lights are off. [Figure 6] This is a circuit diagram showing the internal configuration of drive circuit 20_1a. [Figure 7] This is a time chart showing the operation of drive circuit 20_1a. [Figure 8A] This is a circuit diagram showing the internal state of the drive circuit 20_1a when the light-emitting diode is lit. [Figure 8B] This is a circuit diagram showing the internal state of the drive circuit 20_1a when the light-emitting diode is off (within a predetermined period). [Figure 8C] This is a circuit diagram showing the internal state of the drive circuit 20_1a when the light-emitting diode is turned off (after a predetermined period of time). [Figure 9] Block diagram showing the configuration of LED driver 20A as a modified example of LED driver 20. [Figure 10] This is a circuit diagram showing the internal configuration of each drive circuit 20A_2 to 20_N. [Figure 11A] This is a circuit diagram showing the internal state of the LED driver 20A when the light-emitting diode is lit. [Figure 11B] This is a circuit diagram showing the internal state of the LED driver 20A when the light-emitting diode is turned off.

[0009] [Detailed explanation] [Example 1]

[0010] Figure 1 is a block diagram showing a schematic configuration of a display device 100 including an LED (Light Emitting Diode) driver 20 for backlighting as a load drive circuit according to the present disclosure.

[0011] As shown in FIG. 1, the display device 100 includes a display panel 10, a display controller 11, a scanning driver 12a, a data driver 12b, a backlight panel 13, and an LED driver 20.

[0012] The display panel 10 is a liquid crystal display panel and includes scanning lines SL1 to SLm (m is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen and data lines DL1 to DLn (n is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. A display cell PC responsible for pixels is formed at each intersection of the scanning lines and the data lines.

[0013] The display controller 11 receives a video signal VD and supplies a scanning timing signal indicating the timing for applying a horizontal scanning pulse to each scanning line according to the video signal VD to the scanning driver 12a. Further, based on the video signal VD, the display controller 11 generates a video digital signal DVS including various control signals and a series of display data pieces representing the luminance levels of each pixel, and supplies this to the data driver 12b.

[0014] The scanning driver 12a sequentially applies a horizontal scanning pulse synchronized with the scanning timing signal supplied from the display controller 11 to each of the scanning lines SL1 to SLm of the display panel 10.

[0015] The data driver 12b first takes in, according to the video digital signal DVS, a series of display data pieces corresponding to each pixel included in the video digital signal DVS, in the number of data lines, that is, n pieces at a time. Next, the data driver 12b converts each of the n captured display data pieces into a driving voltage having an analog voltage value corresponding to the luminance level indicated by the display data piece. Then, the data driver 12b supplies the n driving voltages obtained by this conversion as driving signals G1 to Gn to the data lines DL1 to DLn of the display panel 10.

[0016] The backlight panel 13 includes a light guide plate installed on the back surface of the display panel 10 and a plurality of light-emitting diodes (LEDs) as light sources. The backlight panel 13 irradiates the light generated by each of the plurality of light-emitting diodes toward the image display area of the display panel 10 through the above-described light guide plate.

[0017] The LED driver 20 receives an illuminance signal ILD that specifies the illuminance of the backlight, and PWM (Pulse Width Modulation) drives the plurality of light-emitting diodes included in the backlight panel 13 at a duty ratio corresponding to the illuminance indicated by the illuminance signal ILD.

[0018] FIG. 2 is a circuit diagram showing the internal configurations of the plurality of light-emitting diodes included in the backlight panel 13 and the LED driver 20.

[0019] As shown in FIG. 2, the backlight panel 13 includes LED units 13_1 to 13_N. The LED units 13_1 to 13_N have the same configuration, that is, they have light-emitting diodes LE1 to LEr (r is an integer of 2 or more) connected in series. In each of the LED units 13_1 to 13_N, a power supply voltage VLED for causing the light-emitting diodes LE1 to LEr to emit light is applied to the anode of one end light-emitting diode LE1 among the light-emitting diodes LE1 to LEr connected in series. Note that the power supply voltage VLED is set to be higher than r·VF (VF: forward voltage of the light-emitting diode).

[0020] Also, in the LED units 13_1 to 13_N, the cathodes of the other end light-emitting diodes LEr among the light-emitting diodes LE1 to LEr included in each are connected to the external terminals tm1 to tmN of the LED driver 20.

[0021] The LED driver 20 includes drive circuits 20_1 to 20_N provided corresponding to each of the LED units 13_1 to 13_N, and a PWM signal generation circuit 200.

[0022] <The PWM signal generation circuit 200 generates a binary signal (logic level 0 or 1) of a predetermined frequency having a duty cycle corresponding to the illuminance indicated by the illuminance signal ILD described above, as a pulse width modulated signal PWMS. The pulse width modulated signal PWMS in this disclosure is designed to turn on the light-emitting diode at logic level 1 and to turn off the light-emitting diode at logic level 0. The PWM signal generation circuit 200 supplies this pulse width modulated signal PWMS to each of the drive circuits 20_1 to 20_N. The drive circuits 20_1 to 20_N are connected to their respective LED units 13_1 to 13_N via external terminals tm1 to tmN.

[0023] Drive circuits 20_1 to 20_N have the same internal configuration as each other.

[0024] Figure 3 is a circuit diagram showing the internal configuration of drive circuit 20_1, which is an excerpt from drive circuits 20_1 to 20_N.

[0025] As shown in Figure 3, the drive circuit 20_1 includes a selector 21, a differential amplifier 22, a switch control circuit 23, an N-channel output transistor 24, resistors R and Roff, and switches SW1 to SW3.

[0026] Selector 21 receives a control voltage Von to prompt illumination, a control voltage Voff to prompt extinction, and the pulse width modulation signal PWMS described above. The control voltages Von and Voff have the following magnitude relationship.

[0027] Von>Voff>0 Selector 21 selects the control voltage Voff from among the control voltages Von and Voff when the pulse width modulation signal PWMS indicates a logic level of 0, and selects the control voltage Von when the pulse width modulation signal PWMS indicates a logic level of 1. Selector 21 supplies the selected control voltage Vin to the non-inverting input terminal of the differential amplifier 22.

[0028] The differential amplifier 22 performs the following operations based on the power supply voltage VDDL and ground voltage VSS received at its power supply terminals. As described above, the differential amplifier 22 receives the control voltage Vin at its non-inverting input terminal and the source voltage Vs of the output transistor 24 as a feedback voltage at its inverting input terminal. The differential amplifier 22 outputs a drive voltage Vg from its output terminal, which has a voltage value corresponding to the difference between the control voltage Vin and the source voltage Vs, and supplies this to the gate of the output transistor 24.

[0029] The switch control circuit 23 receives the pulse width modulated signal PWMS and supplies a switch control signal Sa to switches SW1 and SW3, which prompts them to turn on if the pulse width modulated signal PWMS indicates a logic level of 1, and to turn them off if the pulse width modulated signal PWMS indicates a logic level of 0. Furthermore, the switch control circuit 23 supplies a switch control signal Sb to switch SW2, which prompts them to turn off if the pulse width modulated signal PWMS indicates a logic level of 1, and to turn them on if the pulse width modulated signal PWMS indicates a logic level of 0.

[0030] The output transistor 24 has its drain connected to the cathode of the light-emitting diode LEr included in the LED unit 13_1. The output transistor 24 outputs a current from its source that corresponds to the drive voltage Vg received at its gate. The output transistor 24 is, for example, an N-channel type DMOS (Double-diffused Metal Oxide Semiconductor) S transistor.

[0031] The resistor Roff is a current-limiting resistor. One end of the resistor Roff is connected to the source of the output transistor 24 via node n1, and the other end is connected to switches SW1 and SW3 and one end of resistor R via node n2.

[0032] Resistor R is used for current / voltage conversion, and its resistance value is significantly lower than that of resistor Roff. The other end of resistor R is connected to the ground voltage VSS.

[0033] Switch SW1 turns ON when the switch control signal Sa supplied from the switch control circuit 23 prompts it to turn ON, connecting node n2 to the inverting input terminal of the differential amplifier 22. On the other hand, when the switch control signal Sa prompts it to turn OFF, switch SW1 turns OFF, disconnecting the connection between the inverting input terminal of the differential amplifier 22 and node n2.

[0034] Switch SW2 turns ON when the switch control signal Sb supplied from the switch control circuit 23 prompts it to turn ON, connecting node n1 to the inverting input terminal of the differential amplifier 22. On the other hand, when the switch control signal Sb prompts it to turn OFF, switch SW2 turns OFF, disconnecting the connection between the inverting input terminal of the differential amplifier 22 and node n1.

[0035] Switch SW3 turns ON when the switch control signal Sa supplied from the switch control circuit 23 prompts it to turn ON, connecting nodes n1 and n2, that is, short-circuiting both ends of resistor Roff. On the other hand, when the switch control signal Sa prompts it to turn OFF, it turns OFF, releasing the short circuit across both ends of resistor Roff.

[0036] In short, the switch circuit control 23 and the switch circuits including switches SW1 to SW3 short-circuit the ends of resistor Roff and connect one end (n2) of resistor R to the inverting input terminal of differential amplifier 22 when turning on (driving) the light-emitting diodes LE1 to LEr. On the other hand, when turning off (not driving) the light-emitting diodes LE1 to LEr, connect one end (n1) of resistor Roff to the inverting input terminal of differential amplifier 22.

[0037] The operation of the drive circuit 20_1 shown in Figure 3 will be explained below with reference to Figures 4, 5A, and 5B.

[0038] Figure 4 is a time chart showing the internal operation of the drive circuit 20_1 in response to the pulse width modulation signal PWMS.

[0039] Figure 5A is a circuit diagram of drive circuit 20_1 showing the states of switches SW1 to SW3 and selector 21 when it receives a pulse width modulation signal PWMS of logic level 1 (t1 to t2) to prompt the light to turn on. Figure 5B is a circuit diagram of drive circuit 20_1 showing the states of switches SW1 to SW3 and selector 21 when it receives a pulse width modulation signal PWMS of logic level 0 (t2 to t1) to prompt the light to turn off.

[0040] [When lit] First, as shown in Figures 4 and 5A, when a pulse width modulation signal PWMS of logic level 1, which prompts illumination, is received, the selector 21 selects the control voltage Von from among the control voltages Von and Voff, and supplies this as the control voltage Vin to the differential amplifier 22. Furthermore, during this time, as shown in Figures 4 and 5A, switches SW1 and SW3 are in the ON state, and switch SW2 is in the OFF state.

[0041] As a result, as shown in Figure 5A, the ends of resistor Roff are short-circuited by switch SW3, so the current output from the source of output transistor 24 flows through resistor R without passing through resistor Roff. At this time, the voltage at one end of resistor R, i.e., the source voltage Vs, is supplied to the inverting terminal of differential amplifier 22 via switch SW1. Consequently, differential amplifier 22 supplies a drive voltage Vg to the gate of output transistor 24, having a voltage value V_H as shown in Figure 4, which corresponds to the difference between the source voltage Vs and the control voltage Von, so that the source voltage Vs becomes equal to the control voltage Von.

[0042] Therefore, the output transistor 24 receives a current corresponding to the drive voltage Vg, Iout=Von / R The output current Iout, represented by the formula, is passed through a current path consisting of the output transistor 24, switch SW3, and resistor R, as shown by the thick solid arrow in Figure 5A. As a result, the output current Iout flows to the light-emitting diodes LE1 to LEr of the LED unit 13_1, causing the light-emitting diodes LE1 to LEr to light up.

[0043] [When the lights are off] Then, as shown in Figures 4 and 5B, when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0, which signals the light to be turned off, the selector 21 selects the control voltage Voff from among the control voltages Von and Voff and supplies it to the differential amplifier 22 as the control voltage Vin. Furthermore, during this time, as shown in Figures 4 and 5B, switches SW1 and SW3 are in the off state, and switch SW2 is in the on state.

[0044] As a result, a resistor Roff is connected in series between the source and resistor R of the output transistor 24, and the voltage at one end of the resistor Roff, i.e., the source voltage Vs, is supplied to the inverting terminal of the differential amplifier 22 via switch SW2. Consequently, the differential amplifier 22 supplies a drive voltage Vg to the gate of the output transistor 24, having a voltage value V_L shown in Figure 4, which corresponds to the difference between the source voltage Vs and the control voltage Voff, so that the source voltage Vs becomes equal to the control voltage Voff. Note that the control voltage Voff is high enough to turn on the output transistor 24, but is significantly lower than the control voltage Von.

[0045] Therefore, the output transistor 24 receives a current corresponding to the drive voltage Vg, Iout_off = Voff / (Roff + R) The output current Iout_off, represented by the formula, flows through the current path consisting of the output transistor 24, resistors Roff and R, as shown by the thick solid arrow in Figure 5B. Although this output current Iout_off flows through the light-emitting diodes LE1 to LEr of the LED unit 13_1, the current value is extremely small, so the light-emitting diodes LE1 to LEr are effectively turned off.

[0046] Therefore, when driving the LED unit 13_1 with PWM, a small output current Iout_off flows even while receiving the pulse width modulation signal PWMS with logic level 0 to prompt the LED to turn off. In this case, the small output current Iout_off flows through the output transistor 24, resistor Roff, and resistor R, so the voltage Vout across the drain of the output transistor 24 is Vout = VLED - (r·VF) VLED: Power supply voltage for illuminating LE1~LEr r: Number of light-emitting diodes (LEs) connected in series VF: Forward voltage of each light-emitting diode LE1 to Ler. This is the result.

[0047] On the other hand, when the output transistor 24 is turned off by a pulse width modulation signal PWMS with logic level 0 to prompt the power off, the voltage Vout across the drain of the output transistor 24 is: Vout=VLED This is the result.

[0048] Therefore, with the drive circuit 20_1, the voltage Vout applied to the drain of the output transistor 24 can be lowered compared to conventional PWM driving, which turns off the output transistor 24 in order to turn off each light-emitting diode of the LED unit 13_1. Consequently, with the drive circuits 20_1 to 20_N, each having the configuration shown in Figure 3, the breakdown voltage of each circuit element, including the output transistor 24, can be lowered, making it possible to reduce the overall size of the LED driver 20. [Example 2]

[0049] Figure 6 is a circuit diagram showing the internal configuration of drive circuit 20_1a, which is another example of the drive circuit 20_1 shown in Figure 3.

[0050] Furthermore, in the drive circuit 20_1a shown in Figure 6, the switch control circuit 23A is used instead of the switch control circuit 23 shown in Figure 3, and a new switch SW4 is added, but all other configurations are the same as the drive circuit 20_1 shown in Figure 3.

[0051] Similar to the switch control circuit 23, the switch control circuit 23A supplies a switch control signal Sa to switches SW1 and SW3, which prompts them to turn on when the pulse width modulation signal PWMS indicates logic level 1, and to turn them off when it indicates logic level 0.

[0052] Furthermore, the switch control circuit 23A supplies a switch control signal Sb to switch SW2 to initiate the off state when the pulse width modulation signal PWMS indicates logic level 1. Subsequently, the switch control circuit 23A continues to supply the switch control signal Sb to initiate the off state to switch SW2 until a predetermined period TS has elapsed from the time of the transition when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0. After this predetermined period TS has elapsed, it supplies the switch control signal Sb to initiate the on state to switch SW2.

[0053] Furthermore, the switch control circuit 23A supplies a switch control signal Sc to the switch SW4, which prompts the switch to be ON during the period from when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0 until the predetermined period TS has elapsed, and prompts the switch to be OFF during the rest of the period.

[0054] Switch SW4 turns ON when the switch control signal Sc prompts it to turn ON, connecting the output terminal and the inverting input terminal of the differential amplifier 22. On the other hand, when the switch control signal Sb prompts it to turn OFF, switch SW4 turns OFF, disconnecting the connection between the output terminal and the inverting input terminal of the differential amplifier 22.

[0055] The operation of the drive circuit 20_1a will be explained below with reference to Figures 7 and 8A to 8C.

[0056] Figure 7 is a time chart showing the internal operation performed by the drive circuit 20_1a in response to the pulse width modulation signal PWMS.

[0057] Figure 8A is a circuit diagram of drive circuit 20_1a showing the state of switches SW1~SW4 and selector 21 when it receives a pulse width modulated signal PWMS at logic level 1 that prompts the light to turn on (t1~t2). Figure 8B is a circuit diagram of drive circuit 20_1a showing the state of switches SW1~SW4 and selector 21 within a predetermined period TS (t2~t4) after the pulse width modulated signal PWMS transitions from logic level 1 to logic level 0 that prompts the light to turn off. Figure 8C is a circuit diagram of drive circuit 20_1a showing the state of switches SW1~SW4 and selector 21 after the predetermined period TS has elapsed after the pulse width modulated signal PWMS transitions to logic level 0 that prompts the light to turn off (t4~t1).

[0058] [When lit] First, as shown in Figures 7 and 8A, when a pulse width modulation signal PWMS of logic level 1, which prompts illumination, is received, the selector 21 selects the control voltage Von from among the control voltages Von and Voff, and supplies this as the control voltage Vin to the differential amplifier 22. Furthermore, during this time, as shown in Figures 7 and 8A, switches SW1 and SW3 are in the ON state, and switches SW2 and SW4 are in the OFF state.

[0059] As a result, as shown in Figure 8A, the ends of resistor Roff are short-circuited by switch SW3, so the current output from the source of output transistor 24 flows through resistor R without passing through resistor Roff. At this time, one end of resistor R, i.e., the source voltage Vs, is supplied to the inverting terminal of differential amplifier 22 via switch SW1. Consequently, differential amplifier 22 supplies a drive voltage Vg to the gate of output transistor 24, having a voltage value V_H as shown in Figure 7, which corresponds to the difference between the source voltage Vs and the control voltage Von, so that the source voltage Vs becomes equal to the control voltage Von.

[0060] Therefore, the output transistor 24 receives a current corresponding to the drive voltage Vg, Iout=Von / R The output current Iout, represented by the formula, is passed through a current path consisting of the output transistor 24, switch SW3, and resistor R, as shown by the thick solid arrow in Figure 8A. As a result, the output current Iout flows to the light-emitting diodes LE1 to LEr of the LED unit 13_1, causing the light-emitting diodes LE1 to LEr to light up.

[0061] [When lights are off (within the designated period of TS)] Next, as shown in Figures 7 and 8B, when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0, which signals the lights to be turned off, the selector 21 selects the control voltage Voff from among the control voltages Von and Voff, and supplies it to the differential amplifier 22 as the control voltage Vin. Furthermore, while the pulse width modulation signal PWMS maintains logic level 0, switches SW1 and SW3 are turned off, as shown in Figures 7 and 8B.

[0062] Furthermore, from the time t2 when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0 until the time t4 when a predetermined period TS has elapsed, switches SW2 and SW4 remain ON, as shown in Figures 7 and 8B.

[0063] As a result, a resistor Roff is connected in series between the source and resistor R of the output transistor 24. Furthermore, the source of the output transistor 24 is connected to the inverting terminal of the differential amplifier 22 via switch SW2 and to the output terminal of the differential amplifier 22 via switch SW4. As a result, as shown in Figure 7, the drive voltage Vg and source voltage Vs drop sharply from the moment t2 when the pulse width modulation signal PWMS transitions from logic level 1 to logic level 0, which prompts the light to turn off.

[0064] [When lights are off (after the designated period TS)] Then, as shown in Figures 7 and 8C, after a predetermined period TS has elapsed since the pulse width modulation signal PWMS transitioned from logic level 1 to logic level 0, which prompts the light to be turned off, switch SW2 transitions from the off state to the on state, and switch SW4 transitions from the on state to the off state. Therefore, the differential amplifier 22 supplies a drive voltage Vg to the gate of the output transistor 24, having a voltage value V_L shown in Figure 7, which corresponds to the difference between the source voltage Vs and the control voltage Voff, so that the source voltage Vs becomes equal to the control voltage Voff. As a result, the output transistor 24 receives a current corresponding to the drive voltage Vg, Iout_off = Voff / (Roff + R) The output current Iout_off, represented by the formula, flows through the current path consisting of the output transistor 24, resistors Roff and R, as shown by the thick solid arrow in Figure 8B. Although this output current Iout_off flows through the light-emitting diodes LE1 to LEr of the LED unit 13_1, the current value is extremely small, so the light-emitting diodes LE1 to LEr are effectively turned off.

[0065] Thus, in the drive circuit 20_1a, as in the drive circuit 20_1, a small output current Iout_off is supplied when the light-emitting diode is turned off by PWM drive. This allows the voltage applied to the output transistor 24 to be lowered during the off operation, making it possible to use low-voltage components for each circuit element, including the output transistor 24.

[0066] Furthermore, in the drive circuit 20_1a, the source of the output transistor is connected to the output terminal and inverting terminal of the differential amplifier 22 by switch SW4 for a predetermined period TS from the moment the PWM drive transitions from the on state to the off state. This makes it possible to rapidly reduce the drive voltage Vg and source voltage Vs applied to the gate of the output transistor 24. Therefore, the drive circuit 20_1a makes it possible to quickly switch from a state in which the output current Iout for turning on the light is flowing to a state in which the output current Iout_off for turning off the light is flowing. [Example 3]

[0067] Figure 9 is a block diagram showing the configuration of LED driver 20A as a modified example of LED driver 20.

[0068] Furthermore, the LED units 13_1 to 13_N shown in Figure 9 are identical to those shown in Figure 2, and are connected to the external terminals tm1 to tmN of the LED driver 20A, similar to those shown in Figure 3.

[0069] Furthermore, the LED driver 20A uses drive circuits 20A_2 to 20A_N instead of drive circuits 20_2 to 20_N shown in Figure 2, and the only difference is the addition of switches Sc1 to ScN; otherwise, the configuration (20_1, 21) is the same as that shown in Figure 2.

[0070] In other words, the drive circuit 20_1 has the same internal configuration as, for example, the drive circuit 20_1 shown in Figure 6, and operates according to the timing chart shown in Figure 7 in response to the pulse width modulation signal PWMS supplied from the switch control circuit 23A.

[0071] On the other hand, each of the drive circuits 20A_2 to 20A_N has the internal configuration shown in Figure 10. The configuration shown in Figure 10 is obtained by removing switches SW2 to SW4 and resistor Roff from the configuration shown in Figure 6, adding switch SW5, and replacing switch control circuit 23A shown in Figure 6 with switch control circuit 23B. Therefore, the other components (21, 22, 24, R, SW1) are the same as those shown in Figure 6.

[0072] The switch control circuit 23B supplies a switch control signal Sa to switch SW1, which prompts it to turn on when the pulse width modulation signal PWMS indicates logic level 1, and to turn it off when it indicates logic level 0. The switch control circuit 23B also supplies a switch control signal Sd to switch SW5, which prompts it to turn on when the pulse width modulation signal PWMS indicates logic level 0, and to turn it off when it indicates logic level 1. Switch SW5 turns on when the switch control signal Sd indicates an ON state, and applies a ground voltage VSS to the output terminal of the differential amplifier 22 and the gate of the output transistor 24. In this way, the switch circuit including the switch control circuit 23B and switches SW1 and SW5 connects one end (n2) of resistor R to the inverting input terminal of differential amplifier 22 when lighting (driving) the light-emitting diodes LE1 to LEr. On the other hand, when turning off (not driving) the light-emitting diodes LE1 to LEr, the connection between one end (n2) of resistor R and the inverting input terminal of differential amplifier 22 is disconnected, and a ground voltage VSS is applied to the inverting input terminal of differential amplifier 22 and the gate of output transistor 24.

[0073] Therefore, in the configuration shown in Figure 10, each of the drive circuits 20A_2 to 20A_N operates similarly to each other when the pulse width modulation signal PWMS indicates logic level 1, which prompts illumination. In other words, the differential amplifier 22 included in each of the drive circuits 20A_2 to 20A_N supplies a drive voltage Vg corresponding to the difference between the source voltage Vs and the control voltage Von to the gate of the output transistor 24, so that the source voltage Vs of the output transistor 24 is equal to the control voltage Von. As a result, the output transistor 24 flows an output current Iout (=Von / R) corresponding to the drive voltage Vg through the light-emitting diodes LE1 to LEr, thereby illuminating the light-emitting diodes LE1 to LEr. On the other hand, when the pulse width modulation signal PWMS indicates logic level 0, which prompts extinguishing, the output transistors 24 of each of the drive circuits 20A_2 to 20A_N are in the off state, and the light-emitting diodes LE1 to LEr are extinguished.

[0074] Each of switches Sc1 to ScN receives a pulse width modulation signal PWMS. If the pulse width modulation signal PWMS indicates a logic level of 0, it is in the ON state, and if it indicates a logic level of 1, it is in the OFF state.

[0075] Specifically, when switch Sc1 is ON, it connects the wiring L1 that connects the drain of the output transistor 24 included in the drive circuit 20_1 to the external terminal tm1 to the shared wiring LL, while when it is OFF, it disconnects the wiring L1 and the shared wiring LL. When switch Sc2 is ON, it connects the wiring L2 that connects the drain of the output transistor 24 included in the drive circuit 20A_2 to the shared wiring LL, while when it is OFF, it disconnects the wiring L2 and the shared wiring LL.

[0076] Similarly, when switches Sc3 to ScN are ON, they connect the drains of the output transistors 24 included in each of the drive circuits 20A_3 to 20A_N to the shared wiring L3 to LN, which individually connect to the external terminals tm3 to tmN. On the other hand, when switches Sc3 to ScN are OFF, they disconnect the connections between each of the wirings L3 to LN and the shared wiring LL.

[0077] The operation of the LED driver 20A, which includes drive circuits 20A_2 to 20A_N having the configurations shown in Figure 10, and drive circuit 20A_1 having the configuration shown in Figure 6, will be described below with reference to Figures 11A and 11B.

[0078] Figure 11A is a block diagram of the LED driver 20A, showing the state of switches Sc1~ScN when a logic level 1 pulse width modulation signal PWMS is received to prompt illumination, and the direction of current flowing through wiring L1~LN and shared wiring LL is indicated by thick arrows.

[0079] [When lit] As shown in Figure 11A, when a pulse width modulation signal PWMS of logic level 1, which prompts illumination, is received, all switches Sc1 to ScN are turned off. Furthermore, each of the drive circuits 20_1 and 20A_2 to 20A_N supplies an output current Iout to each of the LED units 13_1 to 13_N via wiring L1 to LN, as shown by the thick solid arrows in Figure 11A, to illuminate the light-emitting diodes.

[0080] [When the lights are off] As shown in Figure 11B, when a pulse width modulation signal PWMS with logic level 0 prompting the lights to turn off is received, switches Sc1 to ScN all turn ON. Incidentally, as mentioned above, drive circuit 20_1, one of the drive circuits 20_1 and 20A_2 to 20A_N, has the internal configuration shown in Figure 6. Therefore, in response to the pulse width modulation signal PWMS indicating logic level 0, drive circuit 20_1 enters the state shown in Figures 8B and 8C, generates an output current Iout_off, and flows this to the LED unit 13_1 via wiring L1, as shown by the thick solid arrow in Figure 11B.

[0081] In this case, the output current Iout_off is divided and supplied to each of the drive circuits 20A_2 to 20A_N via switches Sc2 to ScN, as shown by the thick arrows in Figure 11B, through switch Sc1 and shared wiring LL.

[0082] Therefore, even when the output transistors 24 in each of the drive circuits 20A_2 to 20A_N are turned off by the pulse width modulation signal PWMS at logic level 0, a voltage corresponding to the current flowing in through switches Sc2 to ScN is applied to the drains of the output transistors 24. This makes it possible to lower the voltage applied to the drains of the output transistors 24 in each of the drive circuits 20A_2 to 20A_N when the lights are off compared to the power supply voltage VLED.

[0083] Therefore, by adopting the LED driver 20A shown in Figure 9, it becomes unnecessary to provide a resistor Roff within each of the drive circuits 20A_2 to 20A_N, making it possible to further reduce the size of the device.

[0084] In the embodiments shown in Figures 3, 6, or 9 above, multiple switches (SW1 to SW5) are provided within each drive circuit (20_1 to 20_N, 20A_2 to 20A_N), and the on / off operation is switched by individually controlling each switch. However, instead of these multiple switches (SW1 to SW5), a switch circuit capable of achieving similar functions to those achieved by the on / off control of each of these switches may be used.

[0085] Furthermore, in the above embodiment, the operation during illumination (driving) and unillumination (not driving) was explained using an LED driver 20 (20A) that drives light-emitting diodes LE1 to LEr connected in series as a single load as an example. However, the load to be driven is not limited to light-emitting diodes, and may be a DC motor, for example.

[0086] Furthermore, although Figure 2 or Figure 9 shows three or more drive circuits (20_1 to 20_N) as N drive circuits within the LED driver 20 or 20A, two or more are sufficient.

[0087] In short, the load drive circuit according to this disclosure only needs to include the following transistors, differential amplifiers, first and second resistors, selector and switch circuits, along with external terminals (tm1 to tmN) for connecting loads (LE1 to LEr).

[0088] Specifically, transistor (24) has its drain connected to an external terminal, receives a drive voltage (Vg) at its gate, and outputs a current (Iout, Iout_off) corresponding to this drive voltage between its drain and source. The differential amplifier (22) generates the drive voltage (Vg) and supplies it to the gate of transistor (24). The first resistor (Roff) has one end connected to the source of transistor (24) and its other end connected to one end of the second resistor (R). A ground voltage is applied to the other end of the second resistor. The selector (21) receives a first voltage (Von) and a second voltage (Voff) lower than the first voltage, and supplies the first voltage (Von) to the non-inverting input terminal of the differential amplifier when driving a load (LE1~LEr), and supplies the second voltage (Voff) to the non-inverting input terminal of the differential amplifier when not driving. The switch circuits (SW1~SW5, 23, 23A) short-circuit the first resistor (Roff) and connect one end (n2) of the second resistor (R) to the inverting input terminal of the differential amplifier when the load is driven, and connect one end (n1) of the first resistor to the inverting input terminal of the differential amplifier when the load is not driven.

[0089] Thus, this disclosure is not limited to the embodiments described in Examples 1 to 3 above, and various improvements and design modifications are possible without departing from the spirit of this disclosure.

[0090] [Note] This specification discloses the following configuration:

[0091] (Composition 1) A load drive circuit comprising: an external terminal for connecting a load; a transistor whose drain is connected to the external terminal, receives a drive voltage at its gate, and flows an output current corresponding to the drive voltage between its drain and source; a differential amplifier that generates the drive voltage and supplies it to the gate of the transistor; a first resistor whose one end is connected to the source of the transistor; a second resistor whose one end is connected to the other end of the first resistor, and to which a ground voltage is applied; a selector that receives a first voltage and a second voltage lower than the first voltage, and supplies the first voltage to the non-inverting input terminal of the differential amplifier when the load is driven, and supplies the second voltage to the non-inverting input terminal of the differential amplifier when the load is not driven; and a switch circuit that short-circuits both ends of the first resistor and connects one end of the second resistor to the inverting input terminal of the differential amplifier when the load is driven, and connects one end of the first resistor to the inverting input terminal of the differential amplifier when the load is not driven.

[0092] (Configuration 2) Define the functions of resistors Roff and R. The load drive circuit according to configuration 1, wherein the second resistor supplies a voltage obtained by converting the output current into a voltage from one end of itself to the inverting input terminal of the differential amplifier, and the first resistor is a current limiting resistor that suppresses the current value of the output current and has a higher resistance value than the second resistor.

[0093] (Configuration 3) Switches SW1 to SW3 shown in Figure 3 are limited The load drive circuit according to configuration 1 or 2, comprising: a first switch that is turned on when the load is driven, connecting one end of the second resistor to the inverting input terminal of the differential amplifier, and is turned off when the load is not driven, disconnecting the connection between the one end of the second resistor and the inverting input terminal of the differential amplifier; a second switch that is turned on when the load is not driven, connecting one end of the first resistor to the inverting input terminal of the differential amplifier, and is turned off when the load is driven, disconnecting the connection between the one end of the first resistor and the inverting input terminal of the differential amplifier; and a third switch that is turned on when the load is driven, short-circuiting both ends of the first resistor, and is turned off when the load is not driven, releasing the short-circuit state between both ends of the first resistor.

[0094] (Configuration 4) Includes switch SW4 shown in Figure 6 and defines the operation of switch SW2 shown in Figure 7. The load drive circuit according to configuration 3, wherein the switch circuit further includes a fourth switch that, when the load transitions from a driven state to a non-driven state, turns on for a predetermined period of time from the moment the load transitions from the driven state to the non-driven state, and connects the gate of the transistor to the output terminal and inverting terminal of the differential amplifier, and the second switch is a switch that remains in the off state for the predetermined period of time from the moment the load transitions from the driven state to the non-driven state.

[0095] (Configuration 5) Control by pulse width modulation signal (PWM) The load drive circuit according to any one of the above configurations 1 to 4, wherein the selector receives a binary signal that alternately and periodically represents a first logic level state that prompts the driving of the load and a second logic level state that prompts the non-driving of the load, and supplies the first voltage to the non-inverting input terminal of the differential amplifier while the binary signal is in the first logic level state, and supplies the second voltage to the non-inverting input terminal of the differential amplifier while the binary signal is in the second logic level state.

[0096] (Composition 6) The load is a plurality of light-emitting diodes connected in series, as described in any one of configurations 1 to 5 above.

[0097] (Configuration 7) LED driver 20A shown in Figures 3, 9 and 10 A driver having a plurality of load drive circuits, each including an external terminal for connecting a load, comprising a shared wiring and a plurality of switches that are turned on only when the load is not being driven and connect the external terminals of each of the plurality of load drive circuits to the shared wiring, wherein one of the plurality of load drive circuits is the load drive circuit described in configuration 1, and each of the other load drive circuits other than the load drive circuit 1 has its drain connected to its own external terminal, receives a drive voltage at its gate and flows an output current corresponding to the drive voltage between its drain and source, and a differential amplifier that generates the drive voltage and supplies it to the gate of the transistor, and The device includes a resistor with one end connected to the source of a transistor and a ground voltage applied to its other end; a selector that receives a first voltage and a second voltage lower than the first voltage, and supplies the first voltage to the non-inverting input terminal of the differential amplifier when the load is driven, and supplies the second voltage to the non-inverting input terminal of the differential amplifier when the load is not driven; and a switch circuit that connects one end of the resistor to the inverting input terminal of the differential amplifier when the load is driven, and disconnects the connection between one end of the resistor and the inverting input terminal of the differential amplifier and applies a ground voltage to the output terminal of the differential amplifier and the gate of the transistor when the load is not driven.

[0098] (Composition 8) The driver according to configuration 7, wherein the load is a plurality of light-emitting diodes connected in series.

[0099] (Configuration 9) Display device in Figure 1, including the LED driver 20 shown in Figure 2. A display device comprising: a liquid crystal display panel including a plurality of scan lines extending horizontally in a two-dimensional screen and a plurality of data lines extending vertically in a two-dimensional screen; a scan driver that sequentially applies horizontal scan pulses to each of the plurality of scan lines; a data driver that supplies a plurality of drive signals to the plurality of data lines, each having a voltage value corresponding to the brightness level of each pixel based on a video signal; a backlight panel installed on the back of the liquid crystal display panel and having a plurality of LED units, each containing a first to r (r is an integer of 2 or more) light-emitting diode connected in series; and an LED driver that drives the first to r light-emitting diodes contained in each of the plurality of LED units, wherein the LED driver includes a plurality of load drive circuits provided corresponding to each of the plurality of LED units, and each of the plurality of load drive circuits is the load drive circuit described in Configuration 1 above, and drives the first to r light-emitting diodes contained in the LED unit corresponding to itself as the load.

[0100] (Configuration 10) Display device in Figure 1, including the LED driver 20A shown in Figure 9. A display device comprising: a liquid crystal display panel including a plurality of scan lines extending horizontally in a two-dimensional screen and a plurality of data lines extending vertically in a two-dimensional screen; a scan driver that sequentially applies horizontal scan pulses to each of the plurality of scan lines; a data driver that supplies a plurality of drive signals to the plurality of data lines, each having a voltage value corresponding to the brightness level of each pixel based on a video signal; a backlight panel installed on the back of the liquid crystal display panel and having a plurality of LED units, each containing a first to r (r is an integer of 2 or more) light-emitting diode connected in series; and an LED driver that drives the first to r light-emitting diodes contained in each of the plurality of LED units, wherein the LED driver is the driver described in configuration 7 above and drives the first to r light-emitting diodes contained in each of the plurality of LED units as the load. [Explanation of Symbols]

[0101] 13 Backlight Panel 20, 20A LED driver 20_1~20_N drive circuit 21 Selector 22 Differential Amplifier 23 Switch control circuit 24 output transistors 200 PWM signal generation circuit LE1~LEr Light-Emitting Diodes R, Roff resistance SW1-SW5, Sc1-ScN switches

Claims

1. External terminals for connecting the load, A transistor whose drain is connected to the aforementioned external terminal, which receives a drive voltage at its gate and flows an output current corresponding to the drive voltage between its drain and source, A differential amplifier that generates the aforementioned drive voltage and supplies it to the gate of the transistor, A first resistor, one end of which is connected to the source of the transistor, A second resistor, one end of which is connected to the other end of the first resistor, and to which a ground voltage is applied at its other end, A selector that receives a first voltage and a second voltage lower than the first voltage, supplies the first voltage to the non-inverting input terminal of the differential amplifier when the load is driven, and supplies the second voltage to the non-inverting input terminal of the differential amplifier when the load is not driven, A load driving circuit including a switch circuit that short-circuits both ends of the first resistor and connects one end of the second resistor to the inverting input terminal of the differential amplifier when the load is being driven, and connects one end of the first resistor to the inverting input terminal of the differential amplifier when the load is not being driven.

2. The second resistor converts the output current into a voltage and supplies the resulting voltage from one of its ends to the inverting input terminal of the differential amplifier. The load drive circuit according to claim 1, wherein the first resistor is a current limiting resistor that limits the current value of the output current and has a higher resistance value than the second resistor.

3. The aforementioned switch circuit is A first switch that turns on when the load is driven, connecting one end of the second resistor to the inverting input terminal of the differential amplifier, and turns off when the load is not driven, disconnecting the connection between the one end of the second resistor and the inverting input terminal of the differential amplifier, A second switch, which is ON when the load is not driven and connects one end of the first resistor to the inverting input terminal of the differential amplifier, and OFF when the load is driven and disconnects the connection between the one end of the first resistor and the inverting input terminal of the differential amplifier, The load driving circuit according to claim 2, further comprising: a third switch which is turned ON when the load is driven, short-circuiting the terminals of the first resistor; and turned OFF when the load is not driven, releasing the short-circuit state across the terminals of the first resistor.

4. The switch circuit further includes a fourth switch that, when the load transitions from a driven state to a non-driven state, turns on for a predetermined period of time from the moment the load transitions from the driven state to the non-driven state, and connects the gate of the transistor to the output terminal and inverting terminal of the differential amplifier. The load drive circuit according to claim 3, wherein the second switch is a switch that maintains an off state for a predetermined period of time from the time the load transitions from the driven state to the non-driven state.

5. The load drive circuit according to any one of claims 1 to 4, wherein the selector receives a binary signal that alternately and periodically represents a first logic level state that prompts the drive of the load and a second logic level state that prompts the non-drive of the load, and while the binary signal is in the first logic level state, the selector supplies the first voltage to the non-inverting input terminal of the differential amplifier, and while the binary signal is in the second logic level state, the selector supplies the second voltage to the non-inverting input terminal of the differential amplifier.

6. The load drive circuit according to claim 1, wherein the load is a plurality of light-emitting diodes connected in series.

7. A driver having multiple load drive circuits, each including an external terminal for connecting a load, Shared wiring and It includes a plurality of switches that are turned on only when the load is not being driven, and which connect the external terminals of each of the plurality of load drive circuits to the shared wiring, One of the plurality of load drive circuits is the load drive circuit described in claim 1, Each of the load drive circuits other than the load drive circuit 1 described above is: A transistor whose drain is connected to its own external terminal, which receives a drive voltage at its gate and which flows an output current corresponding to the drive voltage between its drain and source, A differential amplifier that generates the aforementioned drive voltage and supplies it to the gate of the transistor, A resistor has one end connected to the source of the aforementioned transistor and a ground voltage applied to its other end. A selector that receives a first voltage and a second voltage lower than the first voltage, supplies the first voltage to the non-inverting input terminal of the differential amplifier when the load is driven, and supplies the second voltage to the non-inverting input terminal of the differential amplifier when the load is not driven, A driver including a switch circuit that, when the load is driven, connects one end of the resistor to the inverting input terminal of the differential amplifier, and when the load is not driven, disconnects the connection between the one end of the resistor and the inverting input terminal of the differential amplifier and applies a ground voltage to the output terminal of the differential amplifier and the gate of the transistor.

8. The driver according to claim 7, wherein the load is a plurality of light-emitting diodes connected in series.

9. A liquid crystal display panel including multiple scan lines extending horizontally in a two-dimensional screen and multiple data lines extending vertically in a two-dimensional screen, A scanning driver that sequentially applies horizontal scanning pulses to each of the plurality of scanning lines, A data driver that supplies multiple drive signals to the multiple data lines, each having a voltage value corresponding to the brightness level of each pixel based on the video signal, A backlight panel is installed on the back of the aforementioned liquid crystal display panel and has multiple LED units, each containing a first to r (where r is an integer of 2 or more) light-emitting diode connected in series, A display device comprising: an LED driver provided corresponding to each of the plurality of LED units, each including a plurality of load drive circuits consisting of the load drive circuit described in claim 1, and which drives the first to r light-emitting diodes contained in each of the plurality of LED units as the load.

10. A liquid crystal display panel including multiple scan lines extending horizontally in a two-dimensional screen and multiple data lines extending vertically in a two-dimensional screen, A scanning driver that sequentially applies horizontal scanning pulses to each of the plurality of scanning lines, A data driver that supplies multiple drive signals to the multiple data lines, each having a voltage value corresponding to the brightness level of each pixel based on the video signal, A backlight panel is installed on the back of the aforementioned liquid crystal display panel and has multiple LED units, each containing a first to r (where r is an integer of 2 or more) light-emitting diode connected in series, A display device comprising an LED driver that includes the driver described in claim 7, and drives the first to r light-emitting diodes included in each of the plurality of LED units as the load.

Images