Pad connection abnormality detection circuit
The pad connection abnormality detection circuit uses a latch circuit and determination circuit to generate and process one-shot pulse signals, addressing the challenge of reliably detecting open failures in LSI pad connections by determining the logic level, thereby ensuring accurate detection of connection abnormalities.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-01-16
- Publication Date
- 2026-07-29
AI Technical Summary
Conventional methods struggle to reliably detect open failures in pad connections between an LSI and an external terminal due to uncertainty in the logic circuit's recognition of input signals, making it difficult to determine whether the input is 'L' or 'H'.
A pad connection abnormality detection circuit comprising a latch circuit, a detection signal generation circuit, a reset signal supply unit, and a determination circuit that generates and processes one-shot pulse detection signals to reliably determine the logic level of the pad connection, using transistors and inverters to fix the voltage level and output a determination signal based on signal changes.
Enables reliable detection of open faults in pad connections by determining the logic level of the pad after power-on, ensuring accurate identification of connection abnormalities.
Smart Images
Figure 2026122776000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a pad connection abnormality detection circuit that detects an abnormal connection between a pad and an external terminal.
Background Art
[0002] An external terminal of an LSI (Large Scale Integrated circuit) and a pad are generally connected by a bonding wire. At this time, if an abnormal connection of the pad (for example, an open failure, L short, H short, etc.) occurs, an intended signal cannot be input into the LSI, so there is a possibility that the LSI does not operate as intended.
[0003] In order to detect a bonding failure of a plurality of wires laid in parallel, a plurality of wirings that conduct between a plurality of pads and a first end or a second end of a power transistor, and a shunt current flowing through each of the plurality of wirings and at least one of voltage drops generated according to each wiring resistance component are detected as a sense voltage. A semiconductor chip including a current detection circuit and a logic for determining the wire bonding state of each of the plurality of pads according to the detection result of the current detection circuit has been proposed (for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
[0005] [Summary] When an open failure of a pad occurs, it is unclear whether a logic circuit that receives an input signal recognizes the input as "L" (low) or "H" (high). Therefore, there is a problem that it is difficult to reliably detect an open failure of a pad by a conventional connection abnormality detection method.
[0006] A pad connection abnormality detection circuit according to one aspect of the present disclosure includes: a latch circuit connected to a pad that receives an input signal via an external terminal and takes in the input signal; a detection signal generation circuit connected to the output of the latch circuit and generates a one-shot pulse detection signal when the signal level of the signal input to itself changes between logic level 0 and logic level 1; a reset signal supply unit that supplies a reset signal to fix the voltage of the connection line connecting the pad and the detection signal generation circuit to one of the logic levels; and a determination circuit that receives the detection signal and outputs a determination signal in response to the detection of the one-shot pulse. [Brief explanation of the drawing]
[0007] [Figure 1] This is a circuit diagram showing the configuration of a pad connection abnormality detection circuit according to Embodiment 1 of the present disclosure. [Figure 2] This is a circuit diagram showing an example of the configuration of a judgment circuit. [Figure 3] This is a circuit diagram showing another example configuration of the judgment circuit. [Figure 4] This is a truth table showing the input and output of an RS flip-flop circuit. [Figure 5] This is a time chart showing the operation of the pad connection abnormality detection circuit in Example 1. [Figure 6] This is a circuit diagram showing the configuration of a pad connection abnormality detection circuit according to Embodiment 2 of the present disclosure. [Figure 7] This is a time chart showing the operation of the pad connection abnormality detection circuit in Example 2. [Detailed Description] Preferred embodiments of the present disclosure are described in detail below. In the following descriptions and accompanying drawings of the embodiments, substantially identical or equivalent parts are denoted by the same reference numerals. [Example 1]
[0008] Figure 1 is a circuit diagram showing the configuration of a pad connection abnormality detection circuit 11 according to Embodiment 1 of this disclosure. The pad connection abnormality detection circuit 11 is provided on an LSI (Large Scale Integrated circuit) 100 and is a circuit that detects connection abnormalities in the connection between a pad PD provided on the LSI 100 and an external terminal ET via a bonding wire. In addition to the pad connection abnormality detection circuit 11, the LSI 100 is also provided with a control unit 14 that generates a power-on reset signal POR and an internal circuit 15 that receives signals input via the pad PD.
[0009] The pad connection abnormality detection circuit 11 detects a connection abnormality of pad PD based on the input signal IS, which is input from outside the LSI 100 via the external terminal ET. In this embodiment, the input signal IS is a signal whose signal level changes from logic level 0 (L level) to logic level 1 (H level).
[0010] The pad connection abnormality detection circuit 11 includes a rising edge detection circuit 12 and a determination circuit 13. The rising edge detection circuit 12 consists of a latch unit 21, a reset unit 22, and a one-shot pulse generation unit 23.
[0011] The latch section 21 consists of loop-connected inverters IVA and IVB. Inverter IVA has its input terminal connected to pad PD and outputs a signal from its output terminal that is the inverted version of the input signal IS input from pad PD. Inverter IVB has its input terminal connected to the output terminal of inverter IVA and its output terminal connected to the input terminal of inverter IVA.
[0012] The reset unit 22 consists of a transistor PM1, which is a P-channel MOSFET. The source of transistor PM1 is supplied to the power supply voltage VDD voltage supply line. Transistor PM1 receives a power-on reset signal POR at its gate and turns on or off accordingly. The drain of transistor PM1 is connected to the output node n1 of the latch unit 21 (i.e., the output terminal of inverter IVA). When a low-level power-on reset signal POR is supplied to the gate of transistor PM1, transistor PM1 turns on, and the potential of output node n1 is reset.
[0013] The output node n1 is located on the connection line connecting the pad PD and the one-shot pulse generation unit 23 via the latch unit 21. The reset unit 22 has the function of fixing the voltage logic of the connection line by resetting the potential of the output node n1.
[0014] The one-shot pulse generation unit 23 consists of odd-numbered inverters IV1 to IVn (where n is an odd number) and a NOR gate NR1 connected in series. The first input terminal of the NOR gate NR1 is connected to the output node n1 of the latch unit 21. The second input terminal of the NOR gate NR1 is connected to the output terminal of inverter IVn, which is the final stage inverter.
[0015] The first input terminal of the NOR gate NR1 receives the voltage signal from output node n1, and the second input terminal receives the voltage signal obtained by inverting the voltage of output node n1 by odd-numbered inverters IV1 to IVn. As a result, when a signal whose signal level changes from logic level 0 to logic level 1 is input as the input signal IS, a one-shot pulse edge detection signal DTP is generated and output from the output terminal of the NOR gate NR1.
[0016] The determination circuit 13 receives the edge detection signal DTP output from the rising edge detection circuit 12 and outputs a determination signal DTS based on this signal, indicating whether or not there is an abnormality in the pad connection.
[0017] FIG. 2 is a circuit diagram showing the configuration of the determination circuit 13. The determination circuit 13 includes a switch 31, an initialization circuit 32, and a latch section 33.
[0018] The switch 31 is composed of a transistor NM1 which is an N-channel type MOSFET. The source of the transistor NM1 is grounded, and the gate is connected to the output terminal of the rising edge detection circuit 12. The transistor NM1 receives the edge detection signal DTP at the gate and becomes on or off accordingly.
[0019] The initialization circuit 32 is composed of a transistor PM2 which is a P-channel type MOSFET. The source of the transistor PM2 is supplied to the voltage supply line of the power supply voltage VDD. The transistor PM2 receives the power-on reset signal POR at the gate and becomes on or off accordingly. The drain of the transistor PM2 is connected to a line L1 that connects the drain of the transistor NM1 and the latch section 33. When the L-level power-on reset signal POR is supplied to the gate of the transistor PM2 and the transistor PM2 turns on, the potential of the line L1 is initialized.
[0020] The latch section 33 is composed of inverters IVC and IVD connected in a loop. The input terminal of the inverter IVC is connected to the line L1, and outputs a signal obtained by inverting the potential of the line L1 from the output terminal. The input terminal of the inverter IVD is connected to the output terminal of the inverter IVC, and the output terminal is connected to the input terminal of the inverter IVC.
[0021] With such a configuration, the determination circuit 13 outputs a determination signal DTS that changes to a logic level 1 when an edge detection signal DTP of a one-shot pulse is input with an initial value of logic level 0. When there is no input of the edge detection signal DTP of the one-shot pulse, the signal level of the determination signal DTS is maintained at the logic level 0.
[0022] Note that the configuration of the determination circuit 13 is not limited to this, and it may be configured by a logic circuit such as a flip-flop circuit.
[0023] FIG. 3 is a circuit diagram showing the configuration of a determination circuit 13A, which is another configuration example of the determination circuit 13. The determination circuit 13A includes an RS flip-flop circuit 34 and a transistor NM2.
[0024] In the RS flip-flop circuit 34, the reset terminal R is grounded, and the set terminal S is connected to the output terminal of the rising edge detection circuit 12. The output terminal Q is connected to an output line L2 that outputs a determination signal DTS.
[0025] FIG. 4 is a truth table showing the input-output relationship of the RS flip-flop circuit 34. When the inputs of both the reset terminal R and the set terminal S are at the logic level 0, the previous value is held as the output of the output terminal Q. When the input of the reset terminal R is at the logic level 0 and the input of the set terminal S is at the logic level 1, a signal of the logic level 1 is output from the output terminal Q.
[0026] The transistor NM2 is composed of a P-channel type MOSFET, with its source grounded and its drain connected to the output line L2. The transistor NM2 receives a supply of an inverted reset signal XPOR, which is a signal obtained by determining the logic level of the power-on reset signal POR, at its gate, and accordingly becomes on or off.
[0027] With such a configuration, similar to the determination circuit 13 in FIG. 2, when an edge detection signal DTP of a one-shot pulse is input, the determination circuit 13A changes from the logic level 0 to the logic level 1, and when there is no input of the edge detection signal DTP of the one-shot pulse, it outputs a determination signal DTS that maintains the logic level 0 state.
[0028] Next, the operation of the pad connection abnormality detection circuit 11 of this embodiment will be described with reference to the time chart in FIG. 5.
[0029] When the LSI100 is powered on, the edge detection signal DTP and the judgment signal DTS are initialized accordingly, and at timing T1 shown in the figure, the edge detection signal DTP and the judgment signal DTS are output at logic level 0 (i.e., L level).
[0030] If no pad connection abnormality occurs, the external input signal IS is input to the rising edge detection circuit 12 via the external terminal ET and pad PD. In this state, when the input signal IS transitions from logic level 0 (L level) to logic level 1 (H level), the rising edge detection circuit 12 outputs a one-shot pulse edge detection signal DTP accordingly. Based on the edge detection signal DTP, the determination circuit 13 outputs a determination signal DTS at timing T2 shown in the figure, in which the signal level changes from logic level 0 (L level) to logic level 1 (H level).
[0031] On the other hand, if a pad connection abnormality occurs, the input signal IS is not input to the rising edge detection circuit 12, so the edge detection signal DTP, which is the output of the rising edge detection circuit 12, is fixed at logic level 0 (L level). As a result, the judgment signal DTS, which is the output of the judgment circuit 13, is also fixed at logic level 0 (L level).
[0032] As described above, the pad connection anomaly detection circuit 11 of this embodiment receives an input signal IS whose signal level transitions from logic level 0 to logic level 1, and outputs a determination signal DTS whose signal level changes accordingly. When no pad connection anomaly has occurred, the signal level of the determination signal DTS changes in accordance with the change in the signal level of the input signal IS, while when a pad connection anomaly has occurred, the signal level of the determination signal DTS remains fixed regardless of the change in the signal level of the input signal IS. This makes it possible to detect the occurrence of a pad connection anomaly based on the signal level of the determination signal DTS.
[0033] According to the pad connection abnormality detection circuit 11 of this embodiment, even when an open fault occurs in the pad PD, the logic of the pad PD after power-on (i.e., the logic level of the voltage on the line connected to the pad PD) can be determined, making it possible to reliably detect an open fault in the pad PD as a connection abnormality. [Example 2]
[0034] Next, Embodiment 2 of the present disclosure will be described. Figure 6 is a circuit diagram showing the configuration of the pad connection abnormality detection circuit 41 according to Embodiment 2 of the present disclosure.
[0035] The pad connection abnormality detection circuit 41 is provided on the LSI 200 and is a circuit that detects connection abnormalities in the connection between the pad PD and the external terminal ET via a bonding wire. Unlike in Embodiment 1, in this embodiment, a signal whose signal level changes from logic level 1 (H level) to logic level 0 (L level) is input as the input signal IS.
[0036] The pad connection abnormality detection circuit 41 includes a rising edge detection circuit 42 and a determination circuit 43. The rising edge detection circuit 42 consists of a reset unit 51, a latch unit 52, and a one-shot pulse generation unit 53.
[0037] The reset section 51 consists of a transistor PM3, which is a P-channel MOSFET. The source of transistor PM3 is supplied to the power supply voltage VDD on the voltage supply line. Transistor PM3 receives a power-on reset signal POR at its gate and turns on or off accordingly. The drain of transistor PM3 is connected to input node n2, which receives a signal input from pad PD. When a low-level power-on reset signal POR is supplied to the gate of transistor PM3, transistor PM3 turns on, and the potential of input node n2 is reset.
[0038] The input node n2 is located on a connection line that connects the pad PD and the one-shot pulse generation unit 53 via a latch unit 52. The reset unit 51 has the function of fixing the voltage logic of the connection line by resetting the potential of the input node n2.
[0039] The latch section 52 consists of a loop-connected inverter IVE and IVF. The inverter IVE has its input terminal connected to input node n2 and outputs a signal from its output terminal that is the inverted version of the input signal IS input from input node n2. The inverter IVF has its input terminal connected to the output terminal of the inverter IVE and its output terminal connected to the input terminal of the inverter IVE.
[0040] The one-shot pulse generation unit 53 has the same configuration as the one-shot pulse generation unit 23 of Embodiment 1. The output signal of the latch unit 52, i.e., the inverted signal of the input signal IS, is input to the first input terminal of the NOR gate NR1. In addition, the voltage signal obtained by inverting the output signal of the latch unit 52 by odd-numbered inverters IV1 to IVn is input to the second input terminal of the NOR gate NR1. As a result, when a signal whose signal level changes from logic level 1 to logic level 0 is input to the LSI 200 as the input signal IS, a one-shot pulse edge detection signal DTP is generated and output from the output terminal of the NOR gate NR1.
[0041] The determination circuit 13 receives the edge detection signal DTP output from the one-shot pulse generation unit 53 and outputs a determination signal DTS corresponding to the signal level. The determination circuit 13 has a signal level of logic level 0 when there is no input of a one-shot pulse edge detection signal DTP, and outputs a determination signal DTS in which the signal level changes from logic level 0 to logic level 1 when a one-shot pulse edge detection signal DTP is input. The determination circuit 13 has the same configuration as in Embodiment 1.
[0042] Next, the operation of the pad connection abnormality detection circuit 41 in this embodiment will be explained with reference to the time chart in Figure 7.
[0043] When the LSI200 is powered on, the edge detection signal DTP and the judgment signal DTS are initialized accordingly, and at timing T1 shown in the figure, the edge detection signal DTP and the judgment signal DTS are output at logic level 0 (i.e., L level).
[0044] If no pad connection abnormality occurs, when the external input signal IS transitions from logic level 1 (high level) to logic level 0 (low level), the rising edge detection circuit 42 outputs a one-shot pulse edge detection signal DTP accordingly. Based on the edge detection signal DTP, the determination circuit 13 outputs a determination signal DTS at timing T2 shown in the figure, in which the signal level changes from logic level 0 (low level) to logic level 1 (high level).
[0045] If a pad connection abnormality occurs, the input signal IS is not input to the rising edge detection circuit 12, and the edge detection signal DTP, which is the output of the rising edge detection circuit 42, is fixed at logic level 0 (L level). As a result, the judgment signal DTS, which is the output of the judgment circuit 13, is also fixed at logic level 0 (L level).
[0046] As described above, the pad connection anomaly detection circuit 41 of this embodiment receives an input signal IS whose signal level transitions from logic level 1 to logic level 0, and outputs a determination signal DTS whose signal level changes accordingly. When no pad connection anomaly has occurred, the signal level of the determination signal DTS changes in accordance with the change in the signal level of the input signal IS, while when a pad connection anomaly has occurred, the signal level of the determination signal DTS remains fixed regardless of the change in the signal level of the input signal IS. This makes it possible to detect the occurrence of a pad connection anomaly based on the signal level of the determination signal DTS.
[0047] Similar to the pad connection anomaly detection circuit 11 in Example 1, the pad connection anomaly detection circuit 41 in this embodiment can determine the logic of the line connected to the pad PD after power is turned on, even when an open fault occurs in the pad PD, thus enabling reliable detection of the open fault as a pad connection anomaly.
[0048] This disclosure is not limited to the embodiments described above. For example, in the embodiments described above, the case in which the reset unit 22 (or 51) receives a power-on reset signal POR from the control unit 14 and fixes the potential of the output node n1 (or input node n2) was described. However, it may also be configured to fix the potential of the node by receiving a reset signal other than the power-on reset signal POR. For example, by supplying a reset signal to the reset unit 22 at any timing other than immediately after power-on and fixing the potential of the node, it becomes possible to detect a connection abnormality of the pad PD at a desired timing.
[0049] Furthermore, although the above embodiments described the case in which the reset units 22 and 51 are composed of P-channel type MOSFETs, the configuration of the reset units 22 and 51 is not limited to this, and it is sufficient if they are configured to fix the potential (logic level) of the node connected to the pad PD in response to a reset signal such as a power-on reset signal POR.
[0050] Furthermore, the configuration of the determination circuit 13 is not limited to those shown in the above embodiments. It is sufficient that it is configured to receive a one-shot pulse edge detection signal DTP and output a determination signal DTS in which the signal level changes from logic level 0 to logic level 1, or from logic level 1 to logic level 0.
[0051] (Note) This specification discloses the following configuration:
[0052] (Composition 1) A pad connection abnormality detection circuit comprising: a latch circuit connected to a pad that receives an input signal via an external terminal and takes in the input signal; a detection signal generation circuit connected to the output of the latch circuit and generates a one-shot pulse detection signal when the signal level of the signal input to itself changes between logic level 0 and logic level 1; a reset signal supply unit that supplies a reset signal to fix the voltage of the connection line connecting the pad and the detection signal generation circuit to one of the logic levels; and a determination circuit that receives the detection signal and outputs a determination signal in response to the detection of the one-shot pulse.
[0053] (Configuration 2) The pad connection abnormality detection circuit according to Configuration 1 includes a transistor, one end of which is connected to a power supply voltage line and the other end of which is connected to the connection line, and the control end of which receives the reset signal.
[0054] (Composition 3) The pad connection abnormality detection circuit according to configuration 1 or 2, which includes a first input terminal connected to the connection line and a second input terminal connected to the connection line via an odd number of inverters, and an OR gate that outputs the detection signal from its output terminal.
[0055] (Composition 4) The determination circuit is a pad connection abnormality detection circuit according to any one of configurations 1 to 3, comprising: a switching element having one end connected to a reference potential and a control end that turns on and off in response to the detection signal; a latch unit connected to the other end of the switching element and receiving the signal output to the other end; and a reset unit that receives the reset signal and fixes the voltage of the node connecting the other end of the switching element and the latch unit to one of the logic levels.
[0056] (Composition 5) The determination circuit is a pad connection abnormality detection circuit according to any one of configurations 1 to 3, which includes an RS flip-flop circuit whose set terminal is connected to the output terminal of the detection signal generation circuit and whose reset terminal is connected to a reference potential, and a transistor whose one end is connected to the output terminal of the RS flip-flop circuit and whose other end is connected to the reference potential, and whose control terminal receives a signal which is the inverted reset signal. [Explanation of symbols]
[0057] 100 LSI 11 Pad connection abnormality detection circuit 12. Rising edge detection circuit 13 Judgment circuit 21 Latch section 22 Reset section 23 One-shot pulse generation unit 31 switches 32 Initialization circuit 33 Latch section 34 RS Flip-Flop Circuit 41 Pad connection abnormality detection circuit 42 Rising edge detection circuit 51 Reset section 52 Latch section 53 One-shot pulse generation unit
Claims
1. A latch circuit connected to a pad that receives an input signal via an external terminal and which captures the said input signal, A detection signal generation circuit, connected to the output of the latch circuit, generates a one-shot pulse detection signal when the signal level of the signal input to itself changes between logic level 0 and logic level 1. A reset signal supply unit that supplies a reset signal to fix the voltage of the connection line connecting the pad and the detection signal generation circuit to one of the logic levels, A determination circuit that receives the detection signal and outputs a determination signal in response to the detection of the one-shot pulse, A pad connection abnormality detection circuit having the following features.
2. The pad connection abnormality detection circuit according to claim 1, wherein the reset signal supply unit includes a transistor having one end connected to a power supply voltage supply line and the other end connected to the connection line, and the control end receiving the applied reset signal.
3. The pad connection abnormality detection circuit according to claim 1, wherein the detection signal generation circuit has a first input terminal connected to the connection line and a second input terminal connected to the connection line via an odd number of inverters, and includes a negative OR circuit that outputs the detection signal from its output terminal.
4. The aforementioned determination circuit is One end is connected to a reference potential, and the control end is a switching element that turns on and off in response to the detection signal, A latch unit connected to the other end of the switching element, which captures the signal output to the other end, A reset unit that receives the reset signal and fixes the voltage of the node connecting the other end of the switching element and the latch unit to one of the logic levels, A pad connection abnormality detection circuit according to claim 1, having the following features.
5. The aforementioned determination circuit is An RS flip-flop circuit in which the set terminal is connected to the output terminal of the detection signal generation circuit and the reset terminal is connected to a reference potential, A transistor is connected at one end to the output terminal of the RS flip-flop circuit and at the other end to the reference potential, and receives a signal obtained by inverting the reset signal at its control terminal. A pad connection abnormality detection circuit according to claim 1, including the above.