Data processing method, device, electronic device and storage medium

Abstract

[0009] Embodiments of the present disclosure provide a data processing method, an apparatus, an electronic device, and a storage medium. The data processing method includes the steps of: in response to receiving a write request for a first cache to write first data back to its internal memory, a cache coherency node either writing the first data to its internal memory or discarding the first data, where the write request carries the first data, the cache coherency node is configured to maintain consistency of data stored in multiple caches, the multiple caches including the first cache; and after the cache coherency node writes the first data to its internal memory or discards the first data, the cache coherency node returns a write response signal to the first cache to directly terminate the processing operation for the write request. This method reduces the number of ACK messages, reduces protocol requirements for ACK messages, and can reduce power consumption, delay, and bandwidth occupation due to the transmission of ACK messages. Furthermore, the buffer turnover rate on the master device is optimized, so that for the same performance, fewer buffers are required on the master device side, saving area and power consumption.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from Chinese Patent Application No. 202311598492.4, filed on November 27, 2023, the entire contents of which are incorporated herein by reference.

[0002] SUMMARY OF THE INVENTION The embodiments of the present disclosure relate to a data processing method, a data processing device, an electronic device, and a storage medium. [Background technology]

[0003] A Network-on-a-Chip (NOC) system is a necessary bus system for realizing intercommunication among components in a large-scale integrated circuit. A System-on-a-Chip (SOC) may include multiple types of subsystems, such as a CPU, a GPU, internal memory, and IO devices, and each type of subsystem may have multiple entities (data signals and control signals) that need to communicate with each other to work together.

[0004] In a SOC system, frequent read and write interactions are required between multiple subsystem entities. To ensure high performance data exchange between each subsystem, a NOC system provides a high-bandwidth transaction switching network to connect various on-chip components. Through this network, data can be efficiently transmitted between each subsystem. When caches corresponding to different subsystems operate on data cached at the same address, a consistency issue may occur. To solve this problem, many techniques for maintaining data consistency have emerged. Summary of the Invention [Means for solving the problem]

[0005] At least one embodiment of the present disclosure provides a data processing method, comprising: in response to receiving a write request for a first cache to write first data back to an internal memory, a cache coherency node either writing the first data to an internal memory or discarding the first data, wherein the write request carries the first data, the cache coherency node is configured to maintain consistency of data stored in multiple caches, and the multiple caches include the first cache; and after the cache coherency node writes the first data to its internal memory or discards the first data, the cache coherency node returns a write response signal to the first cache to directly terminate a processing operation for the write request.

[0006] For example, in a data processing method provided by at least one embodiment of the present disclosure, the step of a cache consistency node writing the first data to its internal memory or discarding the first data in response to receiving a write request for a first cache to write the first data back to its internal memory includes the step of the cache consistency node determining, in response to receiving the write request for the first cache to write the first data back to its internal memory, whether the first cache is the same as the cache that currently occupies the first data as recorded on the cache consistency node side, and the step of the cache consistency node writing the first data to its internal memory in response to determining that the first cache is the same as the cache that currently occupies the first data as recorded on the cache consistency node side.

[0007] For example, in a data processing method provided by at least one embodiment of the present disclosure, the step of the cache coherence node returning a write response signal to the first cache to directly terminate the processing operation for the write request after the cache coherence node writes the first data to an internal memory or discards the first data includes the step of the internal memory returning a write response to the cache coherence node indicating that the first data has been written to the internal memory after the cache coherence node writes the first data to the internal memory, and the step of the cache coherence node returning the write response signal to the first cache indicating that the first data has been written back to the internal memory in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, to directly terminate the processing operation for the write request.

[0008] For example, in a data processing method provided by at least one embodiment of the present disclosure, the data processing method further includes a step in which, after the cache coherency node writes the first data to the internal memory, the cache coherency node sets the data state of the first cache to an invalid state, a shared state, or an exclusive state, where the invalid state indicates that the first cache does not cache the first data, the shared state indicates that both the first cache and another cache cache the first data, and the exclusive state indicates that the first data is cached only in the first cache.

[0009] For example, in a data processing method provided by at least one embodiment of the present disclosure, the data processing method further includes a step in which the cache coherence node issues a monitoring signal to the first cache in response to receiving a read request for the first data from a second cache and recording the first data in an exclusive or shared state in the first cache on the cache coherence node side, and a step in which the first cache returns a monitoring response carrying the first data to the cache coherence node in response to the monitoring signal in response to the first cache receiving the monitoring signal after issuing the write request.

[0010] For example, in a data processing method provided by at least one embodiment of the present disclosure, the data processing method further includes a step in which, in response to receiving the monitoring response, the cache coherency node returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that it has received the first data to the cache coherency node, thereby terminating the read request.

[0011] For example, in a data processing method provided by at least one embodiment of the present disclosure, the step of the cache coherence node returning the first data to the second cache in response to receiving the monitoring response includes the step of the cache coherence node returning the first data to the second cache in response to receiving the monitoring response, and setting the data state of the second cache to an exclusive state indicating that the first data is cached only in the second cache.

[0012] For example, in a data processing method provided by at least one embodiment of the present disclosure, the step of the cache coherence node writing the first data to an internal memory or discarding the first data, and then returning a write response signal to the first cache to directly terminate the processing operation for the write request, includes the step of the cache coherence node, after receiving the message, discarding the first data written to the cache coherence node side in accordance with the write request, and returning the write response signal to the first cache to directly terminate the processing operation for the write request.

[0013] For example, in a data processing method provided by at least one embodiment of the present disclosure, the step of the cache consistency node discarding the first data written to the cache consistency node side in response to the write request after receiving the message includes the step of the cache consistency node discarding the first data written to the cache consistency node side in response to the write request determining that the first data written to the cache consistency node side in response to the write request after receiving the message is invalid data.

[0014] At least one embodiment of the present disclosure further provides an electronic device including a plurality of caches and a cache coherence node, wherein the plurality of caches includes a first cache, and the cache coherence node is configured to, in response to receiving a write request for the first cache to write first data back to an internal memory, write the first data to an internal memory or discard the first data, and after the cache coherence node has written the first data to its internal memory or discarded the first data, return a write response signal to the first cache to directly terminate a processing operation for the write request, wherein the write request carries the first data, and the cache coherence node is configured to maintain the consistency of data stored in the plurality of caches.

[0015] For example, in an electronic device provided by at least one embodiment of the present disclosure, the cache consistency node is further configured to, in response to receiving the write request for the first cache to write the first data back to the internal memory, determine whether the first cache is the same as the cache currently occupying the first data as recorded on the cache consistency node side, and, in response to determining that the first cache is the same as the cache currently occupying the first data as recorded on the cache consistency node side, write the first data to the internal memory.

[0016] For example, in an electronic device provided by at least one embodiment of the present disclosure, the internal memory is configured to, after the cache coherence node writes the first data to the internal memory, return a write response to the cache coherence node indicating that the first data has been written to the internal memory, and the cache coherence node is further configured, in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, to return the write response signal to the first cache indicating that the first data has been written back to the internal memory, thereby directly completing the processing operation for the write request.

[0017] For example, in an electronic device provided by at least one embodiment of the present disclosure, the cache coherence node is further configured to issue a monitoring signal to the first cache in response to receiving a read request for the first data from the second cache and recording the first data in an exclusive or shared state in the first cache on the cache coherence node side, and the first cache is configured to return a monitoring response carrying the first data to the cache coherence node in response to the first cache receiving the monitoring signal after issuing the write request.

[0018] At least one embodiment of the present disclosure further provides a data processing device including a memory and a processor, wherein the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions, such that, when executed by the processor, a method according to any of the above embodiments is realized.

[0019] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitoryly stores computer-executable instructions, which, when executed by a processor, realize a method according to any of the above embodiments.

[0020] In order to clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. It should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 shows a schematic diagram of an electronic device. [Figure 2A] FIG. 2A shows a schematic diagram of the electronics that reads the data. [Figure 2B] FIG. 2B shows a schematic diagram of an electronic device that writes back data. [Figure 3A] FIG. 3A shows a schematic flow chart of a data processing method provided by at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B illustrates a schematic diagram of an electronic device for writing back data provided by at least one embodiment of the present disclosure. [Figure 4] FIG. 4 shows a schematic diagram of the read / write operation of an electronic device provided by at least one embodiment of the present disclosure when the read / write is in a collision. [Figure 5] FIG. 5 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. [Figure 6]FIG. 6 shows a schematic diagram of a data processing device provided by at least one embodiment of the present disclosure. [Figure 7] FIG. 7 illustrates a schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0022] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present disclosure, the following clearly and completely describes the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure, and it is obvious that the described embodiments are not all embodiments but only some embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments that can be obtained by those skilled in the art without any creative work fall within the protection scope of the present disclosure.

[0023] Unless otherwise defined, technical or scientific terms used in this disclosure have ordinary meanings that can be understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote order, quantity, or importance, but merely distinguish between different components. Similar terms such as "comprise" or "include" mean that the elements or components listed before "comprise" or "include" cover the elements or components listed after "comprise" or "include" and their equivalents, and do not exclude other elements or components. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," "right," and the like are used solely to indicate relative positional relationships, and if the absolute position of the objects being described changes, the relative positional relationships may change correspondingly.

[0024] To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some well-known functions and components.

[0025] During the operation of a computer system including multiple processors (or processor cores) and multiple cache memories, data at the same address may exist in different caches at the same time. To maintain consistency of data at the same address in each cache, a directory-based consistency protocol has been created. The protocol can track the state of data in the cache memories; for example, a directory storage structure can be implemented using static random access memory (SRAM) similar to the cache memories. For example, the directory storage structure may be implemented using other forms of memory as long as it can implement directory storage.

[0026] Fig. 1 is a schematic diagram of an electronic device (or electronic system) 100. As shown in Fig. 1, the electronic device 100 may include a plurality of cache memories (also abbreviated as "caches") 1-n, processors (or processor cores) 1-n, the Internet, cache coherency nodes 1-n, internal memories 1-n, and directories 1-n.

[0027] For example, each of caches 1 to n is configured to store data storage information corresponding to at least one piece of data information.For example, caches 1 to n may each include one or more sub-caches.

[0028] For example, cache coherency nodes 1-n can help track the state of cached data in cache memories 1-n, respectively, where the state of cached data includes, for example, whether there is only one copy of the cached data in cache 1-n, whether there are multiple copies of the cached data, or whether the data exists only in main memory. Cache coherency nodes 1-n track the state of cache memories 1-n of processors 1-n (e.g., each processor in FIG. 1 may include one or more sub-processors) and store the tracked state information (or directory information) in directories 1-n. When a cache coherency node finds a coherency transaction in the process of monitoring the bus, it queries the tracked state information in directories 1-n and issues a corresponding probe to complete coherency maintenance.

[0029] For example, directories 1-n are configured to store corresponding directory information of data information stored in caches 1-n to maintain cache consistency. For example, a directory includes multiple storage groups, and each storage group can store multiple pieces of directory information. For example, when directory information needs to be stored in a directory, the directory arranges the directory information in the corresponding storage group based on a mapping relationship.

[0030] For example, as shown in Figure 1, the Internet in a system (e.g., a network on chip (NOC)) is directly connected to caches 1-n, which are in turn directly connected to cache coherency nodes 1-n. The Internet is a public communications trunk for transmitting information; for example, the Internet may be a transmission harness made up of electrical components such as wires.

[0031] For example, as shown in FIG. 1, cache coherency nodes 1-n are configured to connect each of directories 1-n to the Internet, and cache coherency nodes 1-n are configured to connect each of internal memories 1-n to the Internet so as to maintain the coherency of all data stored in caches 1-n.

[0032] For example, in a Non-Uniform Memory Access (NUMA) architecture, different combinations of processors (or processor cores) and internal memory devices belong to different nodes, so a directory consistency-based design establishes a directory of static random access memory (SRAM) structures near each internal memory controller. In a NUMA architecture, each node has its own local memory.

[0033] Figure 2A shows a schematic diagram of the electronics that reads the data, and Figure 2B shows a schematic diagram of the electronics that writes the data back.

[0034] For example, in Figure 2A, master device 0 may correspond to any of caches 1-n in Figure 1, slave devices may correspond to any of cache coherence nodes 1-n in Figure 1, and MEM may correspond to any of internal memories 1-n in Figure 1. For example, as shown in Figure 2A, when master device 0 issues an exclusive request RdE (see Table 2 below) to a slave device to obtain exclusive data, since there may be multiple master devices in a system (e.g., an electronic system), the slave device needs to manage data coherency among the multiple master devices. For example, a slave device in the system may use a directory-based cache coherency protocol and record in a directory which master device is caching data and the current state of the data in the corresponding master device.

[0035] For example, as shown in FIG. 2A, when a slave device receives an exclusive request RdE and the corresponding directory on the current slave device side is in an invalid state I, represented by Dir@I in FIG. 2A (see Table 1 below, for example, invalid state I indicates that no master device currently caches this data (e.g., data corresponding to the address requested to be accessed)), the slave device sends a read request Rdmem to its internal memory and receives a data response rddat returned from its internal memory to the slave device, thereby directly reading the data from its main memory (e.g., its internal memory), and returns an exclusive data response DatRspE (see Table 5 below) to the requesting master device 0, setting the corresponding directory on the slave device side to E:Master0 (e.g., represented by Dir@E:Master0 in FIG. 2A), thereby recording that master device 0 has cached this data and is in an exclusive state (E:Exclusive). After receiving the exclusive data response DatRspE, master device 0 sends an ACK message to the slave device to complete the read request.

[0036] A master device generally caches a large amount of data, and overflow scenarios exist in the master device, requiring the overflowed data to be written back from the master device to the slave device. For example, as shown in FIG. 2B, when the cached data in master device 0 overflows, master device 0 issues a write-back request to the slave device (although FIG. 2B illustrates only WBI as an example, this is not limited to this write-back request), and transmits data to be written back to its internal memory, for example, via a signal WrDat, to the slave device. After the slave device confirms receipt of the write-back data, it returns a write response WrRap to master device 0. After receiving the write response WrRap, master device 0 sends a message (or write response) ACK to the slave device. For example, as shown in FIG. 2B, after the slave device receives the message ACK sent from master device 0, the directory status corresponding to the slave device is changed from Dir@E:Master0 to Dir@I. For example, after receiving the message ACK, the slave device sends a write request Rdmem to the internal memory, thereby writing the data to be written back to the internal memory, and then receives a data write response WrRap returned from the internal memory to the slave device, thereby completing the write back request.

[0037] In existing cache coherency protocols, both read and write transactions need to carry an ACK message, which extends the lifecycle of the transaction in the slave device, i.e., occupies the slave device's buffer (e.g., a cache or other storage area that can be used to implement a directory) for a longer period of time, reduces the turnover rate of the slave device's buffer, wastes resources, and requires the transmission of the ACK message to consume a certain amount of power.

[0038] At least one embodiment of the present disclosure provides a data processing method, for example, the data processing method provided by the present disclosure includes the steps of: in response to receiving a write request for a first cache to write first data back to an internal memory, a cache coherency node writing the first data to an internal memory or discarding the first data, the write request carrying the first data, the cache coherency node being configured to maintain consistency of data stored in multiple caches, the multiple caches including the first cache; and after the cache coherency node writes the first data to the internal memory or discards the first data, the cache coherency node returning a write response signal to the first cache to directly terminate a processing operation for the write request.

[0039] In the data processing method of the above embodiment of the present disclosure, the scenario is identified by comparing the write-back transaction with the directory, and the master device directly ends the write transaction processing after receiving the write response, eliminating the need to send an ACK message to the slave device. This reduces the number of ACK messages, reduces the protocol demand for ACK messages, and reduces the power consumption, delay, and bandwidth occupation caused by the transmission of ACK messages. In addition, the buffer rotation rate on the master device side is optimized, and with the same performance, fewer buffers are required on the master device side, saving area and power consumption.

[0040] At least some embodiments of the present disclosure further provide an electronic device including a plurality of caches and a cache coherence node, wherein the plurality of caches includes a first cache, wherein the cache coherence node is configured to, in response to receiving a write request for the first cache to write the first data back to its internal memory, either write the first data to its internal memory or discard the first data, and after the cache coherence node has written the first data to its internal memory or discarded the first data, return a write response signal to the first cache to directly terminate a processing operation for the write request, wherein the write request carries the first data, and wherein the cache coherence node is configured to maintain consistency of data stored in the plurality of caches.

[0041] The technical effects of the electronic device according to the above-described embodiments of the present disclosure are the same as the technical effects of the data processing method described above, and therefore detailed description thereof will be omitted.

[0042] In the above embodiments, the first cache may be any one of multiple caches, and the first data may be, for example, data corresponding to any accessed address; i.e., "first" (and "second," etc.) here is merely used to identify a cache or data as a descriptive object, and does not specifically refer to a particular cache or data.

[0043] Hereinafter, each embodiment of the present disclosure will be described with specific examples.

[0044] 3A shows a schematic flowchart of a data processing method provided by at least one embodiment of the present disclosure. As shown in FIG. 3A, in some embodiments of the present disclosure, the data processing method includes the following steps S101 to S102.

[0045] Step S101, in response to receiving a write request for a first cache to write first data back to an internal memory, a cache coherency node writes the first data to the internal memory or discards the first data, the write request carries the first data, and the cache coherency node is configured to maintain consistency of data stored in multiple caches, the multiple caches including the first cache.

[0046] Step S102: After the cache coherence node writes the first data to its internal memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly terminate the processing operation for the write request.

[0047] 3B illustrates a schematic diagram of an electronic device for writing back data, provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 3B, in response to receiving a write request for a first cache (or "master device 0") to write first data back to its internal memory, a cache coherence node (or "slave device") writes the first data to its internal memory MEM. For example, the write request carries the first data, and the cache coherence node is configured to maintain the coherency of data stored in multiple caches, the multiple caches including the first cache. For example, after the cache coherence node writes the first data to its internal memory MEM, the cache coherence node returns a write response signal WrRsp to the first cache to directly complete the processing operation for the write request.

[0048] 4 illustrates a schematic diagram of a read / write operation of an electronic device provided by at least one embodiment of the present disclosure when a read / write conflict occurs. For example, as shown in FIG. 4, in response to receiving a write request in which a first cache (or "master device 0") writes first data back to its internal memory, a cache coherence node (or "slave device") discards the first data. For example, the write request carries the first data, and the cache coherence node is configured to maintain the consistency of data stored in multiple caches, including the first cache. For example, after the cache coherence node discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly terminate the processing operation for the write request.

[0049] In the present disclosure, for example, Figures 3B and 4 show a specific first cache (e.g., master device 0), a second cache (e.g., master device 1), a cache coherency node (e.g., slave device), an internal memory (e.g., MEM), and specific operations related thereto, but the contents shown in the figures are merely illustrative to facilitate explanation of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto, and all other operations conceivable based on the specific examples of the present disclosure are included within the scope of the present disclosure.

[0050] Below, some provisions of the cache coherence protocol of the embodiment of the present disclosure are exemplarily explained in conjunction with Tables 1-9.

[0051] For example, a master device (or cache) defined in the protocol of the embodiment of the present disclosure has multiple states as shown in Table 1.

[0052] [Table 1]

[0053] For example, in Table 1, the cache state may be the state of the first cache, and the main memory may be the internal memory MEM. For example, the first cache may include an M state, an E state, an S state, and an I state. The M state indicates that the first cache exclusively owns the corresponding data and that the data has been modified; the E state indicates that the first cache exclusively owns the corresponding data and that the data has not been modified; the S state indicates that the first cache shares the corresponding data with other master devices; and the I state indicates that the first cache does not cache the corresponding data. For example, when the first cache is in the M state, the first cache has modified the corresponding data, making the corresponding data in the internal memory MEM invalid. At this time, all other caches are in the I state, in which they do not cache the modified data; when the first cache is in the E state, all other caches are in the I state, in which they do not cache the data; when the first cache is in the S state, the other caches are in the S state, in which they share the data; and when the first cache is in the I state, the other caches can be in any of the M state, the E state, the S state, and the I state.

[0054] It should be noted that in the embodiment of the present disclosure, the state of the master device (e.g., the first cache) is not limited to the four states described above, and the master device may have other different states according to various needs.

[0055] For example, Table 2 shows possible request types issued by a master device, corresponding cache state changes, and response messages of slave devices as defined in the protocol of this disclosure.

[0056] [Table 2]

[0057] The following description will be given taking as an example a case where the master device is the first cache.

[0058] For example, in Table 2, the request type may be a request type issued by the first cache to the slave device. For example, possible read request types issued by the first cache may include RdE (to obtain a copy of exclusive data), RdD (to obtain a copy of data in a non-I state, i.e., a copy of this data needs to be cached), RdS (to obtain a copy of shared data), RdI (to obtain a snapshot of the data and not cache a copy of this data), and RdEE (to obtain exclusive rights to the data without obtaining the data). Embodiments of the present disclosure are not limited thereto, and the first cache may issue various other read request types as needed.

[0059] For example, if the read request type issued by the first cache to the slave device is RdE, the cache state (or cached data state) when the first cache issues the request may be I state, S state, or E state, and when the RdE request is completed, the cache state of the first cache may be E state (in this case, the slave device returns a response DatRspE (see Table 6 below) to the first cache, causing the slave device to obtain a response copy of the data in an exclusive state) or M state (in this case, the slave device returns a response DatRspM (see Table 6 below), causing the slave device to obtain a response copy of the data in a modified state). For example, if the read request type issued by the first cache to the slave device is RdD, the cache state of the first cache may be I state when it issues the request, and when the RdD request is completed, the cache state of the first cache may be S state (in this case, the slave device returns a response DatRspS (see Table 6 below) to the first cache, causing the slave device to obtain a response copy of the data in the shared state), E state (in this case, the slave device returns a response DatRspE to the first cache), or M state (in this case, the slave device returns a response DatRspM to the first cache). For example, if the read request type issued by the first cache to the slave device is RdS, the cache state of the first cache may be I state when it issues the request, and when the RdS request is completed, the cache state of the first cache may be S state (in this case, the slave device returns a response DatRspS to the first cache). For example, if the read request type issued by the first cache to the slave device is RdI, the cache state when the first cache issues the request may be I state, and when the RdI request ends, the cache state of the first cache may be I state (in this case, the slave device returns a response DatRspI (see Table 6 below) to the first cache, causing the slave device to obtain a response of a copy of the data).For example, if the read request type issued by the first cache to the slave device is RdEE, the cache state when the first cache issues the request may be I state or S state, and when the RdEE request ends, the cache state of the first cache may be E state (in this case, the slave device may return a response RspE (see Table 6 below) to cause the slave device to obtain an exclusive rights response).

[0060] For example, in Table 2, possible write request types issued by the first cache may include WBI (write a copy of the cached data back to main memory and set the cache to an invalid I state), WBS (write a copy of the cached data back to main memory and set the cache to a shared S state), and WBE (write a copy of the cached data back to main memory and set the cache to an exclusive E state). Embodiments of the present disclosure are not limited thereto, and the first cache may issue various other write request types as needed.

[0061] For example, if the write request type issued by the first cache to the slave device is WBI, the cache state when the first cache issues the request may be M state, and when the write request WBI is completed, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache). For example, if the write request type issued by the first cache to the slave device is WBS, the cache state when the first cache issues the request may be M state, and when the write request WBS is completed, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache) or S state (in this case, the slave device returns a response WrRsp to the first cache). For example, if the write request type issued by the first cache to the slave device is WBE, the cache state when the first cache issues the request may be M state, and when the write request WBE is completed, the cache state of the first cache may be I state (in this case, the slave device returns a response WrRsp to the first cache), S state (in this case, the slave device returns a response WrRsp to the first cache), or E state (in this case, the slave device returns a response WrRsp to the first cache).

[0062] 3B and 4, the first cache write request is not limited to WBI, and the write request may be WBS or WBE shown in Table 2. For example, when the cached data of the first cache overflows, the first cache can issue a write request WBI to the slave device, and in response to receiving the write request WBI, in which the first cache writes the first data back to the internal memory MEM, the cache coherence node writes the first data to the internal memory MEM (see FIG. 3B) or discards the first data (see FIG. 4). For example, after the cache coherence node writes the first data to the internal memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly terminate the processing operation for the write request. For example, when the cached data of the first cache overflows, the first cache can issue a write request WBS to the slave device, and in response to receiving the write request WBS, in which the first cache writes the first data back to the internal memory MEM, the cache coherence node writes the first data to the internal memory MEM (see FIG. 3B) or discards the first data (see FIG. 4). For example, after the cache coherence node writes the first data to the internal memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly terminate the processing operation for the write request. For example, when the cached data of the first cache overflows, the first cache can issue a write request WBE to the slave device, and in response to receiving the write request WBE, in which the first cache writes the first data back to the internal memory MEM, the cache coherence node writes the first data to the internal memory MEM (see FIG. 3B) or discards the first data (see FIG. 4). For example, after the cache coherence node writes the first data to the internal memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly terminate the processing operation for the write request.

[0063] For example, in response to receiving a write request for a first cache to write first data back to internal memory MEM, the cache consistency node determines whether the first cache is the same as the cache currently occupying the first data as recorded on the cache consistency node side, and in response to determining that the first cache is the same as the cache currently occupying the first data as recorded on the cache consistency node side, the cache consistency node writes the first data to internal memory MEM.

[0064] 3B, in response to receiving a write request from master device 0 to write the first data back to the internal memory MEM, the slave device determines whether the cache currently recorded on the slave device side and exclusively holding the first data is the same as the cache currently recorded on the slave device side and exclusively holding the first data. For example, as shown in FIG. 3B, in response to determining that the cache currently recorded on the slave device side and exclusively holding the first data is the same as the cache recorded on the slave device side and exclusively holding the first data (e.g., Src:Master0==Dir@E:Master0 is recorded on the slave device side), the slave device writes the first data back to the internal memory MEM using an internal memory write operation Wrmem, and after receiving the internal memory write operation Wrmem, the internal memory MEM returns a write response WrRsp to the cache coherency node to indicate to the slave device that the internal memory MEM has successfully received the first data. For example, in response to master device 0 determining that the cache currently holding the first data recorded on the slave device side is not the same as the cache holding the first data (for example, Src:Master0!=Dir@E:Master0 is recorded on the slave device side), the slave device determines that it does not have the authority to write the first data to its internal memory MEM, and does not perform the operation of writing the first data to its internal memory MEM.

[0065] For example, after the cache coherence node writes the first data to the internal memory, the internal memory returns a write response to the cache coherence node indicating that the first data has been written to the internal memory, and in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, the cache coherence node returns a write response signal to the first cache indicating that the first data has been written back to the internal memory, and directly terminates the processing operation for the write request.

[0066] 3B, after the slave device writes the first data to the internal memory MEM, the internal memory MEM returns a write response signal WrRsp to the slave device indicating that the first data has been written to the internal memory MEM, and in response to receiving the write response signal WrRsp from the internal memory MEM indicating that the first data has been written to the internal memory MEM, the slave device returns a write response signal WrRsp to the master device 0 indicating that the first data has been written back to the internal memory MEM, thereby directly terminating the processing operation for the write request. For example, at this time, the master device 0 does not need to send a message to the slave device and directly terminates the processing operation for the write request.

[0067] For example, after the cache coherency node writes the first data to its internal memory, the cache coherency node sets the data state of the first cache to an invalid state, a shared state, or an exclusive state, where the invalid state indicates that the first cache does not cache the first data, the shared state indicates that both the first cache and the other caches cache the first data, and the exclusive state indicates that only the first cache caches the first data.

[0068] For example, after the slave device writes the first data back to the internal memory MEM, the slave device sets the data state of a first cache (e.g., master device 0) among the multiple caches to an invalid state (I state), a shared state (S state), or an exclusive state (e.g., E state). For example, the invalid state indicates that the first cache does not cache the first data, the shared state indicates that both the first cache and the other caches cache the first data, and the exclusive state indicates that the first data is cached only in the first cache.

[0069] For example, as shown in Table 2 above, if the first cache issues a write request WBI to the slave device, when the write request WBI is completed, the cache state of the first cache may be state I. For example, if the first cache issues a write request WBS to the slave device, when the write request WBS is completed, the cache state of the first cache may be state I (e.g., after the first cache writes data back to the internal memory MEM, the data cached in the first cache is replaced with other data) or state S (e.g., after the first cache writes data back to the internal memory MEM, the data cached in the first cache is not replaced with other data). For example, when a first cache issues a write request WBE to a slave device, when the write request WBE is completed, the cache state of the first cache may be an I state (e.g., after the first cache writes the data back to the internal memory MEM, the data cached in the first cache is replaced with other data), an S state (e.g., the data written back to the internal memory MEM by the first cache is shared by other caches), or an E state (e.g., the data written back to the internal memory MEM by the first cache is not shared by other caches, and after the first cache writes the data back to the internal memory MEM, the data cached in the first cache is not replaced with other data).

[0070] For example, as shown in FIG. 4, in response to receiving a read request for the first data from the second cache (or "master device 1") and recording the first data in an exclusive or shared state in the first cache (or "master device 0") in the cache coherence node side (e.g., a directory corresponding to a slave device), the cache coherence node issues a monitoring signal (e.g., ExpRspIDat) to the first cache, and in response to the first cache receiving the monitoring signal after issuing a write request, the first cache returns a monitoring response (e.g., ExpRspIDat) carrying the first data to the cache coherence node in response to the monitoring signal.

[0071] For example, Table 3 shows the types and descriptions of monitoring signals specified in the protocol of the present disclosure, and the detection signal Exp* is used to monitor the cache status and data in the master device and set the monitored master device to the corresponding state.

[0072] [Table 3]

[0073] Table 4 shows the types of supervisory responses defined in the protocol of the present disclosure, that is, supervisory responses that the master device may return to the slave device when monitored by the detection signal Exp*.

[0074] [Table 4]

[0075] Table 5 lists the types and descriptions of non-monitoring response transactions defined in the protocol of this disclosure.

[0076] [Table 5]

[0077] Table 6 is a state transition table and monitoring response operations on the master device side for monitoring transactions specified in the protocol of this disclosure, which defines the target states to which the cache on the master device side can be converted after being monitored, and the transmission of corresponding monitoring response messages.

[0078] [Table 6]

[0079] For example, as shown in Table 6, after the first cache receives the detection signal ExpI, if the current cache state of the first cache is I, S, E, or M, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI (e.g., if the current state of the first cache is I) or ExpRspIDat (e.g., if the current state of the first cache is S, E, or M) to the cache coherence node.

[0080] For example, after the first cache receives the detection signal ExpS, if the current cache state of the first cache is I, the state of the first cache after monitoring signal processing is I, and the first cache returns a detection response ExpRspI to the cache coherence node; after the first cache receives the detection signal ExpS, if the current cache state of the first cache is S, the state of the first cache after monitoring signal processing is S, and the first cache returns a detection response ExpRspS to the cache coherence node; after the first cache receives the detection signal ExpS, if the current cache state of the first cache is E or M, the state of the first cache after monitoring signal processing is S, and the first cache returns a detection response ExpRspS (for example, if the first cache executes a write request WBS or WBE) or ExpRspSDat (for example, if the first cache executes a write request WBI) to the cache coherence node.

[0081] For example, after the first cache receives the detection signal ExpE, if the current cache state of the first cache is I, the state of the first cache after monitoring signal processing is I, and the first cache returns a detection response ExpRspI to the cache coherence node; after the first cache receives the detection signal ExpE, if the current cache state of the first cache is S, the state of the first cache after monitoring signal processing is S, and the first cache returns a detection response ExpRspS to the cache coherence node; after the first cache receives the detection signal ExpE, if the current cache state of the first cache is E or M, the state of the first cache after monitoring signal processing is E or M, and the first cache returns a detection response ExpRspE (for example, if the first cache executes a write request WBS or WBE) or ExpRspEDat (for example, if the first cache executes a write request WBI) to the cache coherence node.

[0082] Table 7 shows a situation where a monitoring transaction defined in the protocol of the present disclosure is processed on the master device side and a collision exists, i.e., when the monitoring transaction arrives at the master device, the master device is currently issuing a read transaction (or read request) Rd* or a write transaction (or write request) WB* for a cache line with the same address.

[0083] [Table 7]

[0084] For example, as shown in Table 7, if the detection signal sent from the cache coherency node to the first cache is ExpI, and the first cache is issuing a read transaction Rd* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is I, S, or E, the state of the first cache after monitoring signal processing is I, and the first cache returns a detection response ExpRspI (e.g., if the state of the master device is I) or ExpRspIDat (e.g., if the state of the first cache is S or E) to the cache coherency node; if the detection signal sent from the cache coherency node to the first cache is ExpI, and the first cache is issuing a write transaction WB* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is M, the first cache returns a detection response ExpRsplDat to the cache coherency node, and the state of the first cache after monitoring signal processing is I.

[0085] For example, as shown in Table 7, if the detection signal sent from the cache coherency node to the first cache is ExpS, and the first cache is issuing a read transaction Rd* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is I, S, or E, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI (e.g., if the state of the first cache is I) or ExpRspIDat (e.g., if the state of the first cache is S or E) to the cache coherency node; if the detection signal sent from the cache coherency node to the first cache is ExpS, and the first cache is issuing a read transaction WB* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is M, the first cache returns a detection response ExpRsplDat to the cache coherency node, and the state of the first cache after processing the monitoring signal ExpS is I.

[0086] For example, as shown in Table 7, if the detection signal sent from the cache coherency node to the first cache is ExpE, and the first cache is issuing a read transaction Rd* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is I, S, or E, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI (e.g., if the state of the first cache is I) or ExpRspIDat (e.g., if the state of the first cache is S or E) to the cache coherency node; if the detection signal sent from the cache coherency node to the first cache is ExpE, and the first cache is issuing a read transaction WB* for a cache line with the same address when the monitoring transaction arrives at the first cache, and if the current state of the first cache is M, the first cache returns a detection response ExpRsplDat to the cache coherency node, and the state of the first cache after processing the monitoring signal ExpE is I.

[0087] Table 8 shows the state transitions that a slave device defined in the protocol of this disclosure may need to perform based on the directory state after receiving a read / write request from a master device (including triggering a monitoring command, returning a response command to the master device, or performing a read / write operation on memory data).

[0088] [Table 8]

[0089] For example, as shown in Table 8, in response to receiving a read request RdE for the first data from the second cache and the first data being in the I state in the directory corresponding to the cache coherence node, the cache coherence node directly reads the first data from its internal memory and returns the first data to the second cache. For example, in response to receiving a read request RdE for the first data from the second cache and the cache coherence node side (e.g., the directory corresponding to the slave device) recording that the first data is in the S state or the exclusive state E in the directory corresponding to the cache coherence node, the cache coherence node issues a monitor signal ExpI to the first cache (monitor the target cache, obtain a copy of the latest data, and set the cached data to an invalid state).

[0090] For example, in response to receiving the monitoring response ExpRspIDat, the cache coherency node returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that it has received the first data to the cache coherency node, thereby terminating the read request. For example, as shown in Figure 4, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (e.g., via a response signal DatRspM), and sets the data status of the master device 1 on the slave device side to an exclusive state (e.g., Dir@E:Master1 is recorded on the slave device side), where the exclusive state (or Dir@E:Master1) indicates that the first data is cached only on the master device 1. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device, indicating that it has received the first data, thereby terminating the read request RdE.

[0091] For example, after receiving the message, the cache coherence node discards the first data written to the cache coherence node in response to the write request, and returns a write response signal to the first cache to directly complete the processing operation for the write request. For example, as shown in FIG. 4, after the slave device receives the message ACK from master device 1, the processing of the read request RdE issued earlier by the master device is completed, and the write request WB* issued earlier by master device 0 is woken up and continues to be processed, which is in a blocking state on the slave device side (the slave device is in a blocking state in the process of processing the read request issued by master device 1 (i.e., because the slave device can only process one transaction with the same address at a time, before the processing of RdE by master device 1 is completed), the write request WB* issued earlier by master device 0 is always in a blocking state)). In this case, the slave device records that master device 1 has acquired exclusive ownership of the first data, and because the write request was issued by master device 0, the data in the write transaction of master device 0 has already expired and become invalid. Therefore, the slave device determines that this write transaction or write operation is invalid due to a conflict (as shown in FIG. 4, Src:Master0!=Dir@E:Master1, i.e., master device 0 requesting the write back is not master device 1, which is the slave device pointing to and has exclusive ownership of the first data), and directly discards the data written by master device 0 to the slave device. For example, the slave device determines that the first data written to the slave device in response to the write request is invalid, discards the first data written to the slave device in response to the write request, and returns a write response signal WrRsp to master device 0 to directly terminate the processing of the write request. For example, after receiving the write response signal WrRsp, the slave device directly terminates the processing of the corresponding write transaction, eliminating the need to send an ACK message to the slave device.

[0092] For example, in response to receiving the second cache's read request for the first data as RdD, RdS, or RdI and the first data being in the I or S state in the directory corresponding to the cache coherence node, the cache coherence node can directly read the first data from its internal memory and return the first data to the second cache. For example, in response to receiving the second cache's read request for the first data as RdD, RdS, or RdI and the cache coherence node side (e.g., the directory corresponding to the slave device) recording that the first data is in the exclusive state E in the directory corresponding to the cache coherence node, the cache coherence node issues a monitor signal ExpS to the first cache (monitor the target cache, obtain the latest copy of the data, and set the cached data to an invalid or shared state).

[0093] For example, in response to receiving the monitoring response ExpRspIDat, the cache coherency node returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that it has received the first data to the cache coherency node, thereby terminating the read request. For example, as shown in Figure 4, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (e.g., via a response signal DatRspM), and sets the data status of the master device 1 on the slave device side to an exclusive state (e.g., Dir@E:Master1 is recorded on the slave device side), where the exclusive state (or Dir@E:Master1) indicates that the first data is cached only on the master device 1. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device, indicating that it has received the first data, thereby terminating the read request (e.g., RdD or RdS).

[0094] For example, after receiving the message, the cache coherency node discards the first data written to it in response to the write request, and returns a write response signal to the first cache to directly terminate the processing operation for the write request. For example, as shown in Figure 4, after a slave device receives a message ACK from master device 1, the processing of the read request RdD, RdS, or RdI issued earlier by master device 1 is completed, and the write request WB* issued earlier by master device 0, which is in a blocking state on the slave device side, is woken up and continues to be processed. At this time, the slave device records that master device 1 has acquired the exclusive or shared state for the first data, and because the write request was issued by master device 0, the data in the write transaction of master device 0 has already become outdated and invalid. Therefore, the slave device determines that this write transaction or write operation is invalid due to a collision, and directly discards the data written to the slave device by master device 0. For example, if the slave device determines that the first data written to it in response to the write request is invalid, the slave device discards the first data written to it in response to the write request and returns a write response signal WrRsp to the master device 0 to directly terminate the processing operation for the write request. For example, after receiving the write response signal WrRsp, the slave device directly terminates the processing of the corresponding write transaction, eliminating the need to send an ACK message.

[0095] For example, in response to receiving a read request for the first data from the second cache as RdEE and the first data being in the I state in the directory corresponding to the cache coherence node, the cache coherence node returns a response RspE (no data monitoring response, and the monitored cache is set to the E state or M state) to the second cache, thereby terminating the read request RdEE. For example, in response to receiving a read request RdEE for the first data from the second cache and the cache coherence node side (e.g., the directory corresponding to the slave device) recording that the first data is in the S state or the exclusive state E in the directory corresponding to the cache coherence node, the cache coherence node issues a monitoring signal ExpE to the first cache (monitor the target cache, obtain a copy of the latest data, and do not change the state of its cached data).

[0096] For example, in response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, and after receiving the first data, the second cache returns a message indicating that it has received the first data to the cache coherence node, thereby terminating the read request. For example, as shown in Figure 4, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (e.g., via the response signal DatRspM). For example, after receiving the first data, the master device 1 returns a message ACK to the slave device, indicating that it has received the first data, thereby terminating the read request RdEE.

[0097] For example, after receiving the message, the cache coherence node discards the first data written to it in response to the write request, and returns a write response signal to the first cache to directly terminate the processing operation for the write request. For example, as shown in Figure 4, after the slave device receives the message ACK from master device 1, the processing of the read request RdEE issued earlier by master device 1 is completed, and the write request WB* issued earlier by master device 0, which is in a blocking state on the slave device side, is woken up and continues to be processed. At this time, the slave device records that master device 0 no longer has exclusive possession of the first data, and because the write request was issued by master device 0, the data in the write transaction of master device 0 has become outdated and invalid data. Therefore, the slave device determines that this write transaction or write operation is invalid due to a collision, and directly discards the data written to the slave device by master device 0. For example, if the slave device determines that the first data written to it in response to the write request is invalid, the slave device discards the first data written to it in response to the write request and returns a write response signal WrRsp to the master device 0 to directly terminate the processing operation for the write request. For example, after receiving the write response signal WrRsp, the slave device directly terminates the processing of the corresponding write transaction, eliminating the need to send an ACK message.

[0098] For example, in response to receiving a write request (e.g., WBI, WBS, or WBE) for data sent by the second cache to the cache coherence node, regardless of the state (e.g., I, S, or E) of the directory at this time, the cache coherence node does not trigger a detection signal and returns a response WrRsp to the second cache. For example, at this time, if the cache coherence node records that the data that the second cache needs to write is in an exclusive state and points to the second cache that issues the write request WBI, it writes the data to its internal memory; otherwise, it discards the data.

[0099] Table 9 is a state transition table defined in the protocol of the present disclosure after a slave device receives a response from a master device.

[0100] [Table 9]

[0101] For example, as shown in Table 9, if a first cache sends a response signal ExpRspI, ExpRspS, or ExpRspE to a cache coherence node, and the cache coherence node receives any type of read request from a second cache (e.g., the cache coherence node creates a read request transaction processing entry and records the state associated with the current read request transaction in response to receiving a read request from the second cache), the cache coherence node needs to read the memory data after receiving the response signal ExpRspI, ExpRspS, or ExpRspE sent from the first cache to the cache coherence node. For example, after the cache coherence node reads the memory data, it sends the data to the second cache and sets the state of the read request transaction processing entry corresponding to the read request of the second cache to a waiting for confirmation state (e.g., WaitACK), and waits for the second cache to send an confirmation signal (ACK) confirming that the data has been successfully received.

[0102] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdI (e.g., in response to receiving the read request RdI from the second cache, the cache coherence node creates a read request transaction processing entry and records the state associated with the current read request transaction), after receiving the response signal ExpRspIDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data to the second cache, and sets the state of the read request transaction processing entry corresponding to the read request RdI of the second cache to a waiting for confirmation state (e.g., WaitACK), and waits for the second cache to send an confirmation signal (ACK) confirming that the data has been successfully received.

[0103] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdS (e.g., the cache coherence node creates a read request transaction processing entry and records the state associated with the current read request transaction in response to receiving the read request RdS from the second cache), after receiving the response signal ExpRspIDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data to the second cache, and sets the state of the read request transaction processing entry corresponding to the read request RdS of the second cache to a waiting for confirmation state (e.g., WaitACK), and waits for the second cache to send an confirmation signal (ACK) confirming that the data has been successfully received.

[0104] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdD (e.g., in response to receiving the read request RdD from the second cache, the cache coherence node creates a read request transaction processing entry to record the state associated with the current read request transaction), after receiving the response signal ExpRspIDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspE carrying data (recording that the second cache has exclusive possession of this data) or DatRspM (recording that the second cache has exclusive possession of the modified data) to the second cache, and sets the state of the read request transaction processing entry of the second cache corresponding to the read request RdD to a confirmation waiting state (e.g., WaitACK), and waits for the second cache to send an acknowledgement signal (ACK) confirming that the data has been successfully received.

[0105] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdE (e.g., in response to receiving the read request RdE from the second cache, the cache coherence node creates a read request transaction processing entry to record the state associated with the current read request transaction), after receiving the response signal ExpRspIDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspE (recording that the second cache has exclusive possession of this data) or DatRspM (recording that the second cache has exclusive possession of the modified data) carrying data to the second cache, and sets the state of the read request transaction processing entry corresponding to the read request RdE of the second cache to a confirmation waiting state (e.g., WaitACK), and waits for the second cache to send an acknowledgement signal (ACK) confirming that the data has been successfully received.

[0106] For example, as shown in Table 9, if a first cache sends a response signal ExpRspSDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdS or RdD (e.g., the cache coherence node creates a read request transaction processing entry to record the state associated with the current read request transaction in response to receiving the read request RdS or RdD from the second cache), after receiving the response signal ExpRspSDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data (recording that the second cache shares this data) to the second cache, and sets the state of the read request transaction processing entry corresponding to the read request RdS or RdD of the second cache to a waiting for confirmation state (e.g., WaitACK), and waits for the second cache to send an confirmation signal (ACK) confirming that the data has been successfully received.

[0107] For example, as shown in Table 9, if the first cache sends a response signal ExpRspEDat to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request RdI (e.g., in response to receiving the read request RdI from the second cache, the cache coherence node creates a read request transaction processing entry and records the state related to the current read request transaction), after receiving the response signal ExpRspEDat sent from the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data (recording that the second cache obtains a copy of this data) to the second cache, and sets the state of the read request transaction processing entry corresponding to the read request RdI of the second cache to an acknowledgement waiting state (e.g., WaitACK), and waits for the second cache to send an acknowledgement signal (ACK) confirming that the data has been successfully received.

[0108] For example, as shown in Table 9, if the first cache sends a response signal ACK to the cache coherence node, and the cache coherence node receives the request type of the second cache as a read request Rd* (e.g., in response to receiving the read request Rd* from the second cache, the cache coherence node creates a read request transaction processing entry or a write request transaction processing entry to record the status associated with the current read request transaction), after receiving the response signal ACK sent from the first cache to the cache coherence node, the cache coherence node sets the status of the read request transaction processing entry to a completed status, and confirms that the data reading has been completed successfully.

[0109] In the data processing method of the embodiment of the present disclosure, the scenario is identified by comparing the write-back transaction with the directory, and the master device directly ends the write transaction processing after receiving the write response, eliminating the need to send an ACK message to the slave device. This reduces the number of ACK messages, reduces the protocol demand for ACK messages, and reduces the power consumption, delay, and bandwidth occupation caused by the transmission of ACK messages. In addition, the buffer rotation rate on the master device side is optimized, and with the same performance, fewer buffers are required on the master device side, saving area and power consumption.

[0110] FIG. 5 is a schematic diagram of an electronic device 60 provided by at least one embodiment of the present disclosure. For example, the electronic device 60 includes a cache coherency node 605, a first cache 606, and a second cache 607. For example, the cache coherency node 605 is configured to write the first data to its internal memory or discard the first data in response to receiving a write request in which the first cache 606 writes the first data back to its internal memory. After the cache coherency node 605 writes the first data to its internal memory or discards the first data, the cache coherency node 605 returns a write response signal to the first cache 606 to directly complete the processing operation for the write request. For example, the write request carries the first data, and the cache coherency node 605 is configured to maintain the consistency of data stored in multiple caches. The caches included in the electronic device 60 of the present disclosure are not limited to two caches (the first cache 606 and the second cache 607) shown in FIG. 5 , and the number of the electronic device 60 can be set to any number as needed.

[0111] For example, the cache consistency node 605 is further configured to, in response to receiving a write request for the first cache 606 to write the first data back to its internal memory, determine whether the first cache 606 is the same cache that currently occupies the first data as recorded on the cache consistency node 605 side, and, in response to determining that the first cache 606 is the same cache that currently occupies the first data as recorded on the cache consistency node 605 side, write the first data to its internal memory.

[0112] For example, the internal memory is configured to, after the cache coherency node 605 writes the first data to the internal memory, return a write response indicating that the first data has been written to the internal memory to the cache coherency node 605. For example, the cache coherency node 605 is further configured, in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, to return a write response signal to the first cache 606 indicating that the first data has been written back to the internal memory, and directly complete the processing operation for the write request.

[0113] For example, cache coherency node 605 is further configured to set the data state of first cache 606 to an invalid state, a shared state, or an exclusive state after cache coherency node 605 writes the first data to its internal memory, where the invalid state indicates that first cache 606 does not cache the first data, the shared state indicates that both first cache 606 and the other caches cache the first data, and the exclusive state indicates that only first cache 606 caches the first data.

[0114] For example, cache coherency node 605 is further configured to issue a monitor signal to first cache 606 in response to receiving a read request for the first data from second cache 607 and recording the first data in an exclusive or shared state at first cache 606. For example, first cache 606 is configured to return a monitor response carrying the first data to cache coherency node 605 in response to first cache 606 receiving the monitor signal after issuing a write request.

[0115] For example, cache coherency node 605 is further configured to, in response to receiving the monitoring response, return the first data to second cache 607. For example, after receiving the first data, second cache 607 is further configured to, after receiving the first data, return a message to cache coherency node 605 indicating that the first data has been received, thereby terminating the read request.

[0116] For example, the cache coherency node 605 is further configured, in response to receiving the monitoring response, to return the first data to the second cache 607 and set the data state of the second cache 607 to an exclusive state, for example, the exclusive state indicating that the first data is cached only in the second cache 607.

[0117] For example, after receiving the message, the cache consistency node 605 is further configured to discard the first data written to the cache consistency node 605 side in response to the write request, and return a write response signal to the first cache 606 to directly terminate the processing operation for the write request.

[0118] For example, the cache consistency node 605 is further configured to, after receiving the message, discard the first data written to the cache consistency node 605 in response to determining that the first data written to the cache consistency node 605 in response to the write request is invalid data.

[0119] In the electronic device 60 of the embodiment of the present disclosure, the scenario is identified by comparing the write-back transaction with the directory, and the master device directly ends the write transaction processing after receiving the write response, eliminating the need to send an ACK message to the slave device. This reduces the number of ACK messages, reduces the protocol demand for ACK messages, and reduces the power consumption, delay, and bandwidth occupation caused by the transmission of ACK messages. In addition, the buffer rotation rate on the master device side is optimized, and with the same performance, fewer buffers are required on the master device side, saving area and power consumption.

[0120] At least some embodiments of the present disclosure further provide a data processing device including a memory and a processor. For example, the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions. For example, when the computer-executable instructions are executed by the processor, a data processing method provided by at least one embodiment of the present disclosure is realized.

[0121] FIG. 6 shows a schematic diagram of a data processing device 500 provided by at least one embodiment of the present disclosure.

[0122] As shown in FIG. 6, an electronic device 500 according to an embodiment of the present disclosure includes a processor 501 and a memory 502, and the processor 501 and the memory 502 can be connected to each other via a bus 503.

[0123] The processor 501 can perform various operations and processes based on programs or codes stored in the memory 502. Specifically, the processor 501 may be an integrated circuit chip having a signal processing function. For example, the processor 501 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or perform various methods and steps disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor, or the processor may be any common processor such as an X86 architecture or an ARM architecture.

[0124] The memory 502 is used to non-temporarily store computer-executable instructions, and the processor 501 is used to execute the computer-executable instructions, which, when executed by the processor 501, implement a data processing method provided by at least one embodiment of the present disclosure.

[0125] For example, memory 502 may be volatile or nonvolatile, or may include both volatile and nonvolatile memory. Nonvolatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as external cache memory. Various forms of RAM are available, including, by way of example, and not limitation, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus dynamic random access memory (DRDRAM). Note that memory for purposes of the methods described herein includes, but is not limited to, these and any other suitable types of memory.

[0126] In the data processing device 500 of the embodiment of the present disclosure, the scenario is identified by comparing the write-back transaction with the directory, and the master device directly ends the write transaction processing after receiving the write response, eliminating the need to send an ACK message to the slave device. This reduces the number of ACK messages, reduces the protocol demand for ACK messages, and reduces the power consumption, delay, and bandwidth occupation caused by the transmission of ACK messages. In addition, the buffer rotation rate on the master device side is optimized, and with the same performance, fewer buffers are required on the master device side, saving area and power consumption.

[0127] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitory stores computer-executable instructions, for example, the computer-executable instructions, when executed by a processor, to implement a data processing method provided by at least one embodiment of the present disclosure.

[0128] 7 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As shown in FIG. 7, a non-transitory storage medium 600 can non-transitory store computer-executable instructions 610, which, when executed by a computer, implement a data processing method provided by any of the embodiments of the present disclosure.

[0129] Similarly, the non-transitory storage medium in embodiments of the present disclosure may be volatile memory, non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that memory for the purposes of the methods described herein includes, but is not limited to, these and any other suitable types of memory.

[0130] The technical effects of the above non-transitory storage medium are the same as those of the above data processing method, and detailed descriptions thereof will be omitted here.

[0131] The flowcharts and block diagrams in the figures illustrate possible system architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, program section, or portion of code, which includes at least one executable instruction for implementing a given logical function. In some alternative implementations, the functions shown in the blocks may occur in a different order than shown in the figures. For example, two blocks shown in succession may actually be executed substantially in parallel or in the reverse order, depending on the functionality involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in a dedicated hardware-based system or a combination of dedicated hardware and computer instructions to perform a given function or operation.

[0132] In general, various exemplary embodiments of the present disclosure may be implemented in hardware, special purpose circuits, software, firmware, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software executable by a controller, microprocessor, or other computing device. When aspects of embodiments of the present disclosure are shown or described as block diagrams, flowcharts, or other graphical representations, it will be understood that the blocks, apparatus, systems, techniques, or methods described herein may be implemented in, by way of non-limiting example, hardware, software, firmware, special purpose circuits, logic, general purpose hardware, controllers, or other computing devices, or some combination thereof.

[0133] The following should be explained about this disclosure.

[0134] (1) In the drawings of the embodiments of the present disclosure, only structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

[0135] (2) For clarity, the thickness and size of layers or structures are exaggerated in the drawings illustrating the embodiments of the present disclosure. As can be understood, when an element such as a layer, film, region, or substrate is said to be located "on" or "under" another element, the element may be located "directly" "on" or "under" the other element, or intermediate elements may be present.

[0136] (3) Unless inconsistent, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0137] The above are merely specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto, but is determined by the appended claims.

Claims

1. 1. A data processing method comprising: a cache coherency node, in response to receiving a write request for a first cache to write first data back to an internal memory, either writing the first data to an internal memory or discarding the first data, the write request carrying the first data, the cache coherency node being configured to maintain consistency of data stored in a plurality of caches, the plurality of caches including the first cache; and after the cache coherence node writes the first data to an internal memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly terminate a processing operation for the write request.

2. the step of the cache coherency node writing the first data to the internal memory or discarding the first data in response to receiving a write request for the first cache to write the first data back to the internal memory includes: In response to receiving the write request for the first cache to write the first data back to the internal memory, the cache coherency node determines whether the first cache is the same cache currently occupying the first data as recorded at the cache coherency node; 2. The data processing method of claim 1, further comprising: in response to determining that the first cache is the same as the cache currently occupying the first data recorded on the cache consistency node side, the cache consistency node writes the first data to the internal memory.

3. the step of the cache coherence node returning a write response signal to the first cache to directly terminate a processing operation for the write request after the cache coherence node writes the first data to an internal memory or discards the first data, after the cache coherency node writes the first data to an internal memory, the internal memory returns a write response to the cache coherency node indicating that the first data has been written to the internal memory; 3. The data processing method of claim 1, further comprising the step of: in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, the cache coherency node returning the write response signal indicating that the first data has been written back to the internal memory to the first cache, thereby directly terminating the processing operation for the write request.

4. The cache coherency node may further include setting a data state of the first cache to an invalid state, a shared state, or an exclusive state after the cache coherency node writes the first data to the internal memory; The data processing method according to any one of claims 1 to 3, wherein the invalid state indicates that the first cache does not cache the first data, the shared state indicates that both the first cache and another cache cache the first data, and the exclusive state indicates that the first data is cached only in the first cache.

5. in response to receiving a read request for the first data from a second cache and recording at the cache coherence node that the first data is in an exclusive or shared state in the first cache, the cache coherence node issues a monitor signal to the first cache; The data processing method of any one of claims 1 to 4, further comprising the step of: in response to the first cache receiving the monitoring signal after issuing the write request, the first cache returning a monitoring response carrying the first data to the cache coherency node in response to the monitoring signal.

6. In response to receiving the monitoring response, the cache coherency node returns the first data to the second cache; 6. The data processing method of claim 5, further comprising: after receiving the first data, the second cache returning a message indicating that the first data has been received to the cache coherency node, thereby terminating the read request.

7. In response to receiving the monitoring response, the cache coherency node returning the first data to the second cache comprises:

7. The data processing method of claim 6, further comprising the step of: in response to receiving the monitoring response, the cache coherency node returning the first data to the second cache; and setting a data state of the second cache to an exclusive state indicating that the first data is cached only in the second cache.

8. the step of the cache coherence node returning a write response signal to the first cache to directly terminate a processing operation for the write request after the cache coherence node writes the first data to an internal memory or discards the first data, 7. The data processing method of claim 6, further comprising the step of: after receiving the message, the cache consistency node discarding the first data written to the cache consistency node side in response to the write request, and returning the write response signal to the first cache to directly terminate the processing operation for the write request.

9. the step of the cache consistency node discarding the first data written to the cache consistency node side in response to the write request after receiving the message, 9. The data processing method of claim 8, further comprising: after receiving the message, in response to determining that the first data written to the cache consistency node side in response to the write request is invalid data, the cache consistency node discarding the first data written to the cache consistency node side in response to the write request.

10. An electronic device, a plurality of caches including a first cache and a cache coherency node; the cache coherency node is configured to, in response to receiving a write request for the first cache to write first data back to an internal memory, either write the first data to the internal memory or discard the first data, and after the cache coherency node has written the first data to the internal memory or discarded the first data, return a write response signal to the first cache to directly terminate a processing operation for the write request, wherein the write request carries the first data, and the cache coherency node is configured to maintain consistency of data stored in the multiple caches.

11. The cache coherency node further comprises: In response to receiving the write request for the first cache to write the first data back to the internal memory, determining whether the first cache is the same cache currently occupying the first data as recorded at the cache coherency node; 11. The electronic device of claim 10, configured to write the first data to the internal memory in response to determining that the first cache is the same as the cache currently occupying the first data recorded on the cache coherency node side.

12. the internal memory is configured to, after the cache coherency node writes the first data to the internal memory, return a write response to the cache coherency node indicating that the first data has been written to the internal memory; 12. The electronic device of claim 10 or 11, wherein the cache coherency node is further configured, in response to receiving the write response from the internal memory indicating that the first data has been written to the internal memory, to return the write response signal indicating that the first data has been written back to the internal memory to the first cache, thereby directly completing the processing operation for the write request.

13. the cache coherence node is further configured to issue a monitor signal to the first cache in response to receiving a read request for the first data from a second cache and recording at the cache coherence node that the first data is in an exclusive or shared state in the first cache; and 13. The electronic device of claim 10, wherein the first cache is configured to return a monitoring response carrying the first data to the cache coherency node in response to the first cache receiving the monitoring signal after issuing the write request.

14. a memory configured to store computer-executable instructions; a processor configured to execute the computer-executable instructions; A data processing apparatus, wherein the computer-executable instructions, when executed by the processor, implement the method of any one of claims 1 to 9.

15. A non-transitory storage medium for non-transitory storage of computer-executable instructions, which, when executed by a processor, implement the method of any one of claims 1 to 9.

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