Frequency-stable low-noise timing signal generator with multiple MEMS resonators and nested PLL structure

Abstract

A frequency synthesizer generates a reference signal using an oven-controlled oscillator ("OCXO"). A nested PLL structure features an outer PLL loop with a divider that performs temperature compensation on the OCXO's output, thereby creating a temperature-compensated OCXO ("TCOCXO"), which also depends on information to select a synthesis frequency. The oscillation source for the outer PLL loop is implemented as an inner PLL loop of the nested PLL structure, which uses the output of a second oscillator ("SXO"), which is the reference frequency, and an electronic VCO. The nested PLL structure is designed so that the phase noise from the TCOCXO dominates the synthesis frequency output at low frequencies, the phase noise from the SXO dominates at medium frequencies, and the phase noise from the electronic VCO dominates at high frequencies.

Description

[Technical Field]

[0001] REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 441,917, filed January 30, 2023 ("Frequency-stable, low-noise timing signal generator having multiple MEMS resonators and nested-PLL structure"), which is incorporated herein by reference.

[0002]

[0002] This disclosure relates to timing signal generators suitable for use in high frequency applications. More specifically, this disclosure relates to high frequency timing signal generator architectures based on the use of multiple MEMS resonators and cascaded PLL structures. The structures provided by this disclosure are particularly useful for frequency synthesizer and / or clock generator applications. [Background technology]

[0003]

[0003] Timing signal generators are ubiquitous in all digital electronic devices, and popular circuit designs are typically based on some type of resonator and a phase-locked loop ("PLL").

[0004] A typical PLL operates using a reference signal having an input frequency, a phase detector, some type of controllable oscillator (typically a voltage-controlled oscillator, or "VCO"), and a feedback path to the phase detector. Many PLL designs, particularly those that generate timing outputs different from the reference signal, also include some type of frequency divider or multiplier in the feedback path; such dividers or multipliers are referred to herein simply as "dividers" to indicate fractions or some other numerical adjustment of the reference signal. The PLL attempts to synchronize the oscillations of the signal from the divider (or VCO, if no divider is present) to the oscillations of the reference signal, with the divider acting almost like a gear, e.g., making the VCO run slower or faster than the input frequency until a frequency-scaled version of the VCO output tracks the reference signal. This scaling causes the VCO to generate a substantially desired output signal (e.g., with a frequency scaled depending on how the divider is used). Generally speaking, a PLL passes phase noise from the reference signal up to an output frequency corresponding to the PLL's loop speed; at higher frequencies, the phase noise from the reference signal is lost and the VCO's phase noise dominates the PLL's output. This basic design works well in many conventional applications and can be used to generate timing signals with frequencies much greater than the input frequency; for example, if a divider in the PLL's feedback path reduces the frequency of the signal from the VCO by 8, the effect is to drive the VCO to generate a frequency 8 times that of the reference signal.

[0005]

[0005] However, as processor clock and signaling speeds continue to increase, the need to generate correspondingly fast and accurate timing signals poses significant design challenges, as phase noise / frequency stability of the PLL's output becomes a much more significant issue. That is, at high frequencies (e.g., gigahertz frequencies and above), and at frequencies associated with sub-nanosecond clock periods, phase noise that is tolerable at much lower frequencies is no longer acceptable and can overwhelm timing margins. In particular, many new electronic devices require the generation of not just one, but typically multiple timing signals with different phase and frequency characteristics. As an example, fifth-generation ("5G") mobile communication devices typically require multi-gigahertz clocks as well as timing signals to support radio frequency ("RF"), wireless local area network ("WLAN"), cellular, Bluetooth, and other modems used in various communication formats. This requirement further complicates the design of timing signal generators; for example, a timing signal generator that may have acceptable phase noise / frequency stability in high-frequency applications may perform poorly when applied to low-frequency tasks, and conversely, a timing signal generator that may have acceptable phase noise / frequency stability in low-frequency applications may perform poorly when applied to high-frequency tasks. Simply put, due to the evolution of digital devices, many existing timing generator designs (e.g., those based on traditional single PLL-based approaches) generally lack the required precision and, for example, cannot operate without unacceptable levels of signal noise and / or frequency stability, given the typical requirements of new-generation digital device technologies.

[0006]

[0006] A set of techniques is needed to address these problems. More specifically, a set of techniques is needed for building timing signal generators with improved frequency stability that can meet the demands associated with very high frequency timing signal generation (especially gigahertz frequencies) and also support the needs of these newer digital devices (e.g., 5G devices). Ideally, such techniques would provide tools to aid in the effective design of frequency synthesizers / clock generators that can accommodate the wide range of timing signal requirements of newer digital devices and provide stable clock and other timing signal generation across the entire frequency range of interest, e.g., from very low to very high frequencies. The present invention addresses these needs and further provides related advantages. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram used to explain one embodiment 101 of a timing signal generator. [Figure 2A]

[0008] 2 is a block diagram used to explain an embodiment 201 that relies on multiple PLLs, shown in the figure as PLL-1, PLL-2, PLL-3, . . . , PLL-k. [Figure 2B]

[0009] 2 is a graph 251 used to discuss the use of multiple PLLs in connection with embodiments described herein. [Figure 3A]

[0010] FIG. 1 is an explanatory diagram used to explain an embodiment 101 of a timing signal generator. [Figure 3B]

[0011] 3 is a graph 331 used to discuss phase noise / frequency stability and how some embodiments can be designed to provide lower phase noise over a wider range of output frequencies. [Figure 3C]

[0012] FIG. 3 is a block diagram of an embodiment 351 of a timing signal generator. [Figure 4A]

[0013] FIG. 4 is an illustration of another embodiment 401 of a timing signal generator. [Figure 4B]

[0014] FIG. 4 is an illustration showing another embodiment 421 of a timing signal generator. [Figure 4C]

[0015] FIG. 4 is an illustration showing another embodiment 431 of a timing signal generator. [Figure 4D]

[0016] FIG. 4 is an illustration showing another embodiment 441 of a timing signal generator. [Figure 4E]

[0017] FIG. 4 is an illustration showing another embodiment 451 of a timing signal generator. [Figure 5A]

[0018] FIG. 1 is a block diagram illustrating one embodiment of an oven-controlled oscillator (“OCXO”). [Figure 5B]

[0019] FIG. 1 is a block diagram illustrating the use of two MEMS resonators to provide a temperature compensated oscillator (“TCXO”) design. [Figure 5C]

[0020] FIG. 1 is a block diagram illustrating an embodiment of a temperature compensated oven controlled oscillator (“TCOCXO”) that is based on the use of two MEMS resonators. [Figure 6]

[0021] 6 shows a more detailed embodiment 601 of a frequency stable low noise timing signal generator with multiple MEMS resonators and a nested PLL structure. [Figure 7A]

[0022] FIG. 7 is a block diagram of an embodiment 701 with various types of frequency scaling options. [Figure 7B]

[0023] For example, this is a block diagram of an embodiment 751 that uses open-loop digital frequency synthesis (“DDS”) where input 763 is used to control frequency selection, i.e., so that one or more downstream PLLs 755 and / or 761 pass the phase noise of the DDS circuit 753 below the loop speed of the PLL and pass the phase noise of the LCXO for high frequencies.

[0008]

[0024] The subject matter defined by the enumerated claims may be better understood by reference to the following detailed description, which should be read in conjunction with the accompanying drawings. This description of one or more specific embodiments, presented below to enable construction and use of various examples of the technology defined by the claims, is not intended to limit the enumerated claims, but rather to illustrate their application. Without limiting the foregoing, this disclosure provides several different examples of techniques for constructing low-noise, frequency-stable timing generators. In specific embodiments, these timing signal generators may be implemented as frequency synthesizer / clock generator circuits that generate highly stable timing signals over a wide range of frequencies suitable for newer digital devices, such as devices fully compatible with 5G mobile computing requirements. Specific die / package configurations are also shown. While specific examples are shown, the principles described herein may also be applied to other methods, devices, and systems. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0025] This disclosure provides techniques to address the aforementioned problems.

[0010]

[0026] In one embodiment, a timing signal generator uses multiple phase-locked loops ("PLLs") that can be used to switch between several oscillation sources depending on the frequency to be generated. For example, a frequency synthesis circuit may receive an input that defines the frequency of interest to be generated. A first PLL causes a performance parameter associated with the first oscillation source to govern its output depending on the frequency of the timing signal to be generated, and for frequencies above the loop speed of the first PLL, a performance parameter associated with a first voltage-controlled oscillator ("VCO") associated with the first PLL governs its output. A second PLL is used to cause a second oscillation source to govern its output depending on the frequency of the timing signal to be generated, and for frequencies above the loop speed of the second PLL, a performance parameter associated with a second VCO associated with the second PLL governs its output. These first and second PLLs can be used in series, parallel, cascaded, nested, or other relationships. For example, in a nested relationship, a second PLL may implement the VCO of a first PLL and be used to achieve control of the VCO of the first PLL, such that the loop speed of the second PLL used to cause phase noise to track the second or third oscillator source exceeds the loop speed of the first PLL. That is, such embodiments may have three or more oscillator sources used to generate timing signal outputs and effectively improve overall phase noise performance by causing the timing signal outputs to emulate the phase noise of an oscillator that best matches the generated timing signal frequency. Generally speaking, alternative embodiments (e.g., situations where the performance parameter of interest is something other than lowest phase noise) may use cascaded, serial, parallel, nested, or other multi-PLL structures to effectively select and / or have the oscillator source dominate the output depending on the generated timing signal frequency. Of course, any number of PLLs and oscillator sources may be used; for example, the techniques described herein are not limited to the use of two PLLs or to a particular number of oscillator sources. In some embodiments, one or more oscillator sources may be received in the form of externally provided frequency reference signals.

[0011]

[0027] In a specific embodiment, a nested PLL structure can be used to effectively select from multiple oscillator sources according to which oscillator source provides the lowest phase noise, given the frequency of the timing signal to be generated. A timing signal generator stably generates a first reference signal using a first oscillator ("FXO"). A nested phase-locked loop ("PLL") structure can be used to generate a timing signal having a desired frequency by multiplying / dividing a baseline frequency. The nested PLL structure includes at least an outermost PLL loop and an innermost PLL loop of the nested PLL structure. The first of these PLLs, i.e., the outermost PLL loop, receives a reference frequency from the FXO and synchronizes the signal generated by the first variable oscillator source to this reference frequency, and the first PLL may include a multiplier / divider (e.g., integer, fractional, or other) to scale the reference frequency (e.g., to generate a frequency much higher than the reference frequency in some applications). Optionally, the FXO may be based on an oven-controlled oscillator ("OCXO") design, a temperature-controlled oscillator ("TCXO") design, or both ("TCOXO"). Note that these variations are not required for all embodiments; in some embodiments, the FXO may be based on an external frequency reference or any type of conventional oscillator (e.g., a microelectromechanical systems, or "MEMS," oscillator, crystal oscillator, LC oscillator, closed-loop frequency generator, phase mixer or interpolator, open-loop frequency generator, or other conventional timing signal generator or circuit). In some embodiments, the FXO may use an open-loop digital frequency generator (e.g., an open-loop direct digital synthesis, or "DDS," device, or digital phase mixer or interpolator). A second PLL loop, in this case the inner PLL loop, acts in place of the VCO of the outer PLL loop, receiving a second reference signal from a second oscillator ("SXO") and synchronizing the second controlled oscillator source to this reference signal.Again, optionally, this SXO can be any type of oscillator or frequency generator described above, such as an oven-controlled oscillator ("OCXO") design, a temperature-controlled oscillator ("TCXO") design, or both ("TCOXO"), although variations of these are not required for all embodiments. The second variable oscillation source can rely on an electronic voltage-controlled oscillator ("VCO"), i.e., it can rely directly on the electronic VCO, or it can synchronize a signal from a further inner loop of a nested PLL structure. In certain applications, the timing signal generator can be a frequency synthesizer and / or clock generator circuit; for example, the aforementioned divider of the first PLL loop can perform frequency scaling in a programmable manner to generate various output frequencies. The second PLL loop can also have a divider, which can be controlled based on the VCO control signal generated by the first PLL loop. The timing signal generator design is advantageously one in which frequency stability is maintained and / or improved over a very wide output frequency range.

[0012]

[0028] It should be noted that one or more resonators of the FXO and / or SXO (or other higher order oscillators) may optionally be implemented using one or more microelectromechanical systems ("MEMS") resonators. Similarly, although specific reference is made herein to a PLL, the term "PLL" should be understood to generally encompass any type of locked loop or similar feedback circuit, including, but not limited to, a delay locked loop, an inverter chain, a phase locked loop, a fractional or integer multiplication loop, and other types of digital or analog feedback circuits conventionally used for phase or frequency adjustment.

[0013]

[0029] In one particular embodiment, extremely stable frequency generation can be achieved by further implementing a TCXO, OCXO, or TCOCXO design in the FXO. Even more specifically, in one optional case, a TCOCXO is used. That is, in addition to maintaining the OCXO's resonator at a constant temperature, in some embodiments, the OCXO's output frequency signal is also further temperature compensated to provide an ultra-stable oscillation reference signal. In some embodiments, the TCOCXO design can be configured to provide a frequency variation of less than one part per billion ("PPB") per degree change in temperature (e.g., per degree Celsius change). The combination of these features (e.g., oven control to maintain the resonator at a certain temperature and further temperature compensation of the ovenized resonator output) facilitates, in some embodiments, providing stable frequency synthesis over a very wide range of interest, e.g., from less than 1 Hertz to tens of gigahertz.

[0014]

[0030] Other embodiments feature the placement of some or all of the structures introduced in this disclosure on a particular die of a packaged or unpackaged electronic device (e.g., a timing signal generator, a frequency synthesizer, and / or a clock generator). Some of these designs facilitate a compact footprint and / or a particular level of integration, allowing, for example, a single “circuit” die to combine and support PLL circuitry, MEMS sustain and / or sense circuitry, oven control circuitry, clock adjustment circuitry, and / or any other permutation and / or combination of these components. For example, one embodiment features a die stack or other multi-die arrangement in which one or more MEMS resonator dies containing both FXO and SXO resonators are compactly juxtaposed with one or more circuit dies. These dies may, for example, optionally be capable of generating all relevant timing signals on-board, effectively eliminating the use of an external oscillator source as one of multiple selectable oscillator sources. In such an embodiment, the circuit die may perform both oscillator functions (e.g., driving and / or processing the outputs of the FXO and SXO) and circuit support for the nested PLL structure described above. As a further example, in one possible embodiment, all such support circuitry may optionally be located on a single CMOS or BiCMOS "circuit die."

[0015]

[0031] In some embodiments, each oscillator (e.g., an FXO or SXO, and / or an oscillator in another level loop in a nested PLL hierarchy) may itself have two or more MEMS resonators, e.g., for reference frequency generation, temperature sensing, and / or other purposes.

[0016]

[0032] Other combinations and permutations of the structures described herein are considered embodiments of the technology described herein, but are not individually and uniquely illustrated by a single dedicated figure in the accompanying figures. Additional features and advantages, and related structural alternatives, will become more apparent to those skilled in the art based on the additional description that follows.

[0017]

[0033] Having thus introduced the major components of an improved timing signal generator, this disclosure proceeds to a more detailed discussion of additional structures and related techniques.

[0018]

[0034] However, before proceeding with this additional description, it will be helpful to first consider some specific terminology. First, it should be understood that contemplated embodiments may include “hardware logic,” “circuitry,” or “circuitry” (each meaning one or more electronic circuits). Generally speaking, unless otherwise specified, these terms may include analog and / or digital circuitry, and may be special purpose or general purpose in nature. For example, as used herein, the term “circuitry” for performing a particular function may include one or more electronic circuits that are “hardwired” or configurable to perform a defined function (i.e., possibly without the aid of instructional logic), and the term may include a microcontroller, microprocessor, FPGA, or other form of processor that, while general in design, executes software or firmware (e.g., instructional logic) that causes or configures a general-purpose circuit to perform a particular function (e.g., configures or directs a circuit processor). Note that, as these descriptions suggest, "circuit" and "circuitry" for one purpose are not necessarily mutually exclusive from "circuit" or "circuitry" for another purpose; for example, such terms may indicate that one or more circuits are configured to perform a certain function, and that one, two, or all of the circuits may be shared with the "circuitry" to perform another function (indeed, "circuitry" often includes a processor); i.e., "circuitry that performs (function X)" and "circuitry that performs (function Y)" may include the same or separate circuitry, depending on the implementation. In this regard, the term "logic" may include hardware logic, instructional logic, or both, unless otherwise specified.Instructional logic may be code written or designed to have a particular structure (architectural features) that, when ultimately executed, causes one or more general-purpose machines (e.g., processors, computers, or other machines) to operate as special-purpose machines, each structured to perform described tasks on processing operands or otherwise perform particular actions or generate particular outputs upon the occurrence of defined events. Generally speaking, the circuits and / or processes described herein may, in some embodiments, be implemented as instructional logic (e.g., instructions stored on a non-transitory machine-readable medium or other software logic), hardware logic, or any combination or permutation thereof, depending on the embodiment or specific design. In connection with various embodiments herein, the term "device" is used to refer to an electronic product (e.g., based on, but not limited to, a chip, system, or board) that comprises circuitry and possibly, but not necessarily, resident software or firmware; examples of devices include, but are not limited to, end consumer products, computers, smartphones, integrated circuits, dies, electronic boards, and / or other embodiments. As used herein, "non-transitory" refers to any tangible (i.e., physical structure) medium, regardless of the type of technology used to represent the data on the medium or the format of data storage; for example, in some cases, a particular representation may be stored optically on the physical medium, while in other cases, a particular representation may be stored magnetically on the physical medium. Thus, when applied to storage and / or computer-readable and / or machine-readable subject matter, the term "non-transitory" indicates that data and / or instructions may be stored on such physical structured storage medium using optical, magnetic, electronic, resistive, and / or other storage formats / technologies; i.e., any type of physical device may be used as the storage medium, including, but not limited to, random access memory, hard disk memory, optical memory, floppy disk, compact disk ("CD"), solid-state drive ("SSD"), server storage, volatile memory, and / or non-volatile memory; i.e., physical objects.Each such medium and / or device may be in a standalone form (e.g., a program disk or solid-state device), or may be embodied as part of resident memory that is part of a larger organization, e.g., an electronic device such as a smartphone, computer, digital television, automobile, mobile device, chip card, dongle, server, printer, etc., or may be embodied as one or more such devices. "Instructions" may be implemented in various forms depending on the embodiment; for example, instructions may take the form of metadata that, when invoked, is effective to invoke a particular action, Java code or web script, code written in a particular programming language (e.g., C++ code), a processor-specific instruction set, or some other form. Depending on the design, instructions may be executed by the same processor, different processors or processor cores, FPGAs, or other configurable circuitry, and may be adapted for execution by a single computer, or on a distributed basis, e.g., using one or more servers, web clients, or application-specific devices, not necessarily all operating simultaneously. The term "integrated circuit" (or "IC") typically refers to a structure having at least one die, whether packaged or not, meaning that a single IC and / or die can also be a type of electronic device. The term "MEMS" refers to electromechanical structures used and / or operating at a circuit board, die, IC, or similar level, whether they are characterized as "miniature," "micro," "nano," or otherwise in terms of scale. As used herein, "substrate" refers to any structure conventionally used to support electronic circuits and / or electronic devices; for example, the term can include wafers, dies, lead frames, silicon offsets or pillars, ceramic supports, ICs, or other structures that can serve as support for these or other elements described herein; the substrate also typically, but not necessarily, provides electrical routing and connections to the supported elements.The terms "divider" and "multiplier" are used interchangeably herein unless otherwise specified and refer to, for example, increasing and / or decreasing the frequency of an oscillator signal by any one of several structures in the feedback path of a PLL loop, whether integer-based, fractional, programmable, or otherwise. As noted above, the term "PLL," unless otherwise indicated, should be interpreted to generally encompass any locked loop structure (e.g., including delay-locked loops and other structures) used for timing control, and, unless otherwise indicated, can take the form of a digital or analog structure, regardless of whether a particular conventional circuit structure (e.g., an XOR gate as a phase detector) is used. The terms "PLL," "PLL loop," and "locked loop circuit" are generally used synonymously in this disclosure. The term "VCO," as used herein, refers to any controllable oscillator, whether current-controlled, voltage-controlled, analog, digital, or otherwise, e.g., an oscillator source that generates a variable frequency as part of a timing signal adjusted by a PLL to synchronize the phase and frequency of a reference frequency.

[0019]

[0035] The meaning of other terms used herein should be clear based on the context. It should be understood that, to the extent any document is incorporated herein by reference, the definition of that document shall take precedence over any conflicting definition provided by such incorporated-by-reference document. It is emphasized that the various elements discussed above or below may be used in any embodiment, in the same or other embodiments, in any desired permutation or combination, and all such permutations and combinations are expressly contemplated by this disclosure. The selection and / or omission of features in any given design or application is within the level of ordinary skill in the art, and no element / structure discussed below should be deemed "essential" for any purpose or function.

[0020]

[0036] FIG. 1 illustrates a first embodiment of a timing signal generator, in this case a frequency synthesizer generally designated by the numeral 101. A selected or programmed value 103 (e.g., a desired frequency f) is input to the frequency synthesizer; depending on the embodiment, such value may be programmed at the time of manufacture, in-situ, or dynamically; for example, FIG. 1A is intended to encompass both examples in which the selected or programmed frequency is fixed by a “fuse” or other assembly-time frequency selection (e.g., for a particular application) and examples in which a programmed digital value is received by the frequency synthesizer 103 and loaded into a register, e.g., to dynamically and / or programmably adjust timing signal generation parameters. The timing signal generator produces an output 105 including one or more timing signal (e.g., clock) frequencies and / or phases as dictated by one or more provided and / or programmed values ​​103. As can be seen, multiple oscillator sources 108, 109, ... 110 are effectively selected, for example, by control circuitry 111, which uses one or more control signals 113 to adjust the frequency synthesis, generally represented by numeral 114. Depending on the embodiment, these control signals may adjust frequency synthesis circuitry, such as a divider / multiplier filter or other circuitry within or outside the feedback loop of the PLL, or may adjust circuitry associated with the oscillator source itself. For example, as indicated by block 115, in one contemplated case, control circuitry 111 may adjust a multiplication / division factor (integer or fractional) within the feedback loop of the PLL (e.g., within frequency synthesis circuitry 114) to control the frequency generated by the VCO; in one embodiment, such operation effectively selects one of the illustrated oscillators (Osc.1 through Osc.N) in a manner that selects the oscillator source with the lowest phase noise as a function of a programmed generation frequency (fp), as referenced in function block 117. Alternatively, it is possible to implement a circuit that automatically distinguishes between oscillator source / control frequency generation as a function of the generated timing signal frequency (e.g., represented by the function F{fp}), again based on another performance parameter (e.g., other than phase noise).As indicated by numeral 118, the illustrated design effectively provides for in-situ selection of the oscillator that will dominate and / or drive output 105 for the frequency range for which the selected oscillator is optimal, given the performance criteria of interest. In some embodiments, control circuitry 111 allows for direct control of the generation by one or more oscillators (Osc.1-Osc.N), as suggested by the presence of dashed (optional) control signal 113. As indicated by numeral 119, in one embodiment, optional in-situ or dynamic programming may also be used to select and / or vary the performance parameters of interest, e.g., to vary the manner in which various vibration sources are distinguished and / or adapted.

[0021]

[0037] As mentioned above, one embodiment controls frequency synthesis depending on which oscillator source produces the best phase noise parameters in the frequency range of interest, based on the criterion that the generated output has a phase noise profile that tracks one of several oscillator sources. Figures 2A and 2B are used to help explain the use of multiple PLLs in oscillator source selection and identification, and these figures are generally considered together.

[0022]

[0038] A frequency synthesizer or other timing signal generator 201 generates or is supplied with a reference frequency (f) 203. Conventionally, a PLL 205 may be used to synchronize the generated timing signal 206 to the phase and frequency of the reference frequency (f) 203, for example, by driving a VCO (not shown in FIG. 2A) faster or slower, thereby generating a stable output. As previously explained, the loop speed of the PLL 205, represented as frequency point "A," causes the signal 206 to track the phase noise of the reference frequency (f) 203 below point "A" and track the frequency of the VCO above point "A." FIG. 2B is a typical phase noise plot 251 (log) illustrating the effect of this distinction: the reference frequency (f) 203 has a phase noise profile roughly corresponding to curve 253; without the PLL, the phase noise would be expected to progress asymptotically, as shown by dashed line 255. In reality, however, due to the finite loop speed of PLL 205, signal 206 tracks the phase noise of the VCO above point "A," i.e., above the loop speed of PLL 205, the phase noise of signal 206 instead takes on the phase noise characteristic of the VCO, progressing asymptotically as shown by dashed line 257.

[0023]

[0039] In accordance with the principles introduced by this disclosure, as shown in FIG. 2A , two or more PLLs, such as a second PLL 207, a third PLL 209, and potentially other PLLs (e.g., a kth PLL 211) (as indicated by oval 210), can be used to effectively select the oscillator source that will dominate the output according to a programmed frequency; in this design, each PLL performs frequency discrimination (and the resulting one or more generated timing signal outputs φ ) in a manner that will effectively “pick” the best oscillator source given a frequency range of interest. out-1 ~φ out-j2B )。 For example, the illustrated second PLL 207 can be designed to have a loop speed corresponding to frequency point "B," in which case the PLL substantially relies on a VCO (not shown) that produces lower phase noise than conventional, as represented by curve 259 of FIG. 2B. Similarly, the optional third PLL 209 can be designed to pass the phase noise of that PLL (i.e., to correspond to loop speed "C," as represented by, for example, phase noise curve 261), up to the kth PLL loop speed (represented by point "K" and phase noise curve 263). Thus, the illustrated design can be designed to pass one or more generated timing signal outputs φ out-1 ~φ out-j , relying on multiple PLLs (e.g., two or more) to generate a phase noise signal φ 1 , depending on which corresponding frequency band (i.e., corresponding to one of the oscillator sources) contains the frequencies being synthesized. For example, it is possible to add PLLs and / or oscillator sources to the left of plot 251 to improve phase noise, as indicated by curve 265 and frequency point A'. As previously mentioned, multiple PLLs can be configured in series, parallel, cascaded, nested, or otherwise, depending on the specific embodiment. FIG. 2A shows a series of PLLs for illustrative purposes, not limitation. It will be understood that combinations and permutations of PLLs can be cascaded and nested (as described above and below). Furthermore, as indicated by reference numerals 213, 215, and 217, multiple timing signals can be generated depending on the embodiment, and these various signals may be combined into a single signal φ 1 , as shown in FIG. 2A, for example, as appropriate for a given embodiment. out-j In the case of 217, one or more "parallel" PLLs, such as numeral 219, can optionally be used to tap off the intermediate stage PLL.

[0024]

[0040] FIG. 3A is a diagram illustrating another embodiment 301 of a timing signal generator employing some of the principles discussed herein. This timing generator is embodied as a frequency synthesizer / clock generator circuit, designed, for example, to selectively generate one or more different frequencies within a range, using a nested PLL structure to effectively select different oscillator sources depending on the frequency to be generated. This embodiment uses a temperature-compensated oven-controlled oscillator ("TCOCXO") 303 to generate a highly stable baseline reference signal, while other embodiments do not require either a TCXO or an OCXO for use as this first oscillator. As shown, this particular TCOCXO is based on at least one MEMS resonator, although this is not required for all embodiments. Depending on preference and implementation, each MEMS resonator can be a piezoelectric or electrostatic MEMS resonator, and can be mixed and matched in a multi-resonator design if desired.

[0025]

[0041] As is well known, resonators are used in electronic devices to generate oscillatory signals having frequencies that can change with temperature. Quartz crystals have traditionally been used as resonators in most digital electronic devices, but newer MEMS resonators, which can be fabricated using semiconductor fabrication techniques, are beginning to replace the use of quartz crystals. The use of oven controls for resonators typically attempts to lock the resonator at a predetermined temperature to mitigate temperature-dependent variations; that is, at least in theory, the temperature-dependent variations inherent in quartz crystals, MEMS, and many other types of resonators have traditionally been considered irrelevant unless temperature variations are allowed. In a typical "oven-controlled" design ("OCXO"), the resonator is held in an insulated chamber or "oven," heated to a particular set-point temperature, and maintained at that temperature (e.g., using feedback control); this temperature is typically above the resonator's normal operating temperature range; for example, if an electronic chip is designed to operate perfectly over an ambient temperature range of -40 to +85°C, an oven-controlled oscillator might keep the resonator at +100°C and prevent this temperature from changing as the ambient temperature changes (e.g., it is generally easier to heat a resonator than to cool it). Because oven controls typically produce a relatively stable oscillator output signal that does not vary significantly with temperature changes, further compensation for temperature variations is considered unnecessary and / or superfluous in many conventional applications.

[0026]

[0042] However, the designs shown in some figures go further by implementing a "TCOCXO" that not only maintains a controlled "oven" (i.e., OCXO), but also measures the temperature of the oven and applies electronic compensation for resonant frequency variations as a function of temperature variations; generally speaking, this temperature control (TC) can be done on a front-end basis, for example, via changes in drive signals or bias voltage adjustments (e.g., in the case of electrostatic designs); in other cases, this temperature control (TC) can be done in downstream circuitry, for example, in a PLL, to electronically adjust the timing signal frequency as a function of the measured temperature.

[0027]

[0043] The design shown in FIG. 3A uses the latter approach. The OCXO block 303 includes a chamber (e.g., often, but not necessarily, a ceramic enclosure), a MEMS die within the chamber, a heating element within the chamber, a temperature sensor, and circuitry that relies on the use of feedback to drive the temperature sensor and heating element so that the MEMS resonator always operates at a predetermined temperature. Depending on the embodiment, the temperature sensor may be located with the MEMS resonator, i.e., on the MEMS die, or near (e.g., abutting) the MEMS die. Like conventional OCXO MEMS resonator designs, the illustrated design includes a resonator body that is designed to exhibit a cubic relationship between temperature change and resonant frequency change, and includes a "turnover temperature," i.e., the point at which the resonant frequency becomes temporarily temperature invariant, at which the slope of the frequency change with temperature switches between positive and negative signs. As previously mentioned, OCXO resonators are typically designed so that this turnover temperature is necessarily higher than the normal ambient temperature operating range. In the illustrated design, this temperature is typically at least 120°C or higher. MEMS-based resonator OCXO designs typically feature a resonator design with a turnover temperature significantly higher than the normal operating temperature range, and the OCXO's thermal control circuitry keeps the resonator heated to precisely this temperature. This is because, at this operating point, the MEMS resonator is relatively insensitive to small variations in temperature; i.e., the resonator's temperature coefficient of frequency ("TCF") is near zero within a narrow range centered around the turnover temperature. The illustrated TCOCXO block 303 also outputs a temperature-dependent signal 305 that is used to provide temperature convergence to downstream circuitry. In the illustrated embodiment, this occurs more specifically within the feedback path of the first or outermost PLL loop 307, where temperature compensation ("TC") is applied in conjunction with frequency synthesis control to control the frequency divider. The feedback loop is used to lock the controlled oscillator-based output, i.e., the output from the TCOCXO block 303, to a reference frequency.In a conventional PLL, the controlled oscillator would typically be a voltage-controlled oscillator (“VCO”), but in the illustrated embodiment, this VCO is effectively replaced by a second PLL loop 315 (i.e., inner PLL loop), in this case implementing a digitally controlled oscillator (“DCO”) 313. Thus, the first PLL loop 307 outputs a digital signal 316 to control this DCO 313, which in turn returns an oscillation signal 317 to the first PLL loop 307. Thus, the first PLL loop 307 controls the DCO to increase or decrease frequency in an attempt to achieve phase lock between the first frequency reference signal 309 and an oscillation signal derived from signal 317 (e.g., a divided-down version of this signal that is controlled in part by the temperature-dependent signal 305). Note that this configuration also relaxes the design constraints of the TCOCXO block 303 and its resonator(s) compared to conventional OCXO designs; i.e., the behavior of the resonator at the turnover point becomes less critical because temperature-dependent variations can be compensated for using programmed coefficients that respond to temperature-dependent signals. Such coefficients are learned and programmed for each product (e.g., at the factory), and also provide a convenient mechanism for compensating for manufacturing process corners. Thus, the illustrated design allows the oven to operate at any temperature, e.g., 15°C above the normal operating temperature range of the electronic device. For example, if an electronic device including a timing generator is desired to operate within a rated temperature range of 0° to +70° Celsius ("C"), -40° to +85°C, -55° to +125°C, or a different temperature range, the OCXO can be designed to heat the resonator to maintain a temperature of approximately +85°C, +100°C, or +140°C, or approximately 15° above whatever temperature range is being used, and the resonator can optionally be designed so that its turnover point coincides with that temperature.

[0028]

[0044] In certain embodiments, the TCOCXO block 303 uses two MEMS resonators. In such designs, the first of the two MEMS resonators is typically designed to have a temperature-invariant resonant frequency over the entire temperature range of interest, while the second of the two MEMS resonators produces a resonant frequency that varies significantly, but ideally linearly, with temperature. The first of the two MEMS resonators is used as the basis for the oscillator output signal 309, while both resonators are used to implement a temperature sensor. In such designs, the frequencies of the two resonators converge or diverge as the temperature changes, enabling accurate temperature determination. Furthermore, because the resonator frequencies generate signals that repeat thousands to millions of times per second, the frequencies can be digitally quantified, and the ratio of the two frequencies can be used to provide a very fine digital measurement of temperature. In one configuration, a MEMS die (i.e., comprising two MEMS resonators) outputs two sinusoidal signals, each representing the resonant frequency of a particular resonator, and the ratio of these two signals is used by downstream circuitry on the circuit die to determine temperature and, for example, to control an oven in a temperature-invariant manner. It should be noted that the two MEMS resonators need not be designed to operate at the exact same frequency; in this regard, the two resonators are typically designed to operate in the kilohertz ("kHz") to megahertz ("MHz") frequency range, with one of the two resonators intentionally designed to have a baseline resonant frequency that differs from the other by approximately + / - 10%. For example, in one contemplated design, one of the two MEMS resonators may be designed to operate in the range of approximately 25-50 MHz, e.g., with a baseline resonant frequency of 35 MHz, while the other resonator is designed to operate at approximately 90-95% of this frequency, e.g., with a baseline resonant frequency of 32 MHz. It should be noted that these specific characteristics are not required for all implementations.

[0029]

[0045] It should again be noted that the use of an OCXO, TCXO, TCOCXO, and / or MEMS resonator is not required for all embodiments; for example, some embodiments simply use a conventional OCXO (e.g., one with a quartz crystal or other resonant structure) to generate a baseline reference frequency that serves as a reference for a nested PLL structure; such a structure provides a stable baseline frequency that works well in combination with the use of an electronic VCO to generate higher frequencies. In some embodiments, controls may be provided to adjust a signal derived from the baseline reference frequency for further temperature compensation ("TCOCXO"). In embodiments implementing a MEMS resonator-based design, a "dual MEMS" resonator design is also not required for all embodiments; for example, other types of temperature sensors (including, but not limited to, those based on transistors, thermistors, diodes, or other structures) may be used. Furthermore, in some designs, the temperature sensor is not on the same die or substrate as the resonator.

[0030]

[0046] Because the oven temperature is controlled to remain constant, the timing signal 309 in the embodiment of FIG. 3A is highly stable, i.e., maintains a well-defined frequency despite changes in the ambient environment (e.g., the electronic device's internal or external environment). However, to enhance this stability, the illustrated OXCO also outputs a temperature-dependent signal 305 that is fed to a first PLL (i.e., outer PLL loop) 307 for temperature compensation, as previously described. Note that, as is common in PLL designs, the illustrated PLL 307 relies on the aforementioned DCO 313, feedback path, and divider, in addition to a phase detector (“PD”) and low-pass filter (“LPF”), to generate another timing signal 311 as an output; the PD, LPF, and feedback path / divider are not individually shown in FIG. 3A , although examples of these elements will be shown in some of the other figures.

[0031]

[0047] The DCO 313 has an overall configuration shown in expanded detail in FIG. 3A. As previously mentioned, this controlled oscillator, or DCO, of the first PLL 307 is provided by a second PLL 315 (i.e., a second, inner PLL loop) that is controlled as a function of signal 316. This second PLL 315 relies on a frequency reference signal from a second oscillator ("SXO") 319 and uses its own controlled oscillator 321 (i.e., which, depending on the embodiment, can be either another PLL loop or an electronic VCO). The second PLL 315 attempts to synchronize the signal generated from this controlled oscillator 321 to the frequency reference signal from the second oscillator ("SXO") 319, effectively implementing a filter that tracks noise from the SXO 319 at mid-range frequencies and noise from the oscillator 321 at high frequencies. The second oscillator 319 can optionally be based on a MEMS resonator design, even a temperature-compensated (“TC”) or “dual MEMS” design. It should be noted, therefore, that in some embodiments, a total of three, four, or more MEMS resonators can be used (e.g., two for the TCOCXO and two for the SXO). As shown, the second PLL optionally has a divider, which may be a fractional-N divider, referenced by numeral 323. As indicated by arrow 325, the controlled oscillator 321 relies in some way on an electronic VCO (i.e., LCVCO 329); in embodiments using more than two PLL loops, the controlled oscillator can be configured similar in design to the inner PLL loop 315, i.e., instantiating oscillator 321 as an additional PLL loop with its own controlled oscillator 327 dependent on LCVCO 329. Ellipse 331 indicates that additional PLL / oscillator stages can also be used, if desired. In this case, the fractional-N divider is optionally pushed down to the innermost PLL (e.g., the feedback loop of the third PLL). Similarly, an electronic VCO or other oscillator suitable for very high frequency generation can be pushed down to the innermost PLL loop.

[0032]

[0048] The effect of these design features is illustrated with reference to Figure 3B, which plots frequency stability / phase noise as a function of output timing signal frequency in a graph generally designated by the numeral 331. In the figure, various noise profiles are represented by lines with different dashed patterns, and will be referred to below to explain the advantages that may be obtained with the structure introduced above. First, note that while these various noise profiles are shown as a series of straight lines for purposes of discussion, they are actually curves with gradually varying slopes that very roughly match the line patterns shown in Figure 3B.

[0033]

[0049] A PLL of a conventional VCO-based design is represented by curve 333, which generally follows point ABC. As can be seen from this curve, such PLLs typically perform with low phase noise at high frequencies but experience increased instability when applied to generating lower-frequency timing signals. In contrast, a conventional MEMS resonator-based oscillator has a phase noise characteristic shown by curve 335, which generally follows point DEF. In a system relying on a MEMS resonator-based oscillator with a VCO-based PLL, the output signal noise characteristic generally follows path DEKBC; that is, at PLL frequencies below the PLL loop speed (represented by point K), the PLL generally passes the phase noise of the MEMS resonator-based oscillator, while the VCO phase noise dominates at higher frequencies. Opening this PLL generally improves the frequency stability of the MEMS-based oscillator, resulting in a noise plot shifted to the left relative to line 335. For example, the use of a MEMS-based TCOCXO in accordance with the embodiments discussed herein results in a noise plot that generally tracks line 337, which follows path GHI in the diagram. As shown above, by using a nested PLL structure, a system can be effectively designed to switch oscillator sources for frequency stability purposes, e.g., the noise plot can be made to generally track points G, J, E, K, B in the diagram. As seen by the shaded parallelogram D, J, H, G, and H, this significantly improves phase noise, especially at low frequencies, compared to designs with only a single PLL loop. At PLL frequencies below the loop tracking speed of the "first" or outer PLL loop, represented by point J in the diagram, the low phase noise of the TCOCXO dominates, while at PLL frequencies between points J and K in the diagram, the phase noise of the traditional MEMS-based resonator oscillator dominates (e.g., from the second oscillator SXO in FIG. 3A ). Finally, as with conventional designs, at high frequencies above the frequency represented by the location of point K in the diagram, the phase noise of the traditional electronic VCO dominates the output of the nested PLL structure.It should be noted that additional PLL loops and associated oscillator stages can be added as needed; for example, using the principles discussed, an optional first additional PLL loop can be used to switch in an oscillator having noise characteristics generally represented by line 339, where the same PLL loop bandwidth considerations just discussed can be applied to eliminate phase noise within second shaded region 341 (represented by parallelogram JNML) and result in a noise plot that generally tracks point GHLMNEKBC. Such additional PLL loops could instead be designed for higher loop bandwidths, per line graph 343, i.e., to eliminate phase noise associated with third shaded region 345 (represented by parallelogram KQPO); of course, it is possible to do these two things together, i.e., have four or more nested PLL loops, and have the nested PLL output generally track the lowest phase noise level represented in FIG. 3B throughout the frequency range of interest.

[0034]

[0050] By providing a timing signal generator design that generally reduces phase noise and has stable frequency characteristics across the entire frequency range of interest, the present embodiments provide a design that is particularly suited to the requirements of some newer digital platforms, which require wide-range frequency synthesis. For example, it has already been mentioned that newer devices typically require the generation of many timing signals, often at widely differing frequencies. Frequency synthesizers are often designed to generate a baseline frequency and then multiply and / or divide it to generate any desired timing speed, from very low to very high frequencies. As noted above, conventional circuit designs often result in excessive phase noise somewhere in the desired frequency spectrum. By promoting a design that generally minimizes phase noise across the entire frequency spectrum of interest, the embodiments presented herein address the issues already addressed and provide greater frequency stability across a wide frequency range, e.g., from less than 1 hertz (<1 Hz) to tens of gigahertz ("GHz").

[0035]

[0051] 3C shows another embodiment 351 of a timing signal generator that can achieve these goals. As shown, an oven-controlled oscillator ("OCXO") 353 generates a first frequency reference signal 355 (shown as φ ref ) for comparison by phase detector ("PD") 361. Regarding dashed (optional) box 357, the OCXO is also optional and is a MEMS-based oscillator based on the "dual MEMS" design seen in the figure, although again, this is not required for all embodiments. Frequency reference signal 355 is fed to a fully digital PLL 359. This digital PLL 359 includes a digital phase detector ("PD") 361, a digital low-pass filter 363, a digitally controlled oscillator ("DCO") 365, a feedback path 367, and a frequency divider 369 in the feedback path. The frequency divider receives an output signal 371 from the DCO and, depending on the control of divider 369, increases or decreases the frequency of this signal, which provides a signal 373 for comparison by phase detector ("PD") 361 (this feedback signal 373 is shown as φ fb1(denoted as ) . Control of divider 369 in this embodiment is dependent on a signal from a temperature compensation circuit and a control input 379, respectively. As noted above, temperature compensation may be omitted in some embodiments, or control 379 (e.g., a frequency synthesis control) may be incorporated elsewhere in the system. PD 361 compares the phase of OCXO output 355 with the phase of feedback signal 373, and provides impetus for the DCO to increase or decrease the frequency of signal 371 depending on whether feedback signal 373 lags or leads frequency reference signal 355. Thus, when a higher frequency is desired to be generated (e.g., as a function of control block 379), the division denominator increases, causing DCO 365 to generate a higher frequency output. Conversely, when a lower frequency is desired, the division decreases (i.e., the feedback frequency increases), causing the DCO to decrease the frequency of its output. As mentioned above, frequency divider 369 (in this embodiment) is also driven based on temperature signal 375 from the OCXO, so that feedback signal 373 offsets temperature variations by slightly increasing or decreasing the DCO frequency. In this regard, temperature compensation (“TC”) circuit 377 generates a digital control signal used to control the frequency divider by referencing a correction factor or other temperature compensation to apply the appropriate amount of correction. Note that temperature compensation can take the form of circuitry implementing an analog or digital polynomial, or simply retrieving a set value from a look-up table, indexed or otherwise, according to variations in signal 375. Because the DCO is a fully digital design in this embodiment, control signals 380A / 380B can be digitized if they are not already in digital form.

[0036]

[0052] The signal from DCO 371 is conditioned for output by processing circuitry 381 and optionally used to generate any number of timing signals for output, e.g., at fixed or programmable variable frequency and / or phase separation depending on the embodiment, represented by oval 382 and the acronym φ for the timing signals. 1-Z These optional timing signal outputs φ 1-Zcan represent common or different harmonics as required, that is, in one embodiment, a plurality of timing signals having a predetermined phase and / or frequency relationship are output, and in another embodiment, the parameters of one or more of these timing signal outputs (e.g., each timing signal) can be set independently.

[0037]

[0053] DCO365 is implemented here as the inner loop of the nested PLL structure, similar to the embodiment introduced in FIG. 3A. In the design of this figure, the inner PLL loop within DCO365 is seen to include an analog phase detector ("PD") 383, an analog low-pass filter ("LPF") 384, a control oscillator 385 for the second PLL loop, and a fractional-N divider 387 within the feedback path of the loop. The output of LPF363 from the digital (outer) PLL loop 359 is used to control the feedback path of this inner PLL loop, which has the effect of driving frequency generation by the DCO based on the noise profile of the second oscillator ("SXO") 389, and at higher frequencies, the phase noise from the control oscillator 385 dominates. In this regard, the analog PD385 compares the phase of the second frequency reference signal 390 from SXO389 with the feedback signal 391 from the fractional-N divider such that adjustment of the divider raises or lowers the speed of the internal PLL's feedback loop, that is, achieves this selection. In this embodiment, the SXO is seen to be also based on the use of a MEMS resonator, and as shown in the figure, this resonator can optionally be a temperature compensation design ("TCXO") and / or a dual MEMS design indicated by numerals 392 and 393. When using the TCXO design, the temperature sensor can be implemented using the same or a different architecture as that described above for OCXO353, for example, it can be a "dual MEMS" structure, or it can be based on the use of a thermistor, diode, transistor, dual MEMS, etc. to measure temperature. Note that it is within the scope of those skilled in the art to select the components necessary to achieve the frequency stability and / or phase noise and / or power requirements for a particular application.

[0038]

[0054] As indicated by the text in controlled oscillator 385, the controlled oscillator may again optionally be an electronic VCO (e.g., an LCVCO). Thus, the illustrated design effectively uses each oscillator—i.e., OCXO, SXO, and LCVCO—for the frequency range in which each oscillator is most efficient for frequency stability. As indicated by oval 394, it is possible to have more than two PLL loops, i.e., one or more additional inner PLL loops, each with its own reference oscillator 395, are used to provide controlled oscillator 385; again, one or more of these may optionally be based on a MEMS resonator architecture 397 and / or a TCXO architecture 398. In the illustrated architecture, the electronic VCO is advantageously relegated to the innermost loop, as indicated by reference numeral 399, because, of the presented options, the electronic VCO has the most suitable phase noise characteristics for higher frequency synthesis. If another type of oscillator works best at very high frequencies, that oscillator can be used as the controlled oscillator source for the inner loop of a nested PLL structure, moving the electronic oscillator elsewhere in the PLL loop hierarchy.

[0039]

[0055] As previously referenced, some embodiments provide particular die configurations that can be used in combination with the various structures introduced above. FIGS. 4A through 4E are used to illustrate some of these configurations. First, these various figures show die-to-die electrical connections and mounts in the form of solder bumps; however, it should be noted that the use of solder bumps in the figures should be understood as a graphical proxy for any type of electrical connection; for example, in some embodiments, wire bonds or other connection types may be used, and / or a mix of connection types including solder bumps may be used. It should also be noted that the structures seen in FIGS. 4A through 4D may optionally be further mounted on some type of substrate and / or packaged, encapsulated, or hermetically sealed, such that they may be sold as integrated, self-contained devices (e.g., packaged frequency synthesizer and / or clock generator integrated circuits (“ICs”)). Such packaging and / or encapsulation are considered to be optionally included in the configurations represented in FIGS. 4A through 4E.

[0040]

[0056] FIG. 4A shows a first configuration 401 having a circuit die 403, a first MEMS die 405, and a second MEMS die 407. Each MEMS die can have a resonator mounted in an internal cavity, e.g., in a sealed environment, and these dies and associated resonators can optionally be processed using different process technologies (e.g., one can be a piezoelectric resonator, the other can be electrostatic, lidded and vented, “single MEMS” / “dual MEMS,” ceramic / plastic encapsulation, and / or bonded lid designs, etc.). In other embodiments, the same or similar process technologies and / or architectures can be used for each MEMS die. The first MEMS die 405 in this embodiment is likely to include thermal insulation to provide thermal insulation; for example, the first die is equipped with an oven 409 having an internal heating element 411 for oven control. Note that these elements of the OCXO design are shown only for the first MEMS die 405 but can be replicated for any MEMS die discussed herein (e.g., any MEMS die shown in any of FIGS. 4A-E and / or other figures). Note that the thermal isolation, represented by numeral 409, can be any suitable material, but in some embodiments, a ceramic material is used to provide the thermal isolation. For simplicity, oven details have been omitted from the remainder of these figures. Each of the MEMS dies 405 / 407 is then seen to be directly mounted to / electrically interconnected with the circuit die 403, e.g., via one or more of solder bump connections 413A, 413B, 413C, and 413D. In this embodiment, the circuit die provides the majority of the processing circuitry for operating the various MEMS devices and providing the nested PLL structure described above.

[0041]

[0057] Thus, while conventional wisdom might suggest that a cascaded PLL architecture, typically in a separately packaged and independently implemented structure, requires a complex multi-IC configuration, some embodiments of the present invention can dramatically reduce this level of complexity by combining one or more of the following with any permutation of these various circuit elements: (1) drive / sense circuitry for each oscillator on a common circuit die (e.g., die 403) or a small number of such dies; (2) circuitry for multiple PLL loops (e.g., analog PLLs and digital PLLs as described in some embodiments herein) on a common circuit die; (3) sense / drive circuitry for one or more PLL loops of a nested PLL structure described herein and one or more MEMS resonators on the common circuit die; and / or (4) oven control and / or temperature compensation circuitry described herein. As a non-limiting example consistent with the depiction of FIG. 4A , the ability to intermix circuitry for each of these elements on common circuit die 403 allows MEMS dies 405 / 407 to be directly implemented on this common single circuit die, resulting in a compact footprint and / or high integration density. As previously mentioned, and similar to other embodiments discussed herein, such devices (e.g., "die stacks") may optionally be packaged and sold as standalone devices, such as a single packaged integrated circuit ("IC") having multiple dies as shown at 415, and such devices may optionally be encased in plastic 416 and / or alternatively packaged as a unitary structure on a common substrate or lead frame, for example, as represented by numeral 417.

[0042]

[0058] 4B illustrates an alternative configuration 421, i.e., a configuration in which a MEMS die is mounted directly or indirectly via other dies above or below a circuit die and / or common substrate 403. While the optional use of packaging and / or additional substrates has been omitted here for simplicity, it should be noted that in each of the embodiments discussed herein, the structures can be packaged together in a common IC die stack, for example, as just shown. As depicted in the figure, the first MEMS die 423 can be either of the MEMS resonator dies / systems introduced above (e.g., OXCO or SXO), while the second MEMS die 425 can be the other of these two, as represented by the term “Digital 1 or 2” appearing in the figure. A first MEMS die 423 is seen to be attached to the circuit die and / or substrate 403 via a first set of solder bump mounts 427A-427B, while a second MEMS die 425 is attached by a different set of mounts 429A-429B, e.g., on the opposite side of the circuit die 403. Note that while two such solder bump mounts are shown, in reality many more exist (and are blocked in this view). For example, a typical OCXO MEMS die may have six or more pins, e.g., for drive force, sensed resonator output, resonator bias voltage, oven control (e.g., pins for receiving analog and / or digital oven control signals, or multiple such signals), and, if necessary, pins for establishing voltage supply rails (e.g., V ... dd and / or V SS / ground). A typical SXO die may have a V バイアスIt may have only three pins, such as for use and for a sense or drive signal interface. However, in order to promote a compact installation area, it is advantageous for each die to be designed to use a minimum number of pins and / or connections for mechanical support and electrical interface, although the number of such pins / connections will depend on the embodiment (e.g., as just shown, in various embodiments, each resonator may be based on an electrostatic, piezoelectric, two-port, and / or other design). Similar to other features discussed herein, the mechanical and / or electrical interconnection options discussed with respect to FIG. 4B can be used in any of the configurations seen in FIGS. 4A through 4E, or in other figures described herein.

[0043]

[0059] 4C shows yet another configuration 431, this time using two circuit dies or substrates, namely 433 and 435. As clearly indicated in the figure, either of these substrates can be CMOS-based or BiCMOS-based circuitry; for example, in some manufacturing processes, it may be more efficient to have a first die dedicated to BiCMOS circuitry (e.g., fabricated using a process technology specific to the BiCMOS die) and a second die dedicated to a different process technology (e.g., a specific CMOS process technology). In the illustrated configuration, for example, the first MEMS die 423 in one embodiment is an OCXO resonator die, the BiCMOS die provides support circuitry such as charge pumps and heater control circuits for this OCXO resonator die, and the second MEMS die 425 can represent a non-OCXO resonator design, for example, supported by purely CMOS circuitry. In such a configuration, both BiCMOS and CMOS circuitry are used to support the OCXO implementation, with the first MEMS die 423 being mounted in a stacked arrangement directly to the BiCMOS die (433) and through that to the CMOS die (435) via solder bump mounts 437A-437B and 438A-B, and the second MEMS die being mounted directly to the CMOS die (435) via solder bump mounts 439A-B. While this configuration shows BiCMOS circuitry being used only on the first MEMS die 423, in reality, one or both dies may be supported by circuitry on either die, with electrical interconnections made using either die as an intermediary (as appropriate for the application), and conversely, each circuit die 433 / 435 may comprise circuitry supporting one or both of the MEMS dies 423 / 425. As shown, the use of BiCMOS or CMOS technology is optional; that is, in a given embodiment, the circuit dies shown may both be CMOS or BiCMOS dies, and in another embodiment, both dies may represent the same or different process technologies.It is also possible to have more than two circuit dies and more than two MEMS dies, e.g., MEMS dies share circuitry on a given circuit die as needed, and there are more than two circuit, resonator, or other dies.

[0044]

[0060] 4D-4E each show an additional "dual circuit die" configuration, generally designated 441 / 451 in each figure. Each of these configurations also includes two MEMS dies, each of which can be designed to support an OCXO, TCXO, or XO configuration, as appropriate, but here all four dies 423 / 425 / 433 / 435 are shown stacked together in a configuration. In FIG. 4D, MEMS dies 423 / 425 are stacked on either side of the circuit die. In FIG. 4D, these various dies are seen interconnected using respective solder bump mounts 443A-443B, 445A-445B, and 447A-447B. In Figure 4E, MEMS die 423 / 425 are stacked on top of one another (e.g., die 425 may have through-silicon vias that allow each of these dies to be stacked directly on top of one another), with each die in this figure interconnected using solder bump mounts 453A-453B, 455A-455B, and 457A-457B. Although not specifically shown here, interleaved die arrangements are also possible; e.g., MEMS / circuit / MEMS / circuit is a special case of the embodiment shown in Figure 4B. As these examples illustrate, nearly any permutation or combination of die arrangements can be used to achieve a compact footprint and / or integrated device, e.g., all of which are facilitated using the novel techniques presented in this disclosure.

[0045]

[0061] 4A-4E each show two MEMS dies, it should be noted that any one of these dies may have multiple MEMS resonators (e.g., any one or more of these dies may be fabricated to support a "dual MEMS" resonator design, resulting in two, three, or more resonators, for example, in the same or different cavities or chambers within the die). Also, in connection with some of the embodiments discussed above, a given MEMS die may have other circuitry, such as an integrated heating element (as shown in FIG. 4A), a temperature sensor, an electrostatic discharge structure, and / or other elements present on the same MEMS die.

[0046]

[0062] FIG. 5A is a diagram used to illustrate an OCXO embodiment 501, which includes a MEMS die 503 having both a MEMS resonator and a temperature sensor. A first MEMS resonator is used to provide an oscillating signal 505 representing the sensed resonant frequency of the resonator. A second MEMS structure forms part of a temperature sensor (“TS”); as discussed elsewhere herein, such a sensor may generally be a second MEMS resonator (i.e., operating in conjunction with the first MEMS resonator), a MEMS thermistor or other type of thermistor, a diode, a transistor, or other structure. Accordingly, the MEMS die 503 also outputs a second signal 507 that is temperature dependent and varies with the operating temperature of the first MEMS resonator (i.e., signals 505 and 507 represent characteristics generated at the exact same temperature, preferably because the temperature sensor is in close proximity to this primary MEMS resonator). These signals are processed as needed to generate a reference frequency signal (f ), as indicated by numerals 509 and 511. r) 517 and a temperature signal (T). The temperature signal is provided as feedback to oven control circuit 513 and is used to drive the oven to maintain a constant temperature, as previously described (i.e., according to control arrow 515). Because the oven is controlled so that the resonator always operates at or near a constant temperature, reference frequency signal 517 is relatively stable. As indicated by dashed structures 518 and 519, the temperature signal can also optionally be used for further temperature compensation of the output reference frequency signal (e.g., thereby implementing a TXOCXO), as will be further illustrated below.

[0047]

[0063] 5B illustrates a TCXO embodiment 521 based on the use of a "dual MEMS" architecture. A MEMS die 523 includes a first MEMS resonator 525 and a second MEMS resonator 527, one of which is designed to operate in a relatively temperature-invariant manner and / or with a resonant frequency that is easily modifiable with temperature (i.e., a "temperature-flat" resonator), while the other of which is designed to have a temperature that varies significantly but linearly with temperature changes (i.e., a "temperature-sensitive" resonator). In this regard, methods for fabricating various types of MEMS resonators that can function as these devices (or as other resonators described herein) are well known to those skilled in the art; see, for non-limiting examples, U.S. Patents ("USPT") 9,774,313, 9,712,128, and 10,696,547. As described therein, MEMS resonators, and / or MEMS resonators and other types of temperature sensors, can be fabricated side-by-side on the same chip in a manner that promotes thermal coupling between them, and techniques are used to specifically engineer the resonator's operating parameters, i.e., design variables such as the resonator's dimensions (size, shape, thickness, length, width, etc.), the relationship of those dimensions to the underlying axes of the single-crystal silicon, doping impurities and relative concentrations, the use of other materials in the design, and many other variables, resulting in precise engineering of temperature-dependent performance. Numerous MEMS resonator designs exist in the art, and existing working examples of dual MEMS resonators and related designs may be found in SiTime Corporation's fabricated products and datasheets (generally available at www.sitime.com). In one embodiment, one or more of the resonators shown in FIG. 5B (and / or other figures) may be electrostatic resonators, and in another embodiment, one or more of them may be piezoelectric resonators. Despite the term "temperature sensing," the signals 529 / 531 from each MEMS resonator are combined to calculate a measure of absolute temperature. Circuitry 533 receiving these signals calculates the divergence of these frequencies (e.g., by taking their ratio or by other means) to generate output signal 535, which directly represents the sensed absolute temperature.This signal 535 is then fed into a look-up table (i.e., to index a programmed temperature correction factor) or applied to circuitry to derive a temperature correction signal 537. This temperature correction signal is then used to generate a temperature compensated frequency output signal (f tc ) 539, the resonant frequency signal (f r ) 509 is supplied to a temperature compensation circuit 538 that corrects the r and / or f tc can be used as the frequency reference signal for the PLL, depending on the design. The temperature compensation circuitry is typically downstream of the circuitry that drives the resonator, e.g., in a downstream PLL, although this is not required in all embodiments, such as temperature compensation schemes that call for adjusting the drive signal used to excite the resonator (i.e., performing the compensation in a "sustain circuit") as discussed above, or designs that adjust the bias voltage of an electrostatic resonator to mitigate frequency variations that are a function of temperature changes. Other designs / configurations are possible.

[0048]

[0064] As noted above, while some embodiments use a "dual MEMS" resonator design for the OCXO, other embodiments may also, or instead, use a "dual MEMS" architecture as a reference for an SXO, or indeed for a third-order or higher stage, to generate a frequency reference. Other embodiments do not use a "dual MEMS" architecture, but may instead use a MEMS resonator plus a thermistor (or other temperature sensor) design, as discussed in connection with FIG. 5A . Finally, in still other embodiments, a PLL reference signal may be generated using a conventional oscillator structure (e.g., quartz crystal, electronic, etc.) for one or more PLL loops.

[0049]

[0065] FIG. 5C shows an example "dual MEMS" design 541 that is similarly ovenized and can therefore be used as a reference for the TCOCXO of FIG. 1A (or other embodiments discussed herein). As with the design shown in FIG. 5B, the MEMS die 523 again has two or more MEMS resonators arranged, for example, side-by-side on a common die, in a manner that promotes thermal shorting between the "TF" and "TS" resonators. Oven control circuitry 543 generates a control signal 545 that is applied to a heating element 546 to regulate the oven temperature. This design produces a reference frequency output (f) that has little to no temperature-dependent variation, i.e., because the oven temperature is not allowed to vary to any appreciable extent. r ) 547. Nevertheless, circuit-based temperature compensation is also applied, as represented by temperature compensation block 549, and the result is a temperature compensated frequency output signal (f tc) 539. A control signal for controlling the frequency compensation is generated by circuitry, which may be an analog or digital signal based on a look-up table (“LUT”) and / or a polynomial, and may be generated, for example, by circuitry 555, as a function of the divergence of the resonant frequencies of the two MEMS resonators. As indicated in the legend appearing in the figure, additional temperature compensation is applied to the frequency reference signal generated by the oven, thereby relaxing the design and / or operating requirements of the oven; for example, it is less important to precisely place the oven and / or any resonators at their turnover temperatures; optionally, the first MEMS resonator shown is designed to have a resonator turnover temperature that is approximately 15° C. higher than the maximum expected operating temperature, and optionally, oven control circuitry 543 is configured to use this temperature as the oven setpoint. As this discussion suggests, in some embodiments, the oven temperature can be set higher or lower than the turnover temperature of the resonator used for frequency generation. In practice, during the manufacture of each particular product (or possibly an entire class of products), the product is surveyed while heating element 546 is cycled at various temperatures, which is used to generate (1) programmable parameters for oven control circuit 543 (i.e., which are then programmed into the circuit and / or supporting memory), and (2) frequency compensation and / or filter parameters (e.g., including data for LUT and / or polynomial circuits, with the resulting data also being programmed into the circuit or supporting memory). Advantageously, the design includes non-volatile memory ("NVM"), not visible in this figure, used for this purpose.

[0050]

[0066] FIG. 6 illustrates an even more detailed embodiment 601 showing some of the unit and die relationships in a particular design. Similar to some of the previously discussed embodiments, this design appears to assume the use of an OCXO 603, an SXO 605, and a nested PLL structure with two PLL loops, including, in this embodiment, a first outer (digital) PLL loop 607 and a second inner (fractional-N, analog) PLL loop 609. These design elements are generally shown with dashed lines to indicate various components, including circuitry (e.g., which elements are associated with the OCXO), that may reside on one or more different dies. FIG. 6 also illustrates the juxtaposition of different die configurations, including a configuration with a first MEMS die 611 (i.e., with one or more resonators in an oven, e.g., ceramic oven chamber 613) and a second MEMS die 615. In this embodiment, the first MEMS die 613 is seen to be a dual MEMS design with each resonator configured as a set of four rings formed at either end of a cross structure, while the second MEMS die 615 is seen to have a single MEMS resonator of a similar structure. In other embodiments, different resonator designs can be used. These various MEMS dies in one configuration are each mounted directly to the CMOS die 617, for example, by solder bump mounts 619; the depictions of these solder bump mounts in the figures should again be considered symbolic; for example, these depictions may represent wire bonds or other conventional types of connections in addition to or instead of the use of solder bumps shown. 6 also refers to a second alternative configuration, i.e., instead of using a single circuit die 617, two circuit dies 621 and 623 can be used instead, including a first circuit die 621 having BiCMOS elements (e.g., used to control the OXCO) and a second die 623 dedicated to CMOS elements used to support the OCXO 603, the SXO 605, the first (outer) PLL loop 607, the second (inner) PLL loop 609, and all of the other circuitry. As previously discussed, other die configurations can also be used.

[0051]

[0067] As seen on the left side of the figure, elements used to support and form part of the OCXO include a heating element 625, a charge pump 627 that drives the heating element, a heated digital-to-analog converter ("DAC") 629, a sense circuit 631, and a sustain circuit 633. As indicated by the optional presence of BiCMOS die 621, these elements may optionally be configured as BiCMOS elements. Alternatively, as indicated by numeral 617, these elements may be implemented in CMOS (e.g., as part of a single die 617). In the case where a dedicated circuit die for the OCXO (or other oscillator type) is used, as represented by numeral 621, such circuit die may be mounted to die 623 (or a common substrate) via a series of solder bump mounts 635. The heating element 625 is used for oven control during normal operation, and in some embodiments, the heating element 625 can also be used for thermal characterization (e.g., to identify and program oven control data, temperature compensation data, and / or other operating parameters, i.e., as part of a calibration operation performed at the factory, after manufacturing, after packaging, and / or in the field) and / or to tune / adjust one or both resonators, for example, using a Joule heating process that changes the resonator dopant properties (see, e.g., USPT 9712128). In some embodiments, the heating element 625 can comprise multiple individual heating devices, for example, one for oven control, one for thermal cycling, and one for Joule heating of each resonator and corresponding adjustment / tuning of the individual resonators, although other configurations and combinations of these structures are expressly contemplated. The charge pump 627 can be used to generate high heat levels for any of these processes. Heating DAC 629 receives a digital serial or parallel word signal (e.g., via solder bump mount 635) that is used to individually address each heating device (if desired) and generate variable amounts of heat as needed. Finally, sense circuit 631 and sustain circuit 633 are used to sense the resonant frequency of each resonator on die 611 and excite the resonator into resonant operation, respectively.

[0052]

[0068] When an OCXO circuit die is used, the illustrated solder bump mounts 635 again provide minimal tweezers for driving the OCXO, and as shown, these typically include at least one digital signal 637 for controlling the heating element, one or more voltage supply rails 639A / B (i.e., labeled "V" and "GND" in the diagram), and respective resonator frequency outputs 641 and 643 ("f res2 " and "f res1 "). Some embodiments may also use a controllable or adjustable bias voltage (e.g., in the case of an electrostatic resonator design). In this regard, the CMOS device on die 617 or die 623 includes a series of circuits used to support the OCXO, including (depending on the configuration) oven control circuit 647, circuit 649 for determining temperature from the resonator signal, and temperature-to-digital converter 651. In the illustrated embodiment, oven control circuit 647 controls heating elements 625, including each constituent heating device, as needed by generating digital signals that are then sent to heating DAC 629; these control signals may be parallel digital signals or sent via a serial interface (e.g., one or more pins), depending on the configuration. Again, the oven control circuit controls the amount of heating in connection with the application the OCXO supports, including maintaining a setpoint temperature during normal operating modes, thermal cycling for device characterization, and / or adjustment / tuning processes, as discussed above. The logic that is part of the oven control circuit, as well as other elements discussed herein, may include dedicated, special-purpose hardware or a combination of general-purpose hardware circuitry and instructional logic referenced elsewhere herein. The temperature determination circuit 649, as referred to elsewhere herein, generates a two frequency signal "f res1 " and "f res2" to determine the absolute temperature, which temperature-to-digital circuit 651 then converts into a set of digital control values ​​653, which are provided as feedback to oven control circuit 647 to obtain the precise absolute temperature within the oven. As indicated by arrow 655, oven control circuit 647 also receives values ​​representing learned oven control parameters from on-board memory 658 (e.g., NVM) for use in normal operation and optional configuration (e.g., for use in thermal cycling / device characterization and / or tuning / adjustment processes). If desired, the signal representing the absolute temperature can optionally be provided to an external output (e.g., for provision to a microprocessor or digital device or other element of the system for downstream use / application), as indicated by numeral 661 at the bottom left of the diagram. Memory 658 also receives programming of learned temperature compensation data (e.g., via external pin 659) that is used to control further temperature compensation subsequently performed by the TCOCXO design during calibration mode. This same pin or another pin 663 can also be used to receive a signal representing the active frequency selection that the system stores in a register 657, which can be implemented using any suitable memory technology, including but not limited to random access memory (“RAM”), the NVM mentioned above, or a different technology. For active temperature compensation of the frequency output by the OCXO, a LUT or polynomial is implemented using the learned TC parameters from memory 658, and the temperature compensation data is then passed to a filter 669, after which, in block 671, the temperature compensation is combined with the active frequency selection parameters stored in the register to generate a first control signal 672 for controlling the digital (outer) PLL loop 607.

[0053]

[0069] The digital (outer) PLL loop 607 includes a digital phase detector (“PD”) 673, a digital low-pass filter (“LPF”) 674, a digitally controlled oscillator (provided by the second PLL loop 609), a frequency divider 675, and a delta-sigma modulator 676. The PD 673 receives a signal 677 (f res1) and a feedback signal 678 generated by a divider 675. Briefly, the output of PD 673 is filtered and, depending on whether signals 677 and 678 are synchronized, controls the DCO (fractional-N, inner PLL loop 609) to increase or decrease the generated frequency. Divider 675 can be an integer and / or fractional divider. This divider is controlled in response to signal 672 and performs both frequency scaling and temperature compensation. If a lower frequency is desired, the divider effectively divides more to delay the feedback signal 678; thus, outer PLL 607 delays the DCO / inner PLL loop 609 in an attempt to synchronize the two, resulting in a lower frequency at timing signal output pin 679. Conversely, if a higher frequency output is desired, divider 675 uses a smaller value and the outer PLL loop attempts to speed up the DCO / inner PLL loop 609. When the timing signal output 679 is at a low frequency, the phase noise (and frequency stability) of the OCXO is passed through and dominates the timing signal output (i.e., has the ultra-stable characteristic of a TCOCXO), but as this frequency increases, the digital (outer) PLL loop 607 will dominate this output with the phase noise of the DCO (i.e., inner PLL loop 609). Note that the timing signal output is conditioned by processing circuitry 681, including, for example, a driver suitable for off-chip / off-device transmission via pin 679, and although a single pin is discussed in this document, the use of number 679 contemplates that differential and / or other signal formats may also be provided (i.e., by respective pins).

[0054]

[0070] SXO 605, as previously mentioned, provides a frequency reference input signal 683 (f res3) and this analog loop is digitally controlled, i.e., functions as a DCO. The SXO includes sense circuitry 684, processing circuitry 685 which generates signal 683 as an output, and sustain circuitry 686 which is used to maintain resonant operation of the MEMS resonator in the second MEMS die 615. Electrical connections to this die include drive and sense signals, as well as voltage bias signals (e.g., again in the case of an electrostatic resonator design); as previously indicated, the second MEMS die 615 could alternatively be of a piezoelectric resonator design. As shown, this support circuitry for the SXO is typically on the primary circuit die (i.e., 617 or 623), which in this embodiment includes at least support circuitry for each of the OXCO 603 and SXO 605, and each of the PLL loops 607 and 609 for oven control and temperature compensation. In one embodiment, the SXO is designed to generate significantly higher frequencies than the OCXO. For example, in one embodiment, 35 MHz and 32 MHz resonators may be used as the temperature flat ("TF") and temperature sensitive ("TS") resonators in a dual MEMS design, while the SXO may include a resonator designed to generate an oscillation signal between 75 and 80 MHz.

[0055]

[0071] The inner PLL loop 609 is shown in the figure as having an analog phase detector (“PD”) 689, an analog low-pass filter (“LPF”) 691, an electronic VCO 693 (e.g., an LCVCO), and a fractional-N divider 694. The analog PD 689 receives a reference signal 683 from the SXO 605 and attempts to drive the electronic VCO (via the LPF 691) to increase or decrease the frequency of the signal 695 until a feedback signal 697 from the fractional-N divider 694 is synchronized with the reference signal 683. The fractional-N divider 694 is then controlled by a variable frequency output 698 from the outer (digital) PLL loop 607. As a result, the fractional-N divider is controlled to increase or decrease the frequency of the signal 695 as a function of the output of the digital LPF 674 from the first (outer) PLL loop 607.

[0056]

[0072] At low frequencies, the OCXO phase noise dominates the frequency output 679 as previously described, while at higher frequencies, the DCO (inner PLL loop 609) phase noise begins to dominate. The DCO phase noise tracks the SXO phase noise at frequencies below the loop speed of the innermost PLL loop 609, and at higher frequencies tracks the phase noise of the electronic VCO 693. Thus, the illustrated circuit design effectively switches between three or more different oscillators, depending on which has the best frequency stability characteristics at a given clock generation frequency, using a nested PLL structure configured as shown.

[0057]

[0073] Returning momentarily to FIG. 3B , note that the effect of this operation is to reduce phase noise (i.e., improve frequency stability) over a wide range of operating frequencies. The illustrated circuit design essentially causes the timing generator of FIG. 6 to roughly follow the phase noise pattern GHJEKBC seen therein. If frequency reference signals of 35 MHz and 78 MHz are generated (according to the exemplary resonator frequencies discussed above), points J and K will roughly correspond to these two frequencies. Thus, a skilled designer can apply these principles to optimize frequency stability over a wide range of frequency generation, for example, by designing MEMS (and / or other) resonators as needed and by using the switching structures discussed, to design phase noise sources at specific frequencies for a given timing signal generator design. As a non-limiting example, if a designer hypothetically wants points J and K in FIG. 1B to be at 5 MHz and 125 MHz, the resonators are simply designed to achieve these results, and as noted above, this can be done in a relatively straightforward manner using MEMS resonators as the basis for at least part of the design. As mentioned, further gains in overall phase noise can be obtained by optionally including additional PLL loops in the nested PLL structure as needed, for example to generally follow the pattern GHLMNEOPQBC when using four PLL loops, and again these can be designed as needed to customize the phase noise / frequency stability in a way that is best seen to suit a particular application.

[0058]

[0074] FIG. 7A illustrates an architecture with a device 701 that may apply multiplication and / or division factors at various points relative to a given stage PLL 703; for example, the illustrated PLL could be any of the PLLs in any of the embodiments discussed above. As previously indicated, a reference frequency signal 705 is used as an input to the PLL. In one possible variation, this reference frequency signal 705 can be generated by an on-board oscillator “X” 705 (which, for example, as previously discussed, may optionally be based on a single or dual MEMS resonator structure and / or a DDS circuit). In other embodiments, the reference frequency signal can be generated off-device (e.g., off-chip) and provided as an input (e.g., via a pin or other die-attach mechanism). As indicated by ovals (numbers) 709 and 710, there may be other circuits, such as one or more “upstream” PLLs and / or one or more “downstream” PLLs (e.g., in series, parallel, cascade, or other configurations), that receive, process, and / or provide these signals. Whether or not such additional PLLs are present, the illustrated PLL 703 includes a feedback loop 711 that optionally multiplies / divides the generated frequency, for example, generated by oscillator "Y" 713 (which is a controllable oscillator that functions as the PLL's VCO); as can be seen, the optional multiplication / division factor is represented by the quantity k1 / k2, indicating that any value, whether unitary, integer, fractional, or otherwise, can be used to scale the feedback signal. Optional structures 715 and 717 (representing multiplication / division factors k3 and k4, which again may be integer, fractional, or otherwise) can be used to provide PLL and / or frequency control outside the feedback path. The illustrated PLL provides a generated frequency output (φ out ) or produces an output 719 that can be processed by another downstream circuit.

[0059]

[0075] FIG. 7B illustrates an embodiment 751 that uses at least one MEMS-based resonator as part of an open-loop direct digital frequency synthesis (“DDS”) circuit 753. Note that, optionally, non-MEMS-based resonators can be used, and / or the MEMS-based design can be implemented as an OCXO, TCXO, TCOCXO, and / or dual-MEMS structure, as referenced in the text at block 754 of the diagram. In the illustrated design, an open-loop DDS is used to generate a reference frequency signal (which typically works well at relatively low frequencies), and the VCO of a downstream PLL is driven to match the frequency of the timing signal generated by the DDS circuit 753, so that the various PLL loop speeds provide a cutoff that causes the generated output (759) to track only the phase noise of the DDS circuit 753 at low frequencies. Advantageously, in some optional embodiments, the output of the open-loop DDS circuit 753 is ultimately fed to a PLL 755 having an LC oscillator 757 as its VCO. From a consideration of the previous embodiment, it can be seen that LC oscillators typically work well when applied to high frequency generation, and in the illustrated design, the loop bandwidth of PLL 755 is such that the (better) phase noise characteristics of the LC oscillator are obtained at the output (φ out , 759). Note that there may optionally be one or more intermediate-stage PLLs 761 (i.e., located between the open-loop DDS circuit 753 and the "jth PLL" shown in the figure, which may feature, for example, the use of additional oscillators). Note that in this embodiment, control of the generated frequency (e.g., provided by a register value) is injected directly into the DDS circuit 753 (as opposed to, for example, being injected into the feedback path of one of the PLLs). Alternatively, it is possible to use the open-loop DDS circuit 753 downstream of one or more other, optional "upstream" PLLs and / or to use the open-loop DDS circuit 753 as an oscillation source that functions as a VCO for such upstream PLLs (e.g., as shown in FIG. 7A).

[0060]

[0076] Considering the above, what has been described is a timing signal generator with improved frequency stability characteristics. In exemplary embodiments, the timing signal generator is implemented as a frequency synthesis and / or clock generator device, for example, as a packaged integrated circuit assembly, or otherwise. Such a device may optionally include one of the die configurations described above, or optionally variations thereof. The device may be packaged and / or hermetically sealed / encapsulated, or otherwise structured. When implemented as a frequency synthesizer, the timing signal generator may achieve improved frequency stability characteristics by using a series, parallel, cascaded, and / or nested multi-PLL structure. In one embodiment, multiple PLLs are arranged, for example, such that the loop bandwidth of each PLL in the nested loop structure selects a different oscillator source depending on the selected output frequency of the device. Given any performance parameter of interest, three or more oscillator sources may be switched between in terms of the oscillator performance characteristics that govern the generated output timing signal; in the particular embodiment discussed above, the performance parameter of interest may be lowest phase noise in the frequency range of interest. In some embodiments, one or more of these oscillation sources may be based on one or more MEMS resonators, and the use of MEMS resonators in such designs facilitates high integration as MEMS resonators can be fabricated along semiconductor manufacturing processes, allowing the entire system to be manufactured as a small die stack, i.e., in a manner that allows it to be implemented as a single multi-die IC (e.g., again with encapsulation, etc.).Any combination and / or permutation of resonator designs, i.e., MEMS resonators, quartz resonators, electronic resonators, LC resonators, single MEMS resonators, dual MEMS resonators, designs having three or more resonators whether configured in series, parallel, or otherwise, temperature compensated oscillators (“TCXOs”), oven controlled oscillators (“OCXOs”), temperature compensated oven controlled oscillators (“TCOCXOs”), electrostatic resonators, piezoelectric resonators, and any resonator and / or oscillator designs now known or hereafter created in adherence with the principles and objectives described herein, may be used in any given stage depending on the design goals or implementation being configured. As a non-limiting example of these principles, in one embodiment of the technology described herein, a cascade structure of two, three, four, or more resonators is used in conjunction with a multi-PLL structure as described, and in a specific example, active temperature compensation can be used in one of the inner PLL loops, i.e., regardless of whether such compensation is used in the outermost loop, and regardless of whether an OCXO or MEMS resonator design is used as the outermost loop. These non-limiting examples again illustrate that the various features described herein are not required for all embodiments.

[0061]

[0077] The circuits and techniques described above may be further constructed using automated systems for fabricating die and / or integrated circuits and may be referred to as instructions on non-transitory media adapted to control the fabrication of such integrated circuits. For example, the components and systems described above may be designed as one or more integrated circuits, or portions of integrated circuits, based on design control instructions that control the fabrication of blocks of the integrated circuits using circuit-forming equipment. The instructions may be in the form of data stored on a computer-readable medium, such as a magnetic tape, optical disk, or magnetic disk, or other such non-transitory medium. Such design control instructions typically encode data structures, other information, or methods that describe circuits that can be physically created as blocks of an integrated circuit. While any suitable format may be used for such encoding, such data structures are commonly described in Caltech Intermediate Format (“CIF”), Calma GDS II Stream Format (“GDSII”), or Electronic Design Interchange Format (“EDIF”), as well as high-level description languages ​​such as VHDL or Verilog, or other forms of register transfer language (“RTL”) descriptions. One skilled in the art of integrated circuit design can develop such a data structure from a circuit diagram and corresponding description of the type detailed above and encode that data structure on a computer-readable medium, and one skilled in the art of integrated circuit fabrication can then use such encoded data to fabricate an integrated circuit that includes one or more of the circuits described herein.

[0062]

[0078] In the foregoing description and the accompanying drawings, specific terms and drawing symbols are set forth to provide a thorough understanding of the present technology. In some cases, these terms and symbols may indicate specific details that are not required to practice the present technology. For example, although the terms “first” and “second” are used herein, unless otherwise specified, these terms are not intended to indicate a particular order but are merely intended to aid in describing the elements of the present technology. In some cases, these terms and symbols may indicate specific details that are not required to practice these embodiments. The terms “exemplary” and “embodiment” are used to express example, rather than preference or requirement. Furthermore, while the present technology has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present technology. Thus, it should be understood that numerous modifications may be made to the exemplary embodiments and that other configurations may be devised without departing from the spirit and scope of the present technology.

[0063]

[0079] As noted above, various documents are incorporated by reference in this disclosure. The definitions provided in this disclosure shall prevail over the meanings of terms used in the documents, whether implicit or otherwise, in the event of a conflict or contradiction (i.e., they shall prevail over any definitions incorporated by reference in the documents).

[0064]

[0080] Various modifications and alterations may be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. Any feature or aspect of an embodiment may be applied, at least where practicable, in combination and / or permutation with other embodiments or in place of a corresponding feature or aspect, and each is similarly considered "optional" with respect to any embodiment and / or combination / permutation. Accordingly, the features of the various embodiments are not intended to be mutually exclusive, and the specification and drawings should be considered in an illustrative, rather than a restrictive, sense.

Claims

1. a first oscillator (FXO); a second oscillator (SXO); a first phase-locked loop (PLL) that receives an output of the FXO and generates a first signal from the output; a second PLL receiving the output of the SXO and generating a second signal from said output, the second PLL having an oscillation source dependent at least in part on an electronic voltage controlled oscillator (VCO) and having a frequency divider controlled in dependence on the first signal; A timing signal generator comprising: The timing signal generator outputs a timing signal depending on the second signal.

2. 10. The timing signal generator of claim 1, wherein the FXO comprises at least one micro-electromechanical system (MEMS) resonator and at least one structure that functions as a temperature sensor.

3. the at least one microelectromechanical system (MEMS) resonator comprises two MEMS resonators; the FXO generates the first signal depending on a resonant frequency of a first resonator of the two MEMS resonators; the at least one structure functioning as a temperature sensor is embodied as the two MEMS resonators; The timing signal generator of claim 2 , further comprising a circuit for generating a temperature dependent signal as a function of the divergence of the resonant frequencies of the two MEMS resonators.

4. the FXO is an oven-controlled oscillator (OCXO); 4. The timing signal generator of claim 3, wherein the OCXO comprises a heating element and a circuit that uses the temperature dependent signal to control the heating element to urge the temperature of the two MEMS resonators to a first temperature.

5. 5. The timing signal generator of claim 4, wherein the timing signal generator comprises circuitry that uses the temperature dependent signal to correct for temperature dependent variations in the resonant frequency, thereby implementing a temperature compensated OCXO (TCOCXO).

6. the frequency divider is a second frequency divider, the FXO generates the output of the FXO in dependence on a resonant frequency of the at least one MEMS resonator; the first PLL comprises a first frequency divider; the timing signal generator further comprising a circuit for generating a temperature dependent signal dependent on an output of the temperature sensor; 3. The timing signal generator of claim 2, wherein the first frequency divider is controlled in dependence on the temperature dependent signal, thereby implementing a temperature compensated oscillator based on the SXO.

7. the timing signal generator comprises a first die and a second die; the FXO is on the first die; 7. The timing signal generator of claim 6, wherein the first PLL circuitry and the second PLL circuitry are each on the second die.

8. 2. The timing signal generator of claim 1, wherein the SXO comprises at least one micro-electromechanical system (MEMS) resonator.

9. 9. The timing signal generator of claim 8, wherein the SXO also comprises at least one structure that functions as a temperature sensor to sense a temperature of the at least one MEMS resonator.

10. the at least one microelectromechanical system (MEMS) resonator comprises two MEMS resonators; the SXO generates the output of the SXO depending on a resonant frequency of a first resonator of the two MEMS resonators; the at least one structure functioning as a temperature sensor is embodied as the two MEMS resonators; the timing signal generator further comprising circuitry for deriving a temperature dependent signal as a function of divergence of the resonant frequencies of the two MEMS resonators; 10. The timing signal generator of claim 9, wherein the timing signal generator comprises circuitry that uses the temperature dependent signal to correct for temperature dependent variations in the resonant frequency, thereby implementing a temperature compensated oscillator (TCXO) based on the second oscillator.

11. 2. The timing signal generator of claim 1, wherein the electronic VCO is an LC voltage controlled oscillator (LCVCO).

12. the SXO is a first SXO, the frequency divider is a first frequency divider, the oscillation source further comprises a second SXO and a third PLL receiving an output of the second SXO, the third PLL having a second frequency divider controlled according to the second signal and an oscillator; the oscillator of the third PLL is the electronic VCO; 2. The timing signal generator of claim 1, wherein the timing signal output by the timing signal generator depends on the output of the third PLL.

13. the first PLL has a first loop speed; the second PLL having a second loop speed; 2. The timing signal generator of claim 1, wherein the first PLL and the second PLL are part of a nested PLL structure such that the phase noise of the timing signal output by the timing signal generator is dominated by the phase noise of the FXO at a first frequency of the timing signal below the first loop speed, by the phase noise of the SXO at a second frequency of the timing signal between the first loop speed and the second loop speed, and by the phase noise of the electronic VCO at a third frequency of the timing signal above the second loop speed.

13. the timing signal generator comprises a programmable register; the first PLL also comprises a frequency divider controlled at least in part depending on the contents of the programmable register; 2. The timing signal generator of claim 1 embodied as a frequency synthesizer, wherein the timing signal output by the timing signal generator has a frequency that depends on the contents of the frequency divider.

14. the timing signal output by the timing signal generator is a first timing signal; the timing signal generator outputs a second timing signal; 2. The timing signal generator of claim 1, wherein the second timing signal and the first timing signal differ from each other in at least one of phase or frequency.

15. the timing signal generator comprises a first die and a second die; At least one of the FXO and the SXO comprises a MEMS resonator; the MEMS resonator is on the first die; 2. The timing signal generator of claim 1, wherein the first PLL circuitry and the second PLL circuitry are each on the second die.

16. the timing signal generator comprises a first die, a second die, and a third die; each of the OCXO and the SXO comprises at least one MEMS resonator; the at least one MEMS resonator of the OCXO is on the first die; the at least one MEMS resonator of the SXO is on the second die; 2. The timing signal generator of claim 1, wherein the first PLL circuit, the second PLL circuit, the circuit that drives the at least one MEMS resonator of the OCXO, and the circuit that drives the at least one MEMS resonator of the SXO are each located on the third die.

17. a first oscillator, which is an oven-controlled oscillator (OCXO) and comprises at least one microelectromechanical system (MEMS) resonator and at least one structure that functions as a temperature sensor; a second oscillator (SXO); a first phase-locked loop (PLL) receiving an output of the OCXO and generating a first signal from the output, the first PLL having a frequency divider; a second PLL receiving the output of the SXO and generating a second signal from said output, the second PLL having an oscillation source dependent at least in part on an electronic voltage controlled oscillator (VCO) and having a frequency divider controlled in dependence on the first signal; A timing signal generator comprising: The timing signal generator outputs a timing signal depending on the second signal.

18. 18. The timing signal generator of claim 17, further comprising a circuit for generating a temperature dependent signal depending on the output of the temperature sensor, the divider of the first PLL being controlled in response to the temperature dependent signal, thereby implementing a temperature compensated OCXO (TCOCXO).

19. the at least one microelectromechanical system (MEMS) resonator comprises two MEMS resonators; the OCXO generates the first signal depending on a resonant frequency of a first resonator of the two MEMS resonators; the at least one structure functioning as a temperature sensor is embodied as the two MEMS resonators; the circuit for deriving the temperature dependent signal deriving the temperature dependent signal as a function of divergence of the resonant frequencies of the two MEMS resonators; 20. The timing signal generator of claim 18, wherein the OCXO comprises a heating element and a circuit for controlling the heating element in dependence on the temperature dependent signal to urge the temperature of the two MEMS resonators to a first temperature.

20. the timing signal generator comprises a first die and a second die; the OCXO is on the first die; 20. The timing signal generator of claim 19, wherein the first PLL circuitry and the second PLL circuitry are each on the second die.

21. 20. The timing signal generator of claim 17, wherein the SXO also comprises at least one micro-electromechanical system (MEMS) resonator.

22. 22. The timing signal generator of claim 21, wherein the SXO also comprises at least one structure that functions as a temperature sensor that senses the temperature of the at least one MEMS resonator of the SXO.

23. the timing signal generator comprises a first die, a second die, and a second die; the at least one MEMS resonator of the OCXO is on the first die; the at least one MEMS resonator of the SXO is on the second die; 22. The timing signal generator of claim 21, wherein the circuitry of the first PLL, the circuitry of the second PLL, the circuitry that drives the at least one MEMS resonator of the OCXO, and the circuitry that drives the at least one MEMS resonator of the SXO are each on the third die.

24. a first oscillator, which is an oven-controlled oscillator (OCXO) and comprises at least one first microelectromechanical system (MEMS) resonator and at least one structure that functions as a temperature sensor; a second oscillator (SXO) comprising at least one second MEMS resonator; a first phase-locked loop (PLL) receiving an output of the OCXO and generating a first signal from the output, the first PLL having a frequency divider; a circuit for generating a temperature dependent signal dependent on the output of the temperature sensor, wherein the frequency divider of the first PLL is controlled in response to the temperature dependent signal, thereby implementing a temperature compensated OCXO (TCOCXO); a second PLL receiving the output of the SXO and generating a second signal from said output, the second PLL having an oscillation source that is an electronic voltage controlled oscillator (VCO) and a frequency divider controlled in dependence on the first signal; A timing signal generator comprising: The timing signal generator outputs a timing signal depending on the second signal.

25. 25. The timing signal generator of claim 24, wherein the electronic VCO is an LCVCO.

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