Method and apparatus for use in a node for wireless communication - Patents.com

Abstract

This application discloses a method and apparatus for use in a node for wireless communication. A first receiver receives a first PDCCH, where the first PDCCH ends at a first symbol. A first transmitter transmits a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol, and the first PUSCH and the second PUSCH overlap in the time domain. Whether the end of the first symbol can precede the start of the second symbol by less than N symbols depends on whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability.

Description

[Technical Field]

[0001] The present application relates to a transmission method and a transmission device in a wireless communication system, and more particularly to a transmission method and a transmission device for radio signals in a wireless communication system supporting a cellular network. [Background technology]

[0002] For the uplink, enhancing the scenario in which multiple PUSCHs are transmitted that overlap in the time domain is an effective means to improve transmission efficiency. Summary of the Invention

[0003] In a scenario in which multiple PUSCHs overlap in the time domain are transmitted, how to improve scheduling flexibility is an important issue that needs to be considered. This application discloses a solution to the above problem. This application can be applied to various wireless communication scenarios, such as single TRP (Transmit / Receive Point) transmission, multi-TRP transmission, single panel transmission, and multi-panel transmission, and achieves similar technical effects. In addition, the use of a unified solution for different scenarios (including, but not limited to, single TRP transmission, multi-TRP transmission, single panel transmission, and multi-panel transmission) also promotes reduction in hardware complexity and cost, or promotion of performance improvement. Where there is no contradiction, embodiments and features in embodiments of any node in this application can be applied to any other node. Where there is no contradiction, embodiments and features in embodiments of this application can be arbitrarily combined with each other.

[0004] In one embodiment, the interpretation of terms in this application refers to the definitions in the 3GPP standard protocol TS36 series.

[0005] In one embodiment, the interpretation of terms in this application refers to the definitions in the 3GPP standard protocol TS38 series.

[0006] In one embodiment, the interpretation of terms in this application refers to the definitions in the 3GPP standard protocol TS37 series.

[0007] In one embodiment, the interpretation of terms in this application refers to the definition of standard protocols from the Institute of Electrical and Electronics Engineers (IEEE).

[0008] The present application discloses a method for use in a first node for wireless communication, the method comprising: receiving a first PDCCH, the first PDCCH ending at a first symbol; transmitting a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol; Including, The first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by fewer than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0009] In one embodiment, an advantage of the above method is increased scheduling flexibility. include.

[0010] In one embodiment, the advantages of the method include improved uplink transmission performance.

[0011] In one embodiment, advantages of the above method include that it leads to reduced transmission delays.

[0012] In one embodiment, advantages of the above method include optimizing the system design to support different user equipment.

[0013] In one embodiment, advantages of the above method include good compatibility.

[0014] In one embodiment, advantages of the above method include minimal changes to existing 3GPP standards and minimal standardization workload.

[0015] According to one aspect of the present application, the method comprises: When the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol may precede the start of the second symbol by less than N symbols. It is characterized by:

[0016] In one embodiment, advantages of the above method include increased scheduling flexibility.

[0017] In one embodiment, advantages of the above method include that it leads to supporting different user equipments and has good compatibility.

[0018] In one embodiment, advantages of the above method include that it leads to reduced transmission delays.

[0019] According to one aspect of the present application, the method comprises: When the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot precede the start of the second symbol by less than N symbols.

[0020] In one embodiment, advantages of the above method include that it leads to supporting different user equipments and has good compatibility.

[0021] According to one aspect of the present application, the method comprises: The second PUSCH is a PUSCH with a configuration grant. It is characterized by:

[0022] In one embodiment, the advantages of the above method include supporting simultaneous transmission of a PUSCH dynamically scheduled by DCI and a PUSCH with a configuration grant of one serving cell in one serving cell, and improving scheduling flexibility or transmission efficiency.

[0023] According to one aspect of the present application, the method comprises: The first PUSCH and the second PUSCH are in the same serving cell. It is characterized by:

[0024] In one embodiment, the advantages of the above method include: leading to support multiple PUSCHs being transmitted simultaneously in one serving cell; and improving scheduling flexibility or transmission efficiency.

[0025] According to one aspect of the present application, the method comprises: N is the number of symbols occupied by the PUSCH preparation time It is characterized by:

[0026] According to one aspect of the present application, the method comprises: The coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value with which the first PUSCH is associated. It is characterized by:

[0027] According to one aspect of the present application, the method comprises: ackNackFeedbackMode is configured separately It is characterized by:

[0028] In one embodiment, advantages of the above method include increased scheduling flexibility.

[0029] The present application discloses a method for use in a second node for wireless communication, the method comprising: transmitting a first PDCCH, the first PDCCH ending at a first symbol; receiving a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol; Including, The first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by fewer than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0030] According to one aspect of the present application, the method comprises: When the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol may precede the start of the second symbol by less than N symbols. It is characterized by:

[0031] According to one aspect of the present application, the method comprises: When the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot precede the start of the second symbol by less than N symbols. It is characterized by:

[0032] According to one aspect of the present application, the method comprises: The second PUSCH is a PUSCH with a configuration grant. It is characterized by:

[0033] According to one aspect of the present application, the method comprises: The first PUSCH and the second PUSCH are in the same serving cell. It is characterized by:

[0034] According to one aspect of the present application, the method comprises: N is the number of symbols occupied by the PUSCH preparation time It is characterized by:

[0035] According to one aspect of the present application, the method comprises: The coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value with which the first PUSCH is associated. It is characterized by:

[0036] According to one aspect of the present application, the method comprises: ackNackFeedbackMode is configured separately It is characterized by:

[0037] The present application discloses a first node used for wireless communication, the first node comprising: a first receiver for receiving a first PDCCH, the first PDCCH ending at a first symbol; a first transmitter for transmitting a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol; Including, The first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by fewer than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0038] The present application discloses a second node for use in wireless communication, the second node comprising: a second transmitter for transmitting a first PDCCH, the first PDCCH ending at a first symbol; a second receiver for receiving a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol; Including, The first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by fewer than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0039] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of the non-limiting embodiments in the following drawings. [Brief explanation of the drawings]

[0040] [Figure 1] 1 illustrates a processing flowchart of a first node according to an embodiment of the present application. [Figure 2] 1 shows a schematic diagram of a network architecture according to an embodiment of the present application; [Figure 3] 1 illustrates a schematic diagram of a radio protocol architecture for user and control planes according to an embodiment of the present application; [Figure 4] 1 shows a schematic diagram of a first communication device and a second communication device according to an embodiment of the present application; [Figure 5] 1 shows a flowchart of signal transmission according to an embodiment of the present application. [Figure 6] FIG. 1 shows a schematic diagram illustrating that the end of a first symbol can precede the start of a second symbol by less than N symbols, according to an embodiment of the present application. [Figure 7] FIG. 1 shows a schematic diagram illustrating that the end of a first symbol cannot precede the start of a second symbol by less than N symbols, according to an embodiment of the present application. [Figure 8]FIG. 1 shows a structural block diagram of a processing unit in a first node device according to an embodiment of the present application. [Figure 9] FIG. 10 illustrates a structural block diagram of a processing unit in a second node device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0041] The technical solutions of the present application are described in further detail below in conjunction with the accompanying drawings. Where there is no contradiction, the embodiments and features in the embodiments of the present application can be arbitrarily combined with each other.

[0042] Embodiment 1 Embodiment 1 illustrates a processing flowchart of a first node according to an embodiment of the present application, as shown in FIG.

[0043] In embodiment 1, the first node in the present application receives a first PDCCH in step 101, and transmits a first PUSCH and a second PUSCH in step 102.

[0044] In embodiment 1, the first PDCCH ends at the first symbol, the first PDCCH schedules the first PUSCH, and the second PUSCH starts at the second symbol, the first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0045] In one embodiment, receiving one PDCCH (Physical Downlink Control Channel) means performing monitoring on this PDCCH.

[0046] In one embodiment, receiving one PDCCH means detecting the DCI format in this PDCCH.

[0047] In one embodiment, receiving one PDCCH means receiving one DCI (Downlink Control Information) on this PDCCH.

[0048] In one embodiment, receiving one PDCCH means receiving a portion of DCI in this PDCCH.

[0049] In one embodiment, receiving one PDCCH means receiving one DCI format in this PDCCH.

[0050] In one embodiment, transmitting one PUSCH (Physical Uplink Shared Channel) means transmitting at least one of a transport block or a CSI (Channel State Information) report on this PUSCH.

[0051] In one embodiment, transmitting one PUSCH (Physical Uplink Shared Channel) means transmitting a signal on this PUSCH.

[0052] In one embodiment, transmitting one PUSCH means transmitting at least one of a transport block or a CSI report on this PUSCH.

[0053] In one embodiment, transmitting one PUSCH means transmitting a signal on this PUSCH, where the transmitted signal includes one bit block that undergoes at least channel coding, scrambling, modulation, layer mapping, pre-encoding, mapping to a virtual resource block, and outputting after mapping from the virtual resource block to a physical resource block.

[0054] In one embodiment, the meaning of transmitting one PUSCH includes transmitting uplink information, and this PUSCH is used to carry uplink information.

[0055] In one embodiment, the meaning of "one PDCCH schedules one PUSCH" includes that this PDCCH schedules the transmission of this PUSCH.

[0056] In one embodiment, "one PDCCH schedules one PUSCH" means that the DCI received on this PDCCH schedules this PUSCH.

[0057] In one embodiment, "one PDCCH schedules one PUSCH" means that the DCI format received on this PDCCH schedules this PUSCH.

[0058] In one embodiment, "one PDCCH schedules one PUSCH" means that the DCI received on this PDCCH schedules this PUSCH.

[0059] In one embodiment, the meaning of "one PDCCH schedules one PUSCH" includes that this PDCCH carries the scheduling information of this PUSCH.

[0060] In one embodiment, "one PDCCH schedules one PUSCH" means that the transmission of this PUSCH is dependent on the reception of this PDCCH.

[0061] In one embodiment, the second PUSCH is a PUSCH comprising a configuration grant.

[0062] In one embodiment, the configuration grant carried by the second PUSCH is a Type 2 configuration grant.

[0063] In one embodiment, the second PUSCH is a PUSCH with a configuration grant activated by a DCI format.

[0064] In one embodiment, the first PUSCH and the second PUSCH are in the same serving cell.

[0065] In one embodiment, the first PDCCH ends at the first symbol in the time domain.

[0066] In one embodiment, the first symbol is occupied by the first PDCCH in the time domain. It is the latest symbol to be

[0067] In one embodiment, the first symbol is symbol i.

[0068] In one embodiment, the first symbol is an OFDM (Orthogonal Frequency Division Multiplexing) symbol.

[0069] In one embodiment, the first symbol is the symbol in the slot.

[0070] In one embodiment, the second PUSCH starts at the second symbol in the time domain.

[0071] In one embodiment, the second symbol is the earliest symbol occupied by the second PUSCH in the time domain.

[0072] In one embodiment, the second symbol is symbol j.

[0073] In one embodiment, the second symbol is an OFDM (Orthogonal Frequency Division Multiplexing) symbol.

[0074] In one embodiment, the second symbol is a symbol in the slot.

[0075] In one embodiment, the first symbol is a symbol of the serving cell in which the first PDCCH is located.

[0076] In one embodiment, the second symbol is a symbol of the serving cell in which the first PUSCH is located.

[0077] In one embodiment, the first symbol and the second symbol are symbols of the same serving cell.

[0078] In one embodiment, the first symbol and the second symbol are symbols of different serving cells.

[0079] In one embodiment, the expression "the first PUSCH and the second PUSCH overlap in the time domain" means a transmission opportunity occupied by the first PUSCH and the second PUSCH overlapping in the time domain.

[0080] In one embodiment, the time domain resources occupied by the first PUSCH and the time domain resources occupied by the second PUSCH at least partially overlap.

[0081] In one embodiment, the expressions "whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" and "whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

[0082] In one embodiment, the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values. The expressions "whether the first PUSCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

[0083] In one embodiment, the meaning of the expression "whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" is whether the end of the first symbol that is less than N symbols before the start of the second symbol is not predicted is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values.

[0084] In one embodiment, the meaning of the expression "whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" is whether the end of the first symbol less than N symbols before the start of the second symbol is allowed or not expected is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values.

[0085] In one embodiment, the meaning of the expression "whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" is The time-domain relationship between the first symbol and the second symbol relates to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values: when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol; and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

[0086] In one embodiment, when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol, and when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

[0087] In one embodiment, N is determined based on the UE processing capabilities.

[0088] In one embodiment, N is based on the smaller of the subcarrier spacing corresponding to the second PUSCH and the subcarrier spacing corresponding to the first PDCCH.

[0089] In one embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0090] In one embodiment, N is greater than zero.

[0091] In one embodiment, N is 5 or greater.

[0092] In one embodiment, N is one of 5, 5.5, and 11.

[0093] In one embodiment, N is one of 10, 12, 23, 36, 144, and 288.

[0094] In one embodiment, when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol, the second PUSCH is a PUSCH with a configuration grant, and the first PUSCH and the second PUSCH are in the same serving cell.

[0095] As a subembodiment of the above embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0096] In one embodiment, when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot precede the start of the second symbol by less than N symbols, the second PUSCH is a PUSCH with a configuration grant, and the first PUSCH and the second PUSCH are in the same serving cell.

[0097] As a subembodiment of the above embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0098] In one embodiment, when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol, the second PUSCH is a PUSCH with a configuration grant, and the first PUSCH and the second PUSCH are in the same serving cell.

[0099] As a subembodiment of the above embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0100] In one embodiment, ackNackFeedbackMode is configured as a separate entity.

[0101] In one embodiment, ackNackFeedbackMode is configured as joint.

[0102] In one embodiment, ackNackFeedbackMode is not configured.

[0103] In one embodiment, ackNackFeedbackMode is a higher layer parameter.

[0104] In one embodiment, ackNackFeedbackMode is an RRC layer parameter.

[0105] In one embodiment, the first node receives the first parameter and Based on the configuration, two PUSCHs are allowed to be transmitted simultaneously on the same serving cell.

[0106] In one embodiment, the first node receives a first parameter, and based on the configuration of the first parameter, two PUSCHs occupying at least one identical RE (resource element) in the same serving cell are both allowed to be transmitted.

[0107] In one embodiment, the first parameters are parameters for the same serving cell.

[0108] In one embodiment, the first parameter is an RRC layer parameter.

[0109] In one embodiment, the first parameter is one parameter in one information element (IE).

[0110] In one embodiment, the name of the first parameter includes STxMP.

[0111] In one embodiment, the name of the first parameter includes multi-DCI.

[0112] In one embodiment, the first node is configured with a higher layer parameter PDCCH-Config for an active BWP (bandwidth portion) of one serving cell, and the higher layer parameter PDCCH-Config includes two different coresetPoolIndex values ​​in the ControlResourceSet.

[0113] In one embodiment, the first node is configured or not configured with a higher layer parameter PDCCH-Config for the active BWP of one serving cell, and the higher layer parameter PDCCH-Config includes two different coresetPoolIndex values ​​in the ControlResourceSet.

[0114] In one embodiment, the first node is configured with neither prioritizationBetweenLP-DG-PUSCHandHP-CG-PUSCH nor prioritizationBetweenHP-DG-PUSCHandLP-CG-PUSCH.

[0115] In one embodiment, the first node is configured with prioritization Between LP-DG-PUSCH and HP-CG-PUSCH or prioritization Between HP-DG-PUSCH and LP-CG-PUSCH, and the first PUSCH and the second PUSCH have the same priority index.

[0116] Embodiment 2 Embodiment 2 illustrates a schematic diagram of one network architecture according to the present application, as shown in FIG.

[0117] 2 illustrates a diagram of a network architecture 200 for 5G NR, LTE (Long Term Evolution), and LTE-A (Long Term Evolution Advanced) systems. The 5G NR or LTE network architecture 200 may be referred to as an Evolved Packet System (EPS) 200 or some other suitable term. The EPS 200 includes a UE (User Equipment) 201, an NG-RAN (Next Generation Radio Access Network) 202, an EPC (Evolved Packet Core) / 5G-CN (5G Core Network) 210, an HSS (Home Subscriber Server) 220, and an Internet The NG-RAN may comprise one or more of the following: a network service 230; an access network (EPS) 230; and a network service 230. The EPS may be interconnected with other access networks, but these entities / interfaces are not shown for simplicity. As shown, the EPS provides packet-switched services; however, those skilled in the art will readily appreciate that the various concepts presented throughout this application can be extended to networks providing circuit-switched services or other cellular networks. The NG-RAN includes an NR Node B (gNB) 203 and other gNBs 204. The gNB 203 provides user plane and control plane protocol termination for the UE 201. The gNB 203 may be connected to the other gNBs 204 via an Xn interface (e.g., backhaul). The gNB 203 may also be referred to as a base station, base transceiver station, radio base station, radio transceiver, transmit / receive function, basic service set (BSS), extended service set (ESS), TRP (transmission / reception point), or other suitable terminology. The gNB 203 provides an access point to the EPC / 5G-CN 210 for the UE 201. Examples of the UE 201 include a mobile phone, a smartphone, a Session Initiation Protocol (SIP) phone, a laptop, a personal digital assistant (PDA), satellite radio, non-terrestrial base station communications, satellite mobile communications, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., an MP3 player), a camera, a game console, a drone, an aircraft, a narrowband Internet of Things device, a machine-type communications device, a land transportation vehicle, an automobile, a wearable device, or any other similarly functional device. Those skilled in the art may also refer to the UE 201 as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a radio unit, a remote unit, a mobile device, a radio device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. The gNB 203 is connected to the EPC / 5G-CN 210 by an S1 / NG interface.The EPC / 5G-CN 210 includes an MME (Mobility Management Entity) / AMF (Authentication Management Field) / UPF (User Plane Function) 211, another MME / AMF / UPF 214, an S-GW (Service Gateway) 212, and a P-GW (Packet Data Network Gateway) 213. The MME / AMF / UPF 211 is a control node that handles signaling between the UE 201 and the EPC / 5G-CN 210. Generally, the MME / AMF / UPF 211 provides bearer and connection management. All user IP (Internet Protocol) packets are forwarded by the S-GW 212, which is itself connected to the P-GW 213. The P-GW 213 provides UE IP address allocation and other functions. The P-GW 213 is connected to the Internet service 230. Internet services 230 include the operator's corresponding Internet protocol services, which may specifically include Internet, intranet, IMS (IP Multimedia Subsystem), and packet-switched streaming services.

[0118] In one embodiment, the UE 201 corresponds to the first node in this application.

[0119] In one embodiment, the UE 201 corresponds to the second node in this application.

[0120] In one embodiment, UE 201 is a UE.

[0121] In one embodiment, gNB203 corresponds to the first node in this application.

[0122] In one embodiment, gNB203 corresponds to the second node in this application.

[0123] In one embodiment, UE201 corresponds to the first node in this application, and gNB203 corresponds to the second node in this application.

[0124] In one embodiment, the gNB 203 is a macrocellular base station.

[0125] In one embodiment, the gNB203 is a microcell base station.

[0126] In one embodiment, the gNB203 is a picocell base station.

[0127] In one embodiment, the gNB203 is a femtocell.

[0128] In one embodiment, the gNB 203 is a base station device that supports large delay differences.

[0129] In one embodiment, the gNB203 is an airborne platform device.

[0130] In one embodiment, the gNB203 is a satellite device.

[0131] Embodiment 3 Embodiment 3 illustrates a schematic diagram of an embodiment of a radio protocol architecture for one user plane and one control plane according to the present application, as shown in FIG. 3. FIG. 3 is a schematic diagram illustrating an embodiment of a radio protocol architecture for a user plane 350 and a control plane 300. FIG. 3 illustrates a radio protocol architecture for the control plane 300 used between a first communication node device (a UE, a gNB, or an RSU in V2X) and a second communication node device (a gNB, a UE, or an RSU in V2X) or between two UEs using three layers, namely, Layer 1, Layer 2, and Layer 3. Layer 1 (L1 layer) is the lowest layer and implements various PHY (physical layer) signal processing functions. The L1 layer is referred to herein as PHY 301. Layer 2 (L2 layer) 305 is above PHY 301 and is responsible for the link between the first communication node device and the second communication node device and between two UEs via PHY 301. The L2 layer 305 includes a MAC (Medium Access Control) sublayer 302, an RLC (Radio Link Control) sublayer 303, and a PDCP (Packet Data Convergence Protocol) sublayer 304, which terminate at the second communication node device. The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. The PDCP sublayer 304 also provides security by encrypting data packets and supports cross-zone mobility of the first communication node device between the second communication node device. The RLC sublayer 303 provides segmentation and reconstruction of upper layer data packets, retransmission of lost data packets, and reordering of data packets to compensate for out-of-order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical channels and transport channels. The MAC sublayer 302 is also responsible for allocating various radio resources (e.g., resource blocks) within a cell between the first communication node devices. The MAC sublayer 302 is also responsible for HARQ operations.The RRC (Radio Resource Control) sublayer 306 in Layer 3 (L3 layer) in the control plane 300 is responsible for obtaining radio resources (i.e., radio bearers) and configuring the lower layers using RRC signaling between the second communication node device and the first communication node device. The radio protocol architecture of the user plane 350 includes Layer 1 (L1 layer) and Layer 2 (L2 layer). The radio protocol architecture for the first and second communication node devices in the user plane 350 is substantially the same as the corresponding layers and sublayers in the control plane 300 for the physical layer 351, the PDCP sublayer 354 in the L2 layer 355, the RLC sublayer 353 in the L2 layer 355, and the MAC sublayer 352 in the L2 layer 355, except that the PDCP sublayer 354 also provides header compression for upper layer data packets to reduce radio transmission overhead. The L2 layer 355 in the user plane 350 further includes an SDAP (Service Data Adaptation Protocol) sublayer 356, which is a sublayer of the SDAP. Sub-layer 356 is responsible for mapping between QoS streams and Data Radio Bearers (DRBs) to support service diversity. Although not shown in the figure, the first communication node device may have several upper layers above L2 layer 355, including a network layer (e.g., IP layer) that terminates at the P-GW on the network side and an application layer that terminates at the other end of the connection (e.g., remote UE, server, etc.).

[0132] As an embodiment, the radio protocol architecture of FIG. 3 is applicable to the first node of the present application.

[0133] In one embodiment, the radio protocol architecture of FIG. 3 is applicable to the second node of the present application.

[0134] In one embodiment, the first PDCCH in this application is generated in PHY 301 .

[0135] In one embodiment, the first PUSCH in this application is generated in PHY 351.

[0136] In one embodiment, the second PUSCH in this application is generated in PHY 351.

[0137] Embodiment 4 Embodiment 4 shows a schematic diagram of a first communication device and a second communication device according to the present application, as shown in Figure 4. Figure 4 is a block diagram of a first communication device 410 and a second communication device 450 communicating with each other in an access network.

[0138] The first communication device 410 comprises a controller / processor 475, a memory 476, a receive processor 470, a transmit processor 416, a multi-antenna receive processor 472, a multi-antenna transmit processor 471, a transmit device / receive device 418, and an antenna 420.

[0139] The second communication device 450 comprises a controller / processor 459, a memory 460, a data source 467, a transmit processor 468, a receive processor 456, a multi-antenna transmit processor 457, a multi-antenna receive processor 458, a transmit device / receive device 454, and an antenna 452.

[0140] For transmissions from the first communication device 410 to the second communication device 450, upper layer data packets from the core network are provided to a controller / processor 475 at the first communication device 410. The controller / processor 475 performs L2 layer functions. For transmissions from the first communication device 410 to the second communication device 450, the controller / processor 475 provides header compression, encryption, packet segmentation and reordering, multiplexing between logical and transport channels, and allocation of radio resources to the second communication device 450 based on various priority metrics. The controller / processor 475 is also responsible for retransmission of lost packets and signaling to the second communication device 450. The transmit processor 416 and the multi-antenna transmit processor 471 implement various signal processing functions for the L1 layer (i.e., the physical layer). The transmit processor 416 implements coding and interleaving to facilitate forward error correction (FEC) at the second communication device 450, as well as mapping of signal clusters based on various modulation schemes (e.g., binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), M-phase shift keying (M-PSK), and M-quadrature amplitude modulation (M-QAM)). The multi-antenna transmit processor 471 performs digital spatial precoding, including codebook-based precoding and non-codebook-based precoding, and beamforming processing on the coded and modulated symbols to generate one or more parallel streams. The transmit processor 416 then maps each spatial stream to subcarriers, multiplexes them with reference signals (e.g., pilots) in the time and / or frequency domains, and then uses an inverse fast Fourier transform (IFFT) to generate a physical channel carrying the time-domain multi-carrier symbol stream. The multi-antenna transmit processor 471 then performs transmit analog precoding / beamforming operations on the time-domain multi-carrier symbol stream. Each transmitting device 418 converts the baseband multi-carrier symbol stream provided by the multi-antenna transmit processor 471 into a radio frequency stream, which is then provided to a different antenna 420.

[0141] In a transmission from the first communication device 410 to the second communication device 450, each receiving device 454 in the second communication device 450 receives the signal via its corresponding antenna 452. Each receiving device 454 recovers the information modulated onto the radio frequency carrier, converts the radio frequency stream into a baseband multi-carrier symbol stream, and provides it to a receive processor 456. The receive processor 456 and the multi-antenna receive processor 458 implement various signal processing functions of the L1 layer. The multi-antenna receive processor 458 performs receive analog precoding / beamforming operations on the baseband multi-carrier symbol stream from the receiving device 454. The receive processor 456 uses a fast Fourier transform (FFT) to convert the baseband multi-carrier symbol stream after the receive analog precoding / beamforming operations from the time domain to the frequency domain. In the frequency domain, the physical layer data signal and reference signal are demultiplexed by the receive processor 456, the reference signal is used for channel estimation, and the data signal undergoes multi-antenna detection in the multi-antenna receive processor 458 to recover any spatial streams destined for the second communication device 450. The symbols on each spatial stream are demodulated and recovered in the receive processor 456 to generate soft decisions. The receive processor 456 then decodes and deinterleaves the soft decisions to recover the upper layer data and control signals transmitted by the first communication device 410 on the physical channel. The upper layer data and control signals are then provided to the controller / processor 459. The controller / processor 459 performs the functions of the L2 layer. The controller / processor 459 may be associated with a memory 460 that stores program codes and data. The memory 460 may be referred to as a computer-readable medium. For transmission from the first communication device 410 to the second communication device 450, the controller / processor 459 provides demultiplexing between transport and logical channels, packet reassembly, decryption, header decompression, and control signal processing to recover upper layer data packets from the core network.The upper layer data packets are then provided to all protocol layers above the L2 layer. Various control signals may also be provided to L3 for L3 processing.

[0142] In a transmission from the second communication device 450 to the first communication device 410, a data source 467 is used in the second communication device 450 to provide upper layer data packets to the controller / processor 459. The data source 467 represents all protocol layers above the L2 layer. Similar to the transmission functions described for the first communication device 410 in a transmission from the first communication device 410 to the second communication device 450, the controller / processor 459 performs header compression, encryption, packet segmentation and reordering, and multiplexing between logical and transport channels based on radio resource allocation, and performs L2 layer functions for the user plane and control plane. The controller / processor 459 also handles retransmission of lost packets and packet forwarding to the first communication device 450. The transmit processor 468 is responsible for signaling to the multi-antenna transmit processor 410. The transmit processor 468 performs modulation mapping and channel coding processing, and the multi-antenna transmit processor 457 performs digital multi-antenna spatial precoding (including codebook-based precoding and non-codebook-based precoding) and beamforming processing, after which the transmit processor 468 modulates the generated spatial streams into multi-carrier / single-carrier symbol streams, which undergo analog precoding / beamforming operations in the multi-antenna transmit processor 457 and are then provided to different antennas 452 by the transmit device 454. Each transmit device 454 first converts the baseband symbol stream provided by the multi-antenna transmit processor 457 into a radio frequency symbol stream, which is then provided to the antenna 452.

[0143] For transmission from the second communication device 450 to the first communication device 410, the functions at the first communication device 410 are similar to the receiving functions described for the second communication device 450 for transmission from the first communication device 410 to the second communication device 450. Each receiving device 418 receives radio frequency signals via its corresponding antenna 420, converts the received radio frequency signals to baseband signals, and provides the baseband signals to the multi-antenna receive processor 472 and the receive processor 470. The receive processor 470 and the multi-antenna receive processor 472 jointly perform the functions of the L1 layer. The controller / processor 475 performs the functions of the L2 layer. The controller / processor 475 may be associated with a memory 476 that stores program codes and data. The memory 476 may be referred to as a computer-readable medium. For transmission from the second communication device 450 to the first communication device 410, the controller / processor 475 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, and control signal processing to recover upper layer data packets from the UE 450. The upper layer data packets from the controller / processor 475 may be provided to the core network.

[0144] In one embodiment, the first node in this application comprises the second communication device 450 and the second node in this application comprises the first communication device 410 .

[0145] As a subembodiment of the above embodiment, the first node is a user equipment and the second node is a user equipment.

[0146] In one subembodiment of the above embodiment, the first node is a user equipment and the second node is a relay node.

[0147] In one subembodiment of the above embodiment, the first node is a relay node and the second node is a user equipment.

[0148] As a subembodiment of the above embodiment, the first node is a user equipment and the second node is a base station device.

[0149] As a subembodiment of the above embodiment, the first node is a relay node and the second node is a base station device.

[0150] As a subembodiment of the above embodiment, the second node is a user equipment and the first node is a base station device.

[0151] In one subembodiment of the above embodiment, the second node is a relay node and the first A node is a base station device.

[0152] As a sub-embodiment of the above embodiment, the second communication device 450 comprises at least one controller / processor, where the at least one controller / processor is responsible for HARQ operations.

[0153] As a sub-embodiment of the above embodiment, the first communication device 410 comprises at least one controller / processor, where the at least one controller / processor is responsible for HARQ operations.

[0154] As a sub-embodiment of the above embodiment, the first communication device 410 includes at least one controller / processor responsible for error detection using an acknowledgement (ACK) and / or negative acknowledgement (NACK) protocol to support HARQ operations.

[0155] In one embodiment, the second communication device 450 includes at least one processor and at least one memory, the at least one memory including computer program code, the at least one memory and the computer program code configured for use with the at least one processor. The second communication device 450 apparatus at least receives a first PDCCH, the first PDCCH ending at a first symbol, and transmits a first PUSCH and a second PUSCH, the first PDCCH scheduling the first PUSCH and the second PUSCH starting at the second symbol, the first PUSCH and the second PUSCH overlapping in the time domain, and whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability.

[0156] As a sub-embodiment of the above embodiment, the second communication device 450 corresponds to the first node in the present application.

[0157] In one embodiment, the second communications device 450 includes a memory that stores a computer-readable program of instructions that, when executed by at least one processor, generates actions including receiving a first PDCCH, the first PDCCH ending at a first symbol; and transmitting a first PUSCH and a second PUSCH, the first PDCCH scheduling the first PUSCH and the second PUSCH starting at the second symbol, and the first PUSCH and the second PUSCH overlapping in the time domain, wherein whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability.

[0158] As a sub-embodiment of the above embodiment, the second communication device 450 corresponds to the first node in the present application.

[0159] In one embodiment, the first communication device 410 includes at least one processor and at least one memory, the at least one memory including computer program code, the at least one memory and the computer program code configured for use with the at least one processor. The first communication device 410 includes at least a first PDCCH, the first PDCCH ending at a first symbol. a PDCCH for transmitting a PDCCH and a PUSCH for receiving a first PUSCH and a second PUSCH, the first PDCCH scheduling the first PUSCH and the second PUSCH starting at the second symbol, the first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0160] As a sub-embodiment of the above embodiment, the first communication device 410 corresponds to the second node in the present application.

[0161] In one embodiment, the first communications device 410 includes a memory that stores a computer-readable program of instructions, which when executed by at least one processor generates actions, including transmitting a first PDCCH, the first PDCCH ending at a first symbol; and receiving a first PUSCH and a second PUSCH, the first PDCCH scheduling the first PUSCH and the second PUSCH starting at the second symbol, and the first PUSCH and the second PUSCH overlapping in the time domain, wherein whether the end of the first symbol can be less than N symbols before the start of the second symbol is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability.

[0162] As a sub-embodiment of the above embodiment, the first communication device 410 corresponds to the second node in the present application.

[0163] In one embodiment, in the present application, at least one of {antenna 452, receiving device 454, multi-antenna receiving processor 458, receiving processor 456, controller / processor 459, memory 460, and data source 467} is used to receive the first PDCCH.

[0164] In one embodiment, at least one of {antenna 420, transmitting device 418, multi-antenna transmit processor 471, transmit processor 416, controller / processor 475, and memory 476} is used to transmit the first PDCCH.

[0165] In one embodiment, in the present application, at least one of {antenna 452, transmitting device 454, multi-antenna transmit processor 458, transmit processor 468, controller / processor 459, memory 460, and data source 467} is used to transmit the first PUSCH.

[0166] In one embodiment, in the present application, at least one of {antenna 420, receiving device 418, multi-antenna receiving processor 472, receiving processor 470, controller / processor 475, and memory 476} is used to receive the first PUSCH.

[0167] In one embodiment, in the present application, at least one of {antenna 452, transmitting device 454, multi-antenna transmit processor 458, transmit processor 468, controller / processor 459, memory 460, and data source 467} is used to transmit the second PUSCH.

[0168] In one embodiment, in the present application, in order to receive the second PUSCH, 420, receiving device 418, multi-antenna receive processor 472, receive processor 470, controller / processor 475, and memory 476} are used.

[0169] Embodiment 5 Embodiment 5 illustrates a flowchart of signal transmission according to an embodiment of the present application, as shown in Figure 5. In Figure 5, a first node U1 and a second node U2 communicate over an air interface.

[0170] The first node U1 receives the first PDCCH in step S511, and transmits the first PUSCH and the second PUSCH in step S512.

[0171] The second node U2 transmits the first PDCCH in step S521, and receives the first PUSCH and the second PUSCH in step S522.

[0172] In embodiment 5, the first PDCCH ends at a first symbol, the first PDCCH schedules a first PUSCH, and the second PUSCH starts at a second symbol, the first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability. When the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, no cases are anticipated where the end of the first symbol is less than N symbols before the start of the second symbol, the second PUSCH is a PUSCH with a configuration grant, and the first PUSCH and the second PUSCH are in the same cell.

[0173] In one subembodiment of embodiment 5, N is the number of symbols occupied by the PUSCH preparation time.

[0174] As a sub-embodiment of embodiment 5, ackNackFeedbackMode is configured as a separate entity.

[0175] As a sub-embodiment of embodiment 5, ackNackFeedbackMode is configured as joint.

[0176] In one embodiment, the first node U1 is the first node in this application.

[0177] In one embodiment, the second node U2 is the second node in this application.

[0178] In one embodiment, the first node U1 is a UE.

[0179] In one embodiment, the first node U1 is a base station.

[0180] In one embodiment, the second node U2 is a base station.

[0181] In one embodiment, the second node U2 is a UE.

[0182] In one embodiment, the air interface between the second node U2 and the first node U1 is a Uu interface.

[0183] In one embodiment, the air interface between the second node U2 and the first node U1 comprises a cellular link.

[0184] In one embodiment, the air interface between the second node U2 and the first node U1 includes a radio interface between a base station device and a user equipment.

[0185] In one embodiment, the air interface between the second node U2 and the first node U1 includes a radio interface between a satellite device and a user equipment.

[0186] In one embodiment, the air interface between the second node U2 and the first node U1 includes a user equipment to user equipment radio interface.

[0187] In one embodiment, the problem to be solved by the present application includes how to improve scheduling flexibility.

[0188] In one embodiment, the problem to be solved by the present application includes a method for improving uplink transmission performance.

[0189] In one embodiment, the problem to be solved by this application includes how to optimize the system design to support different user equipment.

[0190] In one embodiment, the problem to be solved by this application includes how to ensure good compatibility.

[0191] In one embodiment, the problem to be solved by the present application involves clarifying the relationship between the PDCCH and the PUSCH.

[0192] In one embodiment, the problem to be solved by the present application includes clarifying the relationship between whether the end of a first symbol can precede the start of a second symbol by less than N symbols and whether the first PDCCH and second PUSCH are associated with different coresetPoolIndex values.

[0193] In one embodiment, the problem to be solved by the present application includes a method to enhance for scenarios in which a PUSCH scheduled by a PDCCH and a PUSCH with a configuration grant are transmitted simultaneously in order to improve scheduling flexibility or transmission efficiency.

[0194] Embodiment 6 Embodiment 6 shows a schematic diagram illustrating that the end of the first symbol can be less than N symbols before the start of the second symbol according to one embodiment of the present application, as shown in FIG. 6.

[0195] In embodiment 6, when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol may be less than N symbols before the start of the second symbol.

[0196] In one embodiment, the first PDCCH is associated with coresetPoolI. The index value is the coresetPoolIndex value of the ControlResourceSet for configuring the resources occupied by the first PDCCH.

[0197] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value of the control resource set (CORESET) to which the resources occupied by the first PDCCH belong.

[0198] In one embodiment, the coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value of the ControlResourceSet for configuring the search for DCI detected on the first PDCCH.

[0199] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value associated with the DCI that schedules the first PUSCH.

[0200] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value of the control resource set associated with the DCI that schedules the first PUSCH.

[0201] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value associated with the DCI detected on the first PDCCH.

[0202] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value of the control resource set to which the DCI detected on the first PDCCH is associated.

[0203] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value of the control resource set to which the first PDCCH is associated.

[0204] In one embodiment, the coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value with which the first PUSCH is associated.

[0205] In one embodiment, the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value associated with the SRS (Sounding Reference Signal) resource set (SRS resource set) for the transmission of the first PUSCH.

[0206] In one embodiment, the coresetPoolIndex value with which the first PDCCH is associated is configurable.

[0207] In one embodiment, the coresetPoolIndex value to which the second PUSCH is associated is the coresetPoolIndex value associated with the SRS resource set for transmission of the second PUSCH.

[0208] In one embodiment, the coresetPoolIndex value to which the second PUSCH is associated is the coresetPoolIndex value of the control resource set to which the DCI for activating the second PUSCH is associated.

[0209] In one embodiment, the coresetPoolIndex value with which the second PUSCH is associated is the coresetPoolIndex value of the ControlResourceSet for configuring the search for DCI for activating the second PUSCH.

[0210] In one embodiment, the coresetPoolIndex value with which the second PUSCH is associated is configurable.

[0211] In one embodiment, "the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" means that the coresetPoolIndex value to which the first PDCCH is associated is different from the coresetPoolIndex value to which the second PUSCH is associated.

[0212] In one embodiment, coresetPoolIndex is a parameter indicating the index of a CORESET (control resource set) pool.

[0213] In one embodiment, coresetPoolIndex is an RRC layer parameter.

[0214] In one embodiment, a coresetPoolIndex value is the index of a CORESET pool.

[0215] In one embodiment, a coresetPoolIndex value is one of 0 or 1.

[0216] In one embodiment, the phrase "the end of the first symbol may precede the start of the second symbol by fewer than N symbols" means that the end of the first symbol is permitted to precede the start of the second symbol by fewer than N symbols.

[0217] In one embodiment, the phrase "the end of the first symbol may precede the start of the second symbol by less than N symbols" means that the end of the first symbol is not expected to precede the start of the second symbol by less than N symbols.

[0218] In one embodiment, the expression "the end of the first symbol may be less than N symbols before the start of the second symbol" means that it is within the prediction of the first node that the end of the first symbol is less than N symbols before the start of the second symbol.

[0219] In one embodiment, the expression "the end of the first symbol may be less than N symbols before the start of the second symbol" means either one of two cases: the end of the first symbol is at least N symbols before the start of the second symbol, or it is within the first node's prediction that the end of the first symbol is less than N symbols before the start of the second symbol.

[0220] In one embodiment, the end of a first symbol precedes the start of a second symbol by less than N symbols when the end of a first symbol precedes the start of a second symbol and the interval between the end of the first symbol and the start of the second symbol is less than the length of time occupied by N symbols.

[0221] In one embodiment, the end of a first symbol precedes the start of a second symbol by less than N symbols when the end of the first symbol is not later than the start of the second symbol and the interval between the end of the first symbol and the start of the second symbol is less than the length of time occupied by N symbols.

[0222] In one embodiment, when the end of the first symbol does not precede the start of the second symbol, the end of the first symbol precedes the start of the second symbol by less than N symbols.

[0223] In one embodiment, "the end of the first symbol is less than N symbols before the start of the second symbol" means that the end of the first symbol is not at least N symbols before the start of the second symbol.

[0224] Embodiment 7 Embodiment 7 shows a schematic diagram illustrating that the end of the first symbol cannot be less than N symbols before the start of the second symbol according to one embodiment of the present application, as shown in FIG.

[0225] In embodiment 7, when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

[0226] In one embodiment, when the coresetPoolIndex value to which the first PDCCH is associated is the same as the coresetPoolIndex value to which the second PUSCH is associated, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values.

[0227] In one embodiment, when the first node is not configured with different coresetPoolIndex values, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values.

[0228] In one embodiment, "the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values" means that the first PUSCH and the second PUSCH are not associated with different coresetPoolIndex values.

[0229] In one embodiment, "the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values" means that the first PDCCH and the DCI used to activate the second PUSCH are not associated with control resource sets that have different coresetPoolIndex values.

[0230] In one embodiment, the phrase "the end of the first symbol cannot precede the start of the second symbol by less than N symbols" means that the end of the first symbol is not allowed to precede the start of the second symbol by less than N symbols.

[0231] In one embodiment, the phrase "the end of the first symbol cannot precede the start of the second symbol by less than N symbols" means that the end of the first symbol cannot precede the start of the second symbol by less than N symbols. The thing is that it is not predicted to occur less than N symbols before the start of symbol 2.

[0232] In one embodiment, the expression "the end of the first symbol cannot precede the start of the second symbol by less than N symbols" means that it is not within the prediction of the first node that the end of the first symbol precedes the start of the second symbol by less than N symbols.

[0233] In one embodiment, "the end of the first symbol is less than N symbols before the start of the second symbol" means that the end of the first symbol is not at least N symbols before the start of the second symbol.

[0234] In one embodiment, the phrase "the end of the first symbol cannot precede the start of the second symbol by less than N symbols" means that the end of the first symbol precedes the start of the second symbol by at least N symbols.

[0235] In one embodiment, the end of a first symbol precedes the start of a second symbol by at least N symbols when the end of the first symbol is not later than the start of the second symbol and the interval between the end of the first symbol and the start of the second symbol is not shorter than the length of time occupied by N symbols.

[0236] In one embodiment, the end of a first symbol precedes the start of a second symbol by at least N symbols when the end of the first symbol is not later than the start of the second symbol and the interval between the end of the first symbol and the start of the second symbol is longer than the length of time occupied by N symbols.

[0237] Embodiment 8 Embodiment 8 illustrates a structural block diagram of a processing device in a first node device, as shown in Fig. 8. In Fig. 8, a processing device 800 of the first node device includes a first receiver 801 and a first transmitter 802.

[0238] In one embodiment, the first node device 800 is a base station.

[0239] In one embodiment, the first node device 800 is a user equipment.

[0240] In one embodiment, the first node device 800 is a relay node.

[0241] In one embodiment, the first node device 800 is a vehicle-mounted communication device.

[0242] In one embodiment, the first node device 800 is a user equipment having a single panel.

[0243] In one embodiment, the first node device 800 is a user equipment having multiple panels.

[0244] In one embodiment, the first receiver 801 comprises at least one of the antenna 452, the receiving device 454, the multi-antenna receiving processor 458, the receiving processor 456, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0245] In one embodiment, the first receiver 801 comprises at least the first five of the antenna 452, the receiving device 454, the multi-antenna receiving processor 458, the receiving processor 456, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0246] In one embodiment, the first receiver 801 comprises at least the first four of the antenna 452, the receiving device 454, the multi-antenna receiving processor 458, the receiving processor 456, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0247] In one embodiment, the first receiver 801 comprises at least the first three of the antenna 452, the receiving device 454, the multi-antenna receiving processor 458, the receiving processor 456, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0248] In one embodiment, the first receiver 801 comprises at least the first two of the antenna 452, the receiving device 454, the multi-antenna receiving processor 458, the receiving processor 456, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0249] In one embodiment, the first transmitter 802 comprises at least one of the antenna 452, the transmitting device 454, the multi-antenna transmit processor 457, the transmit processor 468, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0250] In one embodiment, the first transmitter 802 comprises at least the first five of the antenna 452, the transmitting device 454, the multi-antenna transmit processor 457, the transmit processor 468, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0251] In one embodiment, the first transmitter 802 comprises at least the first four of the antenna 452, the transmitting device 454, the multi-antenna transmit processor 457, the transmit processor 468, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0252] In one embodiment, the first transmitter 802 comprises at least the first three of the antenna 452, the transmitting device 454, the multi-antenna transmit processor 457, the transmit processor 468, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0253] In one embodiment, the first transmitter 802 comprises at least the first two of the antenna 452, the transmitting device 454, the multi-antenna transmit processor 457, the transmit processor 468, the controller / processor 459, the memory 460, and the data source 467 in FIG. 4 of the present application.

[0254] In one embodiment, the first receiver 801 receives a first PDCCH, where the first PDCCH ends at a first symbol; the first transmitter 802 transmits a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol, where the first PUSCH and the second PUSCH overlap in the time domain, and where the end of the first symbol is less than N symbols before the start of the second symbol. symbols earlier relates to whether the first PDCCH and second PUSCH are associated with different coresetPoolIndex values, and N depends on the UE processing capability.

[0255] In one embodiment, when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol may precede the start of the second symbol by less than N symbols.

[0256] In one embodiment, when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot precede the start of the second symbol by less than N symbols.

[0257] In one embodiment, the second PUSCH is a PUSCH comprising a configuration grant.

[0258] In one embodiment, the first PUSCH and the second PUSCH are in the same serving cell.

[0259] In one embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0260] In one embodiment, the coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value with which the first PUSCH is associated.

[0261] In one embodiment, ackNackFeedbackMode is configured as a separate entity.

[0262] Embodiment 9 Embodiment 9 illustrates a structural block diagram of a processing device in a second node device, as shown in Figure 9. In Figure 9, a processing device 900 of the second node device includes a second transmitter 901 and a second receiver 902.

[0263] In one embodiment, the second node device 900 is a user equipment.

[0264] In one embodiment, the second node device 900 is a base station.

[0265] In one embodiment, the second node device 900 is a satellite device.

[0266] In one embodiment, the second node device 900 is a relay node.

[0267] In one embodiment, the second node device 900 is a vehicle-mounted communication device.

[0268] In one embodiment, the second node device 900 is a user equipment that supports V2X communication.

[0269] In one embodiment, the second node device 900 is user equipment that supports operation in the high frequency spectrum.

[0270] In one embodiment, the second node device 900 is a user equipment that supports operation in a shared spectrum.

[0271] In one embodiment, the second node device 900 is a user equipment that supports XR services.

[0272] In one embodiment, the second node device 900 is one of a test apparatus, a test device, and a test meter.

[0273] In one embodiment, the second transmitter 901 comprises at least one of the antenna 420, the transmitting device 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0274] In one embodiment, the second transmitter 901 comprises at least the first five of the antenna 420, the transmitting device 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0275] In one embodiment, the second transmitter 901 comprises at least the first four of the antenna 420, the transmitting device 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0276] In one embodiment, the second transmitter 901 comprises at least the first three of the antenna 420, the transmitting device 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0277] In one embodiment, the second transmitter 901 comprises at least the first two of the antenna 420, the transmitting device 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0278] In one embodiment, the second receiver 902 comprises at least one of the antenna 420, the receiving device 418, the multi-antenna receiving processor 472, the receiving processor 470, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0279] In one embodiment, the second receiver 902 comprises at least the first five of the antenna 420, the receiving device 418, the multi-antenna receiving processor 472, the receiving processor 470, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0280] In one embodiment, the second receiver 902 comprises at least the first four of the antenna 420, the receiving device 418, the multi-antenna receiving processor 472, the receiving processor 470, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0281] In one embodiment, the second receiver 902 comprises at least the first three of the antenna 420, the receiving device 418, the multi-antenna receiving processor 472, the receiving processor 470, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0282] In one embodiment, the second receiver 902 comprises at least the first two of the antenna 420, the receiving device 418, the multi-antenna receiving processor 472, the receiving processor 470, the controller / processor 475, and the memory 476 in FIG. 4 of the present application.

[0283] In one embodiment, the second transmitter 901 transmits a first PDCCH, where the first PDCCH ends at a first symbol, and the second receiver 902 receives a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH and the second PUSCH starts at a second symbol, and the first PUSCH and the second PUSCH overlap in the time domain, and whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on the UE processing capability.

[0284] In one embodiment, when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol may precede the start of the second symbol by less than N symbols.

[0285] In one embodiment, when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot precede the start of the second symbol by less than N symbols.

[0286] In one embodiment, the second PUSCH is a PUSCH comprising a configuration grant.

[0287] In one embodiment, the first PUSCH and the second PUSCH are in the same serving cell.

[0288] In one embodiment, N is the number of symbols occupied by the PUSCH preparation time.

[0289] In one embodiment, the coresetPoolIndex value with which the first PDCCH is associated is the coresetPoolIndex value with which the first PUSCH is associated.

[0290] In one embodiment, ackNackFeedbackMode is configured as a separate entity.

[0291] Those skilled in the art will understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium such as a read-only memory, a hard disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module unit in the above embodiments can be implemented in the form of hardware or a software function module. This application is not limited to a specific combination of software and hardware. The first node device in this application includes, but is not limited to, a mobile phone, a tablet computer, a laptop, a network access card, a low-power device, an eMTC device, an NB-IoT device, a vehicle-mounted communication device, an aircraft, an airplane, a drone, a remote-controlled aircraft, and other wireless communication devices. The second node device in this application includes, but is not limited to, a mobile phone, a tablet computer, a laptop, a network access card, a low-power device, an eMTC device, an NB-IoT device, a vehicle-mounted communication device, an aircraft, an airplane, a drone, a remote-controlled aircraft, and other wireless communication devices. The term "user equipment" or "UE" or "terminal" as used herein includes, but is not limited to, a mobile phone, a tablet computer, a laptop, a network access card, a low-power device, an eMTC device, an NB-IoT device, a vehicle-mounted communication device, an aircraft, an airplane, a drone, a remote-controlled aircraft, and other wireless communication devices. The term "base station device" or "base station or network side device" as used herein includes, but is not limited to, a macrocell base station, a microcell base station, a home base station, a relay base station, an eNB, a gNB, a transmission / reception point (TRP), a GNSS, a relay satellite, a satellite base station, an airborne base station, a test equipment, a test device, a test instrument, etc.

[0292] Those skilled in the art should understand that the present invention can be implemented in other specified forms without departing from its core or essential characteristics. Therefore, the presently disclosed embodiments should be considered in any way as descriptive, rather than limiting. The scope of the present invention is determined by the appended claims, rather than the foregoing description, and all changes within the meaning and realm of equivalents are deemed to be embraced therein.

Claims

1. a first node used for wireless communication, a first receiver for receiving a first PDCCH, the first PDCCH ending at a first symbol; a first transmitter transmitting a first PUSCH and a second PUSCH, wherein the first PDCCH schedules the first PUSCH, the second PUSCH starts at a second symbol, the second PUSCH is a PUSCH comprising a configuration grant, the first PUSCH and the second PUSCH are in the same serving cell, and the first PUSCH and the second PUSCH overlap in a time domain; Including, Whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability, and the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value to which the first PUSCH is associated. The first node.

2. 2. The first node of claim 1, wherein when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol.

3. 3. The first node of claim 1, wherein when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

4. 3. The first node of claim 1, wherein when the coresetPoolIndex value with which the first PDCCH is associated is the same as the coresetPoolIndex value with which the second PUSCH is associated, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

5. 5. The first node according to claim 1, wherein the expressions "whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" and "whether the first PUSCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

6. The first node according to any one of claims 1 to 5, wherein N is the number of symbols occupied by PUSCH preparation time, and N is determined based on UE processing capability.

7. The first node according to any one of claims 1 to 6, wherein N is based on the smaller of a subcarrier spacing corresponding to the second PUSCH and a subcarrier spacing corresponding to the first PDCCH.

8. 8. The first node according to claim 1, wherein the first node is configured with higher layer parameters PDCCH-Config for an active BWP (Bandwidth Portion) of one serving cell, the higher layer parameters PDCCH-Config including two different coresetPoolIndex values ​​in a ControlResourceSet.

9. 9. The first node according to claim 1, wherein the coresetPoolIndex value to which the first PDCCH is associated is configurable and the coresetPoolIndex value to which the second PUSCH is associated is configurable.

10. The first node according to any one of claims 1 to 9, wherein ackNackFeedbackMode is configured as a separate entity.

11. a second node used for wireless communication, a second transmitter for transmitting a first PDCCH, the first PDCCH ending at a first symbol; a second receiver receiving a first PUSCH and a second PUSCH, wherein the first PDCCH schedules the first PUSCH, the second PUSCH starts at a second symbol, the second PUSCH is a PUSCH comprising a configuration grant, the first PUSCH and the second PUSCH are in the same serving cell, and the first PUSCH and the second PUSCH overlap in the time domain; Including, Whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability, and the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value to which the first PUSCH is associated. The second node.

12. 12. The second node of claim 11, wherein when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol.

13. 13. The second node of claim 11 or 12, wherein when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

14. 13. The second node of claim 11 or 12, wherein when the coresetPoolIndex value with which the first PDCCH is associated is the same as the coresetPoolIndex value with which the second PUSCH is associated, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

15. 15. The second node according to claim 11, wherein the expressions "whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" and "whether the first PUSCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

16. The second node according to any one of claims 11 to 15, wherein N is determined based on UE processing capabilities.

17. The second node according to any one of claims 11 to 16, wherein N is based on the smaller of a subcarrier spacing corresponding to the second PUSCH and a subcarrier spacing corresponding to the first PDCCH.

18. The second node according to any one of claims 11 to 17, wherein N is the number of symbols occupied by the PUSCH preparation time.

19. 19. The second node according to any one of claims 11 to 18, wherein the coresetPoolIndex value to which the first PDCCH is associated is configurable and the coresetPoolIndex value to which the second PUSCH is associated is configurable.

20. The second node according to any one of claims 11 to 19, wherein ackNackFeedbackMode is configured as a separate entity.

21. 1. A method for use in a first node for wireless communication, comprising: receiving a first PDCCH, the first PDCCH ending at a first symbol; transmitting a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH, the second PUSCH starts at a second symbol, the second PUSCH is a PUSCH comprising a configuration grant, the first PUSCH and the second PUSCH are in the same serving cell, and the first PUSCH and the second PUSCH overlap in the time domain; Including, Whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability, and the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value to which the first PUSCH is associated. method.

22. 22. The method in a first node of claim 21, wherein when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol.

23. When the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol is 23. A method in a first node according to claim 21 or 22, wherein the first symbol cannot be less than N symbols before the start of a symbol.

24. 23. The method in a first node of claim 21 or 22, wherein when the coresetPoolIndex value with which the first PDCCH is associated is the same as the coresetPoolIndex value with which the second PUSCH is associated, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

25. 25. The method in a first node according to any one of claims 21 to 24, wherein the expressions "whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" and "whether the first PUSCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

26. The method in a first node according to any one of claims 21 to 25, wherein N is the number of symbols occupied by the PUSCH preparation time, and said N is determined based on UE processing capability.

27. 27. The method in a first node according to any one of claims 21 to 26, wherein N is based on the smaller of a subcarrier spacing corresponding to the second PUSCH and a subcarrier spacing corresponding to the first PDCCH.

28. 28. The method in a first node according to any one of claims 21 to 27, wherein the first node is configured with a higher layer parameter PDCCH-Config of an active BWP (Bandwidth Portion) of one serving cell, the higher layer parameter PDCCH-Config including two different coresetPoolIndex values ​​in a ControlResourceSet.

29. 29. The method in a first node according to any one of claims 21 to 28, wherein the coresetPoolIndex value to which the first PDCCH is associated is configurable and the coresetPoolIndex value to which the second PUSCH is associated is configurable.

30. The method in a first node according to any one of claims 21 to 29, wherein ackNackFeedbackMode is configured as a separate entity.

31. 1. A method for use in a second node for wireless communication, comprising: transmitting a first PDCCH, the first PDCCH ending at a first symbol; receiving a first PUSCH and a second PUSCH, where the first PDCCH schedules the first PUSCH, the second PUSCH starts at a second symbol, the second PUSCH is a PUSCH comprising a configuration grant, the first PUSCH and the second PUSCH are in the same serving cell, and the first PUSCH and the second PUSCH overlap in the time domain; Including, Whether the end of the first symbol can precede the start of the second symbol by less than N symbols is related to whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, where N depends on UE processing capability, and the coresetPoolIndex value to which the first PDCCH is associated is the coresetPoolIndex value to which the first PUSCH is associated. method.

32. 32. The method in a second node of claim 31 , wherein when the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values, the end of the first symbol can be less than N symbols before the start of the second symbol.

33. 33. The method in a second node according to claim 31 or 32, wherein when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

34. 33. The method in a second node of claim 31 or 32, wherein when the coresetPoolIndex value with which the first PDCCH is associated is the same as the coresetPoolIndex value with which the second PUSCH is associated, the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, and when the first PDCCH and the second PUSCH are not associated with different coresetPoolIndex values, the end of the first symbol cannot be less than N symbols before the start of the second symbol.

35. 35. A method in a second node according to any one of claims 31 to 34, wherein the expressions "whether the first PDCCH and the second PUSCH are associated with different coresetPoolIndex values" and "whether the first PUSCH and the second PUSCH are associated with different coresetPoolIndex values" are equivalent or interchangeable.

36. A method in a second node according to any one of claims 31 to 35, wherein N is determined based on UE processing capabilities.

37. 37. The method in a second node according to any one of claims 31 to 36, wherein N is based on the smaller of a subcarrier spacing corresponding to the second PUSCH and a subcarrier spacing corresponding to the first PDCCH.

38. A method in a second node according to any one of claims 31 to 37, wherein N is the number of symbols occupied by PUSCH preparation time.

39. 39. The method in a second node according to any one of claims 31 to 38, wherein the coresetPoolIndex value to which the first PDCCH is associated is configurable and the coresetPoolIndex value to which the second PUSCH is associated is configurable.

40. A method in a second node according to any one of claims 31 to 39, wherein ackNackFeedbackMode is configured as a separate entity.

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