Pulse width modulation for phase-modulating displays.

Abstract

A method for controlling a pulse-width-modulated liquid crystal display is disclosed, in which a repeat period includes A group periods, each group period includes B modulation sections, each modulation section spanning H unit durations, and each modulation section except the last modulation section in the repeat period includes one remainder unit duration. A desired number N of unit duration pulses are distributed among the H unit duration pulses in each modulation section, and the desired remainder pulses are distributed among the multiple remainder unit durations of the modulation sections. A drive sequence is generated in which the repeat period is repeated one or more times.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 440,675, filed February 13, 2024, which claims priority to U.S. Provisional Patent Application No. 63 / 487,795, filed March 1, 2023, entitled "PULSE WIDTH MODULATION FOR PHASE-MODULATING DISPLAY," each of which is incorporated herein by reference in its entirety. [Background technology]

[0002] One goal of phase-modulation applications is to minimize phase ripple, which is undesirable because it obscures detail in the images produced by the phase-modulating display. This goal is particularly challenging for digitally driven liquid crystal displays (LCDs), because these displays can be written to only one of two voltages during operation: a drive voltage corresponding to full "on" (or minimum optical retardation) and a relaxation voltage corresponding to full "off" (or maximum optical retardation). Actual images require the ability to adjust the optical phase retardation, or phase shift, over a continuous range between these limits. In digital displays, this is typically accomplished by repeatedly writing a sequence of "1s" and "0s" to the pixels at a rate much faster than the rise and fall times of the pixel's liquid crystal elements. The liquid crystal (LC) elements respond to this alternating pulse train as a root-mean-square (RMS) voltage determined by the duty cycle of the applied voltage pulses (i.e., the ratio or comparison of the drive voltage time to the relaxation voltage time).

[0003] While this fast-alternating technique allows for highly accurate phase modulation, it does have some limitations. In particular, due to the rapidly alternating voltage waveform, some residual ripple typically exists in the liquid crystal element's response. The magnitude of this ripple is determined by the relationship (e.g., ratio) of the on / off times of the voltage pulse (drive voltage time and relaxation voltage time) to the liquid crystal element's response time. If the liquid crystal element's response time is much slower than the on / off time of the voltage across the liquid crystal element, the amount of ripple will be small due to the averaging effect of the relatively slow liquid crystal element's response. Conversely, if the on / off times of the voltage waveform are long and approach the liquid crystal element's response time, the liquid crystal element will respond partially to each on pulse and off pulse, resulting in significant optical ripple.

[0004] It would therefore be beneficial to provide a technique for driving a phase modulating display with a voltage waveform that reduces phase ripple.

[0005] The drawings are not necessarily drawn to scale, and like numbers may indicate similar components in different views. To easily identify a particular element or description of a process, the most significant digit(s) of a reference number indicates the number of the figure in which that element is first introduced. Some non-limiting examples are shown in the accompanying drawings below. [Brief explanation of the drawings]

[0006] [Figure 1A] The delayed response of a liquid crystal element to a voltage waveform with long alternating periods of drive and relaxation voltages is shown, and the principles underlying some examples are presented. [Figure 1B] The delayed response of a liquid crystal element to a voltage waveform having short alternating periods of drive and relaxation voltages is shown, and the principles underlying some examples are presented. [Figure 2A] Voltage waveforms dominated by relaxation voltages are shown, illustrating the principles underlying some examples. [Figure 2B] The voltage waveforms, dominated by the driving voltage, are shown, illustrating the principles underlying some examples. [Figure 3]5 is a flowchart illustrating operations of a method for controlling a pulse-width modulated liquid crystal display, according to some examples. [Figure 4] 10 illustrates a bit mapping scheme for a drive sequence with overdrive and pre-emphasis periods according to some examples. [Figure 5A] 6 illustrates a first group of repeating periods encoding a grayscale code 666, according to some examples. [Figure 5B] 2 illustrates a first group of repeating periods encoding a grayscale code 282, according to some examples. [Figure 5C] 1 illustrates a first group of repeating periods encoding a grayscale code 26, according to some examples. [Figure 6A] 10 illustrates a first group of repeating periods encoding grayscale code 896, according to some examples. [Figure 6B] 9 illustrates a first group of repeating periods encoding a grayscale code 912, according to some examples. [Figure 6C] 9 illustrates a first group of repeating periods encoding a grayscale code 913, according to some examples. [Figure 7] 10 shows a repeat period of a drive sequence according to some examples, and shows an expanded detailed view of a second group period and a further expanded detailed view of the first and eighth modulation sections of the second group period. [Figure 8A] 10 shows a graph of liquid crystal delay over time for a liquid crystal element of a pixel driven by a driving sequence in accordance with some examples. [Figure 8B] 10A-10C show graphs of liquid crystal delay over time for a liquid crystal element of a pixel driven by each drive sequence for a high grayscale code value with pre-emphasis, a low grayscale code value with pre-emphasis, and a low grayscale code value without pre-emphasis, according to some examples. [Figure 9]1 shows a block diagram of a system for generating drive sequences and driving pixels according to some examples. [Figure 10] 1 illustrates a pixel circuit for driving a liquid crystal element of a pixel according to a received drive sequence, according to some examples. [Figure 11A] 1 illustrates an example timing diagram of an image frame of pixels of a color sequential display, according to some examples. [Figure 11B] 11 shows an example timing diagram of the ODC, G, and SEL signals of the pixel circuit 1000 of FIG. [Figure 11C] 10 shows an example timing diagram of the ROW and DATA signals controlling a column of pixels implemented using the pixel circuit 1000 of FIG. [Figure 11D] 11 shows an example timing diagram of the G and SEL signals during an example cycle period for the pixel circuit 1000 of FIG. 10. DETAILED DESCRIPTION OF THE INVENTION

[0007] This specification describes an example of a technique for controlling a pulse-width modulation liquid crystal display (PWM LCD). As described above, in a digital PWM LCD, phase ripple can occur if the pulse width (i.e., drive voltage period) or the time width between pulses (i.e., relaxation voltage period) is long compared to the relaxation time of the liquid crystal elements in the pixel. However, in a digital LCD control scheme, the number of bits available for encoding the drive sequence to control the pulse width is limited by the system's allowable size, complexity, and power consumption. Therefore, there is a trade-off between three different factors: minimizing the bit length of the drive sequence, achieving fine gradations of pixel grayscale values, and minimizing phase ripple. In the example described here, by evenly distributing pulses of slightly different widths over the period in which the display pixels are driven, a binary drive sequence can be provided that achieves fine grayscale resolution while reducing phase ripple and encodes the drive sequence using a relatively small number of bits.

[0008] As described above, the pixels of the display are driven by a drive sequence made up of voltage levels. At high voltage levels, the pixels are driven to a full "on" state (i.e., minimum phase lag, maximum transmittance), and at low voltages, the pixels are driven to a full "off" state (i.e., maximum phase lag, minimum transmittance). As used herein, the term "transmittance" refers to the degree to which a liquid crystal element allows light to propagate without delay, and transmittance is inversely related to phase lag.

[0009] As mentioned above, the magnitude of the phase ripple of a phase modulation display is determined by the relationship (e.g., ratio) of the on / off time of the voltage pulse (i.e., the time of the drive voltage and the relaxation voltage) to the response time of the liquid crystal element. Therefore, to achieve low ripple phase modulation, it is advantageous to make the alternating voltage pulses as fast as possible compared to the response time of the liquid crystal.

[0010] It will be appreciated that there are many ways to construct a sequence of 1s and 0s that average to the same value. For example, in an 8-bit system, there are 256 periods occupied by these pulses. (The basic period in the examples described herein is referred to as a "unit duration," but in some examples corresponds to the shortest time unit encoded by a binary sequence and may correspond to the least significant bit (LSB) of the binary sequence.) Suppose a grayscale value corresponding to an RMS value of 50% of the voltage range is desired. This corresponds to 128 unit duration pulses out of 256 possible unit durations, and the grayscale value is encoded as a binary grayscale code value of 127. This grayscale value can be achieved with a voltage sequence of 128 "on" periods (i.e., 128 unit periods during which a drive voltage is applied) followed by 128 "off" periods (i.e., 128 unit duration periods during which a relaxation voltage is applied). Alternatively, the sequence could consist of 64 unit durations on, 64 unit durations off, 64 unit durations on, and 64 unit durations off. Or, the sequence could be repeated 16 times (8 on, 8 off). At the limit, the sequence could be repeated 128 times (1 unit duration on, 1 unit duration off). It will be appreciated that a 128 on / 128 off sequence provides the longest dwell time at each voltage, allowing the liquid crystal elements time to at least partially respond to each voltage, resulting in the greatest optical ripple at the expense of more toggling and therefore more dynamic power consumption. Conversely, a 1 on / 1 off sequence provides the shortest time for the liquid crystal elements to respond to individual voltage pulses, and the liquid crystal elements tend to follow the RMS average of the applied voltage, resulting in significantly lower phase ripple.

[0011] FIG. 1A qualitatively illustrates the voltage waveforms and resulting transmittance of a liquid crystal element for a typical display in a 128-on / 128-off case. The two waveforms are shown on a common horizontal time scale. The liquid crystal transmittance 102 waveform shows the degree of transmittance of the liquid crystal element (i.e., no phase lag) when a voltage waveform 104 is applied to the liquid crystal element. The pulse width 106 is relatively wide, 128 unit durations out of a 256-unit duration period; that is, each pulse lasts half the full 256 unit duration (four such periods are shown in FIG. 1A). Because the 128 unit duration is long compared to the liquid crystal relaxation period, the phase ripple 108 is correspondingly relatively high in this example because the liquid crystal transmittance 102 fluctuates dramatically before and after each pulse.

[0012] Figure 1B shows the same data as Figure 1A for the 32 on / 32 off case. The liquid crystal transmittance 112 waveform indicates the degree of transmittance of the liquid crystal element when voltage waveform 110 is applied across it. The pulse width 114 is relatively narrow, only 32 of the 256 unit durations. Because 32 unit durations is short compared to the liquid crystal relaxation period, in this example, the phase ripple 116 is correspondingly relatively low because the liquid crystal transmittance 112 fluctuates a small amount before and after each pulse.

[0013] It will be appreciated that phase shifts between very low and very high levels tend to be problematic in pulse-width-modulated liquid crystal display systems. For an 8-bit system with a repetition period of 255 unit durations (e.g., an 8-bit encoding representing grayscale values ​​from 0 to 255), a desired modulation code (e.g., a binary grayscale code) of "2" requires a pulse sequence that results in a drive voltage for a total of two unit durations and a relaxation voltage for the other 253 unit durations. Similarly, a desired modulation code of "253" requires a pulse sequence that results in a drive voltage for a total of 253 unit durations and a relaxation voltage for only two unit durations. While these cases are highly irregular in nature, the best that can be done in these cases is usually to distribute the modulation pulses as evenly as possible. In fact, this is a general goal for many types of pulse sequences; i.e., to achieve the lowest possible ripple, the distribution of on and off pulses within each sequence should be as uniform as possible.

[0014] 2A shows an illustrative example of a drive sequence using a conventional binary PWM scheme to implement a very low grayscale value, here shown as a grayscale code value of 2 (out of a possible 255). The drive sequence drives a voltage waveform dominated by a relaxation voltage over a first repetition period 206 consisting of 255 unit durations (t=0 to t=255), interrupted only by one short pulse 202 of two unit durations. A second repetition period 208 begins with another one short pulse of two unit durations (t=255 to t=257), and so on. These frames produce an RMS average value 204 of 2 out of a possible 255, corresponding to the desired grayscale value of 2.

[0015] Figure 2B is another illustrative example of a drive sequence similar to Figure 2A, but shown at the other extreme. In Figure 2B, a very high grayscale value, here shown as grayscale code value 253 (out of a possible 255), is implemented using a conventional binary PWM scheme. The drive sequence drives a voltage waveform dominated by a drive voltage comprised of long pulses 214 that occupy 253 of the 255 unit durations of the first repeat period 210. The second repeat period 212 repeats this pattern. Each frame has an RMS average 216 of 253, corresponding to the desired grayscale value of 253.

[0016] However, as noted above, there are typically conflicting requirements and trade-offs between different designs. Driving very fast pulse sequences on large pixel arrays (as is typical in modern displays) can be electrically challenging due to the extremely high data rates required. For example, high-definition (HD) displays typically have approximately 2.2 million pixels. In such displays, writing a sequence of 1s and 0s (possibly different values) to each of these pixels in a column multiple times over a given frame time (e.g., the time it takes for one video frame to be displayed on an LCD) (as in the above-mentioned "once on / once off" case shown in Figure 1B) can be difficult or power-intensive. Another approach is to incorporate WM or DFM modulation hardware into each pixel and configure this hardware to handle the modulation of the pixel based on the written multi-bit data word (i.e., binary drive sequence). This approach addresses the challenge of designing pixel circuitry that can perform this function without excessive complexity. The amount of digital circuitry that needs to be incorporated into each pixel to achieve realistic performance targets would increase the pixel size and pixel pitch, potentially resulting in an overall display size that is too large for the intended use.

[0017] The examples described herein with reference to Figures 3-11A may provide techniques for creating drive sequences that are relatively simple to implement in pixel circuits, yet achieve near-optimal phase ripple results for a given atomic time duration. Some examples describe 10-bit encoding of drive sequences that can be processed by pixel circuits that drive voltages for pixels in pulse-width-modulated liquid crystal displays. In other examples, the implementation of drive sequences can be modified to achieve bit depths greater than or less than 10 bits.

[0018] (Example of how to generate a drive sequence)

[0019] In some examples, a mixed-mode method can be used to generate a drive sequence for a pixel. In some examples, the drive sequence controls the transmittance of the liquid crystal of the pixel over the time it takes the display to display one frame (called a "frame time") or, in the case of a color-sequential display, one color sub-frame. Modern LCDs display frames at a refresh rate, or frame rate, of many frames per second, such as 30 Hz or 120 Hz. In a color-sequential display, each frame is displayed as a series of color sub-frames, such as three color sub-frames per frame (e.g., for an RGB display with a frame rate of 120 Hz, the color sub-frame rate (CSFR) is 360 Hz). The drive sequence is configured to maintain a desired grayscale value of the pixel over the frame time, e.g., to maintain either the grayscale value of the pixel as a whole for the duration of the entire frame or a color-specific grayscale value for the duration of a color sub-frame for a particular color.

[0020] In the examples shown in FIGS. 3-11A, the drive sequence consists of a repeating sequence of repeat periods (referred to herein as a repeat sequence) encoded as a repeating binary sequence, optionally preceded by a pre-emphasis period (also referred to as an "overdrive" period, sometimes encoded as a binary overdrive duration value), followed by a relaxation period, or both. Each repeat period consists of 16 group periods configured as described below. Each group period, in turn, consists of 8 modulation sections configured as described below. Each modulation section corresponds to a pulse of variable width, with the pulse widths of the various modulation sections within a single repeat period varying from one another by at most one unit duration. In the illustrated example, each modulation section consists of a pulse train of 0 to 7 unit interval pulses, with or without one additional unit interval "remainder" pulse depending on the particular grayscale value desired.

[0021] By converting grayscale values ​​into a large number of relatively short pulses and reducing the variation between pulse widths, drive sequences generated in accordance with some examples described herein may address the technical challenge of reducing phase ripple in an image generated by each pixel of a pulse-width modulated display (such as a pulse-width modulated liquid crystal display), while also addressing the technical challenge of encoding and decoding a large number of short pulses according to a simple 10-bit encoding and decoding scheme. This not only improves the functionality of displays such as LCDs, but also the functionality of computers and other digital logic that drive displays by allowing for simple, uncomplicated encoding and decoding of drive sequences for each pixel while reducing phase ripple in the image generated by the display.

[0022] It will be appreciated that in some examples, one or more of such advantages may be achieved while using a different number of group periods, a different number of modulation intervals, a different modulation interval duration, a different residual bit distribution, or a different bit encoding than the examples described herein. For example, in some examples encoding a repeating period having 16 group periods, another 10-bit encoding for the repeating period of the drive sequence may be used, with each of the 16 group periods having four modulation intervals of 16 unit duration (with the last modulation interval of the last group period being 15 unit duration).

[0023] Because each pulse train (driven over the modulation interval) has a width that differs from the others by at most one unit duration, the drive sequence has a short-term RMS voltage that is as close to constant as possible for a given unit duration. At the highest code values ​​(e.g., 1020 out of 1023 possible grayscale values), these durations begin to integrate with each other, appearing as longer pulses. This is unavoidable if the entire available duration is to be utilized. At the limit, for a grayscale value of 1023, all pulses combine, resulting in a continuously higher voltage. Similarly, for a grayscale value of 0, the voltage value remains continuously lower, as expected.

[0024] As noted above, the drive sequence structure for a repetition period is 16 repetitions of the group period, with each group period containing a set of eight modulation sections. The pulses corresponding to the modulation sections all have the same duration (referred to as the main segment pulse duration, denoted here as H) ranging from 0 to 7 unit durations, with the possible exception of an additional "extra" pulse having a duration of one unit duration. Determining the value of H and the distribution of the extra pulses may, in some examples, be performed according to method 300 shown in the flowchart of FIG. 3.

[0025] 3 illustrates an example method 300 for controlling a pulse-width-modulated liquid crystal display by generating a drive sequence. Although the example method 300 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different order without substantially affecting the functionality of the method 300. In other examples, different components of an example device or system implementing the method 300 may perform functions substantially simultaneously or in a particular order.

[0026] According to some examples, the method includes receiving a grayscale value between a minimum grayscale value and a maximum grayscale value at operation 302. The grayscale value may be of any scale, such as an integer value between 0 and 255, or a real value (e.g., represented as a floating-point number encoding).

[0027] According to some examples, the method includes, in operation 304, converting the grayscale value into a number N representing a desired number of unit duration pulses in a repetition period of the drive sequence. As described above, the repetition period is made up of a first number A of group periods (e.g., A=16 in the illustrated example), each group period is made up of a second number B of modulation sections (e.g., B=8 in the illustrated example), and each modulation section is made up of a third number (C−1) of unit durations (e.g., C=8 in the illustrated example). Each modulation section, except for the last modulation section of the last group period, is followed by one additional unit duration, so that the repetition period spans ((A×B×C)−1) unit durations. A detailed diagram of this structure is shown in Figure 7 below.

[0028] The conversion performed in operation 304 essentially normalizes the grayscale values ​​to the number of unit durations in the repeat period. Thus, the output of operation 304 is N=0 for the minimum grayscale value and N=(A×B×C)−1 for the maximum grayscale value. Thus, for example, in an example where the repeat period spans 1023 unit durations, N ranges from 0 to 1023, and A=16, B=8, and C=8, operation 304 normalizes the grayscale values ​​to values ​​between N=0 and N=1023.

[0029] According to some examples, the method includes determining a number of baseline pulses for the group period, D, in operation 306, equal to the Euclidean integer quotient of N divided by A. Thus, in the above example, if the normalized grayscale value is N=666, then the Euclidean integer quotient of N divided by A, D=666, divided by 16 is 41.

[0030] According to some examples, the method includes determining a number of baseline pulses H for the modulation interval in operation 308, equal to the integer quotient obtained by Euclidean division of D by B. Thus, in the above example, the integer quotient of the Euclidean division of D by B, H=41, is divided by 8, resulting in an integer quotient of 5, with a remainder of 1.

[0031] According to some examples, the method includes determining a main segment modulation section pattern of H unit duration pulses in the first H unit durations of each modulation section in operation 310. Thus, in the above example, the eight unit duration modulation section begins with a five unit duration main segment pulse. This may be followed by a three unit duration relaxation voltage period, or, if one extra pulse is added to the modulation section, one additional unit duration pulse followed by a two unit duration relaxation voltage period.

[0032] According to some examples, the method includes, in operation 312, determining a repeating period remainder L2 equal to the integer remainder obtained from Euclidean division of N by A, and determining a group period remainder L equal to the integer remainder obtained from Euclidean division of D by B. Thus, in the above example, the remainder obtained from N divided by A, L2=666, is divided by 16 to obtain a remainder of 10, and the remainder obtained from D divided by B, L=41, is divided by 8 to obtain a remainder of 1.

[0033] It will be appreciated that in some examples, in operations 306, 308, 310, and 312, the values ​​D, H, L, and L2 may be determined using a relatively simple binary mapping operation, such as the exemplary binary mapping shown in FIG. 4 and described below.

[0034] According to some examples, the method includes determining a baseline group period pattern in operation 314. The baseline group period pattern consists of a main segment modulation period pattern applied to each modulation period of the group period and L additional unit duration pulses assigned to unit durations following the first H unit durations in each of the L modulation periods selected from the group period.

[0035] In some examples, the L modulation intervals are selected in operation 314 using a rule or lookup table that distributes the L residual pulses evenly across the group period. An example lookup table for B=8 is shown below. The lookup table indicates which L modulation intervals are selected from eight consecutive modulation intervals in each group period. [Table 1]

[0036] As can be seen from the L remainder lookup table above, L remainder pulses are not added to the last (e.g., eighth) modulation interval of a group period. The last unit duration of the last modulation interval of each group period is reserved to handle L2 remainder pulses in operation 316 below.

[0037] According to some examples, the method includes determining a repeat sequence for the repeat period in operation 316. The repeat sequence consists of a baseline group period pattern repeated for each group period of the repeat period and L2 additional unit duration pulses assigned to unit durations following the first H unit durations of the last modulation interval of each of L2 selected group periods from the repeat period.

[0038] In some examples, similar to operation 314, operation 316 selects the L modulation intervals using a rule or lookup table that distributes the L residual pulses evenly across the group periods. An example lookup table for A=16 is shown below: The lookup table below shows the L group periods selected from 16 consecutive group periods of the repetition period. [Table 2]

[0039] As can be seen from the L2 lookup table above, no remainder is added to the last (e.g., 8) modulation interval of the last (e.g., 16) group period. In the illustrated 10-bit encoding example, this last unit duration of the repeat period is omitted from the repeat sequence, and the next repeat period begins immediately. However, in some examples, this last bit of the repeat sequence can be used to achieve a higher bit depth or for other purposes. However, in the examples shown herein, omitting this last bit means that the 10-bit encoding of the repeat sequence can encode up to 10 (= 2) unit durations of drive voltage (i.e., unit duration pulses) or relaxation voltage (i.e., absence of pulses).

[0040] Thus, in this example where the repetition period spans 1023 unit durations and A=16, B=8, C=8, and N=666, the pulse width for each pulse train in a given modulation interval can be calculated as follows: *Divide the normalized grayscale value N by 16 and keep only the integer part. For example, if N=666, divide by 16 to get 41.63. Truncate the remainder to get 41. *This means that each group period must have 41 unit duration pulses each. * Divide 41 by 8, again keeping only the integer part. In this case, dividing 41 by 8 gives us 5.13 as the unit duration per modulation section. Round down the remainder to get 5. *This means that each modulation interval must have 5 unit duration pulses in its main segment. Denote this value as H (e.g., H=5 in this example). *Multiplying H=5 by C=8 gives a total duration of 40 unit pulse durations per group period, the remainder is L=41-40=1, 1 unit duration per group period. Denote this value as L (e.g., L=1 in this example). *L According to the remainder lookup table, one remainder pulse of unit duration is added to the end of the main segment of the first modulation section of each group period. *This means that the duration of each of the 8 pulse trains in each group period (from first to last) will be 8, 7, 7, 7, 7, 7, 7, 7, 7 unit durations wide. *Multiplying the 41 unit duration of pulses per group period by A=16 leaves us with L2=666-656=10 unit durations per repetition period. Denote this value as L2 (e.g., L2=10 in this example). * According to the L2 remainder lookup table, 10 remainder pulses of one unit duration are added to the end of the main segment of the last modulation section of the last group period. *This means that the duration of each of the 8 pulse trains in the last group period (from first to last) will be 8, 7, 7, 7, 7, 7, 7, 7, 8 unit durations wide.

[0041] According to some examples, the method includes generating a drive sequence for controlling a pulse width modulated liquid crystal display at operation 318. The drive sequence has a repeat sequence that is repeated one or more times.

[0042] (Example of pre-emphasis period)

[0043] For code values ​​less than the maximum grayscale value (e.g., code values ​​less than 1023 in the 10-bit example above), the example method 300 described above may not be as efficient as possible at the beginning of a frame displayed on the display. This is because the liquid crystal needs to approach the desired phase value as quickly as possible, which may require 100% of the duty cycle on-time (i.e., 100% of the time spent at the drive voltage) to reach the desired phase value (assuming the liquid crystal elements begin the frame time at zero transmittance). To address this additional technical challenge, some examples may include a continuous drive voltage of relatively long duration at the beginning of a frame (or subframe, as the case may be). This continuous drive voltage is referred to as a pre-emphasis pulse (or pre-emphasis period or overdrive period). The use of a pre-emphasis period is similar to techniques used in high-speed digital signal transmission.

[0044] Thus, in some examples, the drive sequence further comprises a pre-emphasis period of successive drives (eg, drive voltages) before the repeating sequence is repeated one or more times.

[0045] In some examples, the pre-emphasis period is of different duration depending on the grayscale value. Generally, the higher the desired grayscale value, the longer the pre-emphasis period is required. Determining the optimal duration of the pre-emphasis period may be an empirical process or, in some examples, may be temperature dependent. Thus, in some examples, the pre-emphasis period has a duration that is determined at least in part based on the temperature of the pulse-width-modulated liquid crystal display.

[0046] Once the end of the pre-emphasis period is reached, control of the display may switch to the method 300 outlined above, and the pre-emphasis period may not be repeated until the start of the next image frame or color sub-frame.

[0047] FIG. 4 illustrates a bit mapping scheme for an example drive sequence with overdrive and pre-emphasis periods. The normalized grayscale value N produced in operation 304 is represented as a 10-bit phase value 402. The 10-bit phase value 402 is divided into most significant bits 7-9 (404), which correspond to a main segment value 414, which is H; bits 4-6 (406), which correspond to an L remainder value 416; and bits 0-3 (408), which correspond to an L2 remainder value 418. These three values ​​414, 416, and 418 are processed to generate repeating sequences, respectively, as DATA bits 18-20 (420), DATA bits 15-17 (422), and DATA bits 0-14 (424). The repeating sequences are encoded onto the DATA bus for transmission to the pixel (discussed below with reference to FIG. 10).

[0048] The bit mapping scheme also includes an overdrive mapping table 410 for mapping the value of the most significant bits (bits 7-9 (404) corresponding to the main segment value 414, which is H, and bits 4-6 (406) corresponding to the L remainder value (416)) to an overdrive value 412 indicating the duration of the pre-emphasis period. The overdrive value 412 is encoded on the DATA bus as DATA bits 21-26 (426). Thus, in the illustrated example, the most significant bit of the 10-bit phase value 402 is used to determine the required duration of pre-emphasis. This principle is explained in more detail below with reference to Figures 8A and 8B.

[0049] 5A-5C illustrate respective first group periods 500, 526, 548 of a repetition period in the example described herein. Each illustrated group period 500, 526, 548 has the same values ​​for the L remainder and L2 remainder values, but different values ​​for H. These group periods illustrate the distribution or allocation of the L remainder bits and L2 remainder bits in the first group period of the repetition period.

[0050] FIG. 5A shows a group period 500 with H=5, L=1, and L=10, corresponding to a repetition period with a normalized grayscale code N of 666. The group period 500 begins with a first modulation section 504, in which a first modulation section pattern 502 begins with a main segment pulse of H unit duration 506, followed by a pulse of remainder unit duration 508 (according to an L lookup table that assigns one remainder pulse L=1 to each first modulation section of each group period). The final two unit durations of the first modulation section 504 are relaxation voltages. The second through seventh modulation sections (including an example identified as the third modulation section 516) each have a main segment pulse of five unit durations, with no remainder pulse assigned. The eighth modulation section 518 ends at the end of the group period 514, but begins with a pulse of H unit duration 510, followed by a pulse of remainder unit duration 512. This is because the last modulation interval of the first group period of the repetition period is assigned an L2 remainder pulse according to the L2=10 row of the L2 remainder lookup table. The subsequent (second in this example) group period begins with the same modulation interval as the first group period 500 and is assigned an L remainder pulse duration 520.

[0051] 5B shows the difference in main segment duration from FIG. 5A when the normalized grayscale value N is lowered to 282. As the value of N is lowered, H is lowered from H=5 to H=2. It will be appreciated that although the value of H is lowered by 3 because the normalized grayscale value is (3×128) lower, the L and L2 values ​​are the same as in FIG. 5A, and the residual pulses are assigned to the same modulation interval within group period 526.

[0052] In this example, the group period 526 begins with a first modulation section 524, in which the first modulation section pattern 522 begins with a main segment pulse of H unit duration 528, followed by one pulse of residual unit duration (according to an L lookup table that assigns one residual pulse L=1 to each first modulation section of each group period). The last five unit durations of the first modulation section 524 are relaxation voltages. The second through seventh modulation sections (including the example identified as the third modulation section 540) each have a main segment pulse of two unit durations and no residual pulses assigned. The eighth modulation section 544 ends at the end of the group period 536, but begins with a pulse of H unit duration 532, followed by a pulse of residual unit duration 534. Subsequent group periods begin with the same modulation section as the first group period 526, which is assigned L residual pulse durations 538.

[0053] Figure 5C shows the difference between Figures 5A and 5B in main segment duration when the normalized grayscale value N is reduced to 26. As the value of N is reduced, H is reduced from H=2 to H=0. It will be appreciated that although the value of H is reduced by 2 compared to Figure 5B because the normalized grayscale value is (3 x 128) lower, the L and L2 values ​​are the same as in Figures 5A and 5B, and the residual pulses are assigned to the same modulation interval within group period 548.

[0054] In this example, group period 548 begins with first modulation section 542, where H=0, so first modulation section pattern 546 has a zero-width main segment pulse. Instead, first modulation section 542 begins with a single pulse of remainder unit duration 550. The last seven unit durations of first modulation section 542 are relaxation voltages. The second through seventh modulation sections each have a main segment pulse of zero unit duration and no remainder pulses assigned. Eighth modulation section 556 ends at the end 544 of the group period but begins with a single pulse of remainder unit duration 552. Subsequent group periods begin with the same modulation section as first modulation section 542 of the first group period, and begin with the L remainder pulse unit durations assigned to this modulation section.

[0055] It will be appreciated that the examples described here follow a number of rules: *Within each group period, the set of modulation section pulses always start at the same time, regardless of pulse length or modulus value. In each group period, the first pulse starts at t=0 (relative to the start of the group period), the second pulse starts at t=C (e.g., t=8), the third pulse starts at t=2C (e.g., 16), and so on (times measured in unit durations). The L modulus pulses in each case are added directly to the end of the main segment pulse train. *Even when there is no main segment pulse in a group (H=0), the L remainder pulse and L2 remainder pulse still exist and begin at the time that a main segment pulse would occur in a given modulation interval. Figure 5C shows an example of this when a main segment pulse is absent because H=0. According to the L remainder lookup table, an L remainder pulse should be added to the first modulation interval of the group. Because a main segment pulse is absent, this remainder pulse begins at t=0. According to the L2 remainder lookup table, an L2 remainder pulse should be added to the last pulse of the group, as seen at t=56 in Figure 5C. This L2 remainder pulse should also be added to the eighth pulse in the third, fourth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, and fifteenth group intervals. *For high code values ​​H=C-1 (e.g. H=7), the modulation intervals (except the last modulation interval of the group period) to which L remainders have been added are combined with the beginning of the pulse of the next modulation interval. Similarly, in any sequence where H=C-1 (e.g., H=7), the first pulse of the next group period will be combined with the last pulse of the eighth modulation section of the 16th group period. Examples are shown in Figures 6A to 6C.

[0056] Figure 6A shows the drive sequence for a normalized grayscale code 896. In this example, H=7, L=0, and L2=0. Therefore, all main-segment pulses are seven unit durations long, and there are no residual pulses. Therefore, all gaps between pulses are one unit duration long. A first modulation section 608 includes a first modulation section pattern 602 that begins with a main-segment pulse of H unit durations 604, followed by a gap (at a relaxation voltage) of the remaining unit durations 606. This pattern is repeated for each modulation section until the end 610 of the first group period.

[0057] 6B shows the driving sequence for normalized grayscale code 912. In this example, H=7, L=1, and L2=0. The L=1 entry in the L remainder lookup table requires adding a remainder pulse to the first modulation section of each group period. The remainder pulse added in the remainder unit duration 616 ensures that the pulses in the first modulation section 618 (including the main segment pulses of H unit durations 614 and the remainder pulses of the remainder unit duration 616) and the pulses in the second modulation section are consecutively combined as one pulse, as described above.

[0058] Figure 6C shows a drive sequence for a normalized grayscale code 913, which is one greater than that of Figure 6B. In this example, H=7, L=1, and L2=1. The entry for L2=1 in the L2 remainder lookup table requires an L2 remainder pulse to be added to the last modulation section of the first group period of the repetition period. The L2 remainder pulse added in the remainder unit duration 620 ensures that the pulse in the eighth modulation section 622 and the pulse in the first modulation section of the second group period 624 are continuous together, as described above.

[0059] It will be appreciated that the examples described here follow some additional rules. *Each of the A group periods (e.g., A=16) always starts at the same time, which in the illustrated example are times t=0, t=64, t=128, etc. (in unit duration). *The total duration of one repeat period is 1023 unit durations. If one unit duration is 0.25 μs, the repeat period is 255.75 μs. This is significantly shorter than the typical liquid crystal rise time, so in some cases the repeat sequence may have to be repeated several times to achieve a stable phase modulation level.

[0060] 7 shows, at the top, an activation sequence 702 consisting of a pre-emphasis period 706 followed by multiple repetitions of a repeat period 704 in accordance with the exemplary 10-bit encoding described above. The repeat period 704 begins with a first group period 708 and ends with a sixteenth group period 732. Note that the end of the sixteenth group period 732 coincides with the end of the repeat period 712, but does not include an extra bit, i.e., extra unit duration. However, each of the other group periods includes an L2 extra pulse duration 710 in its last unit duration, i.e., bit position.

[0061] The second row shows a detailed development of the second group period 714. The first modulation section 718 of the second group period 714 follows the end of the first group period 716. The last unit duration of the first modulation section 718 is L remainder unit duration 722. Instead, the eighth modulation section 720 ends with L2 remainder unit duration 724, since this is the last modulation section in the group period.

[0062] The third row shows a detailed exploded view of the first modulation section 718 and the eighth modulation section 720. After the end of the first group period 716, the first modulation section 718 starts at a first unit duration 726 and ends at an L remainder unit duration 722. The eighth modulation section 720 starts at a first unit duration 730 and ends at an L2 remainder unit duration 724.

[0063] It will be appreciated that this drive sequence represents a relatively high grayscale value, where H=C−1, because the L remainder slot and the L2 remainder slot are at the last unit duration position of each modulation interval (as shown in FIGS. 6A-6C).

[0064] 8A shows a graph of liquid crystal transmittance 814 versus time 816 for an example drive sequence over an operating period 818 that includes a pre-emphasis period 802, a steady-state repeat period 806, and a relaxation period 810. For reasons discussed above, in some examples, pre-emphasis may be desirable at the beginning of a frame time or sub-frame time for a pixel driven by the drive sequence. In some examples, a pre-emphasis period may be included in the drive sequence and encoded as a pre-emphasis period duration (also referred to herein as a binary overdrive duration value). In this example, the pre-emphasis period is shown to have a duration of 0.6 ms or less in the context of a field sequential color sub-frame rate (CSFR, i.e., rate of alternating color illumination periods) of 360 Hz and an image frame time of 2.77 ms, although in other examples, the pre-emphasis period may have a longer or shorter duration. Similarly, the duration of steady state 808 is shown as 1.17 ms and the duration of relaxation period 810 is shown as less than 1 ms, although these times may also vary in different examples.

[0065] During the pre-emphasis period 802, when 100% drive voltage is applied, the liquid crystal transmittance 814 increases according to a linear ramp 804. During the repeat period 806, the steady state 808 grayscale value is maintained according to the method 300 described above. During the relaxation period 810, the liquid crystal exhibits liquid crystal relaxation 812 during the period of 100% relaxation voltage in preparation for the next frame or sub-frame.

[0066] FIG. 8B is similar to FIG. 8A , but shows superimposed traces of liquid crystal transmittance 814 versus time 816 for low-code (e.g., low grayscale value) and high-code (e.g., high grayscale value) drive sequences. The high-code liquid crystal transmittance waveform 820 begins with a high-code pre-emphasis linear ramp 824 during a high-code pre-emphasis period 828 that is longer than the low-code pre-emphasis period 830 of the low-code liquid crystal transmittance waveform 822. During the low-code pre-emphasis period 830, the liquid crystal transmittance values ​​are raised to the steady-state low-code grayscale values ​​by a low-code pre-emphasis linear ramp 826. However, without the pre-emphasis period, the pre-emphasis-free ramp 832 to the low-code grayscale values ​​is actually longer than the high-code pre-emphasis period 828. Therefore, in some instances, pre-emphasis may be necessary to avoid the possibility of the low-code grayscale values ​​taking longer to equilibrate than the high-code grayscale values, thereby violating the timing requirements of an image frame or color sub-frame.

[0067] 9 shows a simplified block diagram of a system 900 illustrating how the example drive sequences described herein are generated and used to drive pixels of a display. System 900 includes a drive sequence generator 902 for generating drive sequences according to method 300, a pixel driver 904 configured to drive pixels of a pulse-width modulated liquid crystal display with the drive sequences, and a pixel circuit 1000, which is described in further detail below with reference to FIG.

[0068] 10 shows a pixel circuit 1000. In some examples, the pixel circuit 1000 is a component of a pixel array of a liquid crystal display. The pixel circuit 1000 includes memory for buffering bits of a DATA bus carrying an encoding of a drive sequence (e.g., encoded as described above with reference to the bit mapping of FIG. 4) and logic for driving pixel voltages in accordance with the decoded drive sequence.

[0069] As shown, pixel circuit 1000 includes a pixel electrode 1036 having a mirror element that reflects incident light and drives a time-varying voltage across a liquid crystal element between pixel electrode 1036 and a common electrode 1038 on the display's cover glass. A level shifter circuit 1044 converts the internal logic voltage to a higher voltage suitable for driving the liquid crystal element and, in some examples, may include an XOR logic function to invert the sense of pixel electrode 1036 when inverting the sense of the common electrode 1038 voltage controlled by FLIP signal 1032. A flip-flop 1024 stores and holds the voltage value of pixel electrode 1036 for one cycle of GSET signal 1030. Flip-flop 1024 can also be reset by RESET signal 1034. An OD-ON latch 1026 stores the on / off state 1042 of the overdrive function. A first multiplexer 1028 is controlled by the output of the OD-ON latch 1026 to select either the overdrive count (ODC) signal carried on the ODC bus 1002 or the global (G) signal carried on the global counter (G) bus 1004 as the first operand for the comparator function 1022. A second multiplexer 1020 is controlled by the SEL signal 1006 to select the second operand for the comparator function 1022. A series of storage latches shown as the overdrive latch 1012, main segment latch 1014, L remainder latch 1016, and L2 remainder latch 1018 cache the encoded binary values ​​representing the drive sequence, which are then propagated to drive the pixel electrodes 1036. The bit lengths and bit positions shown in Figure 10 correspond to an example implementation of a 10-bit encoding of the drive sequence described above. In the illustrated example, the value displayed on the first multiplexer 1028 indicates which latch's value is propagated as the output of the first multiplexer 1028. If the on / off state 1042 (denoted as "overdrive enable" signal ODEn) is set to an "on" value (e.g., ODEn=1), the value of the overdrive latch 1012 is propagated in order.Otherwise, when the pixel circuit 1000 is not in overdrive mode (i.e., not in the pre-emphasis period), the value of the SEL signal 1006 determines the output of the first multiplexer 1028. When SEL=0, the value of the main segment latch 1014 is propagated, when SEL=1, the value of the L remainder latch 1016 is propagated, and when SEL=2-16, the value of each of the L2 remainder latches 1018 is propagated.

[0070] FIG. 11A is a timing diagram illustrating an example image frame time for a pixel of a color sequential display. The frame time includes three color subframes: a red subframe 1102, a blue subframe 1104, and a green subframe 1106. Each color subframe 1102, 1104, and 1106 is divided into a number of sequential periods. Specifically, the subframes are divided into a load period 1108 during which grayscale values ​​are received and processed by the pixel circuit 1000, a pre-emphasis period 1110 (denoted as the "OD period," or overdrive period), a steady-state illumination period 1112 (e.g., a red, blue, or green illumination period), and a relaxation period 1114. In some examples, the pre-emphasis period 1110, steady-state illumination period 1112, and relaxation period 1114 may be as described above for the pre-emphasis period 802, repeat period 806 (corresponding to the steady-state illumination period 1112), and relaxation period 810 of FIG. 8A.

[0071] Figure 11B shows a timing diagram of an example overdrive count (ODC) bus 1002 signal 1116 alongside a G / SEL waveform 1142 formed based on the global counter (G) bus 1004 signal and the SEL signal 1006 of the pixel circuit 1000 of Figure 10 during a pre-emphasis period 1110. An example G / SEL waveform 1142 is shown and described below with reference to Figure 11D.

[0072] During the pre-emphasis period 1110, operation of the pixel circuit 1000 proceeds as follows: data to be written to the storage latches 1012, 1014, 1016, and 1018 is provided on the DATA bus 1010, and the ROW signal 1008 is strobed to write the value of the DATA bus 1010 into the storage latches 1012, 1014, 1016, and 1018. The RESET signal 1034 is pulsed to set the voltage value of the pixel electrode 1036 high, and the OD-ON latch 1026 is also set to place the pixel circuit 1000 into overdrive mode. The GSET signal 1030 begins to toggle, acting as a clock signal for the flip-flop 1024. During the subsequent pre-emphasis period, the ODC bus signal 1116 is compared to the value of the overdrive latch 1012, and if the values ​​are equal, the comparator function 1022 registers a match and the time is recorded in the flip-flop 1024. When the output of flip-flop 1024 changes, OD-ON latch 1026 is reset and first multiplexer 1028 thereafter selects G bus 1004 as the first operand for comparator function 1022. This marks the end of the pre-emphasis period and the beginning of the first repeat period to maintain a steady-state grayscale value.

[0073] Thus, the ODC bus signal 1116 is considered a timer signal for the overdrive state and is compared to the value of each overdrive latch 1012 to determine the end time of the pre-emphasis period. In the illustrated example, the ODC bus signal 1116 encodes the duration of the pre-emphasis period from 0 to 63 group periods, with each G / SEL waveform period (e.g., 1118) corresponding to one repeat period. Thus, the 64 group periods (0-63) spanned by the pre-emphasis period correspond to the first repeat period 1118 through the fourth repeat period 1120. However, it will be understood that the range of pre-emphasis period durations encoded in the OD bits stored in the overdrive latch 1012 can be configured to cover any suitable range of durations based on factors such as the characteristics of the liquid crystal element in various examples.

[0074] FIG. 11C shows a timing diagram of an example of the ROW and DATA signals controlling a column of pixels during a steady-state illumination period 1112 implemented using the pixel circuit 1000 of FIG.

[0075] As noted above, before or at the start of the pre-emphasis period (e.g., during the load period 1108), data to be written to the storage latches 1012, 1014, 1016, 1018 is provided on the DATA bus 1010, and the ROW signal 1008 is strobed, causing the value of the DATA bus 1010 to be written into the storage latches 1012, 1014, 1016, 1018. Thus, as shown in Figure 11C, the value 1128 of the DATA bus signal 1134 during the first pulse 1122 of the ROW signal encodes the value of the storage latches to represent row 0, the value 1130 of the DATA bus signal 1134 during the second pulse 1124 of the ROW signal encodes the value of the storage latches to represent row 1, and so on, and the value 1132 of the DATA bus signal 1134 during the Rth pulse 1126 of the ROW signal (number of rows displayed in a frame = R + 1) encodes the value of the storage latches to represent row R.

[0076] FIG. 11D shows a timing diagram of example G and SEL signals for the pixel circuit 1000 of FIG. 10 during an example repeat period.

[0077] During multiple repeat periods spanning steady-state illumination period 1112, different iterations of the repeat period are achieved according to method 300 described above. During each main segment 1138 pulse of the modulation interval, main segment latch 1014 is selected as the first operand of comparator function 1022, and global signal 1136 carried by G bus 1004 is selected as the second operand. The value of global signal 1136 is periodically updated, and GSET signal 1030 is pulsed, clocking the output of comparator function 1022. When comparator function 1022 determines that the values ​​on G bus 1004 and storage latches 1012, 1014, 1016, and 1018 match, the output state of comparator function 1022 changes, thereby defining the width of the pulse of the modulation interval. During each remainder unit duration 1140, the SEL signal 1006 determines which latch or latches to use as operands (e.g., depending on the value shown in the first multiplexer 1028 in FIG. 10). The pixel circuit 1000 then continues to operate in a similar manner, comparing either two bits or one bit from the G bus 1004 with the contents of the latches to generate a pulse (or no pulse) every unit duration, according to method 300 described above.

[0078] (Conclusion)

[0079] As noted above, examples described herein may address one or more technical challenges associated with pulse-width-modulated displays. Some examples described herein may address the technical challenge of reducing phase ripple in an image generated by each pixel of a pulse-width-modulated display (such as a pulse-width-modulated liquid crystal display) by converting grayscale values ​​into a large number of relatively short pulses and reducing the variation between pulse widths, while also addressing the technical challenge of encoding and decoding the large number of short pulses according to a simple 10-bit encoding and decoding scheme. This may improve the functionality of displays such as LCDs, as well as the functionality of computers and other digital logic that drive the displays, by enabling simple, uncomplicated encoding and decoding of drive sequences for each pixel while reducing phase ripple in the image generated by the display.

[0080] Additionally, some examples may address the technical challenge of getting a pixel's liquid crystal element to reach a steady-state phase value as quickly as possible at the beginning of a frame or sub-frame by providing a pre-emphasis period at the beginning of a drive sequence. In some examples herein, the pre-emphasis period may be encoded in a binary format that can be efficiently decoded by the pixel circuitry or other logic used to drive the voltage of the pixel's liquid crystal element.

[0081] Thus, in accordance with the examples described herein, a method and system for controlling a pulse width modulated liquid crystal display may be provided.

[0082] In a first aspect, a method for controlling a pulse-width-modulated liquid crystal display is provided. The method includes determining a desired number N of unit duration pulses over a repetition period, where the repetition period consists of a first number A of group periods, each of which consists of a second number B of modulation sections, each of which includes a third number (C-1) of unit durations, with each modulation section except for the last modulation section of the last group period being followed by one additional unit duration. The method further includes resulting in the repetition period spanning (A x B x C)-1 unit durations. The method further includes determining a number D of baseline pulses in the group period equal to the integer quotient of N divided by A. The method further includes determining a number H of baseline pulses in the modulation section equal to the integer quotient of D divided by B. The method further includes determining a main segment modulation section pattern consisting of H unit duration pulses in the first H unit durations of each modulation section. The method further includes determining a repetition period remainder L2 equal to the integer remainder obtained by Euclidean division of N by A. The method further includes determining a group period remainder L equal to the integer remainder obtained by Euclidean division of D by B. The method further includes determining a baseline group period pattern, where the baseline group period pattern consists of a main segment modulation period pattern applied to each modulation period of the group period and L additional unit duration pulses assigned to unit durations following the first H unit durations in each of L modulation periods selected from the group period. The method further includes determining a repetition sequence for the repetition period, where the repetition sequence consists of the baseline group period pattern repeated for every group period of the repetition period and L2 additional unit duration pulses assigned to unit durations following the first H unit durations in the last modulation period of each of L2 group periods selected from the repetition period.The method further includes determining a desired number N of unit duration pulses over a repetition period, wherein the repetition period comprises determining a baseline group period pattern, wherein the baseline group period pattern comprises generating a drive sequence for controlling a pulse width modulated liquid crystal display, wherein the repetition sequence is repeated one or more times.

[0083] In some examples, in combination with the first aspect, the method may include the drive sequence further having a pre-emphasis period of continuous drive before the repeated sequence that is repeated one or more times.

[0084] In some examples, the method may include, in combination with the first aspect and optionally in combination with one or more of the above examples, the unit duration is a least significant bit (LSB) duration.

[0085] In some examples, the method may, in combination with the first aspect and selectively combining one or more of the above examples, determine the desired number N of unit duration pulses over the repetition period including receiving a grayscale value between a minimum grayscale value and a maximum grayscale value, and converting the grayscale value to the desired number N, where the value N=0 corresponds to the minimum grayscale value and the value N=(A×B×C)−1 corresponds to the maximum grayscale value.

[0086] In some examples, the method may include, in combination with the first aspect and selectively combining one or more of the above examples, A is 16, B is 8, C is 8, and N is encoded as a 10-bit value. Other technical features will be readily apparent to those skilled in the art from the following figures, descriptions, and claims.

[0087] In combination with the first aspect and optionally in combination with one or more of the above examples, the method may include the pre-emphasis period having a duration determined at least in part based on a temperature of the pulse width modulation liquid crystal display.

[0088] In some examples, the method may include, in combination with the first aspect and selectively combining one or more of the above examples, the L modulation sections selected from the 8 consecutive modulation sections of the group period are the first modulation section when L is 1, the first and fifth modulation sections when L is 2, the first, fourth, and seventh modulation sections when L is 3, the first, third, fifth, and seventh modulation sections when L is 4, the first, second, fourth, fifth, and seventh modulation sections when L is 5, the first, second, third, fifth, sixth, and seventh modulation sections when L is 6, and the first, second, third, fourth, fifth, sixth, and seventh modulation sections when L is 7.

[0089] In some examples, the method may be combined with the first aspect and optionally combine one or more of the above examples, such that the L2 group periods selected from the 16 consecutive group periods of the repeating period are the first group period when L2 is 1, the first and ninth group periods when L2 is 2, the first, sixth, and ninth group periods when L2 is 3, the first, fourth, eighth, and twelfth group periods when L2 is 4, and the first, fourth, eighth, and twelfth group periods when L2 is 5. When L2 is 6, the periods are the 1st, 4th, 8th, 11th, and 14th groups; when L2 is 7, the periods are the 1st, 3rd, 5th, 8th, 10th, 12th, and 14th groups; when L2 is 8, the periods are the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, and 15th groups; when L2 is 9, the periods are the 1st, 3rd, 4th, 6th, 8th, 10th, 12th, 13th, and When L2 is 10, the periods are the 1st, 3rd, 4th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups. When L2 is 11, the periods are the 1st, 2nd, 4th, 5th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups. When L2 is 12, the periods are the 1st, 2nd, 3rd, 5th, 6th, 7th, 9th, 10th, 11th, 12th, 14th, and 15th groups. When L2 is 13, the periods are the 1st, 2nd, 3rd, 5th, 6th, 7th, 9th, 10th, 11th, 12th, 14th, and 15th groups. , 3rd, 4th, 6th, 7th, 8th, 9th, 10th, 12th, 13th, 14th, and 15th group periods, and when L2 is 14, the first, second, third, fourth, fifth, sixth, seventh, 9th, 10th, 11th, 12th, 13th, 14th, and 15th group periods, and when L2 is 15, the first, second, third, fourth, fifth, sixth, seventh, 8th, 9th, 10th, 11th, 12th, 13th, 14th, and 15th group periods.

[0090] In some examples, in combination with the first aspect and selectively combining one or more of the above examples, the method may further include driving pixels of a pulse width modulated liquid crystal display with a drive sequence, wherein the pixels have one or more latches operable to store a binary value of the drive sequence, and wherein the drive sequence may include encoding the pre-emphasis period as a binary overdrive duration value. The method may include the pixel having a pixel electrode with a mirror element, the mirror element reflecting incident light and driving a time-varying voltage across the liquid crystal element between the pixel electrode and a common electrode. The method may include the pixel having a level shifter circuit configured to convert an internal logic voltage to a higher voltage suitable for driving the liquid crystal element. The method may include the pixel having logic receiving one or more timer signals and, based on the one or more timer signals, providing an overdrive signal to the level shifter circuit during a pre-emphasis period determined based on a comparison of the one or more timer signals to a binary overdrive duration value, providing a drive signal to the level shifter circuit during each main segment modulation interval pattern of the drive sequence, providing a drive signal to the level shifter circuit during each of L additional unit duration pulses of the drive sequence, and providing a drive signal to the level shifter circuit during each of L2 additional unit duration pulses of the drive sequence.

[0091] In some examples, the method may include, in combination with the first aspect and selectively combining one or more of the above examples, the level shifter circuit comprises an XOR logic function, the XOR logic function configured to invert the sense of the pixel electrode when inverting the sense of the voltage of the common electrode controlled by a FLIP signal.

[0092] In a second aspect, a system for controlling a pulse-width-modulated liquid crystal display is provided. The system includes a drive sequence generator configured to perform operations including receiving normalized grayscale data representing a desired number N of unit duration pulses over a repetition period, where the repetition period consists of a first number A of group periods, each of which consists of a second number B of modulation sections, each of which includes a third number (C-1) of unit durations, with each modulation section except for the last modulation section of the last group period being followed by one additional unit duration. The system further includes, as a result, the repetition period spans (A x B x C)-1 unit durations. The system further includes determining a baseline pulse number D for the group period equal to the integer quotient of N divided by A. The system further includes determining a baseline pulse number H for the modulation section equal to the integer quotient of D divided by B. The system further includes determining a main segment modulation interval pattern consisting of H unit duration pulses in the first H unit durations of each modulation interval. The system further includes determining a repetition interval remainder L2 equal to the integer remainder obtained by Euclidean division of N by A. The system further includes determining a group interval remainder L equal to the integer remainder obtained by Euclidean division of D by B. The system further includes determining a baseline group interval pattern, wherein the baseline group interval pattern consists of the main segment modulation interval pattern applied to each modulation interval of the group interval and L additional unit duration pulses assigned to unit durations following the first H unit durations in each of L modulation intervals selected from the group interval. The system further includes determining a repetition sequence for the repetition period, wherein the repetition sequence consists of the baseline group interval pattern repeated for each group interval of the repetition period and L additional unit duration pulses assigned to unit durations following the first H unit durations in the last modulation interval of each of L2 group intervals selected from the repetition period.The system further includes receiving normalized grayscale data representing a desired number N of unit duration pulses over a repetition period, where the repetition period comprises determining a baseline group period pattern, where the baseline group period pattern comprises generating a drive sequence for controlling a pulse width modulated liquid crystal display, where the repetition sequence is repeated one or more times.

[0093] In some examples, in combination with the second aspect, the system may include the pre-emphasis driver further having a pre-emphasis period of continuous driving before the repeating sequence that is repeated one or more times.

[0094] In some examples, the system may include, in combination with the second aspect and optionally in combination with one or more of the above examples, the unit duration is a least significant bit (LSB) duration.

[0095] In some examples, in combination with the second aspect and selectively combining one or more of the above examples, the system may further include a grayscale normalization unit, wherein the grayscale normalization unit is configured to receive a grayscale value between a minimum grayscale value and a maximum grayscale value, and convert the grayscale value to a desired number N, where the value N=0 corresponds to the minimum grayscale value, and the value N=(A×B×C)−1 corresponds to the maximum grayscale value.

[0096] In some examples, the system may include, in combination with the second aspect and optionally combining one or more of the above examples, A is 16, B is 8, C is 8, and N is encoded as a 10-bit value.

[0097] In some examples, the system may further include a pixel driver for driving pixels of a pulse-width-modulated liquid crystal display with a drive sequence, in combination with the second aspect and selectively combining one or more of the above examples. The system may include a pixel having one or more latches operable to store a binary value of the drive sequence, where the drive sequence includes encoding a pre-emphasis period as a binary overdrive duration value. The system may include a pixel having a pixel electrode with a mirror element, the mirror element reflecting incident light and driving a time-varying voltage across the liquid crystal element between the pixel electrode and a common electrode. The system may include a pixel having a level shifter circuit configured to convert an internal logic voltage to a higher voltage suitable for driving the liquid crystal element. The system may include a pixel having logic that receives one or more timer signals and, based on the one or more timer signals, provides an overdrive signal to a level shifter circuit during a pre-emphasis period determined based on a comparison of the one or more timer signals with a binary overdrive duration value, provides a drive signal to the level shifter circuit during each main segment modulation interval pattern of the drive sequence, provides a drive signal to the level shifter circuit during each of L additional unit duration pulses of the drive sequence, and provides a drive signal to the level shifter circuit during each of L additional unit duration pulses of the drive sequence. Other technical features will be readily apparent to those skilled in the art from the following figures, description, and claims.

[0098] In some examples, in combination with the second aspect and optionally combining one or more of the above examples, the system may include the pre-emphasis period having a duration determined at least in part based on a temperature of the pulse width modulated liquid crystal display.

[0099] In some examples, the system may include, in combination with the second aspect and selectively combining one or more of the above examples, that the L modulation sections selected from the 8 consecutive modulation sections of the group period are the first modulation section when L is 1, the first and fifth modulation sections when L is 2, the first, fourth, and seventh modulation sections when L is 3, the first, third, fifth, and seventh modulation sections when L is 4, the first, second, fourth, fifth, and seventh modulation sections when L is 5, the first, second, third, fifth, sixth, and seventh modulation sections when L is 6, and the first, second, third, fourth, fifth, sixth, and seventh modulation sections when L is 7.

[0100] In some examples, the system may be configured in combination with the second aspect and selectively combining one or more of the above examples, such that the L2 group periods selected from the 16 consecutive group periods of the repeating period are the first group period when L2 is 1, the first and ninth group periods when L2 is 2, the first, sixth, and ninth group periods when L2 is 3, the first, fourth, eighth, and twelfth group periods when L2 is 4, and the L2 When L2 is 5, the periods are the 1st, 4th, 8th, 11th, and 14th groups; when L2 is 6, the periods are the 1st, 4th, 7th, 9th, 12th, and 15th groups; when L2 is 7, the periods are the 1st, 3rd, 5th, 8th, 10th, 12th, and 14th groups; when L2 is 8, the periods are the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, and 15th groups; when L2 is 9, the periods are the 1st, 3rd, 4th, 6th, 8th, 10th, 12th, 13th, and When L2 is 10, the periods are the 1st, 3rd, 4th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups; when L2 is 11, the periods are the 1st, 2nd, 4th, 5th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups; when L2 is 12, the periods are the 1st, 2nd, 3rd, 5th, 6th, 7th, 9th, 10th, 11th, 12th, 14th, and 15th groups; when L2 is 13, the periods are the 1st, 2nd, 3rd, 5th, 6th, 7th, 9th, 10th, 11th, 12th, 14th, and 15th groups; When L2 is 15, the group periods may be the 1st, 2nd, 3rd, 4th, 6th, 7th, 8th, 9th, 10th, 12th, 13th, 14th, and 15th group periods, and when L2 is 14, the group periods may be the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 9th, 10th, 11th, 12th, 13th, 14th, and 15th group periods.

[0101] In some examples, the system may include, in combination with the second aspect and selectively combining one or more of the above examples, the level shifter circuit comprises an XOR logic function, and the XOR logic function is configured to invert the sense of the pixel electrode when inverting the sense of the voltage of the common electrode controlled by a FLIP signal. Other technical features will be readily apparent to those skilled in the art from the following figures, descriptions, and claims.

[0102] It will be appreciated that various aspects of the methods and systems described above can be combined in various combinations or subcombinations.

[0103] (Glossary)

[0104] "Euclidean division" or "division with remainder" refers to the process of dividing an integer dividend by an integer divisor to produce an integer quotient and a natural remainder. The remainder is smaller than the divisor, and the dividend is the divisor times the quotient plus the remainder.

[0105] A "component" refers to, for example, a device, physical entity, or logic having boundaries defined by function or subroutine calls, branch points, APIs, or other techniques that provide division or modularization of specific processing or control functions. A component may be combined with other components via interfaces to perform a machine process. A component may be a packaged functional hardware unit designed for use with other components, or a part of a program that performs specific functions, usually related functions. A component may constitute a software component (e.g., code embodied on a machine-readable medium) or a hardware component. A "hardware component" is a tangible unit capable of performing specific operations, and may be configured or arranged in a specific physical manner. In various examples, one or more computer systems (e.g., standalone computer systems, client computer systems, or server computer systems), or one or more hardware components of a computer system (e.g., a single processor or group of processors), may be configured by software (e.g., an application or application portion) as hardware components that operate to perform specific operations as described herein. Additionally, hardware components may be implemented mechanically, electronically, or any suitable combination thereof. For example, a hardware component may comprise dedicated circuitry or logic that is permanently configured to perform particular operations. A hardware component may be a dedicated processor, such as a field programmable gate array (FPGA) or application specific integrated circuit (ASIC). A hardware component may also comprise programmable logic or circuitry that is temporarily configured by software to perform particular operations. For example, a hardware component may comprise software executed by a general purpose processor or other programmable processor.Once configured by such software, a hardware component becomes a specific machine (or a particular component of a machine) uniquely tailored to perform the function for which it is configured; it is no longer a general-purpose processor. It will be understood that the decision to mechanically implement a hardware component with dedicated, permanently configured circuitry or temporarily configured circuitry (e.g., configured by software) may be made based on cost and time considerations. Thus, the phrase “hardware component” (or “hardware-implemented component”) should be understood to encompass a tangible entity, and to encompass an entity that is physically constructed, permanently configured (e.g., hardwired in hardware), or temporarily configured (e.g., programmed) to operate in a particular manner or perform particular operations described herein. Considering examples in which hardware components are temporarily configured (e.g., programmed), each hardware component may not be configured or instantiated at any instance in time. For example, if a hardware component includes a general-purpose processor that is configured by software to be a special-purpose processor, the general-purpose processor may be configured at different times as different special-purpose processors (e.g., with different hardware components). Thus, for example, software may configure one or more particular processors to implement particular hardware components at one instance and different hardware components at another instance. Hardware components may provide information to and receive information from other hardware components. Thus, the hardware components may be considered to be communicatively coupled. When multiple hardware components are simultaneously present, communication may be achieved via signal transmission between two or more hardware components (e.g., via appropriate circuits and buses).In examples where multiple hardware components are configured or instantiated at different times, communication between two or more hardware components may be achieved, for example, through the storage and retrieval of information in memory structures accessible to the multiple hardware components. For example, one hardware component may perform an operation and store the output of that operation in a communicatively coupled memory device. An additional hardware component may then access the memory device, retrieve the stored output, and process it. A hardware component may initiate communication with an input or output device or operate on a resource (e.g., a collection of information). Various operations of example methods described herein may be performed, at least in part, by one or more processors that are temporarily or permanently configured (e.g., by software) to perform the associated operations. Such processors, whether temporarily or permanently configured, may constitute processor-implemented components that operate to perform one or more operations or functions described herein. As used herein, a "processor-implemented component" refers to a hardware component implemented using one or more processors. Similarly, methods described herein may be at least in part processor-implemented using one or more specific processors, which are examples of hardware. For example, at least some of the operations included in the methods may be performed by one or more processors or processor-implemented components. Further, one or more processors may operate to support performance of the appropriate operations within a "cloud computing" environment or as a "software as a service" (SaaS). For example, at least some of the operations may be performed by a group of computers (examples of machines with processors) accessible via a network (e.g., the Internet) and one or more suitable interfaces (e.g., APIs).The performance of a particular operation may be distributed across multiple processors present within a single machine or across multiple processors located across several machines. In some examples, multiple processors or processor-implemented components may be located in a single geographic location (e.g., in a home environment, an office environment, or a server farm). In other examples, multiple processors or processor-implemented components may be distributed across several geographic locations.

[0106] "Computer-readable storage medium" refers, for example, to both machine storage media and transmission media. Thus, these terms include both storage devices / media and carrier wave / modulated data signals. The terms "machine-readable medium," "computer-readable medium," and "device-readable medium" are synonymous and may be used interchangeably in this disclosure.

[0107] "Machine storage medium" refers to, for example, one or more storage devices and media (e.g., centralized or distributed databases and associated caches and servers) that store executable instructions, routines, and data. Accordingly, the term includes, but is not limited to, solid-state memory, optical media, and magnetic media, including memory both internal and external to a processor. Specific examples of machine storage media, computer storage media, and device storage media include non-volatile memory, including, by way of example, semiconductor memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), FPGAs, and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The terms "machine storage medium," "device storage medium," and "computer storage medium" are synonymous and may be used interchangeably in this disclosure. The terms "machine storage medium," "computer storage medium," and "device storage medium" specifically exclude carrier waves, modulated data signals, and other similar media (at least some of which are encompassed by the term "signal media").

[0108] "Non-transitory computer-readable storage medium" refers, for example, to a tangible medium capable of storing, encoding, or transmitting instructions for execution by a machine.

[0109] "Signal medium" refers to an intangible medium capable of storing, encoding, or transmitting instructions for execution by a machine, for example, including digital or analog communication signals and other intangible media that facilitate the communication of software or data. The term "signal medium" is intended to include all forms of modulated data signals, carrier waves, and the like. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. The terms "transmission medium" and "signal medium" are synonymous and may be used interchangeably in this disclosure.

Claims

1. 1. A method for controlling a pulse width modulated liquid crystal display, comprising: determining a desired number N of unit duration pulses over a repetition period, where: the repeating period consists of a first number A of group periods, each of the group periods is composed of a second number B of modulation sections; each of the modulation intervals includes a third number (C-1) of unit durations, and each of the modulation intervals except for the last modulation interval of the last group period is followed by one additional unit duration; As a result, the repeating period spans (A x B x C) - 1 units of duration, determining a number of baseline pulses D for said group period, said number D being equal to the integer quotient obtained by Euclidean division of N by A; determining a number H of baseline pulses in said modulation interval, said number H being equal to the integer quotient obtained by Euclidean division of D by B; determining a main segment modulation section pattern consisting of H unit duration pulses in the first H unit durations of each modulation section; determining a repeat period remainder L2 equal to the integer remainder obtained by Euclidean division of N by A; determining a group term remainder L equal to the integer remainder obtained by Euclidean division of D by B; determining a baseline group duration pattern, where: The baseline group period pattern comprises: the main segment modulation section pattern applied to each modulation section of the group period; L additional unit duration pulses assigned to unit durations following the first H unit durations in each of the L modulation sections selected from the group period; It consists of determining a repetition sequence for said repetition period, wherein: The repeating sequence comprises: the baseline group period pattern being repeated for each group period of the repetition period; L2 additional unit duration pulses assigned to the unit durations following the first H unit durations of the last modulation section of each of the L2 group periods selected from the repetition period; It consists of generating a drive sequence for controlling the pulse width modulation liquid crystal display, the drive sequence being repeated one or more times; A method comprising:

2. 10. The method of claim 1, The driving sequence further includes a pre-emphasis period of continuous driving before the repeating sequence, which is repeated one or more times. method.

3. 3. The method of claim 2, the pre-emphasis period having a duration determined at least in part based on a temperature of the pulse width modulation liquid crystal display; method.

4. 10. The method of claim 1, the unit duration is a least significant bit (LSB) duration; method.

5. 10. The method of claim 1, Determining the desired number N of unit duration pulses over the repetition period comprises: receiving a grayscale value between a minimum grayscale value and a maximum grayscale value; converting the grayscale values ​​to the desired number N; The value N=0 corresponds to the minimum grayscale value, The value N=(A×B×C)−1 corresponds to the maximum grayscale value. method.

6. 10. The method of claim 1, A is 16, B is 8, C is 8, N is encoded as a 10-bit value, method.

7. 7. The method of claim 6, The L modulation sections selected from the eight consecutive modulation sections of the group period are When L is 1, it is the first modulation section, When L is 2, the first and fifth modulation sections are When L is 3, the first, fourth, and seventh modulation sections are When L is 4, the first, third, fifth, and seventh modulation sections are When L is 5, the modulation sections are the first, second, fourth, fifth, and seventh. When L is 6, the modulation sections are the first, second, third, fifth, sixth, and seventh. When L is 7, the modulation sections are the first, second, third, fourth, fifth, sixth, and seventh. method.

8. 8. The method of claim 7, The L2 group periods selected from the 16 consecutive group periods of the repeating period are When L2 is 1, it is the first group period; When L2 is 2, it is the first and ninth group periods; When L2 is 3, the first, sixth, and ninth group periods are included. When L2 is 4, the first, fourth, eighth, and twelfth group periods are used. When L2 is 5, the first, fourth, eighth, eleventh, and fourteenth group periods are included. When L2 is 6, the first, fourth, seventh, ninth, twelfth, and fifteenth group periods are included; When L2 is 7, the first, third, fifth, eighth, tenth, twelfth, and fourteenth group periods are included. When L2 is 8, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth group periods are included. When L2 is 9, the periods are the 1st, 3rd, 4th, 6th, 8th, 10th, 12th, 13th, and 15th groups; When L2 is 10, the periods are the 1st, 3rd, 4th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups. When L2 is 11, the periods are the first, second, fourth, fifth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, and fifteenth groups; When L2 is 12, the periods are the first, second, third, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, fourteenth, and fifteenth groups; When L2 is 13, the periods are the first, second, third, fourth, sixth, seventh, eighth, ninth, tenth, twelfth, thirteenth, fourteenth, and fifteenth groups; When L2 is 14, the periods are the first, second, third, fourth, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth groups; When L2 is 15, the periods are the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth groups. method.

9. 3. The method of claim 2, further comprising driving pixels of the pulse width modulation liquid crystal display with the driving sequence; The pixel is one or more latches operable to store binary values ​​of the drive sequence, wherein the drive sequence encodes the pre-emphasis period as a binary overdrive duration value; a pixel electrode having a mirror element, where the mirror element reflects incident light and drives a time varying voltage across a liquid crystal element between the pixel electrode and a common electrode; a level shifter circuit configured to convert an internal logic voltage to a higher voltage suitable for driving the liquid crystal element; Logic and It has The logic is: receiving one or more timer signals; and based on the one or more timer signals, providing an overdrive signal to the level shifter circuit for the pre-emphasis period determined based on a comparison of the one or more timer signals to the binary overdrive duration value; providing a driving signal to the level shifter circuit during each main segment modulation period pattern of the driving sequence; providing a drive signal to the level shifter circuit during each of the L additional unit duration pulses of the drive sequence; providing a drive signal to the level shifter circuit during each of the L2 additional unit duration pulses of the drive sequence. It is operable as method.

10. 10. The method of claim 9, the level shifter circuit has an XOR logic function; the XOR logic function is configured to invert the sense of the pixel electrode when inverting the sense of the common electrode voltage controlled by a FLIP signal; method.

11. 1. A system for controlling a pulse width modulated liquid crystal display, comprising: A drive sequence generation unit is provided, The drive sequence generation unit receiving normalized grayscale data representing a desired number N of unit duration pulses over a repetition period, wherein: the repeating period consists of a first number A of group periods, each of the group periods is composed of a second number B of modulation sections; each of the modulation intervals includes a third number (C-1) of unit durations, and each of the modulation intervals except for the last modulation interval of the last group period is followed by one additional unit duration; As a result, the repeating period spans (A x B x C) - 1 units of duration, determining a number of baseline pulses D for said group period, said number D being equal to the integer quotient obtained by Euclidean division of N by A; determining a number H of baseline pulses in said modulation interval, said number H being equal to the integer quotient obtained by Euclidean division of D by B; determining a main segment modulation section pattern consisting of H unit duration pulses in the first H unit durations of each modulation section; determining a repeat period remainder L2 equal to the integer remainder obtained by Euclidean division of N by A; determining a group term remainder L equal to the integer remainder obtained by Euclidean division of D by B; determining a baseline group duration pattern, where: The baseline group period pattern comprises: the main segment modulation section pattern applied to each modulation section of the group period; L additional unit duration pulses assigned to unit durations following the first H unit durations in each of the L modulation sections selected from the group period; It consists of determining a repetition sequence for said repetition period, wherein: The repeating sequence comprises: the baseline group period pattern being repeated for each group period of the repetition period; L2 additional unit duration pulses assigned to the unit durations following the first H unit durations of the last modulation section of each of the L2 group periods selected from the repetition period; It consists of generating a drive sequence for controlling the pulse width modulation liquid crystal display, the drive sequence being repeated one or more times; The drive sequence generator is configured to perform operations including: system.

12. 12. The system of claim 11, the pre-emphasis driver further includes a continuous driving pre-emphasis period before the repeating sequence, which is repeated one or more times; system.

13. 13. The system of claim 12, the pre-emphasis period having a duration determined at least in part based on a temperature of the pulse width modulation liquid crystal display; system.

14. 12. The system of claim 11, the unit duration is a least significant bit (LSB) duration; system.

15. 12. The system of claim 11, further comprising a grayscale normalization unit; The grayscale normalization unit receiving a grayscale value between a minimum grayscale value and a maximum grayscale value; converting said grayscale values ​​to said desired number N, where the value N=0 corresponds to said minimum grayscale value and the value N=(A×B×C)−1 corresponds to said maximum grayscale value; It is configured to do these things: system.

16. 12. The system of claim 11, A is 16, B is 8, C is 8, N is encoded as a 10-bit value, system.

17. 17. The system of claim 16, The L modulation sections selected from the eight consecutive modulation sections of the group period are When L is 1, it is the first modulation section, When L is 2, the first and fifth modulation sections are When L is 3, the first, fourth, and seventh modulation sections are When L is 4, the first, third, fifth, and seventh modulation sections are When L is 5, the modulation sections are the first, second, fourth, fifth, and seventh. When L is 6, the modulation sections are the first, second, third, fifth, sixth, and seventh. When L is 7, the modulation sections are the first, second, third, fourth, fifth, sixth, and seventh. system.

18. 18. The system of claim 17, The L2 group periods selected from the 16 consecutive group periods of the repeating period are When L2 is 1, it is the first group period; When L2 is 2, it is the first and ninth group periods; When L2 is 3, the first, sixth, and ninth group periods are included. When L2 is 4, the first, fourth, eighth, and twelfth group periods are used. When L2 is 5, the first, fourth, eighth, eleventh, and fourteenth group periods are included. When L2 is 6, the first, fourth, seventh, ninth, twelfth, and fifteenth group periods are included; When L2 is 7, the first, third, fifth, eighth, tenth, twelfth, and fourteenth group periods are included. When L2 is 8, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth group periods are included. When L2 is 9, the periods are the 1st, 3rd, 4th, 6th, 8th, 10th, 12th, 13th, and 15th groups; When L2 is 10, the periods are the 1st, 3rd, 4th, 6th, 8th, 9th, 11th, 12th, 13th, and 15th groups. When L2 is 11, the periods are the first, second, fourth, fifth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, and fifteenth groups; When L2 is 12, the periods are the first, second, third, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, fourteenth, and fifteenth groups; When L2 is 13, the periods are the first, second, third, fourth, sixth, seventh, eighth, ninth, tenth, twelfth, thirteenth, fourteenth, and fifteenth groups; When L2 is 14, the periods are the first, second, third, fourth, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth groups; When L2 is 15, the periods are the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth groups. system.

19. 13. The system of claim 12, a pixel driver for driving pixels of the pulse width modulation liquid crystal display with the driving sequence; The pixel is one or more latches operable to store binary values ​​of the drive sequence, wherein the drive sequence encodes the pre-emphasis period as a binary overdrive duration value; a pixel electrode having a mirror element, where the mirror element reflects incident light and drives a time varying voltage across a liquid crystal element between the pixel electrode and a common electrode; a level shifter circuit configured to convert an internal logic voltage to a higher voltage suitable for driving the liquid crystal element; Logic and It has The logic is: receiving one or more timer signals; and based on the one or more timer signals, providing an overdrive signal to the level shifter circuit for the pre-emphasis period determined based on a comparison of the one or more timer signals to the binary overdrive duration value; providing a driving signal to the level shifter circuit during each main segment modulation period pattern of the driving sequence; providing a drive signal to the level shifter circuit during each of the L additional unit duration pulses of the drive sequence; providing a drive signal to the level shifter circuit during each of the L2 additional unit duration pulses of the drive sequence; system.

20. 20. The system of claim 19, the level shifter circuit has an XOR logic function; the XOR logic function is configured to invert the sense of the pixel electrode when inverting the sense of the common electrode voltage controlled by a FLIP signal; system.

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