Pixel circuit and display panel

Abstract

The present invention relates to a pixel circuit, its driving method, and a display panel. The pixel circuit comprises a drive module (10) that generates a drive current according to the potential difference between a control terminal and a first terminal, a first storage module (20) whose first terminal is electrically connected to the control terminal of the drive module (10) and whose second terminal is electrically connected to the first terminal of the drive module (10), and a lock control module (30) whose control terminal is configured to access a lock control signal and whose first terminal is electrically connected to the control terminal of the drive module (10), wherein the second terminal of the first storage module (20) or the second terminal of the lock control module (30) is configured to access a data signal, the lock control module (30) is configured to float the potential of the control terminal of the drive module (10) in response to the lock control signal being turned off at the time of signal lock, and the first storage module (20) is configured to store the voltage associated with the signal accessed at the time of signal lock.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on March 1, 2023, with an application number of 202310187094.7, and all the contents of the above application are incorporated herein by reference.

[0002] This application relates to the field of display technologies, for example, pixel circuits and their driving methods, and display panels.

Background Art

[0003] With the continuous development of display technologies, the application scope of display panels is becoming increasingly wide, and the requirements for display panels by people are also increasing. Pixel circuits in display panels play a very important role in driving light-emitting elements to emit light stably. However, in the driving process of pixel circuits, the data writing effect deteriorates, affecting the display effect of display panels.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This application provides a pixel circuit, its driving method, and a display panel for improving the display effect of a display panel by improving the data writing effect of the pixel circuit.

Means for Solving the Problems

[0005] In an embodiment of this application, a driving module configured to generate a driving current according to the potential difference between a control end and a first end and drive a light-emitting element to emit light; a first storage module with a first end electrically connected to the control end of the driving module and a second end electrically connected to the first end of the driving module; a lock control module configured such that a control end accesses a lock control signal and a first end is electrically connected to the control end of the driving module. The second end of the first storage module or the second end of the lock control module is configured to access data signals, The lock control module is configured to cause the potential of the control terminal of the drive module to float in response to the lock control signal being turned off at the time of signal lock, and the first storage module is configured to store the voltage associated with the signal accessed at the time of signal lock. Provides a pixel circuit.

[0006] Preferably, the first storage module includes a first capacitor whose first end is the first end of the first storage module and whose second end is the second end of the first storage module. The lock control module includes a first transistor whose gate is the control terminal of the lock control module, whose first pole is the first terminal of the lock control module, and whose second pole is the second terminal of the lock control module.

[0007] Preferably, the second end of the first storage module is configured to access the data signal, and the second end of the lock control module is configured to be connected to the first reference signal line. The aforementioned pixel circuit is A first data transmission module is configured to be turned on during the data writing phase, including the signal lock point, and to transmit the data signal to the output terminal of the first data transmission module. The system further comprises a second storage module connected between the output terminal of the first data transmission module and the second terminal of the first storage module, and configured to couple the potential transition of the output terminal of the first data transmission module to the second terminal of the first storage module, Preferably, the first data transmission module includes a second transistor configured such that its gate is connected to a first scan line, its first pole is connected to a data line, and its second pole is the output terminal of the first data transmission module. The second storage module includes a second capacitor, the first of which is electrically connected to the output terminal of the first data transmission module, and the second of which is electrically connected to the second terminal of the first storage module.

[0008] Preferably, the pixel circuit is A first reset module is electrically connected to the output terminal of the first data transmission module and is configured to turn on before the data writing stage and to reset the second storage module by employing a first reset signal; and a second reset module is electrically connected to the second terminal of the drive module and is configured to turn on in a threshold compensation stage set before the data writing stage and to store the threshold voltage of the drive module in the first storage module by discharging the first terminal of the drive module via the drive module and the second reset module. The system further includes a first light-emitting control module connected in series with the drive module and the light-emitting element, between the first power supply and the second power supply, and configured to turn on during the initialization stage, which is set before the threshold compensation stage, and the light-emitting stage, which is set after the data writing stage.

[0009] Preferably, the second end of the lock control module is configured to access the data signal, The aforementioned pixel circuit is It is configured to turn on during the data writing phase and transmit the data signal to the output terminal of the second data transmission module, and the second data transmission module includes the data writing phase which includes the signal locking phase. A third storage module is connected between the output terminal of the second data transmission module and the second terminal of the lock control module, and is configured to couple the potential transition of the output terminal of the second data transmission module to the second terminal of the lock control module. The system further comprises a reference signal transmission module configured to transmit a second reference signal to the second end of the first storage module in response to the transmission control signal being turned on, and which is turned off at the same time as the lock control module or later than the lock control module, Preferably, the lock control signal is multiplexed with the transmission control signal. Preferably, the second data transmission module includes a third transistor configured such that its gate is connected to a second scan line, its first pole is connected to a data line, and its second pole is the output terminal of the second data transmission module. The third storage module includes a third capacitor whose first end is electrically connected to the output terminal of the second data transmission module and whose second end is electrically connected to the second terminal of the lock control module. The reference signal transmission module comprises a fourth transistor whose gate is connected to a transmission control signal line, whose first pole is connected to a second reference signal line, and whose second pole is connected to the second terminal of the first storage module.

[0010] Preferably, the pixel circuit is A third reset module is electrically connected to the output terminal of the second data transmission module and is configured to reset the third storage module by employing a second reset signal before the data writing stage. A second light emission control module is connected between the first power supply and the second terminal of the drive module and is configured to turn on in the light emission stage set after the data writing stage, The system further comprises a third light-emitting control module connected between the first end of the drive module and the anode of the light-emitting element, and configured to be turned on before the data writing step and during the light-emitting step, Of these, the second end of the first storage module is electrically connected directly to the first end of the drive module, or electrically connected to the first end of the drive module via the third light emission control module. Preferably, the control terminal of the third reset module and the control terminal of the third light emission control module are connected to the same control signal line.

[0011] Preferably, the second end of the lock control module is configured to access the data signal, The aforementioned pixel circuit is The system further comprises a fourth storage module, the first of which is electrically connected to the second of the first storage module, and the second of which is connected to a first power supply. Preferably, the fourth storage module includes a fourth capacitor whose first end is the first end of the fourth storage module and whose second end is the second end of the fourth storage module.

[0012] Preferably, the pixel circuit is A fourth reset module is electrically connected to the second end of the first storage module and is configured to turn on during an initialization phase set before the threshold compensation phase and to turn off during the threshold compensation phase set before the data writing phase, which includes the signal lock point. A fifth reset module is electrically connected to the first end of the first storage module, is turned on before the data writing stage, and is configured to transmit a third reset signal to the first end of the first storage module. The system further includes a fourth light emission control module connected between the first power supply and the second end of the drive module, and configured to turn on in light emission stages set before the data writing stage and after the data writing stage.

[0013] The embodiments of the present invention further provide a display panel equipped with a pixel circuit according to any embodiment of the present invention.

[0014] In the embodiments of the present application, a data writing step including a signal locking point and a light emission step are used to drive a pixel circuit according to any embodiment of the present application, and include a data writing step including a signal locking point and a light emission step. In the data writing stage, before the signal locking time point, the lock control signal is controlled such that the lock control module is turned on, and the potential difference across both ends of the first accumulation module is made to change according to the change of the data signal. At the signal locking time point, the lock control signal undergoes a potential transition to control the lock control module to turn off, floating the potential of the control terminal of the driving module, and the first accumulation module accumulates a voltage related to the signal accessed at the signal locking time point. In the light emitting stage, the driving module generates a driving current according to the voltage accumulated by the first accumulation module at the signal locking time point to drive the light emitting element to emit light. A driving method for a pixel circuit is further provided.

Advantages of the Invention

[0015] In the pixel circuit according to the embodiment of the present application, by providing a driving module, a first accumulation module, and a lock control module, it is not necessary to pass through the driving module itself, and a new data writing form is provided in which the data writing path in the pixel circuit passes through the first accumulation module and the lock control module. Therefore, the embodiment of the present application can improve the display effect of the display panel by improving the data writing effect of the pixel circuit.

Brief Description of the Drawings

[0016] [Figure 1] It is a structural schematic diagram of a pixel circuit according to an embodiment of the present application. [Figure 2] It is a structural schematic diagram of another pixel circuit according to an embodiment of the present application. [Figure 3] It is a driving timing schematic diagram of a pixel circuit according to an embodiment of the present application. [Figure 4] It is a structural schematic diagram of another pixel circuit according to an embodiment of the present application. [Figure 5] It is a driving timing schematic diagram of another pixel circuit according to an embodiment of the present application. [Figure 6]This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 7] This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 8] This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 9] This is a schematic diagram illustrating the driving timing of another pixel circuit according to an embodiment of the present invention. [Figure 10] This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 11] This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 12] This is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. [Figure 13] This is a schematic diagram illustrating the driving timing of another pixel circuit according to an embodiment of the present invention. [Figure 14] This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention. [Modes for carrying out the invention]

[0017] The embodiment of the present application provides a pixel circuit. Figure 1 is a schematic diagram of the structure of a pixel circuit according to the embodiment of the present application. Referring to Figure 1, the pixel circuit comprises a drive module 10, a first storage module 20, and a lock control module 30.

[0018] The drive module 10 is configured to generate a drive current in accordance with the potential difference between the control terminal G and the first terminal S of the drive module 10, thereby driving the light-emitting element to emit light. The first terminal of the first storage module 20 is electrically connected to the control terminal G of the drive module 10, and the second terminal of the first storage module 20 is electrically connected to the first terminal S of the drive module 10. The control terminal of the lock control module 30 is accessed by a lock control signal Ssd, the first terminal of the lock control module 30 is electrically connected to the control terminal G of the drive module 10, and the second terminal of the first storage module 20 or the second terminal of the lock control module 30 is configured to access a data signal Vdata (Figure 1 shows an example where the second terminal of the first storage module 20 is configured to access a data signal Vdata). The lock control module 30 is configured to float the potential of the control terminal G of the drive module 10 in response to the lock control signal Ssd being turned off at the time of signal lock, and the first storage module 20 is configured to store the voltage associated with the signal Vdata accessed at the time of signal lock.

[0019] For example, the drive module 10 may include a drive transistor whose gate is the control terminal G of the drive module 10, whose source is the first terminal S of the drive module 10, and whose drain is the second terminal D of the drive module 10. The second terminal of the first storage module 20 or the second terminal of the lock control module 30 may access the data signal Vdata directly or indirectly. A connection terminal configured to access the data signal Vdata is defined as a data connection terminal. Thus, direct access to the data signal Vdata means that the data connection terminal is directly connected to the data line. Indirect access to the data signal Vdata means that the data connection terminal is connected to the data line via another module, that is, a signal containing information about the data signal Vdata is transmitted to the data connection terminal after processing of the data signal Vdata by another module.

[0020] The first storage module 20 may include storage elements such as capacitors, and the storage elements such as capacitors are configured to store the potential difference between the control terminal G and the first terminal S of the drive module 10. Taking a capacitor as an example, the storage element has the following characteristics. When both ends of the capacitor are accessed by the source signal, the potential difference across the capacitor may change in accordance with the change in either source signal. When neither end of the capacitor is accessed by the source signal and the potential is floating, the potential difference across the capacitor remains fixed regardless of whether the potential of the source signal at the other end of the capacitor changes, and is maintained at the potential difference stored in the capacitor when the source signal at the potential-floating end disappears. When one end of the capacitor is not accessed by the source signal, if the source signal at the other end of the capacitor is held at a fixed potential and does not provide a potential change, the potentials across the capacitor do not change, and the potential difference between the ends does not change. However, when the potential of the source signal at the other end of the capacitor changes, based on the coupling effect of capacitance, the potential at the end not accessed by the source signal also changes in accordance with the change in the source signal, but the potential difference across the capacitor still does not change. Based on the above characteristics, the first storage module 20 may be configured such that one end is directly or indirectly accessed by the data signal Vdata, and the other end of the first storage module 20 is directly or indirectly accessed by a fixed power supply. The signal lock time may be set to any point in time within the row time during which the data voltage required for the pixel circuit of that row is held in the data signal Vdata. The row time may be understood as the time during which the data voltage required for one row of pixel circuits is maintained in the data signal Vdata, or as the interval time during which the data signal Vdata is refreshed. At the signal lock time, the connection between the first storage module 20 and the data signal Vdata and / or the fixed power supply may be cut off so that the first storage module 20 stores the voltage associated with the data signal Vdata at the signal lock time.Of these, the voltage stored in the first storage module 20 may be the potential difference across the first storage module 20, and the voltage associated with the data signal Vdata may be understood as a voltage to which the information of the data signal Vdata is attached, for example, a voltage that is multiple-dependent with the data voltage, or a voltage that is in a functional relationship with the data voltage that can be calculated based on the data transmission process and the storage characteristics of the first storage module 20.

[0021] The lock control module 30 may include a switching element such as a transistor. The lock control module 30 may be provided at one end for connection to the fixed power supply of the first storage module 20, or at one end for receiving the data signal Vdata of the first storage module 20. The potential transition time when the lock control signal Ssd changes from the ON potential to the cutoff potential of the lock control module 30 can be the signal lock time. For example, if the lock control module 30 is provided at one end for connection to the fixed power supply of the first storage module 20, at the potential transition edge when the lock control signal Ssd changes from the ON potential to the cutoff potential, the lock control module 30 is shut off, the potential of the control terminal G of the drive module 10 becomes floating, the power supply source of the fixed power supply of the first storage module 20 is cut off, and the first storage module 20 can store and hold the potential difference at the potential transition time of the lock control signal Ssd. For example, if the lock control module 30 is provided at one end for connection to the fixed power supply of the first storage module 20, the pixel circuit may further include a data writing module, such as a transistor, which is connected to the other end of the first storage module 20 and configured to control whether or not a data signal Vdata can be transmitted to the first storage module 20. If the lock control module 30 is provided at one end for connection to the data signal Vdata of the first storage module 20, the pixel circuit may further include an auxiliary storage element, such as a capacitor, which is connected to the other end of the first storage module 20 and indirectly provides a fixed power supply signal to the other end of the first storage module 20.

[0022] As can be seen from the above analysis, in the pixel circuit according to the embodiment of the present invention, the data writing path passes through the first storage module 20 and the lock control module 30, but does not need to pass through the channel of the drive transistor. At the potential transition edge of the lock control signal Ssd, i.e., at the signal lock point, the potential stored in the first storage module 20 is locked, and data writing is completed at the same time. Therefore, in the embodiment of the present invention, there is no need to wait for the process of the gate potential of the drive transistor to change gradually, and rapid data writing can be realized. If the data writing stage includes the signal lock point, and the signal lock point is configured to be within the row time in which the data signal Vdata holds the data voltage necessary for the pixel circuit of that row, the first storage module 20 can be controlled to accurately store the voltage signal related to the data voltage of that row, thereby realizing an accurate data writing process.

[0023] Furthermore, the time duration of the data writing phase may exceed the line time, and in this embodiment, it is permissible for data voltage information from adjacent lines to enter the pixel circuit of that line. Before the potential transition of the lock control signal Ssd, the potentials of multiple nodes in the data writing path can change according to the voltage of the data signal Vdata. Compared to pixel circuits in related technologies (e.g., pixel circuits with a 7T1C structure), there is no risk of irreversible writing due to the data voltage of the next line being unable to start the drive transistor, so it is permissible for the data voltage of the previous line or multiple lines to enter the pixel circuit of that line. In addition, after the potential transition of the lock control signal Ssd, the potential difference between the control terminal G and the first terminal S of the drive module 10 is maintained in the first storage module 20, and even if another voltage transition occurs in the data signal Vdata, it does not affect the maintenance of the potential difference between the control terminal G and the first terminal S of the drive module 10. Therefore, the on-pulse width of the control signals related to the data writing process may be greater than the line time. In this way, the risk of failure of the scanning circuit that provides the above control signals can be effectively reduced, the stability of the control signals can be improved, and the effectiveness of data writing can be guaranteed.

[0024] In the subsequent light emission stage, the lock control signal Ssd is held at a cutoff potential so that the lock control module 30 remains off, the first storage module 20 is held at the voltage stored at the time of signal lock, and the drive module 10 generates a drive current according to this voltage to drive the light-emitting element to emit light at a target brightness corresponding to the data signal Vdata at the time of signal lock.

[0025] Based on the above, the pixel circuit according to the embodiment of the present application provides a new data writing method in which the data writing path in the pixel circuit passes through the first storage module 20 and the lock control module 30, without the need to go through the drive module 10 itself, by providing a drive module 10, a first storage module 20 and a lock control module 30.Therefore, by controlling the lock control module 30 to change from an ON state to an OFF state at the signal lock point, the data information at that point can be locked, and the voltage related to the signal Vdata accessed at the signal lock point can be quickly and accurately stored in the first storage module 20.In addition, since the data writing stage includes the signal lock point and the signal lock point is configured to be within the row time in which the data voltage necessary for the pixel circuit of that row is held in the data signal Vdata, an accurate data writing process can be realized. In this embodiment, there is no limit to the duration of the data writing phase, and during the data writing process, data voltage information of adjacent rows is allowed to enter the pixel circuit of that row. Therefore, the on-pulse width of the control signals related to the data writing process may be greater than the row time. In this way, the risk of failure of the scanning circuit for providing the control signals is effectively reduced, the stability of the control signals is improved, and the effectiveness of data writing can be guaranteed. Accordingly, the on-pulse width of the scanning signal related to the data writing process may be greater than the row time. In this way, the risk of failure of the scanning circuit is effectively reduced, the stability of the scanning signal is improved, and the effectiveness of data writing can be guaranteed. Therefore, the structure of the pixel circuit according to this embodiment can improve the display effect of the display panel by improving the data writing effect of the pixel circuit.

[0026] In the above embodiment, the functional modules in the pixel circuit were functionally described. Below, the possible structures of each functional module will be described, and other functional modules and control timings that the pixel circuit may have will be interpreted.

[0027] Figure 2 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present invention. Referring to Figure 2, based on the above embodiment, preferably the first storage module 20 comprises a first capacitor Cst1 whose first end is the first end of the first storage module 20 and whose second end is the second end of the first storage module 20. Since the first storage module 20 according to this embodiment consists of a single capacitor, the structure of the first storage module 20 is simplified and easier to realize.

[0028] Continuing to refer to Figure 2, based on the above embodiment, preferably the lock control module 30 includes a first transistor M1 whose gate is the control terminal of the lock control module 30, whose first pole is the first terminal of the lock control module 30, and whose second pole is the second terminal of the lock control module 30. Since the lock control module 30 according to this embodiment consists of one transistor, the structure of the lock control module 30 is simplified and easier to realize.

[0029] Continuing to refer to Figure 2, in one embodiment, preferably, the second end of the first storage module 20 is configured to indirectly access the data signal Vdata, and the second end of the lock control module 30 is connected to the first reference signal line to access the first reference signal Vref1. The first reference signal Vref1 is, for example, a DC signal with a fixed potential.

[0030] Figure 2 mainly shows the structure related to the data writing process in the pixel circuit. Exemplarily, the structure related to the data writing process includes, in addition to the first storage module 20 and the lock control module 30, a first data transmission module 610 and a second storage module 620 to assist in data writing. The second storage module 620 is connected between the output terminal of the first data transmission module 610 and the second terminal of the first storage module 20. The first data transmission module 610 is configured to turn on during the data writing phase and transmit the data signal Vdata to the output terminal of the first data transmission module 610, while the second storage module 620 is configured to couple the potential transition at the output terminal of the first data transmission module 610 to the second terminal of the first storage module 20. The data writing phase includes the signal locking phase.

[0031] The first data transmission module 610 includes a second transistor M2 whose gate is connected to a first scan line to access a first scan signal S1, whose first pole is connected to a data line to access a data signal Vdata, and whose second pole is the output terminal of the first data transmission module 610. The second storage module 620 includes a second capacitor Cst2 whose first terminal N1 is electrically connected to the output terminal of the first data transmission module 610, and whose second terminal is electrically connected to the second terminal of the first storage module 20.

[0032] The following describes the data writing process of a pixel circuit, using an example where all transistors are P-type transistors, with reference to Figure 3. For example, in the case of a data signal Vdata, the data voltage Vb is the data voltage required for the current row of the pixel circuit, the data voltage Va is the data voltage for the previous row, and the data voltage Vc is the data voltage for the next row. Assuming that the data writing stage T3 is maintained for three row times h, the data writing stage T3 of the pixel circuit includes the following:

[0033] Before the signal lock time ts, both the lock control signal Ssd and the first scan signal S1 are at a low potential. Both the first transistor M1 and the second transistor M2 are turned on, the first reference signal Vref1 is transmitted to the first terminal of the first capacitor Cst1 via the first transistor M1, and the data signal Vdata is transmitted to the first terminal N1 of the second capacitor Cst2 via the second transistor M2. When the data signal Vdata changes from the data voltage Va to the data voltage Vb, the second capacitor Cst2 couples the potential change at its first terminal N1 to the second terminal of the first capacitor Cst1, and the potential difference across the first capacitor Cst1 changes according to the potential at its second terminal.

[0034] The signal lock time ts is the time period during which the data voltage Vb is maintained for the data signal Vdata. At the signal lock time ts, the rising edge of the lock control signal Ssd appears, the lock control signal Ssd jumps to a high potential, and the first scan signal S1 is held at a low potential. The first transistor M1 turns off, and the second transistor M2 turns on. The first terminal of the first capacitor Cst1 (i.e., the gate of the drive transistor DTFT) becomes floating, the fixed signal source for the first capacitor Cst1 is disconnected, the potential difference across the first capacitor Cst1 is locked, and at this time, the information of the data signal Vdata is stored in the first capacitor Cst1.

[0035] After the signal lock time ts, the lock control signal Ssd becomes high potential, and the first scan signal S1 is held at a low potential. The first transistor M1 turns off, and the second transistor M2 turns on. The first terminal of the first capacitor Cst1 remains floating, and the data signal Vdata is transmitted to the first terminal N1 of the second capacitor Cst2 via the second transistor M2. As the data signal Vdata changes from the data voltage Vb to the data voltage Vc, the potentials of the first terminal N1 of the second capacitor Cst2, as well as the first and second terminals of the first capacitor Cst1, all change accordingly, but the potential difference across the first capacitor Cst1 remains the same as the potential difference at the signal lock time ts.

[0036] As can be seen from the above, the on-pulse of the first scan signal S1 is longer than the line time h, and the three data voltage values ​​of the data signal Vdata enter the first terminal N1 of the second capacitor Cst2 before and after the data writing stage T3, but in reality, only the voltage related to the data voltage Vb is collected and locked by the first capacitor Cst1.

[0037] The following describes a complete pixel circuit that applies the above data writing structure. Figure 4 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application. Referring to Figure 4, based on the above embodiment, the pixel circuit preferably further comprises a first reset module 410, a second reset module 420, and a first light emission control module 510. Of these, the first reset module 410 is electrically connected to the output terminal of the first data transmission module 610. The second reset module 420 is electrically connected to the second terminal D of the drive module 10. The first light emission control module 510 is connected in series with the drive module 10 and the light-emitting element L between the first power supply and the second power supply.

[0038] The first reset module 410 includes a fifth transistor M5 whose gate is accessed by a first control signal Re1, whose first pole is accessed by a first reset signal Vini1, and whose second pole is electrically connected to the output terminal of the first data transmission module 610. The second reset module 420 includes a sixth transistor M6 whose gate is accessed by a first control signal Re1, whose first pole is accessed by a first reference signal Vref1, and whose second pole is electrically connected to the second terminal D of the drive module 10. The first light emission control module 510 includes a seventh transistor M7 and an eighth transistor M8. Both the gate of the seventh transistor M7 and the gate of the eighth transistor M8 are accessed by the first light emission control signal EM1. The first pole of the seventh transistor M7 is connected to the first power supply and accesses the first power supply signal VDD. The second pole of the seventh transistor M7 is electrically connected to the first terminal S of the drive module 10. The first pole of the eighth transistor M8 is electrically connected to the second terminal D of the drive module 10. The second pole of the eighth transistor M8 is electrically connected to the anode of the light-emitting element L. The cathode of the light-emitting element L is connected to the second power supply and accesses the second power supply signal VSS. Of these, the first power supply signal VDD and the second power supply signal VSS are DC signals with different potentials; for example, the first power supply signal VDD is a high-potential signal and the second power supply signal VSS is a low-potential signal. The first reset signal Vini1 may be a DC signal with a fixed potential.

[0039] Figure 5 is a schematic diagram of the drive timing of another pixel circuit according to an embodiment of the present application. Referring to Figures 4 and 5, the drive process of the pixel circuit exemplary includes the following:

[0040] In initialization stage T1, the first light emission control signal EM1 is at a low potential, turning on the seventh transistor M7 and the eighth transistor M8; the first scan signal S1 is at a high potential, turning off the second transistor M2; and after successive low-potential pulses of the first control signal Re1 and the lock control signal Ssd arrive, the first transistor M1, the fifth transistor M5, and the sixth transistor M6 all turn on. The first reset signal Vini1 is transmitted to the first terminal N1 of the second capacitor Cst2 via the fifth transistor M5. The first reference signal Vref1 is transmitted to the gate of the drive transistor DTFT via the first transistor M1. Simultaneously, the first reference signal Vref1 is transmitted to the drain of the drive transistor DTFT via the sixth transistor M6, and then to the anode of the light-emitting element L via the eighth transistor M8, resetting the anode of the light-emitting element L. The first power supply signal VDD is transmitted to the source of the drive transistor DTFT via the seventh transistor M7. At this stage, both the first capacitor Cst1 and the second capacitor Cst2 are discharged and reset.

[0041] In threshold compensation stage T2, both the first control signal Re1 and the lock control signal Ssd are at low potentials, while both the first scan signal S1 and the first light emission control signal EM1 are at high potentials. Both the seventh transistor M7 and the eighth transistor M8 are turned off. The first reset signal Vini1 is then transmitted to the first terminal N1 of the second capacitor Cst2 via the fifth transistor M5. The first reference signal Vref1 is then transmitted to the gate of the drive transistor DTFT via the first transistor M1. The source of the drive transistor DTFT is discharged via the drive transistor DTFT and the sixth transistor M6, and as the source potential of the drive transistor DTFT gradually falls from the potential of the first power supply signal VDD to Vref1-Vth1, the drive transistor DTFT is turned off, and threshold compensation of the drive transistor DTFT is completed. At this time, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the drive transistor DTFT.

[0042] In the data writing phase T3, immediately after entering the data writing phase, the lock control signal Ssd and the first scan signal S1 are both at a low potential, while the first control signal Re1 and the first light emission control signal EM1 are both at a high potential. The fifth transistor M5 and the sixth transistor M6 are turned off, and the first transistor M1 and the second transistor M2 are kept on. The data signal Vdata is written to the first terminal N1 of the second capacitor Cst2 via the second transistor M2, causing the potential of the first terminal N1 of the second capacitor Cst2 to transition from the first reset signal Vini1 to the current data voltage Va of the data signal Vdata. The first reference signal Vref1 is then transmitted to the gate of the drive transistor DTFT via the first transistor M1. A potential transition occurs at the first terminal N1 of the second capacitor Cst2. The potential transition amount at the first terminal N1 of the second capacitor Cst2 is coupled to the second terminal of the first capacitor Cst1 via the second capacitor Cst2, resulting in a potential transition amount of (Vdata-Vini1)·(Cst2) / (Cst1+Cst2+Cgs). Therefore, the voltage difference across the first capacitor Cst1 is Vth1+(Vdata-Vini1)·(Cst2) / (Cst1+Cst2+Cgs), where Cgs is the capacitance between the gate and source of the driving transistor DTFT.

[0043] At the signal lock time ts, the lock control signal Ssd jumps to a high potential, which turns off the first transistor M1 and makes the first terminal of the first capacitor Cst1 (i.e., the gate of the drive transistor DTFT) floating. At this time, the data signal Vdata is maintained at the data voltage Vb, so the potential difference across the first capacitor Cst1 is locked to Vth1 + (Vb - Vini1) · (Cst2) / (Cst1 + Cst2 + Cgs). In other words, both the data signal Vdata information and the threshold voltage information of the drive transistor DTFT for that row are stored in the first capacitor Cst1. Exemplarily, the rising edge of the first control signal Re1 may be set to precede the rising edge of the lock control signal Ssd by one row time, i.e., 1h.

[0044] After the signal lock time ts, the lock control signal Ssd is maintained at a high potential, the first transistor M1 is kept off, and the first terminal of the first capacitor Cst1 remains floating. The data signal Vdata can still be transmitted to the first terminal N1 of the second capacitor Cst2 via the second transistor M2. When the data signal Vdata transitions to the data voltage Vc, the voltage enters the pixel circuit, but the potential transition amount coupled from the second capacitor Cst2 to the second terminal of the first capacitor Cst1 is simultaneously coupled to the first terminal of the first capacitor Cst1 by the first capacitor Cst1, so the data voltage Vc is effectively nullified, and the potential difference across the first capacitor Cst1 remains at Vth1 + (Vb - Vini1) · (Cst2) / (Cst1 + Cst2 + Cgs).

[0045] In the light emission stage T4, the first light emission control signal EM1 is at a low potential, while the first control signal Re1, the lock control signal Ssd, and the first scan signal S1 are all at high potentials. The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are all turned off, and the seventh transistor M7 and the eighth transistor M8 are all turned on, and the drive transistor DTFT generates a drive current to light up the light-emitting element L. The drive current is a function of Vgs-Vth1, where Vgs is equal to the potential difference across the first capacitor Cst1. Once the structure of the pixel circuit is determined, the first capacitor Cst1, the second capacitor Cst2, and Cgs are also determined to constant values, so the drive current is actually a function of Vdata-Vini1, meaning the magnitude of the drive current is independent of the threshold voltage Vth1 of the drive transistor DTFT, and threshold compensation is realized.

[0046] From the above, the time width of the data writing stage T3 exceeds the time h for one row. In this embodiment, in the data writing stage T3, the data signal Vdata has three possible values, and only the data voltage Vb at the signal lock time ts is valid for the pixel circuit of that row. The rising edge of the lock control signal Ssd corresponds to one sampling operation, and the data voltage Vb at this time is locked and stored in the first capacitor Cst1. The data voltage of adjacent rows can enter this circuit, but it is considered invalid. The embodiment of this application provides a pixel circuit structure of 7T2C overall. In the driving process, separating the threshold compensation process and the data writing process is advantageous for extending the threshold compensation time, improving the threshold compensation effect on the driving transistor DTFT, improving the uniformity of the display panel brightness, and simultaneously enabling high-frequency refresh and high resolution of the display panel.

[0047] For example, all transistors in a pixel circuit may be P-type transistors, manufactured using a low-temperature polysilicon (LTPS) process. This fully utilizes the advantages of LTPS transistors, such as their high mobility, strong driving capability, and mature technology, while simultaneously reducing the manufacturing cost of the display panel.

[0048] In the above embodiment, it is illustrated that all transistors in the pixel are P-type transistors, but this is not limited to the present invention. In other embodiments, some or all transistors may be replaced with N-type transistors as needed, and the potential levels of the control signals accessed by the transistors may be adjusted accordingly. For example, as shown in Figure 6, all transistors in the data writing structure may be replaced with N-type transistors.

[0049] Figure 7 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application, and Figure 7 mainly shows the structure relating to the data writing process. Referring to Figure 7, in another embodiment, preferably, the second terminal of the lock control module 30 is configured to indirectly access the data signal Vdata. Exemplarily, in the structure relating to the data writing process, in addition to the first storage module 20 and the lock control module 30, a second data transmission module 710, a third storage module 720, and a reference signal transmission module 730 are further included. The third storage module 720 is connected between the output terminal of the second data transmission module 710 and the second terminal of the lock control module 30, and the reference signal transmission module 730 is electrically connected to the second terminal of the first storage module 20. Of these, the second data transmission module 710 is turned on during the data writing stage and is configured to transmit the data signal Vdata to the output terminal of the second data transmission module 710. The third storage module 720 is configured to couple the potential transition at the output terminal of the second data transmission module 710 to the second terminal of the lock control module 30. The reference signal transmission module 730 is configured to transmit the second reference signal Vref2 to the second terminal of the first storage module 20 in response to the transmission control signal Sc being turned on. The transmission control signal Sc controls the reference signal transmission module 730 to turn off at the same time as the lock control module 30 or with a delay, thereby preventing the second terminal of the first storage module 20 from floating too early and preventing the first storage module 20 from accurately storing the voltage associated with the data signal Vdata at the signal lock time ts. The second reference signal Vref2 is, for example, a DC signal with a fixed potential.

[0050] Preferably, the lock control signal Ssd may be multiplexed with the transmission control signal Sc so that the lock control module 30 and the reference signal transmission module 730 are controlled to turn off simultaneously at the signal lock time ts. This configuration reduces the number of signal lines in the display panel, which is advantageous for simplifying the display panel structure and simplifies the wiring design of the display panel.

[0051] The second data transmission module 710 includes a third transistor M3 whose gate is connected to the second scan line to access the second scan signal S2, whose first pole is connected to the data line to access the data signal Vdata, and whose second pole is the output terminal of the second data transmission module 710. The third storage module 720 includes a third capacitor Cst3 whose first terminal is electrically connected to the output terminal of the second data transmission module 710, and whose second terminal is electrically connected to the second terminal of the lock control module 30. The reference signal transmission module 730 includes a fourth transistor M4 whose gate is connected to the transmission control signal line to access the transmission control signal Sc, whose first pole is connected to the second reference signal line to access the second reference signal Vref2, and whose second pole is connected to the second terminal of the first storage module 20.

[0052] The application of the structure will be explained below with reference to a pixel circuit that applies the data writing structure. Figure 8 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application. Referring to Figure 8, based on the above embodiment, the pixel circuit preferably further comprises a third reset module 430, a second light emission control module 520, and a third light emission control module 530. Of these, the third reset module 430 is electrically connected to the output terminal of the second data transmission module 710. The second light emission control module 520 is connected between the first power supply and the second terminal D of the drive module 10, and the third light emission control module 530 is connected between the first terminal S of the drive module 10 and the anode of the light-emitting element L.

[0053] The third reset module 430 includes a ninth transistor M9 whose gate is accessed by the second control signal Re2, whose first pole is accessed by the second reset signal Vcom, and whose second pole is electrically connected to the output terminal of the second data transmission module 710. The second light emission control module 520 includes a tenth transistor M10 whose gate is accessed by the second light emission control signal EM2, whose first pole is accessed by the first power supply signal VDD, and whose second pole is electrically connected to the drain of the drive transistor DTFT. The third light emission control module 530 includes an eleventh transistor M11 whose gate is accessed by the third light emission control signal EM3, whose first pole is electrically connected to the source of the drive transistor DTFT (the first terminal S of the drive module 10), and whose second pole is electrically connected to the anode of the light-emitting element L. The second reset signal Vcom is, for example, a DC signal with a fixed potential.

[0054] Preferably, the control terminal of the third reset module 430 and the control terminal of the third light emission control module 530 may be connected to the same control signal line, that is, the third light emission control signal EM3 is multiplexed with the second control signal Re2 to reduce the number of signal lines in the display panel.

[0055] Figure 9 is a schematic diagram of the driving timing of another pixel circuit according to an embodiment of the present invention. Referring to Figures 8 and 9, an example is given in which the lock control signal Ssd is multiplexed with the transmission control signal Sc, and the third light emission control signal EM3 is multiplexed with the second control signal Re2, and in an example in which all transistors are N-type transistors, the driving process of the pixel circuit includes the following.

[0056] In threshold compensation stage T2, both the lock control signal Ssd and the third light emission control signal EM3 are at high potential, while both the second scan signal S2 and the second light emission control signal EM2 are at low potential. The first transistor M1, the fourth transistor M4, the ninth transistor M9, and the eleventh transistor M11 are all turned on, while the third transistor M3 and the tenth transistor M10 are both turned off. The second reset signal Vcom is transmitted to the first terminal of the third capacitor Cst3 via the ninth transistor M9. The second reference signal Vref2 is transmitted to the anode of the light-emitting element L via the fourth transistor M4, and then to the source of the drive transistor DTFT via the eleventh transistor M11. The first power supply signal VDD is transmitted to the drain of the drive transistor DTFT via the tenth transistor M10, and then to the gate of the drive transistor DTFT via the first transistor M1. At the start of threshold compensation stage T2, the gate potential of the drive transistor DTFT is momentarily raised to a level slightly lower than the first power supply signal VDD, controlling the drive transistor DTFT to turn on. The drive current starts from the drain of the drive transistor DTFT and flows through the drive transistor DTFT, the 11th transistor M11, and the 4th transistor M4, and is transmitted in the direction of the second reference signal line (i.e., the signal line configured to provide the second reference signal Vref2) until the gate and drain potentials of the drive transistor DTFT fall to Vref2 + Vth1. At this time, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the drive transistor DTFT.

[0057] In data writing phase T3, immediately after entering data writing phase T3, the third light emission control signal EM3 transitions to a low potential, the second scan signal S2 transitions to a high potential, the lock control signal Ssd is maintained at a high potential, and the second light emission control signal EM2 is maintained at a low potential. The ninth transistor M9 and the eleventh transistor M11 are turned off, and the third transistor M3 is turned on. The data signal Vdata is written to the first terminal of the third capacitor Cst3 via the third transistor M3, thereby transitioning the potential of the first terminal of the third capacitor Cst3 from the second reset signal Vcom to the current data voltage Va of the data signal Vdata. The potential of the source of the drive transistor DTFT becomes floating and is held at the potential of the second reference signal Vref2. The second reference signal Vref2 is still transmitted to the second terminal of the first capacitor Cst1 via the fourth transistor M4. When a potential transition occurs at the first terminal of the third capacitor Cst3, and the potential transition amount is coupled via the third capacitor Cst3 and transmitted to the first terminal of the first capacitor Cst1 via the first transistor M1, the potential transition amount is (Vdata-Vcom)·(Cst3) / (Cst1+Cst3+Cgs), so the voltage difference across the first capacitor Cst1 becomes Vth1+(Vdata-Vcom)·(Cst3) / (Cst1+Cst3+Cgs), of which Cgs is the capacitance between the gate and source of the driving transistor DTFT.

[0058] At the signal lock time ts, the lock control signal Ssd falls to a falling edge, dropping to a low potential. This turns off the first transistor M1 and the fourth transistor M4, causing both the first and second terminals of the first capacitor Cst1 to become floating, and disconnecting both the data signal source and the fixed signal source of the first capacitor Cst1. At this time, the data signal Vdata is the data voltage Vb, and therefore the potential difference across the first capacitor Cst1 is locked to Vth1 + (Vb - Vcom) · (Cst3) / (Cst1 + Cst3 + Cgs). In other words, the information of the data signal Vdata for that row and the threshold voltage information of the driving transistor DTFT are both stored in the first capacitor Cst1.

[0059] After the signal lock time ts, the lock control signal Ssd is maintained at a low potential, the first transistor M1 and the fourth transistor M4 are kept off, and the data signal Vdata can still be transmitted to the first end of the third capacitor Cst3 via the third transistor M3, but because the first transistor M1 is off, the potential transition amount coupled by the third capacitor Cst3 cannot be transmitted to the first end of the first capacitor Cst1, and the potential difference across the first capacitor Cst1 is still maintained at Vth1 + (Vb - Vcom) · (Cst3) / (Cst1 + Cst3 + Cgs).

[0060] In the light emission stage T4, the second light emission control signal EM2 and the third light emission control signal EM3 are both at high potential, while the lock control signal Ssd and the second scan signal S2 are both at low potential. The first transistor M1, the third transistor M3, and the fourth transistor M4 are all turned off. The tenth transistor M10 and the eleventh transistor M11 are both turned on, and the drive transistor DTFT generates a drive current to light up the light-emitting element L. The ninth transistor M9 is turned on, and the second reset signal Vcom is transmitted through the ninth transistor M9 to the first terminal of the third capacitor Cst3, completing the reset of the third capacitor Cst3. Similarly, since the drive current is a function of Vgs - Vth1, and Vgs is equal to the potential difference across the first capacitor Cst1, the drive current is actually a function of (Vb - Vcom)·(Cst3) / (Cst1 + Cst3 + Cgs), and the drive current is independent of the threshold voltage Vth1 of the drive transistor DTFT.

[0061] In the above embodiment, the second terminal of the first capacitor Cst1 is indirectly connected to the source of the drive transistor DTFT, that is, connected to the source of the drive transistor DTFT via the 11th transistor M11, but this is not limited to the present invention. In other embodiments, as shown in Figure 10, the second terminal of the first capacitor Cst1 may be directly connected to the source of the drive transistor DTFT, and the drive timing corresponding to the pixel circuit shown in Figure 10 may still refer to Figure 9. The difference in the drive process is that in the threshold compensation stage T2, the discharge path of the drive transistor DTFT does not go through the 11th transistor M11 but goes directly through the 4th transistor M4, and in addition, the second reference signal Vref2 is transmitted to the anode of the light-emitting element L via the 11th transistor M11 after passing through the 4th transistor M4.

[0062] In the above embodiment, it is illustrated that all transistors in the pixel are N-type transistors, but this is not limited to the present invention. In other embodiments, some or all of the transistors may be replaced with P-type transistors as needed, and the potential levels of the control signals accessed by the transistors may be adjusted accordingly.

[0063] Figure 11 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application. Referring to Figure 11, in another embodiment, preferably, the second terminal of the lock control module 30 is accessed by a data signal Vdata. Figure 11 mainly shows the structure relating to the data writing process in the pixel circuit. Exemplarily, in the structure relating to the data writing process, in addition to the first storage module 20 and the lock control module 30, there is further a fourth storage module 80 whose first terminal is electrically connected to the second terminal of the first storage module 20 and whose second terminal is connected to a first power supply to access a first power supply signal VDD. The fourth storage module 80 includes a fourth capacitor Cst4 whose first terminal is the first terminal of the fourth storage module 80 and whose second terminal is the second terminal of the fourth storage module 80.

[0064] The application of the structure will be explained below with reference to a pixel circuit that applies the data writing structure. Figure 12 is a schematic diagram of the structure of another pixel circuit according to an embodiment of the present application. Referring to Figure 12, based on the above embodiment, the pixel circuit preferably further comprises a fourth reset module 440, a fifth reset module 450, and a fourth light emission control module 540. The fourth reset module 440 is electrically connected to the second end of the first storage module 20, the fifth reset module 450 is electrically connected to the first end of the first storage module 20, and the fourth light emission control module 540 is connected between the first power supply and the second end D of the drive module 10.

[0065] The fourth reset module 440 includes a 12th transistor M12 whose gate is accessed by the third control signal Re3, whose first pole is accessed by the third reference signal Vref3, and whose second pole is electrically connected to the second terminal of the first capacitor Cst1. The fifth reset module 450 includes a 13th transistor M13 whose gate is accessed by the fourth control signal Re4, whose first pole is accessed by the third reset signal Vini2, and whose second pole is electrically connected to the first terminal of the first capacitor Cst1. The fourth light emission control module 540 includes a 14th transistor M14 whose gate is accessed by the fourth light emission control signal EM4, whose first pole is accessed by the first power supply signal VDD, and whose second pole is electrically connected to the drain of the drive transistor DTFT. Of these, the second terminal of the first capacitor Cst1 is directly electrically connected to the source of the drive transistor DTFT and the anode of the light-emitting element L. The third reference signal Vref3 and the third reset signal Vini2 may both be DC signals with a fixed potential.

[0066] Figure 13 is a schematic diagram of the driving timing of another pixel circuit according to an embodiment of the present application. Referring to Figures 12 and 13, if we take an example where all transistors are N-type transistors, the driving process of the pixel circuit includes the following:

[0067] In initialization phase T1, the lock control signal Ssd is at a low potential, while the third control signal Re3, the fourth control signal Re4, and the fourth light emission control signal EM4 are all at a high potential. The first transistor M1 is turned off, and the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned on. The third reference signal Vref3 is transmitted via the twelfth transistor M12 to the second terminal of the first capacitor Cst1, the first terminal of the fourth capacitor Cst4, and the anode of the light-emitting element L. The third reset signal Vini2 is transmitted via the thirteenth transistor M13 to the first terminal of the first capacitor Cst1, and the first power supply signal VDD is transmitted via the fourteenth transistor M14 to the drain of the drive transistor DTFT. In initialization phase, the first capacitor Cst1, the fourth capacitor Cst4, and the anode of the light-emitting element L are all reset.

[0068] In threshold compensation stage T2, the third control signal Re3 changes to a low potential. The 12th transistor M12 turns off, and the first power supply signal VDD is subsequently transmitted to the drain of the drive transistor DTFT via the 14th transistor M14, and the third reset signal Vini2 is subsequently transmitted to the first end of the first capacitor Cst1 via the 13th transistor M13. The drive transistor DTFT turns on, and the first power supply signal VDD charges the source of the drive transistor DTFT via the 14th transistor M14 and the drive transistor DTFT, and the potential of the source of the drive transistor DTFT gradually rises until the drive transistor DTFT turns off, completing the threshold compensation of the drive transistor DTFT. At this time, the potential difference stored across the first capacitor Cst1 is the threshold voltage Vth1 of the drive transistor DTFT.

[0069] In the data writing phase T3, immediately after entering the data writing phase, the lock control signal Ssd is at a high potential, while the third control signal Re3, the fourth control signal Re4, and the fourth light emission control signal EM4 are all at low potentials. The first transistor M1 turns on, and the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 all turn off. The data signal Vdata is transmitted to the first terminal of the first capacitor Cst1 via the first transistor M1, and the potential at the first terminal of the first capacitor Cst1 changes from the third reset signal Vini2 to the data signal Vdata. The fourth capacitor Cst4 is connected to the first power supply signal VDD and controls the amount of potential transition in the first capacitor Cst1. The voltage drop across the first capacitor Cst1 is (Vdata-Vini2)·(Cst4+Coled) / (Cst4+Vgs+Cst1+Coled)+Vth1, where Cgs is the capacitance between the gate and source of the drive transistor DTFT, and Coled is the parasitic capacitance of the light-emitting element L. In this embodiment, the fourth capacitor Cst4 is primarily configured to provide a large scale factor; that is, by increasing (Cst4+Coled) / (Cst4+Vgs+Cst1+Coled), the sensitivity of data voltage writing is ensured and the range of data voltage variation is reduced.

[0070] At the signal lock time ts, the lock control signal Ssd falls to a low potential, which turns off the first transistor M1, causing the first terminal of the first capacitor Cst1 to become floating, and disconnecting the data signal source of the first capacitor Cst1. At this time, the data signal Vdata is maintained at the data voltage Vb, so the potential difference across the first capacitor Cst1 is locked to (Vb-Vini2)·(Cst4+Coled) / (Cst4+Vgs+Cst1+Coled)+Vth1. In other words, the information of the data signal Vdata for that row and the threshold voltage information of the driving transistor DTFT are both stored in the first capacitor Cst1, and the data writing process is completed.

[0071] In the light emission stage T4, the fourth light emission control signal EM4 is at a high potential, while the lock control signal Ssd, the third control signal Re3, and the fourth control signal Re4 are all at low potentials. The 14th transistor M14 turns on, and the drive transistor DTFT generates a drive current to light up the light-emitting element L. The drive current is a function of Vgs - Vth1, where Vgs is equal to the potential difference across the first capacitor Cst1. Therefore, the drive current is actually a function of Vdata - Vini2, and the magnitude of the drive current is independent of the threshold voltage Vth1 of the drive transistor DTFT.

[0072] In the above embodiment, it is illustrated that all transistors in the pixel circuit are N-type transistors, but this is not limited to the present invention. In other embodiments, some or all of the transistors may be replaced with P-type transistors as needed, and the potential levels of the control signals accessed by the transistors may be adjusted accordingly.

[0073] Based on the above, the embodiments of the present application are applicable to various pixel circuits and provide a novel data writing structure and related drive timing that can solve the problem of reduced data writing efficiency in related technologies. In the data writing process in related technologies, the data writing path must pass through the channel of the drive transistor, so at the data writing stage of the pixel circuit of that row, the data signal must be held at the data voltage required for that row. During the data writing process, the data voltage of an adjacent row is not allowed to enter the row in question, thereby avoiding situations where writing is not possible because the data voltage of the row cannot start the transistor due to the writing of the data voltage of the previous row, or situations where erroneous writing occurs because the data voltage of the next row can start the transistor again. For this reason, the on-pulse width of the scan signal must not exceed the row time. Furthermore, the data writing process requires that the gate of the transistor be charged from its initial potential to the sum of the data voltage and the drive transistor threshold voltage for a duration that is sufficient to turn it off, thereby limiting the data writing speed of the pixel circuit. On the other hand, as user demands for display panel quality and functionality continue to increase, line times are being shortened. However, when line times are short, the data writing phase ends prematurely, and the data voltage cannot be sufficiently written to the transistor gate, thus compromising the data writing effectiveness. Furthermore, due to process limitations and the influence of parasitic capacitance, the scanning circuit has difficulty generating a scanning signal with a very narrow on-pulse. When line times are short, the scanning circuit has difficulty providing a stable scanning signal, which further affects the data writing effectiveness.

[0074] The data writing structure according to the embodiment of the present invention samples the data signal using the potential transition edge of the lock control signal, resulting in a very short sampling time and extremely high speed during data writing. At the same time, it is permissible for the on-pulse width of the scanning signal to be larger than the line time, eliminating the need to provide a scanning signal with an excessively narrow pulse width even in high refresh frequency scenarios, thus simplifying the design of the pixel circuit and scanning circuit in high refresh frequency scenarios. Furthermore, the pixel circuit applying this data writing structure can achieve separation of the threshold compensation stage and the data writing stage, allowing the threshold compensation time to be extended without being limited by the line time, achieving a better compensation effect, improving display uniformity, and allowing the threshold compensation stages of pixel circuits in different rows to overlap in time, without affecting the refresh frequency of the display panel. Therefore, the pixel circuit according to the embodiment of the present invention can improve the data writing effect and threshold compensation effect of the pixel circuit, and can achieve both high resolution and high refresh frequency of the display panel.

[0075] Embodiments of the present application further provide a method for driving a pixel circuit, which can be used to drive a pixel circuit according to any embodiment of the present application and which has corresponding effects. The driving method may include a data writing stage including a signal locking stage and an illumination stage. Exemplary, the driving method includes the following:

[0076] During the data writing phase, before the signal lock point, the lock control signal controls the lock control module to turn on, causing the potential difference across the first storage module to change in accordance with the change in the data signal.

[0077] At the signal lock point, the lock control signal undergoes a potential transition to control the lock control module to turn off, causing the potential of the control terminal of the drive module to float, and the first storage module stores the voltage associated with the signal accessed at the signal lock point.

[0078] During the light emission phase, the drive module generates a drive current according to the voltage accumulated by the first storage module at the signal lock point, and drives the light-emitting element to emit light.

[0079] The pixel circuit driving method according to the embodiment of the present invention provides a new data writing method in which the data writing path in the pixel circuit passes through the first storage module and the lock control module, without the need to go through the drive module itself. Therefore, by controlling the lock control module to change from an ON state to an OFF state at the signal lock point, the data information at that point can be locked, and the voltage associated with the signal accessed at the signal lock point can be quickly and accurately stored in the first storage module. An accurate data writing process can be realized by configuring the data writing stage to include the signal lock point, and the signal lock point to be within the row time in which the data signal holds the data voltage necessary for the pixel circuit of that row. In this embodiment, there is no limit to the duration of the data writing stage, and it is permissible for data voltage information of adjacent rows to enter the pixel circuit of that row during the data writing process. Therefore, the on-pulse width of the control signals related to the data writing process may all be larger than the row time. In this way, the risk of the scanning circuit for providing the control signals failing can be effectively reduced, the stability of the control signals can be improved, and the effectiveness of data writing can be guaranteed. Therefore, the embodiment of the present invention can improve the display effect of the display panel by improving the data writing effect of the pixel circuit.

[0080] In the embodiments of the pixel circuit, driving methods were described for different pixel circuits. However, all of these driving methods can be considered as driving methods for the pixel circuit according to the embodiments of the present invention, and redundant information will not be repeated here.

[0081] Embodiments of the present application further provide a display panel comprising a pixel circuit according to any embodiment of the present application and having corresponding effects. Figure 14 is a schematic diagram of the structure of a display panel according to an embodiment of the present application. Referring to Figure 14, exemplary, a plurality of pixel circuits 100 are arranged in an array in the display area AA of the display panel. The display panel further comprises a scanning circuit 101 and a plurality of first scanning lines LS1, the scanning circuit 101 being configured to provide a lock control signal to the pixel circuit 100 via the first scanning lines LS1. In addition, the display panel further comprises a drive chip 102 and a plurality of data lines Ld, the drive chip 102 being configured to provide a data signal to the pixel circuit 100 via the data lines Ld.

Claims

1. A drive module configured to generate a drive current according to the potential difference between a control terminal and a first terminal, and to drive a light-emitting element to emit light, A first storage module having a first end electrically connected to the control end of the drive module and a second end electrically connected to the first end of the drive module, The system comprises a lock control module whose control terminal is configured to access a lock control signal and whose first terminal is electrically connected to the control terminal of the drive module, The second end of the first storage module or the second end of the lock control module is configured to access data signals, The lock control module is configured to cause the potential of the control terminal of the drive module to float in response to the lock control signal being turned off at the time of signal lock, and the first storage module is configured to store the voltage associated with the signal accessed at the time of signal lock. Pixel circuit.

2. The first storage module includes a first capacitor whose first end is the first end of the first storage module and whose second end is the second end of the first storage module. The lock control module comprises a first transistor whose gate is the control terminal of the lock control module, whose first pole is the first terminal of the lock control module, and whose second pole is the second terminal of the lock control module. The pixel circuit according to claim 1.

3. The second end of the first storage module is configured to access the data signal, and the second end of the lock control module is configured to be connected to the first reference signal line. The aforementioned pixel circuit is A first data transmission module is configured to be turned on during the data writing stage, including the signal lock time, and to transmit the data signal to the output terminal of the first data transmission module. The system further comprises a second storage module connected between the output terminal of the first data transmission module and the second terminal of the first storage module, and configured to couple the potential transition of the output terminal of the first data transmission module to the second terminal of the first storage module. The pixel circuit according to claim 1.

4. A first reset module is electrically connected to the output terminal of the first data transmission module, is turned on before the data writing stage, and is configured to reset the second storage module by employing a first reset signal, A second reset module, which is electrically connected to the second end of the drive module, turns on in a threshold compensation stage set before the data writing stage, and is configured to discharge the first end of the drive module via the drive module and the second reset module, thereby accumulating the threshold voltage of the drive module in the first storage module; The system further comprises a first light-emitting control module connected in series with the drive module and the light-emitting element between the first power supply and the second power supply, and configured to turn on during the initialization stage set before the threshold compensation stage and the light-emitting stage set after the data writing stage. The pixel circuit according to claim 3.

5. The second end of the lock control module is configured to access the data signal, The aforementioned pixel circuit is A second data transmission module is configured to be turned on during the data writing stage, including the signal lock point, and to transmit the data signal to the output terminal of the second data transmission module. A third storage module is connected between the output terminal of the second data transmission module and the second terminal of the lock control module, and is configured to couple the potential transition of the output terminal of the second data transmission module to the second terminal of the lock control module. The system further comprises a reference signal transmission module configured to transmit a second reference signal to the second end of the first storage module in response to the transmission control signal being turned on, and which is turned off at the same time as the lock control module or with a delay compared to the lock control module. The pixel circuit according to claim 1.

6. The lock control signal is multiplexed with the transmission control signal. The pixel circuit according to claim 5.

7. A third reset module is electrically connected to the output terminal of the second data transmission module and is configured to reset the third storage module by employing a second reset signal before the data writing stage. A second light emission control module is connected between the first power supply and the second end of the drive module and is configured to turn on in the light emission stage set after the data writing stage, The system further comprises a third light-emitting control module connected between the first end of the drive module and the anode of the light-emitting element, and configured to be turned on before the data writing step and during the light-emitting step, Of these, the second end of the first storage module is either directly electrically connected to the first end of the drive module, or electrically connected to the first end of the drive module via the third light emission control module. The pixel circuit according to claim 5.

8. The control terminal of the third reset module and the control terminal of the third light emission control module are connected to the same control signal line. The pixel circuit according to claim 7.

9. The second end of the lock control module is configured to access the data signal, The aforementioned pixel circuit is The system further comprises a fourth storage module, the first of which is electrically connected to the second of the first storage module, and the second of which is connected to a first power supply. The pixel circuit according to claim 1.

10. A fourth reset module is electrically connected to the second end of the first storage module and is configured to turn on during an initialization phase set before the threshold compensation phase and to turn off during the threshold compensation phase set before the data writing phase, which includes the signal lock point. A fifth reset module is electrically connected to the first end of the first storage module, is configured to turn on before the data writing stage, and transmits a third reset signal to the first end of the first storage module. The system further comprises a fourth light emission control module connected between the first power supply and the second end of the drive module, and configured to turn on in light emission stages set before the data writing stage and after the data writing stage. The pixel circuit according to claim 9.

11. The first data transmission module includes a second transistor configured such that its gate is connected to a first scan line, its first pole is connected to a data line, and its second pole is the output terminal of the first data transmission module. The second storage module includes a second capacitor whose first end is electrically connected to the output terminal of the first data transmission module and whose second end is electrically connected to the second terminal of the first storage module. The pixel circuit according to claim 3.

12. The second data transmission module comprises a third transistor configured such that its gate is connected to a second scan line, its first pole is connected to a data line, and its second pole is the output terminal of the second data transmission module. The third storage module includes a third capacitor whose first end is electrically connected to the output terminal of the second data transmission module and whose second end is electrically connected to the second terminal of the lock control module. The reference signal transmission module comprises a fourth transistor whose gate is connected to a transmission control signal line, whose first pole is connected to a second reference signal line, and whose second pole is connected to the second terminal of the first storage module. The pixel circuit according to claim 5.

13. The fourth storage module includes a fourth capacitor whose first end is the first end of the fourth storage module and whose second end is the second end of the fourth storage module. The pixel circuit according to claim 7.

14. A pixel circuit comprising the one described in any one of claims 1 to 13, Display panel.

15. Used to drive a pixel circuit according to any one of claims 1 to 13, and comprising a data writing step including a signal locking step and a light emission step, In the data writing stage, before the signal lock point, the lock control signal controls the lock control module to turn on, causing the potential difference across the first storage module to change in accordance with the change in the data signal. At the signal lock point, the lock control signal undergoes a potential transition to control the lock control module to turn off, causing the potential of the control terminal of the drive module to float, and the first storage module stores the voltage associated with the signal accessed at the signal lock point. In the light-emitting stage, the drive module generates a drive current according to the voltage accumulated by the first storage module at the signal lock point, and drives the light-emitting element to emit light. A method for driving pixel circuits.

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