Multilayer capacitors

Abstract

The present invention is directed toward multilayer capacitors, circuit boards including multilayer capacitors, and integrated circuit packages including multilayer capacitors. The multilayer capacitor includes a body portion comprising alternating dielectric layers and electrode layers. Each electrode layer includes a first electrode having a base section, a connecting section, and a central section, a first connecting edge extending from a first front edge of the base section to a first edge of the central section, and a second connecting edge extending from a second front edge of the base section to a second edge of the central section. At least one portion of the first or second connecting edge of the first electrode of the electrode layer is not perpendicular to the respective first or second edge of the central section of the first electrode.

Description

[Technical Field]

[0001] Related applications This application is based on U.S. Provisional Patent Application No. 63 / 420,726, filed on 31 October 2022, which claims priority, and the literature is incorporated herein by reference. [Background technology]

[0002] Multilayer capacitors are generally constructed to have multiple dielectric and internal electrode layers arranged in a stack. During manufacturing, the stacked dielectric and internal electrode layers are pressed and sintered to realize a substantially integrated capacitor body. Various configurations and designs have been used for the dielectric and internal electrode layers in an attempt to improve the performance of these capacitors.

[0003] However, these configurations are generally manipulated as rapid changes are occurring in the electronics industry, which requires new performance standards. In particular, various application design considerations have created the need to redefine capacitor parameters and their performance in high-speed environments, especially in terms of faster and higher-density integrated circuits. For example, higher currents, higher density circuit boards, and rising costs have all played a role in drawing attention to the need for better and more efficient capacitors. In addition, the design of various electronic components has been driven by the general industry trend toward miniaturization and increased functionality. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 7,177,137 [Patent Document 2] U.S. Patent No. 7,463,474 [Overview of the project] [Problems that the invention aims to solve]

[0005] From this perspective, there is a need to provide capacitors with improved operating characteristics. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The multilayer capacitor has a first end and a second end, the second end being spaced apart from the first end in a longitudinal direction perpendicular to the transverse direction, and the transverse and longitudinal directions are perpendicular to the Z direction, respectively. The multilayer capacitor includes a body, the body having an upper surface and a bottom surface opposite the upper surface along the Z direction. The body includes alternating dielectric layers and electrode layers, the electrode layers including a first electrode layer and a second electrode layer. Each electrode layer includes a first electrode having a base section, a connecting section and a central section, a first connecting edge of the connecting section extending from a first front edge of the base section to a first edge of the central section, and a second connecting edge of the connecting section extending from a second front edge of the base section to a second edge of the central section. Furthermore, the multilayer capacitor includes a plurality of external terminations, including a first external termination disposed on at least one of the upper or bottom surfaces, and a second external termination disposed on at least one of the upper or bottom surfaces. The first external termination is electrically connected to the first electrode layer along at least one of the first or second leading edges of the first electrode of the first electrode of the first electrode layer. The second external termination is electrically connected to the second electrode layer along at least one of the first or second leading edges of the first electrode of the second electrode layer. At least one portion of the first or second connecting edge of the first electrode of the electrode layer is not perpendicular to the respective first or second edge of the central section of the first electrode.

[0007] Other features and embodiments of the present invention are described in more detail below.

[0008] A complete and implementable disclosure of the present invention (including its best mode for those skilled in the art) is described more specifically in the remainder of the specification (including by reference to the accompanying drawings). [Brief explanation of the drawing]

[0009] [Figure 1A] This is an external perspective view of the generally top and side of one embodiment of a capacitor including two external terminations according to the present invention. [Figure 1B] This is a perspective view of the capacitor shown in Figure 1A, mounted on a mounting surface, according to the present invention. [Figure 1C] This is a side perspective view of the electrode layer of the capacitor shown in Figure 1A, according to an embodiment of the present invention. [Figure 1D] This is a side view perspective of the electrode layer of the capacitor shown in Figure 1A, according to another embodiment of the present invention. [Figure 1E] This is a perspective view of one embodiment of the arrangement of the electrode layer of the present invention. [Figure 1F] This is a side view perspective of the electrode layer of the capacitor shown in Figure 1A, according to another embodiment of the present invention. [Figure 1G] This is a side perspective view of the electrode layer of the capacitor shown in Figure 1A, according to yet another embodiment of the present invention. [Figure 2A] This is a top view of another embodiment of the electrode of the present invention. [Figure 2B] This is a side view perspective of the electrode layer of the capacitor shown in Figure 2A, according to various embodiments of the present invention. [Figure 2C] This is a side view perspective of the electrode layer of the capacitor shown in Figure 2A, according to various embodiments of the present invention. [Figure 3A] This is an external perspective view of the top and side of one embodiment of a 2x2 package capacitor according to the present invention. [Figure 3B] This is an external perspective view of the generally top and side of another embodiment of a 2x2 package capacitor according to the present invention. [Figure 3C]A perspective view of the top and side of the capacitor of FIG. 3A, including a set of alternating dielectric layers and internal electrode layers of FIG. 1F. [Figure 4A] An external perspective view generally of the top and side of one embodiment of a 2×4 package capacitor according to the present invention. [Figure 4B] A perspective view of the top and side of the capacitor of FIG. 4A, including a set of alternating dielectric layers and internal electrode layers of FIG. 2D. [Figure 5A] An external perspective view generally of the top and side of one embodiment of a 4×4 package capacitor according to the present invention. [Figure 5B] A perspective view of the top and side of the capacitor of FIG. 5A, including a set of alternating dielectric layers and internal electrode layers of FIG. 2D. [Figure 6] A side view of a printed circuit board and integrated circuit package including a packaged capacitor according to the present invention. [Figure 7] A side view of a printed circuit board and integrated circuit package including a plurality of multilayer ceramic capacitors of the prior art.

MODE FOR CARRYING OUT THE INVENTION

[0010] It should be understood by those skilled in the art that this discussion is merely an illustration of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0011] Generally speaking, the present invention is directed to multilayer capacitors. A multilayer capacitor (or simply a capacitor) includes at least one set of alternating dielectric layers and electrode layers and a plurality of external terminations within a single body portion. Further, the electrode layer can include electrodes having a particular configuration. More specifically, at least one electrode layer includes an electrode having at least one edge that is not perpendicular to an intersecting edge. That is, aspects of the present disclosure relate to controlling the shape of the electrodes in order to improve the operating characteristics of the capacitor (e.g., increasing the breakdown voltage, etc.).

[0012] As used herein, a first edge described as “not perpendicular” to a second edge generally means that the first and second edges meet or intersect in such a manner that the intersecting edges do not generally form a right or 90-degree angle. Such intersections of edges may also be referred to as non-orthogonal. Furthermore, one of the two edges may also be referred to as a non-perpendicular edge. Additionally or alternatively, an electrode having such a first edge that is not perpendicular to a second intersecting edge may be described in terms of the overall shape of the electrode, which would be understood to include a non-perpendicular intersecting edge.

[0013] Various examples of electrodes including at least one portion of an edge that is not perpendicular to the intersecting edges are described and illustrated herein. For example, an electrode may have a connecting section and a central section as defined herein, with an angle greater than 90° and less than 180° formed between the edge of the central section and the connecting edge of the connecting section. Although not intended to be limited by theory, such angles may generally provide electrodes having a Y-shaped configuration.

[0014] As another example, an electrode may include at least one curved or rounded connecting edge. A curved or rounded connecting edge may define a rounded corner. A rounded corner may provide an increased breakdown voltage by reducing electric field / charge concentration. For example, a rectangular electrode generally concentrates electric field and charge concentration at its corners, making dielectric breakdown of the dielectric more likely to occur near the corners of the dielectric. According to embodiments of the present disclosure, at least a portion of at least one edge that is not perpendicular to the intersecting edges may be curved or rounded, which may reduce electric field concentration in the dielectric material. For example, the corners of an electrode and the corners of a charged portion of a dielectric generally do not coincide, but they may still be relatively close to each other. As a result, reducing charge concentration at the corners of the electrode further reduces charge concentration in the charged portion of the dielectric. And reducing charge concentration increases the breakdown voltage compared to other similar capacitors using conventional electrodes.

[0015] Additionally, in some embodiments, the periphery of the electrode may be free from geometric discontinuities. For example, rounded corners may seamlessly blend into adjacent straight edges of the electrode without geometric discontinuity. Geometric discontinuities are generally described by referring to the order of the corresponding derivation. For example, a shape can generally be defined by a coordinate function (e.g., Cartesian or polar coordinates). A shape is geometrically continuous if there is no discontinuity in the coordinate function itself. Similarly, a shape is geometrically continuous up to the first order if there is no discontinuity in both the coordinate function and its first derivative. Electrodes having a periphery that is geometrically continuous at least up to the first order can further reduce electric field and charge concentration at corners and / or along the edges of electrodes adjacent to corners. This reduction can increase the dielectric breakdown voltage of the capacitor compared to conventional electrode designs.

[0016] Furthermore, the inventors have discovered that by utilizing such a configuration for the capacitor and the electrode layers therein, and by utilizing specific materials for the electrodes and dielectrics as described herein, multilayer capacitors can have a low equivalent series resistance, particularly over a wide frequency range. In particular, such a low equivalent series resistance can be realized and beneficial at relatively high frequencies.

[0017] In this regard, a capacitor can have an equivalent series resistance of 100 ohms or less, for example, 75 ohms or less, for example, 50 ohms or less, for example, 40 ohms or less, for example, 30 ohms or less, for example, 25 ohms or less, for example, 20 ohms or less, for example, 15 ohms or less, for example, 10 ohms or less, for example, 8 ohms or less, for example, 5 ohms or less, for example, 3 ohms or less, for example, 2 ohms or less, for example, 1 ohm or less, and so on. The equivalent series resistance can be 0.01 ohms or more, for example, 0.1 ohms or more, for example, 0.2 ohms or more, for example, 0.3 ohms or more, for example, 0.5 ohms or more, for example, 0.8 ohms or more, for example, 1 ohm or more, for example, 2 ohms or more, for example, 3 ohms or more, for example, 5 ohms or more, for example, 8 ohms or more, for example, 10 ohms or more. Such an equivalent series resistance can be realized when measured over a frequency range such as 1 GHz to 10 GHz, for example, 2 GHz to 10 GHz, for example, 3 GHz to 10 GHz, for example, 4 GHz to 9 GHz. The equivalent series resistance can be measured using common techniques known in the art and as described herein.

[0018] In some embodiments, the capacitor can exhibit the equivalent series resistance described above around a single frequency. For example, in one embodiment, the capacitor can exhibit the equivalent series resistance described above at about 2 GHz, for example, at about 3 GHz, for example, at about 4 GHz, for example, at about 5 GHz, for example, at about 6 GHz, for example, at about 7 GHz, for example, at about 8 GHz, for example, at about 9 GHz, for example, at about 10 GHz. In one embodiment, the capacitor can exhibit the equivalent series resistance described above at more than one of the frequencies described above.

[0019] In addition to exhibiting relatively low equivalent series resistance due to the specific configuration of the electrodes and capacitor, as well as selective control over the materials for the electrodes and dielectric, the resulting capacitor can also exhibit low equivalent series inductance. In certain applications, it is desirable to maintain the lowest possible inductance (i.e., parasitic inductance). Using the capacitor of the present invention allows for a significant reduction in inductance. In particular, minimizing the distance or path for ground connection can help reduce inductance. Generally, using the capacitor of the present invention as illustrated in Figure 6 can allow for at least an order of magnitude reduction in inductance compared to using multiple individual multilayer ceramic capacitors as illustrated in Figure 7. For example, using the capacitor of the present invention can result in inductances on the order of picohrenes or even femtohenries compared to prior art capacitors exhibiting larger inductances. Generally, the inductance can be less than 1 nanohenry. In particular, the inductance can be 900 picohrenies or less, for example, 750 picohrenies or less, for example, 500 picohrenies or less, for example, 400 picohrenies or less, for example, 250 picohrenies or less, for example, 100 picohrenies or less, for example, 50 picohrenies or less, for example, 25 picohrenies or less, for example, 15 picohrenies or less, for example, 10 picohrenies or less. The inductance can be 1 femtohenry or more, for example, 25 femtohenries or more, for example, 50 femtohenries or more, for example, 100 femtohenries or more, for example, 250 femtohenries or more, for example, 500 femtohenries or more, for example, 750 femtohenries or more. Minimizing such inductance can contribute to good performance (especially good decoupling performance), especially under high-speed transient conditions.Furthermore, a low equivalent series inductance value can also be characterized by a low impedance value, which reflects parasitic inductance.

[0020] The electrode layers in the set can be stacked laterally, so that they are perpendicular to the mounting surface. In this respect, each electrode layer extends in the longitudinal and Z directions, both of which are perpendicular to the transverse direction. By arranging the dielectric and electrode layers in a stacked or laminated configuration, the capacitor can be called a multilayer capacitor, and in particular, when the dielectric layer includes ceramic, it can be called a multilayer ceramic capacitor.

[0021] Furthermore, in some embodiments, multiple sets of alternating dielectric and electrode layers can be contained within a single capacitor body. For example, a multilayer capacitor may include a first set of alternating dielectric and electrode layers, as well as a second set of alternating dielectric and electrode layers. The capacitor may also include external terminations electrically connected to the electrode layers, which are formed on the upper surface of the capacitor and on the bottom surface of the capacitor opposite the upper surface. In other embodiments, the capacitor may include at least three sets, for example, at least four sets, of alternating dielectric and electrode layers. However, it should be understood that the present invention may include any number of sets of alternating dielectric and electrode layers and is not necessarily limited. In addition, sets of alternating dielectric and electrode layers may be separated from adjacent sets by a certain distance. For example, the distance is greater than the thickness of the individual dielectric layers in the set. In particular, the distance can be at least twice the thickness of the dielectric layers in the set, for example, at least three times, for example, at least five times, for example, at least ten times, etc.

[0022] Generally, the thickness of the dielectric layer and the internal electrode layer is not limited and can be any thickness as desired depending on the performance characteristics. For example, the thickness of the electrode layer is not limited to about 500 nm or more, for example, about 1 μm or more, for example, about 1.5 μm or more, for example, about 2 μm or more, for example, about 3 μm or more, for example, about 4 μm or more. The thickness of the electrode layer can be about 10 μm or less, for example, about 5 μm or less, for example, about 4 μm or less, for example, about 3 μm or less, for example, about 2.5 μm or less, for example, about 2 μm or less. For example, the internal electrode layer can have a thickness of about 1 μm to about 2 μm.

[0023] In addition, the present invention is not necessarily limited to the number of internal electrode layers in each set of alternating dielectric layers and internal electrode layers, or in the capacitor as a whole. For example, each set may include 10 or more, for example 25 or more, for example 50 or more, for example 100 or more, for example 200 or more, for example 300 or more, for example 500 or more, for example 600 or more, for example 750 or more, for example 1,000 or more internal electrode layers. Each set can have an internal electrode layer of 5,000 or less, for example, 4,000 or less, for example, 3,000 or less, for example, 2,000 or less, for example, 1,500 or less, for example, 1,000 or less, for example, 750 or less, for example, 500 or less, for example, 400 or less, for example, 300 or less, for example, 250 or less, for example, 200 or less, for example, 175 or less, for example, 150 or less, etc. Furthermore, the entire capacitor can contain the above number of electrode layers.

[0024] In addition to alternating internal electrode layers and dielectric layers, the capacitor also includes a first external terminal and a second external terminal, the first external terminal being electrically connected to the first internal electrode layer and located on a first surface of the capacitor (e.g., the upper surface); the second external terminal being electrically connected to the first internal electrode layer and located on a second surface of the capacitor (e.g., the lower surface); similarly, a third external terminal being electrically connected to the second internal electrode layer and located on the first surface of the capacitor; and a fourth external terminal being electrically connected to the second internal electrode layer and located on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative).

[0025] Furthermore, a capacitor may include external terminals on opposing end surfaces. For example, one or more external terminals may extend from a first surface (e.g., the upper surface) and / or a second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminals may be present only partially on the end surface and not cover the entire end surface. In another embodiment, the capacitor may not include external terminals on opposing end surfaces. In one particular embodiment, the external terminals may not be present on the side surfaces of the capacitor. Nevertheless, the external terminals generally include at least one first polarity terminal and at least one second and opposite polarity terminal. A capacitor may include at least one, for example, at least two, for example, at least four, for example, at least six, for example, at least eight, etc., first polarity terminals and / or second and opposite polarity terminals on the upper surface of the capacitor. Additionally, a capacitor may include the above-mentioned number of terminals on the lower surface of the capacitor.

[0026] A capacitor may have an equal number of first polarity terminals and / or second polarity terminals on its upper and lower surfaces. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the upper surface of the capacitor. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the lower surface of the capacitor. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second and opposite polarity terminals present on the upper and lower surfaces of the capacitor. Typically, similar polarity terminals on the lower surface of the capacitor corresponding to a particular set of alternating dielectric and internal electrode layers are electrically connected to similar polarity terminals on the upper surface of the capacitor. Similar polarity terminals located on the upper and lower surfaces of the capacitor do not necessarily have to be meshed with each other. In this regard, corresponding similar polarity terminals on the upper and lower surfaces may not be offset by terminal position, but instead may be positioned directly above or directly below another similar polarity terminal on the opposite upper or lower surface. In other words, corresponding similar polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers, and, among other things, the corresponding lead tabs of such sets, may be substantially aligned. Being substantially aligned means that the offset of one lateral edge of a polarity terminal on the upper surface from its side edge is within + / -10% of the offset of the corresponding polarity terminal on the lower surface from its side edge, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc.

[0027] The specific arrangement of capacitor elements (e.g., the orientation of the electrode layers, the number of alternating layers within a single capacitor body) can offer several advantages. For example, the capacitor of the present invention can be mounted on a circuit board as a surface-mount capacitor, providing a smaller footprint on the circuit board. This can also enable a reduction in the size of the circuit board.

[0028] The capacitor of the present invention can be further described according to embodiments as illustrated in Figures 1A to 1G, Figures 2A to 2C, Figures 3A to 3C, Figures 4A to 4B, Figures 5A to 5B, and Figure 6.

[0029] Figures 1A to 1G disclose one embodiment of a multilayer capacitor 10. Generally, the capacitor 10 includes a body portion 16 which comprises a plurality of alternating dielectric layers and electrode layers 102, 104. A first external termination 12 and a second external termination 14 are formed on the capacitor body portion 16.

[0030] For example, the capacitor 10 has a 1x2 configuration. That is, the capacitor 10 includes two external terminals arranged in a linear manner in a single dimension on the upper and bottom surfaces of the capacitor. In the embodiment depicted, the capacitor 10 includes external terminals arranged in a linear manner or in a single row along the longitudinal direction L, which can be referred to as a linear terminal arrangement. Furthermore, in the embodiment depicted, the external terminals 12, 14 are spaced apart from the side surfaces 18e, 18f of the capacitor body 16, so that only dielectric material is disposed between the external terminals 12, 14 and the side surfaces 18e, 18f.

[0031] The main body 16 includes six surfaces. For example, referring to Figure 1A, the main body 16 includes an upper surface 18a and an opposing bottom surface 18b in the Z direction 136 or width direction. The main body 16 may also include two end surfaces 18c, 18d extending between the upper surface 18a and the bottom surface 18b. The end surfaces 18c, 18d may face each other in the longitudinal direction 132 or length direction. The end surfaces 18c, 18d may extend in the transverse direction 134 and the Z direction 136. Similarly, the main body 16 may also include two side surfaces 18e, 18f extending between the upper surface 18a and the bottom surface 18b. The side surfaces 18e, 18f may extend in the longitudinal direction 132 and the Z direction 136. In one embodiment, the side surfaces 18e, 18f may be parallel to the main surface of the electrode. Similarly, in one embodiment, the upper surface 18a and the bottom surface 18b can be perpendicular to the main surface of the electrode. Thus, in one embodiment, the body portion 16 includes at least six total surfaces (for example, one top, one bottom, two sides, and two ends). In this regard, the body portion 16 can have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0032] Furthermore, as illustrated in Figure 1B, the capacitor 10 can be mounted on a mounting surface 11 (for example, a printed circuit board or a substrate). In this regard, the multilayer capacitor can be configured to be mounted on a mounting surface such that the electrode layers are perpendicular to the mounting surface.

[0033] The multilayer capacitor 10 may include a plurality of electrode layers 102, 104 and dielectric layers stacked in the transverse direction 134. Some dielectric layers may include electrode layers formed on them. Generally, the thickness of the dielectric layers and electrode layers is not limited and can be any thickness as desired depending on the performance characteristics of the capacitor. For example, the electrode layers may have a thickness of about 1 μm to about 2 μm, but electrode layers of other thicknesses, as described herein, can also be used. In addition, in one embodiment, the thickness of the dielectric layer may be defined according to the aforementioned thickness of the electrode layer. It should also be understood that such a thickness of the dielectric layer may be applied to layers between any electrode layers.

[0034] Figure 1C illustrates a side view of one embodiment of an electrode configuration according to an aspect of the present disclosure. More specifically, the electrode layers may include, for example, a first electrode layer 102 and a second electrode layer 104 in an alternating arrangement, as described below with reference to Figure 1E. Referring to Figure 1C, each electrode layer 102, 104 may include a first electrode 106 and a second electrode 108. The first electrode 106 may have a base section 114. For example, the base section 114 of the first electrode 106 may have a vertical edge 121 extending in the longitudinal direction 132 and extending in the Z direction 136. The base section 114 may also include a first front edge 114a and a second front edge 114b opposite the first front edge 114a along the Z direction 136. The first and second leading edges 114a and 114b extend in the longitudinal direction 132, respectively, and intersect the vertical edge 121, so that the edges 114a, 114b, and 121 define the boundary of the first electrode 106 in the base section 114.

[0035] The second electrode 108 may have a base section 114. For example, the base section 114 of the second electrode 108 may also have a transverse edge that extends in the longitudinal direction 132 and in the Z direction 136.

[0036] Furthermore, the first electrode 106 may have a central section 112. The central section 112 may have a vertical edge 123 extending in the longitudinal direction 132 and extending in the Z direction 136. The vertical edge 123 of the central section 112 is on the opposite side of the vertical edge 121 of the base section 114, and the vertical edges 121 and 123 define the longitudinal boundary of the first electrode 106. In addition, the central section 112 may include a first edge 112a and a second edge 112b on the opposite side of the first edge 112a along the Z direction 136. The first and second edges 112a and 112b extend in the longitudinal direction 132, respectively, and intersect the vertical edge 123, so that the edges 112a, 112b, and 123 define the boundary of the first electrode 106 in the central section 112.

[0037] The central section 112 of the first electrode 106 may have a first width 127 extending, for example, in the Z direction 136. In addition, the base section 114 of the first electrode 106 may have a second width 129 extending, for example, in the Z direction 136. In this regard, the location of the first width 127 may be offset in the longitudinal direction 132 from the location of the second width 129, so that the location of the second width 129 is closer to the external end to which it is electrically connected. Such a configuration can allow adjustment of the overlap area between the central sections 112 of adjacent electrodes in the lateral direction 134. Furthermore, in at least some embodiments, the second width 129 of the base section 114 may be larger than the first width 127 of the central section 112.

[0038] In addition, a central end gap distance 133 can be formed in the longitudinal direction 132 between the longitudinal end of the central section 112 of the first electrode 106 and the longitudinal end of the base section 114 of the second electrode 108. Therefore, in one embodiment, the ratio of the central end gap distance 133 to the capacitor length 15 (Figure 1A) can be 0.01 or more, for example, 0.05 or more, for example, 0.1 or more, for example, 0.2 or more, for example, 0.3 or more, for example, 0.4 or more, etc. The ratio can also be, for example, 0.5 or less, for example, 0.4 or less, for example, 0.3 or less, for example, 0.2 or less, for example, 0.1 or less, etc.

[0039] Generally, the internal electrode layers 102, 104 include at least one lead tab 1002, 1004 extending along the Z direction 136 from the upper and bottom edges of the central section 112 of the internal electrode layer. For example, as shown in Figure 1C, the first lead tab 1002 extends from the upper edge 112a of the central section 112, and the second lead tab 1004 extends from the bottom edge 112b. Generally, the lead tabs 1002, 1004 of the electrode layers 102, 104 extend to the upper and bottom surfaces of the capacitor, helping to form the external terminations 12, 14. In this regard, the lead tabs 1002, 1004 are exposed on the upper surface 18a and bottom surface 18b of the capacitor, allowing for connections between the central section 112 of the internal electrode layer and the external terminations 12, 14. For example, lead tabs 1002, 1004 are defined by a base section 114 and may include first and second leading edges 114a, 114b, the first and second leading edges 114a, 114b extending to the edge of the dielectric layer, allowing for the formation of external terminations 12, 14 on the upper surface 18a and the bottom surface 18b.

[0040] The lengths of the lead tabs 1002 and 1004 can vary as desired, but are typically about 0.3 mm to about 1.2 mm, in some embodiments about 0.4 mm to about 1.1 mm, and in some embodiments about 0.5 mm to about 1 mm. When more than one lead tab is present along the edge, each lead tab can have the same length. In another embodiment, each lead tab may have a different length. For example, a lead tab substantially aligned with the side edge of the internal electrode layer can have a longer length than a lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. Being substantially aligned generally means that the offset of one lateral edge of the first lead tab and / or second lead tab at the upper edge from the lateral edge is within + / -10%, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc., of the offset of the corresponding lateral edge of the first lead tab and / or second lead tab at the bottom edge from the lateral edge.

[0041] The lead tabs 1002 and 1004 located at the upper and lower edges of the internal electrode layers 102 and 104 can be aligned vertically. That is, the lateral edge of the first lead tab 1002 (extending along the Z direction 136) can be aligned with the lateral edge of the second lead tab 1004 (extending along the Z direction 136) on the opposite side of the first lead tab 1002. In addition, such lateral edges of the lead tabs 1002 and 1004 can be aligned with the side edges 121 of the internal electrode layers 102 and 104. However, it should be understood that the lateral edges of the lead tabs 1002 and 1004 can be aligned with each other but offset from the side edges 121.

[0042] As described, the relationship between the lateral edge of the first lead tab at the upper edge and the lateral edge of the second lead tab at the bottom edge, as described for the internal electrode layer 102, can also be applied to the internal electrode layer 104. Such an arrangement makes it possible to form a gap between the first lead tab 1002 of the first internal electrode layer 102 and the first lead tab 1002 of the second internal electrode layer 104. Similarly, a gap can be formed between the second lead tab 1004 of the first internal electrode layer 102 and the second lead tab 1004 of the second internal electrode layer 104. The size of each gap can be substantially the same.

[0043] The lead tabs 1002 can be arranged in parallel with the lead tabs 1004 extending from the internal electrode layers 102 and 104, so that the lead tabs extending from the alternating electrode layers 102 and 104 can be aligned in their respective rows. For example, the lead tabs 1002 and 1004 of the internal electrode layer 102 can be arranged in their respective stacked configurations, while the lead tabs 1002 and 1004 of the internal electrode layer 104 can be arranged in their respective stacked configurations.

[0044] It is understood that the lead tabs 1002 and 1004 of electrode layer 102 are connected to the external termination 12, while the lead tabs 1002 and 1004 of electrode layer 104 are connected to the external termination 14. Thus, each lead tab 1002 and 1004 of electrode layer 102 interlocks with each other's lead tabs 1002 and 1004 of electrode layer 104 in a similar manner to the external terminations 12 and 14. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0045] The distance between adjacent exposed lead tabs of the internal electrode layer in a given column can be specifically designed to help ensure guided formation of the terminations. The distance between exposed lead tabs of the internal electrode layer in a given column can be, for example, in the range of about 0.25 μm to about 10 μm, in some embodiments in the range of about 0.5 μm to about 5 μm, and in some embodiments in the range of about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of electrode tabs can be, but is not limited to, at least twice as large as the distance between adjacent lead tabs in a given column to ensure that individual terminations do not mix. In some embodiments, the distance between adjacent columnar stacks of exposed metallization can be about four times (4x) the distance between adjacent exposed electrode tabs in a particular stack. However, such distances can vary depending on the desired capacitance performance and circuit board configuration. For example, the distance can be approximately 0.1 mm to approximately 1.5 mm, in some embodiments approximately 0.2 mm to approximately 1.3 mm, and in some embodiments approximately 0.3 mm to approximately 1 mm, when determined based on the center point of each lead tab or the distance between adjacent lateral edges of the lead tabs. In addition, such distances can correspond to the separation distance of balls on a ball grid array.

[0046] Still referring to Figure 1C, the first electrode 106 may also have a connecting section 116. The connecting section 116 may extend from the base section 114 in the longitudinal direction 132. In particular, the connecting section 116 may extend between the base section 114 and the central section 112 and connect to the base section 114 and the central section 112. For example, the first connecting edge 116a of the connecting section 116 extends from the first front edge 114a of the base section 114 to the first edge 112a of the central section 112, and the second connecting edge 116b of the connecting section 116 extends from the second front edge 114b of the base section 114 to the second edge 112b of the central section 112. Therefore, the first connecting edge 116a intersects the first front edge 114a and the first edge 112a, connecting the base section 114 to the central section 112 along one longitudinal side of the first electrode 106, and the second connecting edge 116b intersects the second front edge 114b and the second edge 112b, connecting the base section 114 to the central section 112 along the other opposite longitudinal side of the first electrode 106.

[0047] The connecting section 116 may have a third width 131 that extends, for example, in the Z direction 136. In this regard, the location of the third width 131 may be offset in the longitudinal direction 132 from the locations of the first width 127 and the second width 129. In one embodiment, the third width 131 of the connecting section may be smaller than the second width 129 of the base section 114. Alternatively, the third width 131 of the connecting section may be larger than the first width 127 of the central section 112. In this regard, the location of the third width 131 may be between the locations of the first width 127 and the second width 129.

[0048] Furthermore, the third width 131 can vary within the connecting section 116. For example, the third width 131 may have a first value at one location within the connecting section 116 and a second different value at another location within the connecting section 116, with the two locations within the connecting section 116 spaced apart from each other along the longitudinal direction 132.

[0049] At least one portion of the first connecting edge 116a or the second connecting edge 116b is not perpendicular to the edges 112a, 112b of the central section where the connecting edges 116a, 116b intersect. For example, in one embodiment, the first connecting edge 116a of the connecting section 116 can form a first angle 141 with the first edge 112a of the central section 112. Such an angle 141 can be greater than 90° and less than 180°. For example, such an angle 141 can be greater than 90°, for example 95° or more, for example 100° or more, for example 110° or more, for example 120° or more, for example 130° or more, for example 140° or more, and so on. Such an angle 141 can be less than 180°, for example, 175° or less, 170° or less, 160° or less, 150° or less, 140° or less, 130° or less, 120° or less, 110° or less, and so on. Although not intended to be limited by theory, such configurations can generally provide a Y-shaped electrode configuration.

[0050] Furthermore, in the embodiment depicted in Figure 1C, a second angle 147 is formed between the second edge 112b of the central section 112 and the second connecting edge 116b of the connecting section 116, and the second angle 147 is greater than 90° and less than 180°, as described above with reference to the first angle 141. Thus, with respect to the first electrode 106 shown in Figure 1C, at least a portion of the first connecting edge 116a is not perpendicular to the first edge 112a, and at least a portion of the second connecting edge 116b is not perpendicular to the second edge 112b. With respect to the embodiment depicted, it will also be understood that at least a portion of the first connecting edge 116a is not perpendicular to the first front edge 114a, and at least a portion of the second connecting edge 116b is not perpendicular to the second front edge 114b.

[0051] In a further embodiment as illustrated in Figure 1D, the connecting section 116 may also form an angle 143 with the base section 114. For example, the base section 114 may have a first transverse edge portion 130a extending in the Z direction 136 and a second transverse edge portion 130b extending in the Z direction 136, with the first and second transverse edge portions 130a and 130b intersecting the first connecting edge portion 116a and the second connecting edge portion 116b, respectively. At least a portion of the second connecting edge portion 116b may not be perpendicular to the vertical edge portion 130 of the base section 114, for example, such a vertical edge portion 130 may form an angle 143 with the second connecting edge portion 116b of the connecting section 116. Similarly, at least a portion of the first connecting edge 116a does not have to be perpendicular to the vertical edge 130 of the base section 114, and an angle 143 is defined between the first connecting edge 116a and the vertical edge 130. Such an angle 143 can be greater than 90° and less than 180°. For example, such an angle 143 can be greater than 90°, such as 95° or more, such as 100° or more, such as 110° or more, such as 120° or more, such as 130° or more, such as 140° or more. Such an angle 143 can be less than 180°, for example, 175° or less, 170° or less, 160° or less, 150° or less, 140° or less, 130° or less, 120° or less, 110° or less, and so on.

[0052] The embodiment in Figure 1F is substantially similar to the embodiments in Figures 1C to 1E, however, the embodiment of electrode layers 102 and 104 in Figure 1F omits the second electrode 108 and includes only the first electrode 106. Otherwise, the first electrode shown in Figure 1F has the same configuration as the first electrode 106 shown in Figures 1C and 1D, which generally has a Y-shape, and at least a portion of the connecting edges 116a and 116b is not perpendicular to the respective edges 112a and 112b where the connecting edges 116a and 116b intersect. Furthermore, it will be recognized that in some embodiments, the capacitor 10 may have only the first electrode 106 configured as shown in Figure 1D, and may include electrode layers 102 and 104 that omit the second electrode 108 in one or more electrode layers 102 and 104 of the dielectric and electrode layer stack.

[0053] As illustrated, the connecting edges 116a, 116b of the connecting section 116 can extend in both the longitudinal direction 132 and the Z direction 136. In one embodiment, such edges can be linear edges, so that the connecting edges 116a, 116b are substantially linear. Such linear edges are illustrated in Figures 1C and 1D. In another embodiment, such edges can be curved edges having a curved / rounded configuration.

[0054] For example, Figure 1G illustrates electrode layers 102, 104 having curved or rounded connecting edges 116a, 116b. That is, Figure 1G illustrates electrode layers 102, 104 in which at least one of the first electrode 106 or the second electrode 108 has at least one rounded corner. As used herein, “rounded” can refer to a peripheral portion having the shape of a circular or elliptical arc. Alternatively, “rounded” can refer to any suitable edge that is curved / bow-shaped but not precisely circular or elliptical.

[0055] Additionally, in some embodiments, the periphery of the first electrode 106 and / or the second electrode 108 may be free from geometric discontinuities. For example, rounded corners may blend seamlessly into adjacent straight edges without any geometric discontinuities. In some embodiments, at least one of the first electrode 106 and / or the second electrode 108 may have a geometrically continuous shape. In other words, there may be no discontinuities in the coordinate function describing the shape (for example, in Cartesian or polar coordinates). In some embodiments, the shape may be geometrically continuous up to the first order. In other words, the first derivative of the coordinate function describing the shape of the first electrode 106 and / or the second electrode 108 may not contain any discontinuities.

[0056] Such a rounded corner configuration can reduce the concentration of electric fields and charges at the rounded corners and / or along the edges of electrodes 106 and 108 adjacent to the rounded corners. Such reduction can increase the dielectric breakdown voltage of the capacitor incorporating electrode layers 102 and 104 compared to a conventional electrode configuration.

[0057] As described herein, corners can be intersections between two edges of electrodes 106 and 108. In some embodiments, each corner of the first electrode 106 and each corner of the second electrode 108 can be rounded. However, in other embodiments, as shown in Figure 1G, some of the electrode corners are rounded and others are not. For example, in the illustrated embodiment, the first connecting edge 116a and the second connecting edge 116b are curved or rounded, respectively, and at least a portion of each connecting edge 116a, 116b is not perpendicular to the first edge 112a and the second edge 112b, respectively, and the first electrode 106 has two rounded corners at the transition from the base section 114 to the central section 112. Creating rounded corners may incur additional manufacturing costs compared to non-rounded corners; therefore, a mixed corner configuration can offer similar benefits to embodiments with more (e.g., all) rounded corners, along with reduced manufacturing costs.

[0058] It should be understood that additional configurations relating to rounded and unrounded corners are possible within the scope of this disclosure. For example, in some embodiments, the second electrode 108 may similarly have two rounded corners and two unrounded corners, for example, the rounded corners of the second electrode 108 may be adjacent to the first electrode 106, and the unrounded corners of the second electrode 108 may face away from the first electrode 106. In other embodiments, the first electrode 106 may have only rounded corners, while the second electrode 108 may have only unrounded corners, and in yet another embodiment, the first electrode 106 may not have rounded corners, while the second electrode 108 may have only rounded corners.

[0059] Other modifications and / or combinations are possible within the scope of this disclosure. For example, the first electrode 106 may have a generally Y-shaped electrode configuration and one or more rounded corners. In electrodes 106, 108 on various electrode layers 102, 104, a different number and / or configuration of connecting edges that are not perpendicular to the edge of the central section may be used. For example, one or more electrode layers 102, 104 may have electrodes 106, 108 having a different connecting section 116 configuration than at least one of the other electrode layers 102, 104.

[0060] As further shown in Figures 1C, 1D, 1F, and 1G, the respective leading edges 114a, 114b of the base section 114 of the first electrode 106 can also have a specific length 135 extending in the longitudinal direction 132. Generally, such a length 135 of the base section can be defined as the distance between the vertical edge 121 and the point of transition between the base section 114 and the connecting section 116. For example, each of the first leading edge 114a and the second leading edge 114b can generally have a slope of 0°, and the point where the slope changes can be considered the aforementioned point of transition. Nevertheless, such a length can be 0.05 or more of the capacitor length 15 as defined herein, and can be, for example, 0.1 or more, for example, 0.15 or more, for example, 0.2 or more, for example, 0.3 or more, and so on. Such a length 135 can be 0.5 or less of the capacitor length 15, for example, 0.4 or less, for example, 0.3 or less, for example, 0.25 or less, for example, 0.2 or less, for example, 0.15 or less.

[0061] As also illustrated in Figures 1C, 1D, and 1G, the base section 114 of the second electrode 108 may also have a specific length 145 extending in the longitudinal direction 132. Such a length may be 0.05 or more of the capacitor length 15, for example, 0.1 or more, for example, 0.15 or more, for example, 0.2 or more, for example, 0.3 or more, etc. Such a length 145 may be 0.5 or less of the capacitor length 15, for example, 0.4 or less, for example, 0.3 or less, for example, 0.25 or less, for example, 0.2 or less, for example, 0.15 or less, etc.

[0062] In one embodiment, the lengths 135 and 145 described above can be different. In one particular embodiment, the lengths 135 and 145 described above can be substantially the same.

[0063] Furthermore, the first external end 12 may have a first lateral edge 122 (Figure 1A). The first lateral edge 122 may extend in the Z direction 136 and / or the lateral direction 134. The first lateral edge 122 may define the end width BW of the first external end 12, and the second external end 14 may also have an end width BW. The external ends 12 and 14 have an end length BL along the upper surface 18a, and the end length BL extends in the longitudinal direction 132.

[0064] The first lateral edge 122 of the first external terminal 12 can substantially align with the vertical edge 130 of the base section 114 of the first electrode 106 in the longitudinal direction. Such a vertical edge 130 can be located where the base section 114 ends and the connecting section 116 begins. For example, the first lateral edge 122 of the first external terminal 12 can be within 5% of the vertical edge 130 of the base section 114 of the first electrode 106 in the longitudinal direction, based on the length of the base section 114 of the first electrode 106, and can be within, for example, 4%, 3%, 2%, 1%, 0.8%, 0.6%, 0.5%, 0.4%, 0.3%, 0.2%, 0.1%.

[0065] Similarly, the second external terminal 14 may have a second lateral edge 124 (Figure 1A). The second lateral edge 124 may extend in the Z direction 136 and / or the lateral direction 134. The second lateral edge 124 of the second external terminal 14 may substantially align in the longitudinal direction with the vertical edge 130 of the base section 114 of the first electrode 106. Such a vertical edge 130 may be located where the base section 114 ends and the connecting section 116 begins. For example, the second lateral edge 124 of the second external terminal 14 can be within 5% of the vertical edge 130 of the base section 114 of the first electrode 106 in the longitudinal direction, based on the length of the base section 114 of the first electrode 106, and can be within, for example, 4%, 3%, 2%, 1%, 0.8%, 0.6%, 0.5%, 0.4%, 0.3%, 0.2%, or 0.1%.

[0066] In addition, the first lateral edge 122 of the first external terminal 12 can substantially align in the longitudinal direction with the lateral edge 126 (Figure 1E) of the base section 114 of the second electrode 108 of the electrode layer 104. For example, the first lateral edge 122 of the first external terminal 12 can be within 5% of the lateral edge 126 of the base section 114 of the second electrode 108 in the longitudinal direction, based on the length of the base section 114 of the second electrode 108, and can be within, for example, 4%, 3%, 2%, 1%, 0.8%, 0.6%, 0.5%, 0.4%, 0.3%, 0.2%, or 0.1%.

[0067] Similarly, the second lateral edge 124 of the second external terminal 14 can substantially align in the longitudinal direction with the lateral edge 128 of the base section 114 of the second electrode 108 of the electrode layer 102 (Figure 1E). For example, the second lateral edge 124 of the second external terminal 14 can be within 5% of the lateral edge 128 of the base section 114 of the second electrode 108 in the longitudinal direction, based on the length of the base section 114 of the second electrode 108, for example, within 4%, for example, within 3%, for example, within 2%, for example, within 1%, for example, within 0.8%, for example, within 0.6%, for example, within 0.5%, for example, within 0.4%, for example, within 0.3%, for example, within 0.2%, for example, within 0.1%.

[0068] As shown herein, dielectric layers and electrode layers can be stacked to form a set of alternating layers. As described elsewhere herein, one, two, three, four, or more sets of stacked alternating dielectric and electrode layers can be arranged within a single capacitor body. Capacitor 10 includes a single set of dielectric and electrode layers to form the capacitor body 16, but the capacitor body can include additional sets of stacked layers, as described with reference to Figures 3A to 5B, for example.

[0069] Referring to Figure 1E, the multiple first electrode layers 102 and the multiple second electrode layers 104 can be arranged in an alternating mirror-symmetry configuration. For example, the electrode layers can be interleaved in a relationship where they are positioned opposite each other with a space between them, with the dielectric layers positioned between each electrode layer. As illustrated, the central sections 112 of each electrode layer overlap at least partially. Although Figure 1E illustrates a total of four electrode layers, however, it should be understood that any number of electrode layers can be used to obtain the desired capacitance for a desired application. For example, a capacitor can contain 10 or more internal electrode layers, for example 25 or more, for example 50 or more, for example 100 or more, for example 200 or more, for example 300 or more, for example 500 or more, for example 600 or more, for example 750 or more, for example 1,000 or more internal electrode layers. The capacitor may include an internal electrode layer of 5,000 or less, such as 4,000 or less, for example, 3,000 or less, for example, 2,000 or less, for example, 1,500 or less, for example, 1,000 or less, for example, 750 or less, for example, 500 or less, for example, 400 or less, for example, 300 or less, for example, 250 or less, for example, 200 or less, for example, 175 or less, for example, 150 or less.

[0070] The present invention provides a multilayer capacitor having a unique electrode arrangement and configuration that offers various benefits and advantages as described herein. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and can be any materials commonly used in the art, and can be formed using any methods commonly used in the art.

[0071] Generally, dielectric layers can be formed from a specific type of material having a particular dielectric constant. For example, in one embodiment, the dielectric layer can be formed from a material having a relatively high dielectric constant (K). Such dielectric constants can be greater than 125, for example, 200 or more, for example, 500 or more, for example, 1,000 or more, and less than or equal to about 40,000, for example, about 30,000 or less, for example, about 20,000 or less. In other embodiments, the dielectric layer can be formed from a material having a relatively low dielectric constant (K). For example, the dielectric constant can be 10 or more, for example, 15 or more, for example, 20 or more, for example, 30 or more, for example, 40 or more, for example, 50 or more, for example, 60 or more, for example, 70 or more, for example, 80 or more, for example, 90 or more. The dielectric constant can be 125 or less, for example, 110 or less, for example, 100 or less, for example, 90 or less, for example, 80 or less, for example, 70 or less, for example, 60 or less, for example, 50 or less, for example, 40 or less, for example, 30 or less, for example, 20 or less, and so on.

[0072] Generally, these materials can include ceramics. Ceramics can be supplied in various forms, such as wafers (e.g., pre-fired) or dielectric materials that are co-fired within the device itself. Specific examples of these types of materials include, for example, NPO(COG), X7R (approximately 3,000 to approximately 7,000), X7S, Z5U, and / or Y5V materials. It should be noted that the materials described above are described by their industry-recognized definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and therefore should be recognized by those skilled in the art.

[0073] In one particular embodiment, the dielectric layer may include NPO(COG) material. Generally, these materials are recognized as EIA Class I ceramic materials. These materials may have a relatively low temperature coefficient. For example, although not intended to be limited by theory, these materials may have a minimum variation in capacitance as a function of temperature. In addition, such materials may have a relatively low dielectric constant, as shown above. Therefore, such materials may have a relatively small capacitance per unit volume.

[0074] For example, these materials can have capacitance changes with temperature such as 0 ± 30 ppm / °C, 0 ± 25 ppm / °C, 0 ± 20 ppm / °C, 0 ± 15 ppm / °C, 0 ± 10 ppm / °C, 0 ± 5 ppm / °C, or 0 ppm / °C. In other words, these materials can change by ±0.3%, ±0.25%, ±0.2%, ±0.15%, ±0.1%, ±0.05%, or 0% from -55°C to 125°C. With respect to the above, the capacitance value at 25°C can be used as a reference point. In this regard, the capacitance can be in the range of 10 pF to 0.01 μF. For example, capacitance can be 0.5pF or more, for example 1pF or more, for example 5pF or more, for example 10pF or more, for example 50pF or more, for example 100pF or more, for example 200pF or more, for example 500pF or more, for example 800pF or more, for example 1nF or more, for example 5nF or more. Capacitance can be 10nF or less, for example 8nF or less, for example 5nF or less, for example 3nF or less, for example 1nF or less, for example 900pF or less, for example 700pF or less, for example 500pF or less, for example 300pF or less, for example 200pF or less, for example 100pF or less, for example 50pF or less, for example 20pF or less. The above references to capacitance can refer to the capacitance of a capacitor.

[0075] These ceramic materials (including NPO (COG) ceramic materials), and the resulting dielectric layer can include perovskites such as barium titanate and related solid solutions (such as barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (such as lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate, etc. In one particular embodiment, for example, barium strontium titanate ( "BSTO") of the chemical formula Ba x Sr 1-x TiO3 can be used, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. In this regard, in one embodiment, the dielectric layer can include titanate. Other suitable perovskites are, for example, Ba x Ca 1-x TiO3 (where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6), Pb x Zr 1-x TiO3 ("PZT") (where x is in the range of about 0.05 to about 0.4), lead lanthanum zirconate titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconate titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4 can be included. Further additional complex perovskites are A[B1 1 / 3 B2 2 / 3 O3 materials (where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), and B2 is Ta z Nb 1-zIt is possible to include (where z can be a value from 0 to 1). In this regard, in one embodiment, the material and the corresponding dielectric layer may include a titanate such as barium titanate.

[0076] In further embodiments, these ceramic materials (including NPO(COG) ceramic materials) and the resulting dielectric layer may contain oxides. For example, the oxides may include zinc, zirconium, niobium, magnesium, tantalum, titanium, cobalt, strontium, neodymium, samarium, silicon, or mixtures thereof. In one embodiment, the oxide may include rare earth oxides. In one embodiment, the ceramic material may contain at least titanium dioxide. In one embodiment, the ceramic material may contain zirconium dioxide. In further embodiments, the ceramic material may contain silicon dioxide. In one embodiment, the ceramic material may contain titanium dioxide, zirconium dioxide, silicon dioxide, or mixtures thereof.

[0077] In further embodiments, these ceramic materials (including NPO(COG) ceramic materials) and the resulting dielectric layers may include combinations of titanates and oxides. In particular, they may include combinations of barium titanate and oxides.

[0078] Electrodes and electrode layers can be formed from any of the various different metals known in the art. Electrode layers can be made from metals such as conductive metals. Materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, aluminum, zinc, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold, may also be suitable. Electrodes can also be made from low-resistance materials such as silver, copper, gold, aluminum, and palladium. In one particular embodiment, the electrode layer can include nickel or an alloy thereof. In another particular embodiment, the electrode layer can include copper or an alloy thereof.

[0079] Each electrode layer 102, 104 may contain one or more electrodes, as described with reference to Figures 1C to 1G. For example, in some embodiments, each electrode layer 102, 104 may contain a first electrode 106 and a second (counter) electrode 108, as shown in Figures 1C to 1E and 1G. In other embodiments, each electrode layer 102, 104 may contain a single electrode, as illustrated in Figure 1F.

[0080] Generally, capacitors as described herein refer to a specific electrode configuration. However, it should be understood that other types of electrodes and / or electrode layers, as known in the art, may also be used in capacitors. For example, these other electrodes and / or electrode layers may include, but are not limited to, shield electrodes, dummy electrodes, floating electrodes, and the like. For example, in one embodiment, the capacitor may include a shield electrode. In another embodiment, the capacitor may include a dummy electrode. In a further embodiment, the capacitor may include a floating electrode. In addition, such electrodes may have any shape as is generally known in the art. However, in one embodiment, the capacitor may not include a shield electrode, a dummy electrode, and / or a floating electrode. For example, in one embodiment, the capacitor may not include a shield electrode. In another embodiment, the capacitor may not include a dummy electrode. In a further embodiment, the capacitor may not include a floating electrode.

[0081] As shown in Figure 1A, in addition to the main body 16 which includes the dielectric layer and electrode layers 102 and 104, the capacitor 10 may also include a first external termination 12 and a second external termination 14. The first external termination 12 may be connected (for example, electrically connected) to the first electrode 106 of the first electrode layer 102 and the second (counter) electrode 108 of the second electrode layer 104. The second external termination 14 may be connected (for example, electrically connected) to the first electrode 106 of the second electrode layer 104 and the second (counter) electrode 108 of the first electrode layer 102.

[0082] For example, the first external termination 12 can be electrically connected to the first electrode layer 102 along at least one of the first leading edge 114a or second leading edge 114b of the base section 114 of the first electrode 106 of the first electrode layer 102. The second external termination 14 can be electrically connected to the second electrode layer 104 along at least one of the first leading edge 114a or second leading edge 114b of the base section 114 of the first electrode 106 of the second electrode layer 104. The leading edges 114a, 114b can assist in the formation of the external terminations 12, 14 as further described herein.

[0083] External ends 12 and 14 can be formed on the respective end surfaces 18c and 18d of the main body 16. However, external ends 12 and 14 can also be located on other surfaces. For example, external ends can extend to the upper surface 18a and the bottom surface 18b, as well as the two side surfaces 18e and 18f. In particular, external end 12 can extend to the upper surface 18a, the bottom surface 18b, and the side surfaces 18e and 18f. Similarly, external end 14 can extend to the upper surface 18a, the bottom surface 18b, and the side surfaces 18e and 18f. In the embodiment shown in Figure 1A, the first external end 12 extends to the upper surface 18a, the bottom surface 18b, and the end surface 18c, and the second external end 14 extends to the upper surface 18a, the bottom surface 18b, and the end surface 18d, such that the external ends 12 and 14 are spaced apart from the side surfaces 18e and 18f. In a further embodiment, the external ends may be formed on the upper surface only, on the bottom surface only, or on both the upper and bottom surfaces, for example, such that the external ends are spaced apart from one or more of the end surfaces 18c and 18d or the side surfaces 18e and 18f.

[0084] Generally, the outer termination can have an average thickness of approximately 500 μm or less, for example, approximately 400 μm or less, approximately 250 μm or less, approximately 150 μm or less, approximately 100 μm or less, approximately 50 μm or less, approximately 40 μm or less, approximately 30 μm or less, approximately 25 μm or less, and approximately 20 μm or less. The outer termination can have an average thickness of approximately 5 μm or more, for example, approximately 10 μm or more, approximately 15 μm or more, approximately 25 μm or more, and approximately 50 μm or more. For example, the outer termination can have an average thickness of about 5 μm to about 50 μm, for example, about 10 μm to about 40 μm, for example, about 15 μm to about 30 μm, for example, about 15 μm to about 25 μm. In one embodiment, the above thickness refers to the average thickness of the entire outer termination (for example, one containing more than one layer). In another embodiment, the above thickness refers to the average thickness of a single layer of the outer termination.

[0085] With respect to the embodiments discussed herein, the external termination can be formed from any of the various different metals known in the art. The external termination can be made from metals such as conductive metals. The materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In one particular embodiment, the external termination can include copper or an alloy thereof.

[0086] External terminations can be formed using any method commonly known in the art. External terminations can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrushing, etc.

[0087] In one embodiment, the external termination can be formed such that it is relatively thick. For example, such a termination can be formed by applying a thick metal strip to the exposed portion of the electrode layer (for example, by immersing the capacitor in a liquid external termination material). Such a metal can be in a glass matrix and can include silver or copper. As an example, such a strip can be printed and fired onto the capacitor. Subsequently, an additional plating layer of metal (e.g., nickel, tin, solder, etc.) can be generated on the termination strip so that the capacitor can be soldered to a substrate. Such application of a thick strip can be carried out using any method commonly known in the art (for example, by a termination machine and printing wheel for transferring metal-loaded paste onto the exposed electrode layer).

[0088] A thickly plated outer end can have an average thickness of approximately 500 μm or less, for example, approximately 300 μm or less, for example, approximately 200 μm or less, for example, approximately 150 μm or less, for example, approximately 100 μm or less, for example, approximately 80 μm or less. A thickly plated outer end can have an average thickness of approximately 25 μm or more, for example, approximately 35 μm or more, for example, approximately 50 μm or more, for example, approximately 75 μm or more. For example, a thickly plated outer end can have an average thickness of approximately 25 μm to approximately 150 μm, for example, approximately 35 μm to approximately 125 μm, for example, approximately 50 μm to approximately 100 μm. In one embodiment, the above thickness refers to the average thickness of the entire outer end (for example, including more than one layer). In another embodiment, the above thickness refers to the average thickness of a single layer of the outer end.

[0089] In another embodiment, the outer termination can be formed such that it is a thin film plating of metal. Such a thin film plating can be formed by depositing a conductive material (e.g., a conductive metal) onto an exposed portion of the electrode layer. For example, the leading edge of the electrode layer can be exposed so as to allow for the formation of a plated termination.

[0090] A thinly plated outer end can have an average thickness of about 50 μm or less, for example, about 40 μm or less, for example, about 30 μm or less, for example, about 25 μm or less. A thinly plated outer end can have an average thickness of about 5 μm or more, for example, about 10 μm or more, for example, about 15 μm or more. For example, an outer end can have an average thickness of about 5 μm to about 50 μm, for example, about 10 μm to about 40 μm, for example, about 15 μm to about 30 μm, for example, about 15 μm to about 25 μm. In one embodiment, the thickness described above refers to the average thickness of the entire outer end (for example, including more than one layer). In another embodiment, the thickness described above refers to the average thickness of a single layer of the outer end.

[0091] Generally, external terminations can include plated terminations. For example, external terminations can include electroplated terminations, electroless plated terminations, or a combination thereof. For example, electroplated terminations can be formed via electroplating. Electroless plated terminations can be formed via electroless plating.

[0092] When multiple layers constitute the outer termination, the outer termination can include electroplated and electroless plated terminations. For example, electroless plating can be used initially to deposit the initial layer of material. The plating technique can then be switched to an electrochemical plating system, which can enable faster accumulation of the material.

[0093] When forming plated ends by any of the plating methods, the leading edge of the electrode layer exposed from the main body of the capacitor is exposed to the plating solution. By exposure, in one embodiment, the capacitor can be immersed in the plating solution.

[0094] The plating solution contains a conductive material (e.g., a conductive metal) and is used to form a plated end. Such a conductive material can be any of the materials described above or any that is commonly known in the art. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solution, such that the plated layer and outer end contain nickel. Alternatively, the plating solution can be a copper acid bath or other suitable copper solution, such that the plated layer and outer end contain copper.

[0095] Additionally, it should be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. Furthermore, the additives may be used to use the plating solution at a desired pH. In one embodiment, resistance-reducing additives may be used in the solution to assist in complete plating, as well as in the bonding of the plating material to the exposed leading edges of the capacitor and electrodes.

[0096] The capacitor can be exposed, submerged, or immersed in a plating solution for a predetermined amount of time. Such exposure time is not necessarily limited, but can be sufficient to allow enough plating material to deposit to form a plated end. In this regard, the time should be sufficient to allow the formation of a continuous connection between the desired exposed adjacent leading edges of the electrodes.

[0097] Generally, the difference between electrolytic and electroless plating is that electrolytic plating uses an electrical bias (for example, by using an external power supply). Electrolytic plating solutions typically have a high current density range, e.g., 10 to 15 amp / ft. 2It may be exposed to (rated 9.4 volts). The connection can be formed by a negative connection to the capacitor, which requires the formation of plated terminations, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite to the polarity of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the metal at the exposed leading edge of the electrode layer.

[0098] Various pretreatment steps can be used before immersing or exposing the capacitor to the plating solution. Such steps can be performed for a variety of purposes, including catalytically accelerating, and / or improving, the adhesion of the plating material to the leading edge of the electrodes.

[0099] Additionally, an initial cleaning step may be used prior to plating or any other pretreatment step. Such a step may be used to remove any oxide buildup that forms on the exposed edges of the electrodes. This cleaning step may be particularly useful in assisting the removal of any nickel oxide buildup when the internal electrodes or other conductive elements are formed from nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning tank (e.g., one containing an acid cleaner). In one embodiment, the exposure can be over a predetermined time (e.g., on the order of about 10 minutes). Alternatively, cleaning can be achieved by a chemical polishing or hyper-rising step.

[0100] In addition, to promote the deposition of conductive materials, a step may be taken to activate the exposed metal leading edge of the electrode. Activation can be achieved by immersion in a palladium salt, a photo-patterned palladium organometallic precursor (via a mask or laser), a screen-printed or inkjet-deposited palladium compound, or an electrophoretic palladium deposit. It should be recognized that the palladium-based activation is disclosed merely as an example of an activating solution, which often works well for activating exposed tab portions formed from nickel or its alloys. However, it should be understood that other activating solutions may also be available.

[0101] Furthermore, instead of or in addition to the activation step described above, the activating dopant can be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer contains nickel and the activating dopant contains palladium, the palladium dopant can be introduced into the nickel ink or composition forming the electrode layer. Doing so makes it possible to eliminate the palladium activation step. It should be further understood that some of the above activation methods, such as organometallic precursors, are also useful for co-deposition of glass-forming agents to improve adhesion to the generally ceramic body of the capacitor. When the activation step is performed as described above, traces of the activating material may often remain on the exposed conductive portion before and after terminal plating.

[0102] Additionally, post-plating treatment steps may be required. Such steps can be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step may be used after the plating step. Such heating can be performed via baking, laser subjecting, UV exposure, microwave exposure, arc welding, etc.

[0103] As shown herein, the external end may include at least one plating layer. In one embodiment, the external end may include only one plating layer. However, it should be understood that the external end may include multiple plating layers. For example, the external end may include a first plating layer and a second plating layer. In addition, the external end may include a third plating layer. The materials of these plating layers may be any of those described above, or may be those commonly known in the art.

[0104] For example, one plating layer (e.g., a first plating layer) may contain copper or an alloy thereof. Another plating layer (e.g., a second plating layer) may contain nickel or an alloy thereof. Another plating layer (e.g., a third plating layer) may contain tin, lead, gold, or a combination thereof (e.g., an alloy). Alternatively, the initial plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, an initial copper plating layer may be formed, followed by a nickel layer.

[0105] In one embodiment, the initial plating layer or first plating layer can be a conductive metal (e.g., copper). This area can then be covered by a second layer containing a resistive polymer material for sealing. The area can then be polished to selectively remove the resistive polymer material and then re-plated with a third layer containing a conductive metallic material (e.g., copper).

[0106] The aforementioned second layer above the initial plating layer can correspond to a solder barrier layer (e.g., a nickel-solder barrier layer). In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel) onto the initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for the layer (the aforementioned solder barrier layer) include nickel-phosphorus, gold, and silver. In some embodiments, the aforementioned third layer above the solder barrier layer can correspond to a conductive layer (e.g., plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder).

[0107] In addition, a layer of metal plating may be formed, followed by an electroplating step to provide a resistive alloy or a higher resistive metal alloy coating (e.g., electroless Ni-P alloy) on such metal plating. However, it should be understood that any metal coating is possible, as will be understood by those skilled in the art from the full disclosure herein.

[0108] It should be recognized that any of the steps described above can occur as a bulk process, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes (all of which are commonly known in the art). Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminations, which requires processing of individual components).

[0109] As described herein, the formation of an external termination is generally guided by the location of the exposed edge of the internal electrode layer. Such a phenomenon can be referred to as "self-determinism" because the formation of the externally plated termination is determined by the configuration of the exposed conductive metal of the electrode layer at a selected peripheral location on the capacitor. In some embodiments, the capacitor may include a "dummy tab" to provide exposed conductive metal along a portion of the capacitor body that does not contain other electrodes (e.g., an active electrode or a shield electrode). In some embodiments, one or more "dummy tabs," "dummy electrodes," anchor tabs, and / or anchor electrodes may be additional features for a nucleate function that occurs, for example, during an FCT (Fine Copper Termination, Electroless Plating) process. Such dummy or anchor tabs or electrodes may be positioned internally or externally to the body of the component to nucleate the metallized plating material to form the externally plated termination in the FCT process. For example, a first set of dummy tabs can be connected to a first external termination, and a second set of dummy tabs can be connected to a second external termination. Generally, the second electrodes 108 of the internal electrode layers 102 and 104 can be dummy or anchor tabs or electrodes that assist in the formation of the first external termination 12 and the second external termination 14.

[0110] The second electrode (i.e., dummy or anchor tab or electrode) can have any configuration known in the art. For example, in some embodiments, as shown in the figures, the second electrode can have a rectangular configuration or shape, while in other embodiments, the second electrode can have a C-shaped or L-shaped configuration. For example, the second electrode can have a base section and at least one (e.g., two) electrode arms extending from the base section (particularly from the lateral ends of the base section). Such electrode arms can extend longitudinally away from the ends of the capacitor body. Furthermore, such electrode arms of the second electrode can be longitudinally aligned. However, it will be recognized that the second electrode can have any shape as is generally known in the art.

[0111] Additional aspects of the above techniques for forming thin-film plated terminations are described in U.S. Patents 7,177,137 and 7,463,474 by Ritter et al., which are incorporated herein by reference for all purposes. It should be recognized that additional techniques for forming capacitor terminations may also be within the scope of this technique. Exemplary alternatives, but not limited to, include forming terminations by plating, magnetization, masking, electrophoresis / static, sputtering, vacuum deposition, printing, or other techniques for forming both thick and thin conductive layers.

[0112] Referring back to the figures (in particular, Figures 1A and 1B), in some embodiments, the first transverse edge 122 of the first external end 12 can be offset longitudinally 132 from the end surface 18c and face away from the end surface 18c. The second transverse edge 124 of the second external end 14 can be offset longitudinally from the end surface 18d and face away from the end surface 18d. Referring to Figure 1B, the second transverse edge 124 can be offset longitudinally 132 from the first transverse edge 122 by an external end gap distance 39. In this respect, the external end gap distance 39 can be formed in the longitudinal direction 132.

[0113] The external termination gap distance 39 can be approximately 100 μm or more, for example, approximately 150 μm or more, for example, approximately 200 μm or more, for example, approximately 300 μm or more, for example, approximately 400 μm or more, for example, approximately 500 μm or more, for example, approximately 600 μm or more. The external termination gap distance 39 can be approximately 1,000 μm or less, for example, approximately 900 μm or less, for example, approximately 800 μm or less, for example, approximately 700 μm or less, for example, approximately 600 μm or less.

[0114] Referring to Figures 1A and 1B, in some embodiments, the multilayer capacitor 10 can have a capacitor length 13 in the longitudinal direction 132 between the ends of the capacitor (i.e., including the external terminations on the end surfaces 18c, 18d). The capacitor length 13 can be about 600 μm or more, for example, about 700 μm or more, for example, about 800 μm or more, for example, about 900 μm or more, for example, about 1,000 μm or more, for example, about 1,200 μm or more, for example, about 1,400 μm or more. The capacitor length 13 can be approximately 3,000 μm or less, for example, approximately 2,500 μm or less, for example, approximately 2,200 μm or less, for example, approximately 1,800 μm or less, for example, approximately 1,600 μm or less, for example, approximately 1,500 μm or less, for example, approximately 1,400 μm or less, for example, approximately 1,300 μm or less, for example, approximately 1,200 μm or less, for example, approximately 1,100 μm or less. Therefore, in one embodiment, the ratio of the external termination gap distance 39 to the capacitor length 13 can be 0.1 or more, for example, 0.2 or more, for example, 0.3 or more, for example, 0.4 or more, for example, 0.5 or more, for example, 0.6 or more, for example, 0.7 or more. The ratio can be 0.9 or less, for example, 0.8 or less, for example, 0.7 or less, for example, 0.6 or less, for example, 0.5 or less.

[0115] Similarly, in some embodiments, the main body portion 16 of the capacitor 10 may have a main body length 15 in the longitudinal direction 132 between the end surfaces 18c, 18d of the capacitor main body portion 16. The main body length 15 may be about 600 μm or more, for example, about 700 μm or more, for example, about 800 μm or more, for example, about 900 μm or more, for example, about 1,000 μm or more, for example, about 1,200 μm or more, for example, about 1,400 μm or more, and so on. The length of the main body portion 15 can be approximately 3,000 μm or less, for example, approximately 2,500 μm or less, for example, approximately 2,200 μm or less, for example, approximately 1,800 μm or less, for example, approximately 1,600 μm or less, for example, approximately 1,500 μm or less, for example, approximately 1,400 μm or less, for example, approximately 1,300 μm or less, for example, approximately 1,200 μm or less, for example, approximately 1,100 μm or less. Therefore, in one embodiment, the ratio of the external end gap distance 39 to the length of the main body portion 15 can be 0.1 or more, for example, 0.2 or more, for example, 0.3 or more, for example, 0.4 or more, for example, 0.5 or more, for example, 0.6 or more, for example, 0.7 or more. The ratio can be 0.9 or less, for example, 0.8 or less, for example, 0.7 or less, for example, 0.6 or less, for example, 0.5 or less.

[0116] In one embodiment, the capacitor 10 (or a portion thereof) can be symmetric with respect to a longitudinal centerline extending in the longitudinal direction 132. In another embodiment, the capacitor 10 (or a portion thereof) can be symmetric with respect to a transverse centerline extending in the transverse direction 134. In a further embodiment, the capacitor 10 (or a portion thereof) can be symmetric with respect to a Z-axis centerline extending in the Z-direction 136.

[0117] As illustrated in Figures 1A and 1B, the capacitor 10 includes two external terminations formed on the upper and bottom surfaces. However, as shown above, the present invention is not limited by the number of external terminations.

[0118] For example, Figure 2A illustrates a capacitor 20 with four external terminations on its top and bottom surfaces, respectively. Similar reference numerals are used in Figures 2A to 2C to indicate the same or similar features as in Figures 1A to 1G.

[0119] As illustrated in Figure 2A, the capacitor 20 has a 1×4 configuration. That is, the capacitor 20 includes two external terminals arranged in a linear manner in a single dimension on the upper and bottom surfaces of the capacitor. In the embodiment depicted, the capacitor 20 includes external terminals arranged in a linear manner or in a single row along the longitudinal direction L, which can be referred to as a linear terminal arrangement. In this regard, the capacitor 20 includes a body 26, the body 26 having a total of four external terminals 22a, 22b, 24a, 24b on the upper surface 28a and four corresponding external terminals (not shown) on the bottom surface 28b, the external terminals 22a, 22b, 24a, 24b on the upper surface 28a being electrically connected to the corresponding external terminals 22a, 22b, 24a, 24b on the bottom surface 28b. Furthermore, in the depicted embodiment, the external terminations 22a, 22b, 24a, and 24b are positioned at a distance from the side surfaces 28e and 28f of the capacitor body 26, so that only the dielectric material is disposed between the external terminations 22a, 22b, 24a, and 24b and the side surfaces 28e and 28f.

[0120] In addition, the external terminals 22a and 24a extend along the respective end surfaces 28c and 28d of the main body 26, from the upper surface 28a to the bottom surface 28b. For example, the external terminal 22a wraps around from the upper surface 28a along the end surface 28c to the bottom surface 28b, and the external terminal 24a wraps around from the upper surface 28a along the end surface 28d to the bottom surface 28b. The external terminals 22a and 24a can be referred to as end external terminals.

[0121] The first external termination 22a and the third external termination 22b can be connected to the first electrode 206 of the first electrode layer 202 and the second (counter) electrode 208 of the second electrode layer 204 (for example, by electrical connection). The second external termination 24a and the fourth external termination 24b can be connected to the first electrode 206 of the second electrode layer 204 and the second (counter) electrode 208 of the first electrode layer 202 (for example, by electrical connection).

[0122] For example, the first external termination 22a can be electrically connected to the first electrode layer 202 along at least one of the first leading edge 214a or second leading edge 214b of the first base portion 214-1 of the first electrode 206 of the first electrode layer 202. The second external termination 24a can be electrically connected to the second electrode layer 204 along at least one of the first leading edge 214a or second leading edge 214b of the first base portion 214-1 of the first electrode 206 of the second electrode layer 204. The third external termination 22b can be electrically connected to the first electrode layer 202 along at least one of the third leading edge 214c or fourth leading edge 214d of the second base portion 214-2 of the first electrode 206 of the first electrode layer 202. The fourth external termination 24b can be electrically connected to the second electrode layer 204 along at least one of the third leading edge 214c or fourth leading edge 214d of the second base portion 214-2 of the first electrode 206 of the second electrode layer 204. The leading edges 214a, 214b, 214c, and 214d can assist in the formation of the external terminations 22a, 22b, 24a, and 24b, as further described herein.

[0123] Additionally, the capacitor 20 in Figure 2A includes at least one first polarity terminal and at least one second and opposite polarity terminal on the upper surface. Although not shown, the bottom surface includes at least one first polarity terminal and a second and opposite polarity terminal. Among other things, as shown in Figure 2A, the capacitor 20 includes two positive terminals 22a, 22b and two negative terminals 24a, 24b on the upper surface 28a.

[0124] The main body 26 of the capacitor 20 has a length 25 extending in the longitudinal direction 232, which can be measured from one end surface 28c to the opposite end surface 28d. Furthermore, the main body 26 of the capacitor 20 has a width 127 extending in the lateral direction 234, which can be measured from one side surface 28e to the opposite side surface 28e. In addition, the main body 26 of the capacitor 20 has a height 29 extending in the Z direction 236, which can be measured from the upper surface 28a to the opposite bottom surface 28b.

[0125] As shown in Figure 2A, the external ends 22a, 22b, 24a, and 24b each have an end width BW extending in the lateral direction 234. Furthermore, the external ends 22a and 24a have an end length BLA along the upper surface 18a, and this end length BLA extends in the longitudinal direction 232. Similarly, the external ends 22b and 24b have an end length BLB along the upper surface 18a, which also extends in the longitudinal direction 232. It will be recognized that one or both ends 22a, 24a or one or both ends 22b, 24b may each have an end length BLA or BLB along the bottom surface 18b, which may be the same as or different from the respective end lengths BLA and BLB along the upper surface 18a.

[0126] Although not shown herein, it will be recognized that the capacitor 20 can be mounted on a mounting surface (for example, a printed circuit board or substrate, such as the mounting surface 11 shown in Figure 1B). In this regard, the multilayer capacitor can be configured to be mounted on a mounting surface such that the electrode layers are perpendicular to the mounting surface.

[0127] As shown in the figures, the multilayer capacitor 20 can be constructed substantially the same as the multilayer capacitor 10 described with respect to Figures 1A and 1B. However, the multilayer capacitor 20 has first and second electrode layers 202, 204 having multiple base sections 214, connecting sections 216, and a central section 212, as further described below.

[0128] The multilayer capacitor 20 may include multiple electrode layers 202, 204 and dielectric layers stacked in the lateral direction 234. Some dielectric layers may include electrode layers formed on them. Generally, the thickness of the dielectric layers and electrode layers is not limited and can be any thickness as desired depending on the performance characteristics of the capacitor.

[0129] Figure 2B illustrates a side view of one embodiment of an electrode configuration according to an aspect of the present disclosure, and Figure 2C illustrates a side view of one embodiment of an electrode configuration according to an aspect of the present disclosure. The electrode configuration of Figure 2B can be described as a generally Y-shaped electrode configuration (including multiple Y-shapes) similar to the embodiments of Figures 1C to 1F, and the electrode configuration of Figure 2C can be described as a generally multi-tab rounded-edge configuration similar to the embodiment of Figure 1G. Each of the electrode configurations shown in Figures 2B and 2C has at least one portion of an edge that is not perpendicular to the edges it intersects.

[0130] Specifically referring to Figure 2B, each electrode layer 202, 204 can include the first electrode 206. Although not shown, it will be recognized that in some embodiments, the electrode layers 202, 204 can also include a second electrode 208, as shown in Figure 2C and similar to the embodiments in Figures 1C-1E. The first electrode 206 can have a first base section 214-1 and a second base section 214-2. For example, each of the first base section 214-1 and the second base section 214-2 of the first electrode 206 can have vertical edges 221a, 221b, respectively, extending in the longitudinal direction 232 and extending in the Z direction 236. The first base section 214-1 can also include a first front edge 214a and a second front edge 214b opposite the first front edge 214a along the Z direction 236. The first and second leading edges 214a and 214b extend longitudinally 232, respectively, and intersect the first vertical edge 221a, so that the edges 214a, 214b, and 221a define the boundary of the first electrode 206 in the first base section 214-1. Similarly, the second base section 214-2 may also include a third leading edge 214c and a fourth leading edge 214d opposite the third leading edge 214c along the Z direction 236. The third and fourth leading edges 214c and 214c extend longitudinally 232, respectively, and intersect the second vertical edge 221b, so that the edges 214c, 214d, and 221b define the boundary of the first electrode 206 in the second base section 214-2.

[0131] Furthermore, the first electrode 206 may have a first central section 212-1 and a second central section 212-2. The first central section 212-1 may extend longitudinally 232 to the second vertical edge 221b of the second base section 214-2. The second central section 212-2 may have a vertical edge 223 that extends longitudinally 232 and extends in the Z direction 236. The vertical edge 223 of the second central section 212-2 is on the opposite side of the first vertical edge 221a of the first base section 214-1, and the vertical edges 221a and 223 define the longitudinal boundary of the first electrode 206. Furthermore, the first central section 212-1 may include a first edge 212a and a second edge 212b opposite the first edge 212a along the Z direction 236. The first and second edges 212a and 212b extend longitudinally 232, respectively, and intersect the second vertical edge 221b of the second base section 214-2, so that the edges 212a, 212b, and 221b define the boundary of the first electrode 106 in the first central section 212-1. The second central section 212-2 may include a third edge 212c and a fourth edge 212d opposite the third edge 212c along the Z direction 236. The third and fourth edges 212c and 212d extend in the longitudinal direction 232, respectively, and intersect the vertical edge 223 of the second central section 212-2, so that the edges 212c, 212d, and 223 define the boundary of the first electrode 106 in the second central section 212-2.

[0132] Each central section 212-1, 212-2 of the first electrode 206 may have a first width 227 extending, for example, in the Z direction 236. In addition, each base section 214-1, 214-2 of the first electrode 206 may have a second width 229 extending, for example, in the Z direction 236. In this regard, the location of the first width 227 may be offset in the longitudinal direction 232 from the location of the second width 229, such that the location of the second width 229 is closer to the external end to which the first electrode 206 is electrically connected. Such a configuration can allow adjustment of the overlap area between the central sections 212 of adjacent electrodes in the lateral direction 234. Furthermore, in at least some embodiments, the second width 229 of each base section 214-1, 214-2 may be greater than the first width 227 of each central section 212-1, 212-2.

[0133] Generally, the internal electrode layers 202, 204 include at least one lead tab 2002a, 2004a extending along the Z direction 236 from the upper and bottom edges of the first central section 212-1, and at least one lead tab 2002b, 2004b extending along the Z direction 236 from the upper and bottom edges of the second central section 212-2. Generally, the lead tabs 2002a, 2004a, 2002b, 2004b of the electrode layers 202, 204 extend to the upper and bottom surfaces of the capacitor and help form the external terminals 22a~b, 24a~b. In this regard, the lead tabs 2002a, 2004a, 2002b, and 2004b are exposed on the upper surface 28a and bottom surface 28b of the capacitor, enabling connections between the central sections 212-1, 212-2 of the internal electrode layers and the external terminals 22a-b, 24a-b. For example, the lead tabs 2002a and 2004a of the electrode layers 202 and 204 may be defined by a first base section 214-1 and may include first and second leading edges 214a and 214b, the first and second leading edges 214a and 214b extending to the edges of the dielectric layer, enabling the formation of external terminals 22a and 24a on the upper surface 28a and bottom surface 28b. The lead tabs 2002b and 2004b of the electrode layers 202 and 204 are defined by a second base section 214-2 and may include third and fourth leading edges 214c and 214d, which extend to the edges of the dielectric layer and allow for the formation of external terminals 22b and 24b on the upper surface 28a and bottom surface 28b.

[0134] The lead tabs 2002a, 2004a, 2002b, and 2004b can generally be configured as described above with respect to the lead tabs 1002 and 1004 of the capacitor 10. For example, the lengths of the lead tabs 2002a, 2004a, 2002b, and 2004b can vary as desired, but are typically about 0.3 mm to about 1.2 mm, in some embodiments about 0.4 mm to about 1.1 mm, and in some embodiments about 0.5 mm to about 1 mm. When more than one lead tab is present along the edge, each lead tab can have the same length. In another embodiment, each lead tab may have different lengths. For example, a lead tab substantially aligned with the side edge of the internal electrode layer can have a longer length than a lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. Substantially aligned generally means that the offset from the side edge of one lateral edge of the first lead tab and / or second lead tab at the upper edge is within + / -10%, e.g., within + / -5%, e.g., within + / -4%, e.g., within + / -3%, e.g., within + / -2%, e.g., within + / -1%, e.g., within + / -0.5%, etc., of the offset from the side edge of the corresponding lateral edge of the first lead tab and / or second lead tab at the bottom edge.

[0135] The lead tabs 2002a, 2004a, 2002b, and 2004b located at the upper and lower edges of the internal electrode layers 202 and 204 can be aligned vertically. For example, as shown in Figure 2B, the lateral edge of the first lead tab 2002a (extending along the Z direction 136) can be aligned with the lateral edge of the second lead tab 2004a (extending along the Z direction 136) on the opposite side of the first lead tab 2002a. In addition, such lateral edges of the lead tabs 2002a and 2004a can be aligned with the side edge 221a of the internal electrode layer 202. However, it should be understood that the lateral edges of the lead tabs 2002a and 2004a can be aligned with each other but offset from the side edge 221a. The third lead tab 2002b and the fourth lead tab 2004b can be aligned with each other, as described with respect to the first lead tab 2002a and the second lead tab 2004a.

[0136] The relationship between the lateral edge of the first lead tab at the upper edge and the lateral edge of the second lead tab at the bottom edge, as described for the internal electrode layer 202, can also be applied to the internal electrode layer 204. Such an arrangement makes it possible to form a gap between the first lead tab 2002a of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204. Furthermore, a gap may be formed between the third lead tab 2002b of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204, and another gap may be formed between the third lead tab 2002b of the first internal electrode layer 202 and the first lead tab 2002a of the second internal electrode layer 204. Similarly, a first gap may be formed between the second lead tab 2004a of the first internal electrode layer 202 and the fourth lead tab 2004b of the second internal electrode layer 204; a second gap may be formed between the fourth lead tab of the first internal electrode layer 202 and the fourth lead tab 2004b of the second internal electrode layer 204; and a third gap may be formed between the fourth lead tab 2004b of the first internal electrode layer 202 and the second lead tab 2004a of the second internal electrode layer 204. The sizes of each gap may be substantially the same, or the size of at least one gap may differ from that of the others. For example, the size of the gap between the first lead tab 2002a of the first internal electrode layer 202 and the third lead tab 2002b of the second internal electrode layer 204 can be different from the size of the gap between the third lead tab 2004a of the first internal electrode layer 202 and the third lead tab 2004a of the second internal electrode layer 204.

[0137] With respect to a given electrode layers 202 and 204, lead tabs 2002a can be arranged in parallel with lead tabs 2004a, and lead tabs 2002b can be arranged in parallel with lead tabs 2004b, so that lead tabs extending from alternating electrode layers 202 and 204 can be aligned in their respective rows. For example, lead tabs 2002a and 2004a of the internal electrode layer 202 can be arranged in their respective stacked configurations, while lead tabs 2002a and 2004a of the internal electrode layer 204 can be arranged in their respective stacked configurations. Similarly, lead tabs 2002b and 2004b of the internal electrode layer 202 can be arranged in their respective stacked configurations, while lead tabs 2002b and 2004b of the internal electrode layer 204 can be arranged in their respective stacked configurations. Therefore, in the embodiment shown in Figure 2B, the stacked electrode layers 202 and 204 can form lead tabs in each of the four rows.

[0138] It is understood that the lead tabs 2002a and 2004a of electrode layer 202 are connected to the external termination 22a, while the lead tabs 2002a and 2004a of electrode layer 204 are connected to the external termination 24a. Furthermore, the lead tabs 2002b and 2004b of electrode layer 202 are connected to the external termination 22b, while the lead tabs 2002b and 2004b of electrode layer 204 are connected to the external termination 24b. Thus, each of the lead tabs 2002a, 2004a, 2002b, and 2004b of electrode layer 202 interlocks with each of the lead tabs 2002a, 2004a, 2002b, and 2004b of electrode layer 204 in a similar manner to the external terminations 22a, 22b, 24a, and 24b. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0139] The distance between adjacent exposed lead tabs of the internal electrode layer in a given column can be specifically designed to help ensure guided formation of the terminations. The distance between exposed lead tabs of the internal electrode layer in a given column can be, for example, in the range of about 0.25 μm to about 10 μm, in some embodiments in the range of about 0.5 μm to about 5 μm, and in some embodiments in the range of about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of electrode tabs can be, but is not limited to, at least twice as large as the distance between adjacent lead tabs in a given column to ensure that individual terminations do not mix. In some embodiments, the distance between adjacent columnar stacks of exposed metallization can be about four times (4x) the distance between adjacent exposed electrode tabs in a particular stack. However, such distances can vary depending on the desired capacitance performance and circuit board configuration. For example, the distance can be approximately 0.1 mm to approximately 1.5 mm, in some embodiments approximately 0.2 mm to approximately 1.3 mm, and in some embodiments approximately 0.3 mm to approximately 1 mm, when determined based on the center point of each lead tab or the distance between adjacent lateral edges of the lead tabs. In addition, such distances can correspond to the separation distance of balls on a ball grid array.

[0140] Still referring to Figure 2B, the first electrode 206 may have a first connecting section 216-1 and a second connecting section 216-2. The first connecting section 216-1 may extend from the first base section 214-1 in the longitudinal direction 232. In particular, the first connecting section 216-1 may extend between the first base section 214-1 and the first central section 212-1, connecting the first base section 214-1 and the first central section 212-1. Similarly, the second connecting section 216-2 may extend from the second base section 214-2 in the longitudinal direction 232. In particular, the second connecting section 216-2 may extend between the second base section 214-2 and the second central section 212-2, connecting the second base section 214-2 and the second central section 212-2.

[0141] As shown in the embodiment of Figure 2B, the first connecting edge 216a of the first connecting section 216-1 extends from the first front edge 214a of the first base section 214-1 to the first edge 212a of the first central section 212-1, and the second connecting edge 216b of the first connecting section 216-1 extends from the second front edge 214b of the first base section 214-1 to the second edge 212b of the first central section 212-1. Thus, the first connecting edge 216a intersects the first front edge 214a and the first edge 212a, connecting the first base section 214-1 to the first central section 212-1 along one longitudinal side of the first electrode 206. The second connecting edge 216b intersects the second front edge 214b and the second edge 212b, connecting the first base section 214-1 to the first central section 212-1 along the other longitudinal side opposite the first electrode 206.

[0142] Furthermore, the third connecting edge 216c of the second connecting section 216-2 extends from the third front edge 214c of the second base section 214-2 to the third edge 212c of the second central section 212-2, and the fourth connecting edge 216b of the second connecting section 216-2 extends from the fourth front edge 214d of the second base section 214-2 to the fourth edge 212d of the second central section 212-2. Thus, the third connecting edge 216c intersects the third front edge 214c and the third edge 212c, connecting the second base section 214-2 to the second central section 212-2 along one longitudinal side of the first electrode 206. The fourth connecting edge 216d intersects the fourth front edge 214d and the fourth edge 212d, connecting the second base section 214-2 to the second central section 212-2 along the other longitudinal side opposite the first electrode 206.

[0143] Each connecting section 216-1, 216-2 may have a third width 231 extending, for example, in the Z direction 236. In this regard, the location of the third width 231 may be offset in the longitudinal direction 232 from the locations of the respective first width 227 and the respective second width 229. In one embodiment, the third width 231 of each connecting section 216-1, 216-2 may be smaller than the second width 229 of the respective base sections 214-1, 214-2. Also, the third width 231 of each connecting section 216-1, 216-2 may be larger than the first width 227 of the respective central sections 212-1, 212-2. In this regard, the location of the third width 231 may be between the locations of the first width 227 and the second width 229 with respect to each Y-shaped portion of the first electrode 206.

[0144] Furthermore, the third width 231 can vary within the connecting sections 216-1 and 216-2. For example, the third width 231 may have a first value at one location within each of the connecting sections 216-1 and 216-2, and a second different value at another location within each of the connecting sections 216-1 and 216-2, with the two locations within each of the connecting sections 216-1 and 216-2 spaced apart from each other along the longitudinal direction 232.

[0145] At least one portion of the first connecting edge 216a, the second connecting edge 216b, the third connecting edge 216c, or the fourth connecting edge 216d is not perpendicular to the respective edges 212a, 212b, 212c, 212d of the central section where the respective connecting edges 216a, 216b, 216c, 216d intersect. For example, in one embodiment, the first connecting edge 216a of the first connecting section 216-1 can form a first angle 241 with the first edge 212a of the first central section 212-1. Similarly, the third edge 212c of the second central section 212-2 can form a first angle 241 with the third connecting edge 216c of the second connecting section 216-2. Such an angle 241 can be greater than 90° and less than 180°. For example, such an angle 241 may be within the range described above with respect to angle 141. Although not intended to be limited by theory, such configurations can provide generally Y-shaped electrode configurations through the first base section 214-1 through the first central section 212-1 and through the second base section 214-4 through the second central section 212-2, so that the embodiments depicted include multiple Y-shapes.

[0146] Furthermore, in the embodiment shown in Figure 2B, a second angle 247 is formed between the second edge 212b and the second connecting edge 216b, and the second angle 247 is greater than 90° and less than 180°, as described above with respect to the first angle 241. Also, a second angle 247 is formed between the fourth edge 212d and the fourth connecting edge 216d, and the second angle 247 is greater than 90° and less than 180°, as described above with respect to the first angle 241. Therefore, it can be recognized that the second Y-shape of the first electrode 206 shown in Figure 2B is configured in the same way as the first Y-shape of the first electrode 206. For example, the first base section 214-1, the first connecting section 216-1, and the first central section 212-1 of the first electrode 206 define a first Y-shape, and the second base section 214-2, the second connecting section 216-2, and the second central section 212-2 of the first electrode 206 define a second Y-shape. The first and second Y-shapes of the first electrode can be generally similar to each other, or the Y-shapes can be different from each other; for example, the first angle 241 of one Y-shape of the first electrode 206 can have a different value from the first angle 241 of the other Y-shape of the first electrode 206.

[0147] Furthermore, with respect to the first electrode 206 shown in Figure 2B, at least a portion of the first connecting edge 216a is not perpendicular to the first edge 212a, and at least a portion of the second connecting edge 216b is not perpendicular to the second edge 212b. Moreover, at least a portion of the third connecting edge 216c is not perpendicular to the third edge 212c, and at least a portion of the fourth connecting edge 216d is not perpendicular to the fourth edge 212d. With respect to the depicted embodiment, it will also be understood that at least a portion of the first connecting edge 216a is not perpendicular to the first front edge 214a, at least a portion of the second connecting edge 216b is not perpendicular to the second front edge 214b, at least a portion of the third connecting edge 216c is not perpendicular to the third front edge 214c, and at least a portion of the fourth connecting edge 216d is not perpendicular to the fourth front edge 214d.

[0148] Figure 2C illustrates electrode layers 202, 204, where at least one of the first electrode 206 or the second electrode 208 has at least one portion of an edge that is not perpendicular to the intersecting edge, according to embodiments of the present disclosure. For example, at least one of the first electrode 206 or the second electrode 208 includes a rounded corner, the rounded edge of the rounded corner being not perpendicular to the intersecting edge. As described with respect to Figure 1G, “rounded” can refer to a periphery having the shape of a circular or elliptical arc, or it can refer to any suitable edge that is not precisely circular or elliptical but is curved or arched. Additionally, in some embodiments, the peripheries of the first electrode 206 and / or the second electrode 208 can be free from geometric discontinuities, for example, as described above with respect to the embodiment of Figure 1G. The rounded corner configuration makes it possible to reduce the concentration of electric fields and charges at the corners and / or along the edges of electrodes 206, 208 adjacent to the corners, which makes it possible to increase the dielectric breakdown voltage of the capacitor incorporating electrode layers 202, 204 compared to conventional electrode configurations.

[0149] Electrode layers 202 and 204 can be configured similarly to the electrode layers 202 and 204 described with respect to Figure 2B, but have curved or rounded connection edges 216a, 216b, 216c, and 216d of their respective connection sections 216-1 and 216-2, rather than linear connection edges 216a, 216b, 216c, and 216d as shown in Figure 2B. For example, as shown in Figure 2C, the first connecting edge 216a defines a first rounded corner having a first radius r1, the second connecting edge 216b defines a second rounded corner having a second radius r2, the third connecting edge 216c defines a third rounded corner having a third radius r3, and the fourth connecting edge 216d defines a fourth rounded corner having a fourth radius r4. Therefore, at least a portion of the connecting edges 216a, 216b, 216c, and 216d is not perpendicular to the respective edges 212a, 212b, 212c, and 212d that are intersected by each of the connecting edges.

[0150] Furthermore, in the embodiment shown in Figure 2C, the first electrode 206 defines an additional rounded corner, and the second electrode 208 also includes a rounded corner. For example, the first electrode 206 defines a fifth rounded corner and a sixth rounded corner between the first central section 212-1 and the second base section 214-2, the rounded corners having radii r5 and r6, respectively. The second electrode 208 defines a seventh rounded corner with radius r7 and an eighth rounded corner with radius r8, the seventh and eighth rounded corners defined at the intersection of the edges of the second electrode 208 closest to the first electrode 206.

[0151] It will be recognized that the radii of the various rounded corners in electrode layers 202 and 204 can be the same, or at least one radius can be different from the others. For example, as shown in Figure 2C, the seventh radius r7 and the eighth radius r8 of the second electrode 208 can be equal to each other, but not equal to any of the first radius r1, the second radius r2, the third radius r3, the fourth radius r4, the fifth radius r5, and / or the sixth radius r6 of the first electrode 206 (they can be equal to each other, but different from the seventh and eighth radii r7 and r8).

[0152] As further shown in Figure 2C, a central end gap distance 233 can be formed longitudinally 232 between the longitudinal end of the second central section 212-2 of the first electrode 206 and the longitudinal end of the base section 214 of the second electrode 208. Thus, in one embodiment, the ratio of the central end gap distance 233 to the capacitor length 25 (Figure 2A) can be 0.01 or greater, for example 0.05 or greater, for example 0.1 or greater, for example 0.2 or greater, for example 0.3 or greater, for example 0.4 or greater, etc. The ratio can be, for example 0.5 or less, for example 0.4 or less, for example 0.3 or less, for example 0.2 or less, for example 0.1 or less, etc.

[0153] Other modifications and / or combinations are possible within the scope of this disclosure. For example, the first electrode 206 may have a generally Y-shaped configuration and one or more curved or rounded connecting edges 216a, 216b, 216c, 216d. In electrodes 206, 208 on various electrode layers 202, 204, it is possible to use a different number and / or configuration of connecting edges that are not perpendicular to the edges of the respective central sections, i.e., one or more electrode layers 202, 204 may have electrodes 206, 208 having a different connecting edge configuration than at least one other electrode layer 202, 204.

[0154] As further shown in Figures 2B and 2C, the respective leading edges 214a, 214b, 214c, and 214d of the base sections 214-1 and 214-2 of the first electrode 206 can also have a specific length 235 extending in the longitudinal direction 232. Generally, such a length 235 of each base section can be defined as the distance between the vertical edges 221a and 221b and the point of transition between the respective base sections 214-1 and 214-2 and the respective connecting sections 216-1 and 216-2. For example, the leading edges 214a, 214b, 214c, and 214d can each generally have a slope of 0°, and the point where the slope changes can be considered the aforementioned point of transition. Nevertheless, such length 235 can be 0.05 or more of the capacitor length 25 (Figure 2A) as defined herein, for example, 0.1 or more, for example, 0.15 or more, for example, 0.2 or more, for example, 0.3 or more, etc. Such length 235 can be 0.5 or less of the capacitor length 25, for example, 0.4 or less, for example, 0.3 or less, for example, 0.25 or less, for example, 0.2 or less, for example, 0.15 or less, etc.

[0155] As also illustrated in Figure 2C, the base section 214 of the second electrode 208 may also have a specific length 245 extending in the longitudinal direction 232. Such a length may be 0.05 or more of the capacitor length 25, for example, 0.1 or more, for example, 0.15 or more, for example, 0.2 or more, for example, 0.3 or more, etc. Such a length 245 may be 0.5 or less of the capacitor length 25, for example, 0.4 or less, for example, 0.3 or less, for example, 0.25 or less, for example, 0.2 or less, for example, 0.15 or less, etc.

[0156] In one embodiment, the lengths 235 and 245 described above can be different. In one particular embodiment, the lengths 235 and 245 described above can be substantially the same. Furthermore, the length 235 of the first base section 214-1 may be the same as or different from the length 235 of the second base section 214-2.

[0157] Furthermore, referring to Figure 2A, the first end outer termination 22a may have a first transverse edge 222. The first transverse edge 222 may extend in the Z direction 236 and / or transverse direction 234. The first transverse edge 222 of the first outer termination 22a may substantially align in the longitudinal direction with the vertical edge 230 (Figures 2B, 2C) of the first base section 214-1 of the first electrode 206. Such a vertical edge 230 may be located where the end of the first base section 214-1 and the first connecting section 216-1 begin. For example, the first lateral edge 222 of the first end outer terminal 22a can be within 5%, for example, 4%, for example, 3%, for example, 2%, for example, 1%, for example, 0.8%, for example, 0.6%, for example, 0.5%, for example, 0.4%, for example, 0.3%, for example, 0.2%, for example, 0.1% in the longitudinal direction of the first base section 214-1 of the first electrode 206, based on the length 235 of the first base section 214-1 of the first electrode 206.

[0158] Similarly, the second end outer termination 24a may have a second lateral edge 224 (Figure 2A). The second lateral edge 224 may extend in the Z direction 236 and / or the lateral direction 234. The second lateral edge 224 of the second outer termination 24a may substantially align in the longitudinal direction with the vertical edge 230 of the first base section 214-1 of the first electrode 206. Such a lateral edge 224 may be located where the end of the first base section 214-1 and the first connecting section 216-1 begin. For example, the second lateral edge 224 of the second end outer terminal 24a can be within 5%, for example, within 4%, for example, within 3%, for example, within 2%, for example, within 1%, for example, within 0.8%, for example, within 0.6%, for example, within 0.5%, for example, within 0.4%, for example, within 0.3%, for example, within 0.2%, for example, within 0.1% in the longitudinal direction of the vertical edge 230 of the first base section 214-1 of the first electrode 206, based on the length 235 of the first base section 214-1 of the first electrode 206.

[0159] It is recognized that the first lateral edge 222 of the first end outer termination 22a can be aligned with the vertical edge 230 of the first electrode 206 of the electrode layer 202 or electrode layer 204, while the second lateral edge 224 of the second end outer termination 24a can be aligned with the vertical edge 230 of the other first electrode 206 of the electrode layer 202 or electrode layer 204.

[0160] In addition, the first lateral edge 222 of the first end outer termination 22a can substantially align with the lateral edge 226 (Figure 2C) of the base section 214 of the second electrode 208 of the electrode layer 202, while the second lateral edge 224 of the second end outer termination 24a can substantially align with the lateral edge (not shown) of the base section 214 of the second electrode 208 of the electrode layer 204. For example, the respective lateral edges 222, 224 of the respective end outer terminals 22a, 24a can be within 5%, for example, 4%, for example, 3%, for example, 2%, for example, 1%, for example, 0.8%, for example, 0.6%, for example, 0.5%, for example, 0.4%, for example, 0.3%, for example, 0.2%, for example, 0.1% in the longitudinal direction of the respective lateral edges of the base section 214 of the second electrode 208, based on the length 245 of the base section 214 of the second electrode 208.

[0161] As shown herein, the dielectric and electrode layers of the capacitor 20 can be stacked to form a set of alternating layers. For example, the electrode layers can be interleaved in a manner in which the dielectric layers are positioned between each electrode layer, with a gap between them, and any number of dielectric and electrode layers can be included in each stack as described herein. Furthermore, as described elsewhere herein, one, two, three, four, or more sets of stacked alternating dielectric and electrode layers can be arranged within a single capacitor body. The capacitor 20 includes a single set of dielectric and electrode layers to form the capacitor body 26, but the capacitor body can include additional sets of stacked layers, as described with reference to Figures 3A to 5B, for example.

[0162] Referring here to Figures 3A to 7, in embodiments including multiple stacks of alternating dielectric and electrode layers arranged within a single capacitor body, each set of alternating dielectric and internal electrode layers defines a capacitive element. Each set of alternating dielectric and electrode layers includes dielectric layers arranged alternately with electrode layers. In particular, the electrode layers include a first electrode layer and a second electrode layer interleaved in a relationship of opposing and spaced apart, with the dielectric layers positioned between each electrode layer. In at least some embodiments, the first and second electrode layers can be configured as described above with respect to the first and second electrode layers 102, 104 of capacitor 10 and / or the first and second electrode layers 202, 204 of capacitor 20. For example, each capacitive element within a single capacitor body can include a stack of the first and second electrode layers 102, 104 or the first and second electrode layers 202, 204.

[0163] The specific arrangement of capacitive elements within a single, integrated package (i.e., a single body) can offer several advantages. For example, such capacitors can be mounted on a circuit board as surface-mount capacitors, providing a smaller footprint on the circuit board. This can also enable a reduction in the size of the circuit board.

[0164] One obvious advantage of capacitors and configurations that utilize multiple capacitive elements within a single body, compared to using multiple individual multilayer ceramic capacitors, is related to direct power-to-ground connection. As illustrated in Figure 6, such a capacitor 608 (having multiple capacitive elements within a single body) can be mounted (e.g., surface-mounted) on a circuit board 606 which includes a substrate (e.g., an insulating layer) having an upper and lower surface. The circuit board 606 has multiple defined current paths therein (not shown). The external terminations of the capacitor 608 are electrically in communication with each of the predetermined current paths of the circuit board 606. In addition, the external terminations of the capacitor 608 can be physically connected to the circuit board 606 using any method commonly known in the art, such as general soldering techniques.

[0165] As illustrated in Figure 6, the integrated circuit package 602 can also be provided on a circuit board 606. The integrated circuit package 602 can be connected to the circuit board 606 using a ball grid array 604. The circuit board may further include a processor 600. The processor 600 can similarly be connected to the integrated circuit package 602 using a ball grid array 612.

[0166] Generally, the ball grid array 604 can be configured such that the pitch is 1.5 mm or less, for example 1.25 mm or less, for example 1 mm or less, for example 0.8 mm or less, for example 0.6 mm or less, and 0.4 mm or more, for example 0.5 mm or more, for example 0.6 mm or more.

[0167] In addition, the integrated circuit package 602 can also be connected to the circuit board 606 using a capacitor 608 as defined herein. In this regard, the internal electrode layers of the capacitor 608 can be positioned so that they are orthogonal to the horizontal plane of the circuit board 606 and the integrated circuit package 602. In other words, the internal electrode layers of the capacitor 608 can be positioned so that they are substantially non-parallel to the circuit board 606. For example, the capacitor 608 can be positioned between the integrated circuit package 602 and the circuit board 606, so that the capacitor 608 is "sandwiched" between the two components. In this regard, the capacitor 608 is directly connected to the integrated circuit package 602 and the circuit board 606. For example, the capacitor 608 can be connected (e.g., physically and / or electrically) to the circuit board 606 and / or the circuit package 602 using any method commonly known in the art, such as a general soldering technique.

[0168] By using the capacitor in the configuration described above, the capacitor 608 can be made to remove some of the original ball grid array 604. However, the capacitor 608 can still be surrounded by the ball grid array 604, as illustrated in Figure 6.

[0169] Therefore, as shown in Figure 6, the capacitor 608 of the present invention can be directly connected to the integrated circuit package 602 and the circuit board 606 (for example, a printed circuit board). This direct connection allows current 610 to flow through the capacitor, thereby providing a direct power-to-ground connection.

[0170] On the other hand, a prior art circuit board 706 is illustrated in Figure 7. The circuit board 706 includes a processor 700, an integrated circuit package 702, and ball grid arrays 704 and 712. However, instead of using a single integrated capacitor package like the capacitor 608 in Figure 6, the circuit board 706 in Figure 7 uses multiple individual multilayer ceramic capacitors 708.

[0171] This configuration, using a single integrated capacitor, can enable various advantages and benefits compared to a circuit board using multiple individual multilayer ceramic capacitors. One obvious advantage of the capacitor and configuration of the present invention compared to using multiple individual multilayer ceramic capacitors is related to a direct power-to-ground connection, as shown in Figure 6, where the capacitor of the present invention is directly connected to the integrated circuit package 602 and the circuit board 606. When multiple individual capacitors are provided, as in the prior art as shown in Figure 7, a particular multilayer capacitor 708 cannot make a direct connection to the circuit board 706 and the integrated circuit package 702 for various reasons, including slight differences in height. Due to such uniformity issues, it can be difficult to use multiple individual multilayer capacitors to make a connection. As a result, as illustrated in Figure 7, there are two current paths: (1) current 714 between the processor 700 and the individual capacitor 708, and (2) current 716 between the processor 700 and the circuit board 706. In such a configuration, a direct power-to-ground connection cannot be obtained.

[0172] In addition to the above, although not illustrated herein, in one embodiment the integrated circuit package itself can include a multilayer capacitor. In this regard, the capacitor can be directly embedded within the package. Such incorporation of the capacitor can allow for size reduction, which may be beneficial for a variety of electronic applications.

[0173] Referring here to Figures 3A to 5B, various embodiments of a capacitor having multiple capacitive elements will be described. Figures 3A and 3B respectively illustrate a capacitor 30 in a 2x2 configuration. That is, the capacitor 30 includes two terminations along the respective dimensions of the upper surface 38a and the bottom surface 38b. In this respect, the capacitor 30 includes a total of four external terminations 32, 34 on the upper surface and four corresponding external terminations (not shown) on the bottom surface, with the external terminations on the upper surface being electrically connected to the corresponding external terminations on the bottom surface. In the embodiment of Figure 3A, the external terminations 32, 34 are spaced apart from both the end surfaces 38c, 38d and the side surfaces 38e, 38f of the capacitor 38. In the embodiment of Figure 3B, the external terminations 32, 34 are spaced apart from the side surfaces 38e, 38f of the capacitor 38 but extend along the end surfaces 38c, 38d.

[0174] The capacitor 30 in Figures 3A and 3B includes two sets 350 of alternating dielectric layers and internal electrode layers, as illustrated in Figure 3C. Each set 350 of alternating dielectric layers and internal electrode layers includes internal electrode layers 102, 104 and dielectric layers (not shown) in an alternating arrangement. The sets 350 of alternating dielectric layers and internal electrode layers are spaced apart from each other by a spacing distance t. For example, the spacing distance t can be defined between the first set 350a and the second set 350b of alternating dielectric layers and internal electrode layers.

[0175] The spacing distance t between sets can be approximately 0.2 μm to approximately 10 μm, in some embodiments approximately 0.5 μm to approximately 8 μm, and in some embodiments approximately 1 μm to approximately 5 μm. Additionally, the spacing distance t can be at least twice the distance between adjacent lead tabs in a given column, in some embodiments at least approximately three times, and in some embodiments approximately four to eight times, in order to ensure that individual ends do not mix.

[0176] Generally, the electrode layers 102 and 104 are configured as described with respect to Figure 1F. However, the electrode layers 102 and 104 can also be configured as described with respect to other embodiments of the capacitor 10. For example, when the external terminations 32 and 34 extend along the ends 38c and 38d of the capacitor 30 (as well as the upper surface 38a and the bottom surface 38b), the internal electrode layers 102 and 104 can be configured as in Figures 1C, 1D, or 1G, and in particular have a second electrode 108 to assist in the formation of the external terminations 32 and 34 along the end surfaces 38c and 38d. Furthermore, with respect to an embodiment of the capacitor 30 as shown in Figure 3A, it will be recognized that the base sections 114 of the electrode layers 102 and 104 can be positioned at a distance from the end surfaces 38c and 38d of the capacitor 30, for example, the dielectric material can be arranged along the leading edge (extending along the Z direction) of the base section 114 to define the entire end surfaces 38c and 38d of the capacitor 30.

[0177] As illustrated in Figures 3A to 3C, the capacitor 30 includes four external terminations on each surface. However, as stated above, the present invention is not limited by the number of external terminations.

[0178] For example, Figure 4A illustrates a capacitor 40 having a 2x4 configuration. That is, the capacitor 40 includes two terminations along one dimension of the upper surface 48a and the bottom surface 48b, and four terminations along the other dimension. In this respect, the capacitor 40 includes a total of eight external terminations 42a, 42b, 44a, and 44b on the upper surface 48a, and eight corresponding external terminations (not shown) on the bottom surface 48b, with the external terminations on the upper surface 48a being electrically connected to the corresponding external terminations 42a, 42b, 44a, and 44b on the bottom surface 48b.

[0179] Although not shown in the figure, it will be recognized that the capacitor 40 can also be configured to have end external terminations 42a, 44b extending along the end surfaces 48c, 48d. That is, similar to the capacitor 30 shown in Figure 3B, the external terminations 42a, 44b adjacent to the end surfaces 48c, 48d can extend along the end surfaces 48c, 48d as well as the upper surface 48a and the bottom surface 48b. In such an embodiment, the leading edge of the first base section 214-1 (extending along the Z direction) is positioned on the end surfaces 48c, 48d (rather than being spaced away from them), and the first base section 214-1 along its leading edge can assist in the formation of the external termination along the end surfaces 48c, 48d.

[0180] The capacitor 40 in Figure 4A includes two sets 450 of alternating dielectric layers and internal electrode layers, as illustrated in Figure 4B. Each set 450 of alternating dielectric layers and internal electrode layers includes internal electrode layers 202, 204 and dielectric layers (not shown) in an alternating arrangement. The sets 450 of alternating dielectric layers and internal electrode layers are spaced apart from each other by a spacing distance t. For example, the spacing distance t can be defined between the first set 450a and the second set 450b of alternating dielectric layers and internal electrode layers.

[0181] The spacing distance t between sets can be approximately 0.2 μm to approximately 10 μm, in some embodiments approximately 0.5 μm to approximately 8 μm, and in some embodiments approximately 1 μm to approximately 5 μm. Additionally, the spacing distance t can be at least twice the distance between adjacent lead tabs in a given column, in some embodiments at least approximately three times, and in some embodiments approximately four to eight times, in order to ensure that individual ends do not mix.

[0182] Generally, the electrode layers 202 and 204 are configured as described with respect to Figure 2B. However, the electrode layers 202 and 204 can also be configured as described with respect to other embodiments of the capacitor 20. For example, when the external terminations 42a and 44b extend along the ends 48c and 48d of the capacitor 40 (as well as the upper surface 48a and the bottom surface 48b), the internal electrode layers 202 and 204 can be configured as in Figure 2C, and in particular have a second electrode 208 to assist in the formation of the external terminations 42a and 44b along the end surfaces 48c and 48d. Furthermore, with respect to an embodiment of the capacitor 40 as shown in Figure 4A, it will be recognized that the first base section 214-1 of the electrode layers 202, 204 can be positioned at a distance from the end surfaces 48c, 48d of the capacitor 40, for example, the dielectric material can be arranged along the leading edge (extending along the Z direction) of the first base section 214-1 to define the entire end surfaces 48c, 48d of the capacitor 40.

[0183] As another example of a different number of external terminations, Figure 5A illustrates a capacitor 50 having a 4x4 configuration. That is, the capacitor 50 includes four terminations along one dimension of the top surface 58a and bottom surface 58b, and four terminations along the other dimension. In this respect, the capacitor 50 includes a total of 16 external terminations 52a, 52b, 54a, 54b on the top surface 58a and 16 corresponding external terminations (not shown) on the bottom surface 58b, with the external terminations on the top surface 58a being electrically connected to the corresponding external terminations 52a, 52b, 54a, 54b on the bottom surface 58b.

[0184] Although not shown in the figure, it will be recognized that the capacitor 50 can also be configured to have end external terminations 52a, 54b extending along the end surfaces 58c, 58d. That is, similar to the capacitor 30 shown in Figure 3B, the external terminations 52a, 54b adjacent to the end surfaces 58c, 58d can extend along the end surfaces 58c, 58d as well as the upper surface 58a and the bottom surface 58b. In such an embodiment, the leading edge of the first base section 214-1 (extending along the Z direction) is positioned on the end surfaces 58c, 58d (rather than being spaced away from them), and the first base section 214-1 along its leading edge can assist in the formation of the external termination along the end surfaces 58c, 58d.

[0185] The capacitor 50 in Figure 5A includes four sets 550 of alternating dielectric layers and internal electrode layers, as illustrated in Figure 5B. Each set 550 of alternating dielectric layers and internal electrode layers includes internal electrode layers 202, 204 and dielectric layers (not shown) in an alternating arrangement. The sets 550 of alternating dielectric layers and internal electrode layers are spaced apart from each other by a spacing distance t, which may be the same or different between each set 550. For example, a first spacing distance t1 can be defined between a first set 550a and a second set 550b, a second spacing distance t2 can be defined between a second set 550b and a third set 550c, and a third spacing distance t3 can be defined between a third set 550c and a fourth set 550d. The first interval distance t1 can be the same as the second interval distance t2 and / or the third interval distance t3, for example, at least one of the first interval distance t1, the second interval distance t2, and the third interval distance t3 is different from the other interval distances t1, t2, and t3.

[0186] Similar to the embodiments discussed above, the spacing distances "t1", "t2", and / or "t3" between sets can be from about 0.2 μm to about 10 μm, from about 0.5 μm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. Additionally, the spacing distances "t1", "t2", and / or "t3" can be at least twice the distance between adjacent lead tabs in a given column, from at least about three times, and in some embodiments from about four times to about eight times, to ensure that individual ends do not mix.

[0187] Generally, the electrode layers 202 and 204 are configured as described with respect to Figure 2B. However, the electrode layers 202 and 204 can also be configured as described with respect to other embodiments of the capacitor 20. For example, when the external terminations 52a and 54b extend along the ends 58c and 58d of the capacitor 50 (as well as the upper surface 58a and the bottom surface 58b), the internal electrode layers 202 and 204 can be configured as in Figure 2C, and in particular have a second electrode 208 to assist in the formation of the external terminations 52a and 54b along the end surfaces 58c and 58d. Furthermore, with respect to an embodiment of the capacitor 50 as shown in Figure 5A, it will be recognized that the first base section 214-1 of the electrode layers 202, 204 can be positioned at a distance from the end surfaces 58c, 58d of the capacitor 50, for example, the dielectric material can be arranged along the leading edge (extending along the Z direction) of the first base section 214-1 to define the entire end surfaces 58c, 58d of the capacitor 50.

[0188] Capacitors 30, 40, and 50 each include at least one first polarity terminal and at least one second and opposite polarity terminal on their upper surface, and at least one first polarity terminal and at least one second and opposite polarity terminal on their bottom surface. For example, Figure 3A includes two positive terminals 32 and two negative terminals 34 on the upper surface 38a.

[0189] Generally, similar polarity terminations on the bottom surface of a capacitor, corresponding to a particular set of alternating dielectric and internal electrode layers, are electrically connected to similar polarity terminations on the top surface of the capacitor. Similar polarity terminations positioned on the top and bottom surfaces of the capacitor do not necessarily have to mesh with each other. In this regard, corresponding similar polarity terminations on the top and bottom surfaces may not be offset by their termination position, but instead may be positioned directly above or below another similar polarity termination on the opposite top or bottom surface. In other words, corresponding similar polarity terminations, corresponding to a particular set of alternating dielectric and internal electrode layers, can be substantially aligned. The substantial alignment means that the offset from the side edge of one lateral edge of a polarity end on the upper surface is within + / -10% of the offset from the side edge of the corresponding polarity end on the bottom surface, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%.

[0190] Furthermore, the pitch of the external terminations (i.e., the nominal distance between centers, also called the center-to-center spacing) can generally be determined by a particular circuit board configuration. The pitch between external terminations in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch between adjacent external terminations in the other direction (i.e., the y-direction or the x-direction, respectively). In other words, the pitch between any two adjacent external terminations can be substantially the same as the pitch between any other two adjacent external terminations.

[0191] The pitch can be approximately 0.1 mm or more, for example, approximately 0.2 mm or more, for example, approximately 0.3 mm or more, for example, 0.4 mm or more, for example, approximately 0.5 mm or more, for example, approximately 0.6 mm or more, for example, approximately 0.7 mm or more, for example, approximately 0.8 mm or more, for example, approximately 0.9 mm or more, for example, approximately 1.0 mm or more. The pitch can be approximately 2.0 mm or less, for example, approximately 1.5 mm or less, for example, approximately 1.4 mm or less, for example, approximately 1.3 mm or less, for example, approximately 1.2 mm or less, for example, approximately 1.1 mm or less, for example, approximately 1.0 mm or less. For example, the pitch can be approximately 0.2 mm, approximately 0.4 mm, approximately 0.6 mm, approximately 0.8 mm, approximately 1.0 mm, approximately 1.2 mm, etc. In particular, the pitch can be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch can be about 0.6 mm, for example, 0.6 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc. In another embodiment, the pitch can be about 0.8 mm, for example, 0.8 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc. In a further embodiment, the pitch can be about 1 mm, for example, 1 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc.

[0192] In addition, the external terminations can be positioned in a manner similar to that of the ball grid array. For example, the external terminations can be provided to make contact as is typically used by the ball grid array (particularly the surrounding ball grid array). In this regard, the pitch of the external terminations can be the same as the pitch of the surrounding ball grid array. That is, the pitch can be within 10% of the pitch of the surrounding ball grid array, for example, within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc.

[0193] In addition, as in a ball grid array, the external terminations can be provided in rows and columns. That is, the external terminations can be provided such that they exist in at least two rows and at least two columns. For example, the external terminations can be provided in at least two rows, for example, at least three rows, etc., for example, at least four rows, etc. The number of rows can be determined by the number of different sets of alternating dielectric layers and internal electrode layers. In addition, the external terminations can be provided in at least two columns, for example, at least three columns, etc., for example, at least four columns, etc. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0194] The capacitors in Figures 3A to 5B use sets of alternating dielectric layers and internal electrode layers 102, 104 or 202, 204, but it should be understood that other configurations are also possible. For example, a set 350 of alternating dielectric layers and internal electrode layers 102, 104 (for example, in any of Figures 1C to 1G) can also be used in capacitors similar to capacitors 40 and 50 in Figures 4A to 5B. In this regard, rather than using only two sets 350 of alternating dielectric layers and internal electrode layers in capacitor 30 in Figures 3A to 3C, the capacitor can use up to eight sets 350 of alternating dielectric layers and internal electrode layers 102, 104. For example, capacitor 30 can use two to eight sets 350 of alternating dielectric layers and internal electrode layers.

[0195] Additionally, the embodiment shown in the figure uses only four internal electrode layers per set of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention can and is not necessarily limited to including any number of internal electrode layers per set.

[0196] Generally, the present invention provides a capacitor having a unique configuration that offers various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and can be any materials commonly used in the art, and can be formed using any methods commonly used in the art.

[0197] Accordingly, Figures 3A to 5B provide various exemplary arrangements of multiple capacitive elements in a single integrated package (i.e., a single body). For example, capacitors 30 and 40 each contain two capacitive elements, while capacitor 50 contains four capacitive elements. However, as described herein, it is possible to include different numbers of capacitive elements in a single capacitive body, such as two, three, four, five, six, or more capacitive elements.

[0198] As discussed earlier and described herein, the arrangement of multiple capacitive elements within a single integrated package or single body can offer several advantages. For example, such capacitors can be mounted on a circuit board as surface-mount capacitors, providing a smaller footprint on the circuit board, which can also enable a reduction in the size of the circuit board. Furthermore, another advantage of capacitors and configurations that utilize multiple capacitive elements within a single body (compared to, for example, using multiple individual multilayer ceramic capacitors) is a direct power-to-ground connection, where the capacitor can be directly connected to the integrated circuit package and the circuit board, which allows current to flow through the capacitor and provides a direct power-to-ground connection.

[0199] In the embodiments described herein, the internal electrode layer is generally oriented in a vertical configuration. Naturally, this is not always necessary, and it is equally appropriate to use other geometric configurations (e.g., a horizontal configuration).

[0200] The disclosed capacitors can be used in a variety of applications. For example, these applications can include communications-related applications. These can include 5G, mobile devices, devices requiring high-frequency communications, base stations, and V2X (vehicle-to-everything technology). These applications can also include powertrains, safety equipment, and ADA (Advanced Driver-Assistance Systems).

[0201] Examples A multilayer capacitor as defined herein was manufactured according to the specifications disclosed herein. In particular, a 2×4 multilayer capacitor was manufactured, comprising two sets of alternating dielectric and internal electrode layers. Each internal electrode layer included two lead tabs extending from the upper edge and two lead tabs extending from the bottom edge. The capacitor included eight external terminations on the upper surface and eight external terminations on the bottom surface, with four external terminations on each surface having a first polarity and the remaining four external terminations on each surface having a second and opposite polarity. The capacitor contained approximately 300 active internal electrode layers, each layer positioned approximately 4 microns apart from adjacent internal electrode layers in the set.

[0202] [Table 1]

[0203] Test method A test assembly can be used to test the performance characteristics of a capacitor (e.g., equivalent series resistance) according to an aspect of this disclosure. For example, the capacitor can be mounted on a test board. The input and output lines can be connected to the test board, respectively. The test board can include microstrip lines (or test traces) that electrically connect the input and output lines to the respective external terminations of the capacitor. The test traces can be spaced at intervals of only about 0.432 mm (0.017 inches) or about 0.610 mm (0.024 inches).

[0204] The input signal can be applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 series source measure unit (SMU), e.g., a Keithley 2410-C SMU), and the resulting capacitor output signal can be measured on the output line (e.g., using a source signal generator). The equivalent series resistance can be determined over a frequency range of 1 GHz to 10 GHz. This test method can be repeated for multiple capacitors of the same design and nominal dimensions.

[0205] These and other modifications and variations of the present invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the aspects of the various embodiments can be interchanged, both in whole and in part. Furthermore, those skilled in the art will understand that the foregoing description is merely illustrative and not intended to limit the invention, and that the invention is further described in such appended claims. [Explanation of Symbols]

[0206] 10 Multilayer Capacitors 11 Mounting surface 12 First external termination 13 Capacitor length 14. Second external termination 15 Capacitor length 16 Capacitor body 18a Upper surface 18b Bottom surface 18c end surface 18d end surface 18e Side surface 18f Side surface 20 multilayer capacitors 22a First external termination 22b Third external termination 24a Second external termination 24b Fourth external termination 25 Capacitor length 26 Capacitor body 28a Upper surface 28b Bottom surface 28c end surface 28d end surface 28e Side surface 28f Side surface 30 multilayer capacitors 32 external termination 34 External termination 38a Upper surface 38b Bottom surface 38c end surface 38d end surface 38e Side surface 38f Side surface 39 External termination gap distance 40 multilayer capacitors 42a external termination 42b external termination 44a external termination 44b external termination 48a Upper surface 48b Bottom surface 48c end surface 48d end surface 48e Side surface 48f Side surface 50 multilayer capacitors 52a external termination 52b external termination 54a external termination 54b external termination 58a Upper surface 58b Bottom surface 58c end surface 58d end surface 58e Side surface 58f Side surface 102 First electrode layer 104 Second electrode layer 106 First electrode 108 Second electrode 112 Central Section 112a First edge 112b Second edge 114 Base Section 114a First leading edge 114b Second leading edge 116 Connection Section 116a First connecting edge 116b Second connecting edge 121 Vertical edge 122 First lateral edge 123 Vertical Edge 124 Second lateral edge 126 Lateral edge 127 First width 128 Lateral edge 129 The second width 130 Vertical Edge 130a First lateral edge portion 130b Second lateral edge portion 131 The third width 132 Longitudinal direction 133 Center end gap distance 134 Horizontal 135 Length 136 Z direction 141 First angle 143 angle 145 Length 147 Second Angle 202 First electrode layer 204 Second electrode layer 206 First electrode 208 Second electrode 212 Central Section 212-1 First Central Section 212-2 Second Central Section 212a First edge 212b Second edge 212c Third edge 212d Fourth edge 214 Base Section 214-1 First base section 214-2 Second base section 214a First leading edge 214b Second leading edge 214c Third leading edge 214d Fourth leading edge 216 Connection Section 216-1 First Connection Section 216-2 Second Connection Section 216a First connecting edge 216b Second connecting edge 216c Third connecting edge 216d Fourth connecting edge 221a First vertical edge 221b Second vertical edge 222 First lateral edge 223 Vertical Edge 224 Second lateral edge 226 Lateral edge 227 First width 229 Second width 230 Vertical Edge 231 The third width 232 Longitudinal direction 233 Center end gap distance 234 Horizontal 235 Length 236 Z direction 241 First angle 245 Length 247 Second angle 350 sets 350a First set 350b Second set 450 sets 450a First set 450b Second set 550 sets 550a First set 550b Second set 550c 3rd set 550d 4th set 600 Processors 602 Integrated Circuit Package 604 Ball Grid Array 606 Circuit Board 608 Capacitor 610 Current 612 Ball Grid Array 700 processor 702 Integrated Circuit Package 704 Ball Grid Array 706 Circuit Board 708 Multilayer Ceramic Capacitor 712 Ball Grid Array 714 Current 716 Current 1002 Lead Tab 1004 Lead Tab 2002a First lead tab 2002b Third lead tab 2004a Second lead tab 2004b Fourth lead tab BL end length BLA End Length BLB End Length BW End width r1 is the first radius r² Second radius r3 Third radius r4, the fourth radius r5 Fifth radius r6, the sixth radius r7, the seventh radius r8 is the eighth radius t interval distance t1 First interval distance t2 Second interval distance t3 Third interval distance

Claims

1. A multilayer capacitor having a first end and a second end, wherein the second end is spaced apart from the first end in a longitudinal direction perpendicular to the transverse direction, and the transverse and longitudinal directions are perpendicular to the Z direction, and the multilayer capacitor is, The main body comprises an upper surface and a bottom surface facing the upper surface along the Z direction, and the main body includes alternating dielectric layers and electrode layers, the electrode layers include a first electrode layer and a second electrode layer, and each electrode layer is A first electrode having a base section, a connecting section, and a central section, The first connecting edge of the connecting section extends from the first front edge of the base section to the first edge of the central section, and The second connecting edge of the connecting section extends from the second front edge of the base section to the second edge of the central section. The main body, A plurality of external ends, including a first external end disposed on at least one of the upper surface or the bottom surface, and a second external end disposed on at least one of the upper surface or the bottom surface. Includes, The first external termination is electrically connected to the first electrode layer along at least one of the first or second leading edges of the first electrode of the first electrode of the first electrode layer. The second external termination is electrically connected to the second electrode layer along at least one of the first or second leading edges of the first electrode of the second electrode layer. A multilayer capacitor in which at least one portion of the first or second connection edge of the first electrode of the electrode layer is not perpendicular to the respective first or second edge of the central section of the first electrode.

2. The multilayer capacitor according to claim 1, wherein the first connecting edge of the connecting section forms a first angle greater than 90° and less than 180° with the first edge of the central section.

3. The multilayer capacitor according to claim 2, wherein the first angle is between 100° and 160°.

4. The multilayer capacitor according to claim 1, wherein the first connection edge of the connection section is a linear edge.

5. The multilayer capacitor according to claim 1, wherein the first connection edge of the connection section is a curved edge.

6. The multilayer capacitor according to claim 1, wherein the second connecting edge of the connecting section forms a second angle greater than 90° and less than 180° with the second edge of the central section.

7. The multilayer capacitor according to claim 6, wherein the second angle is between 100° and 160°.

8. The multilayer capacitor according to claim 1, wherein the second connection edge of the connection section is a linear edge.

9. The multilayer capacitor according to claim 1, wherein the second connection edge of the connection section is a curved edge.

10. The multilayer capacitor according to claim 1, wherein the base section of the first electrode has a vertical edge extending in the Z direction and a length extending in the longitudinal direction, and the first outer end has a first lateral edge extending in the lateral direction, the first lateral edge of the first outer end is within 5% of the vertical edge of the base section based on the length of the base section.

11. The multilayer capacitor according to claim 1, wherein the base section includes a first vertical edge, the first vertical edge of the base section forming a second angle greater than 90° and less than 180° with the first connecting edge of the connecting section.

12. The multilayer capacitor according to claim 11, wherein the second angle is between 100° and 160°.

13. The multilayer capacitor according to claim 1, wherein the base section includes a second vertical edge, and the first vertical edge of the base section forms a second angle greater than 90° and less than 180° with the second connecting edge of the connecting section.

14. The multilayer capacitor according to claim 13, wherein the second angle is between 100° and 160°.

15. The multilayer capacitor according to claim 1, wherein the main body portion has a length in the longitudinal direction between the first end and the second end of the multilayer capacitor, the first external termination portion has a first lateral edge portion, the second external termination portion has a second lateral edge portion, the second lateral edge portion is offset from the first lateral edge portion in the longitudinal direction by an external termination gap distance, and the ratio of the length of the main body portion to the external termination gap distance is 0.2 to 0.

8.

16. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is symmetrical in the transverse direction with respect to a longitudinal center line extending in the longitudinal direction.

17. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is symmetrical in the Z direction with respect to a lateral center line extending in the lateral direction.

18. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is configured to be mounted on a mounting surface, and the electrode layer is perpendicular to the mounting surface.

19. The multilayer capacitor according to claim 1, wherein each electrode layer further includes a second electrode that lies coplanar with the first electrode.

20. The multilayer capacitor according to claim 19, wherein the central end gap distance is formed in the longitudinal direction between the central section of the first electrode and the base section of the second electrode.

21. The multilayer capacitor according to claim 20, wherein the central end gap distance is 2% to 40% of the length of the main body of the capacitor.

22. The multilayer capacitor according to claim 20, wherein the central end gap distance is 5% to 40% of the length of the central section of the first electrode.

23. The multilayer capacitor according to claim 19, wherein the second electrode extends to 5% to 50% of the length of the main body of the capacitor.

24. The multilayer capacitor according to claim 1, wherein the central section of the first electrode extends from 40% to less than 100% of the length of the main body of the capacitor.

25. The multilayer capacitor according to claim 24, wherein the central section extends to less than 50% to 100% of the length of the main body of the capacitor.

26. The multilayer capacitor according to claim 1, wherein the first electrode comprises copper.

27. The multilayer capacitor according to claim 1, wherein each electrode layer further comprises a second electrode, and the first electrode and the second electrode comprise copper.

28. The multilayer capacitor according to claim 1, wherein the plurality of dielectric layers include an NPO material.

29. The multilayer capacitor according to claim 1, wherein the plurality of dielectric layers include a titanate.

30. The multilayer capacitor according to claim 29, wherein the plurality of dielectric layers further comprise an oxide.

31. The multilayer capacitor according to claim 1, wherein the first connection edge is a rounded corner, and the second connection edge is a rounded corner.

32. The multilayer capacitor according to claim 31, wherein at least one electrode layer further includes a second electrode that is coplanar with the first electrode.

33. The multilayer capacitor according to claim 32, wherein the second electrode has at least one rounded corner.

34. The multilayer capacitor according to claim 33, wherein the second electrode is generally rectangular in configuration.

35. The multilayer capacitor according to claim 31, wherein the central section of the first electrode extends from 40% to less than 100% of the length of the main body of the capacitor.

36. The multilayer capacitor according to claim 35, wherein the central section extends to less than 50% to 100% of the length of the main body of the capacitor.

37. The multilayer capacitor according to claim 32, wherein a gap exists between the first electrode and the second electrode.

38. The multilayer capacitor according to claim 37, wherein the gap is 2% to 40% of the length of the main body of the capacitor.

39. The multilayer capacitor according to claim 37, wherein the gap is 5% to 40% of the length of the central section of the first electrode.

40. The multilayer capacitor according to claim 32, wherein the second electrode extends to 5% to 50% of the length of the main body of the capacitor.

41. The multilayer capacitor according to claim 1, wherein the plurality of external terminations include more than two external terminations arranged in a linear manner.

42. The multilayer capacitor according to claim 1, wherein the plurality of dielectric layers and the plurality of electrode layers include a first set of layers and a second set of layers, the first set of layers includes first portions of the plurality of dielectric layers stacked alternately with first portions of the plurality of electrode layers, and the second set of layers includes second portions of the plurality of dielectric layers stacked alternately with second portions of the plurality of electrode layers.

43. The multilayer capacitor according to claim 42, wherein the spacing distance is defined between the first set of layers and the second set of layers.

44. The multilayer capacitor according to claim 1, wherein the capacitor comprises at least three sets of alternating dielectric layers and electrode layers.

45. A circuit board comprising a capacitor as described in claim 1, wherein the capacitor is positioned on the circuit board.

46. The circuit board according to claim 45, wherein the substrate further includes an integrated circuit package, the capacitor is positioned vertically between the circuit board and the integrated circuit package, and the circuit board, the capacitor, and the integrated circuit package are in a stacked arrangement.

47. The circuit board according to claim 46, wherein the capacitor is directly connected to the circuit board and the integrated circuit package.

48. An integrated circuit package comprising the capacitor described in claim 1.

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