Multilayer capacitors

Abstract

The present invention is directed to multilayer capacitors, circuit boards including multilayer capacitors, and integrated circuit packages including multilayer capacitors. The multilayer capacitor includes a body, the body having an upper surface, a bottom surface, opposing side surfaces, and opposing end surfaces, and includes alternating dielectric layers and internal electrode layers. Each internal electrode layer includes at least one lead tab extending from the upper edge and bottom edge of the main body of the internal electrode layer, respectively. The capacitor also includes an external terminal, which is electrically connected to the internal electrode layer and is arranged in a linear manner on at least one of the upper surface or the bottom surface. The external terminal is positioned at a distance from the side edges of the body, such that only dielectric material is disposed between the external terminal and the side edges of the body.

Description

[Technical Field]

[0001] Related applications This application is based on U.S. Provisional Patent Application No. 63 / 420,722, filed on 31 October 2022, which claims priority, and the literature is incorporated herein by reference. [Background technology]

[0002] Multilayer capacitors are generally constructed to have multiple dielectric and internal electrode layers arranged in a stack. During manufacturing, the stacked dielectric and internal electrode layers are pressed and sintered to realize a substantially integrated capacitor body. Various configurations and designs have been used for the dielectric and internal electrode layers in an attempt to improve the performance of these capacitors.

[0003] However, these configurations are generally manipulated as rapid changes are occurring in the electronics industry, which requires new performance standards. In particular, various application design considerations have created the need to redefine capacitor parameters and their performance in high-speed environments, especially in terms of faster and higher-density integrated circuits. For example, higher currents, higher density circuit boards, and rising costs have all played a role in drawing attention to the need for better and more efficient capacitors. In addition, the design of various electronic components has been driven by the general industry trend toward miniaturization and increased functionality. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 7,177,137 [Patent Document 2] U.S. Patent No. 7,463,474 [Overview of the project] [Problems that the invention aims to solve]

[0005] From this perspective, there is a need to provide capacitors with improved operating characteristics. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The multilayer capacitor includes a body, the body having an upper surface, a bottom surface opposite the upper surface, a pair of side surfaces opposite each other along the transverse direction, and a pair of end surfaces opposite each other along the longitudinal direction. The body also has side edges defining the transverse boundaries of the upper surface and the bottom surface, the side edges including a first upper side edge, a second upper side edge, a first bottom side edge, and a second bottom side edge, respectively, extending longitudinally between the pair of end surfaces. The first upper side edge and the second upper side edge are opposite each other along the transverse direction, and the first bottom side edge and the second bottom side edge are opposite each other along the transverse direction. The body includes alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes a main body having an upper edge, a bottom edge opposite the upper edge, and two side edges extending between the upper and bottom edges; at least one lead tab extending from the upper edge of the main body of the internal electrode layer; and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer. The multilayer capacitor also includes external terminals, including a first external terminal and a second external terminal. The first external terminal is disposed on at least one of the upper or bottom surfaces and is electrically connected to the first internal electrode layer, and the second external terminal is disposed on at least one of the upper or bottom surfaces and is electrically connected to the second internal electrode layer. The external terminals are arranged in a linear manner on at least one of the upper or bottom surfaces of the main body, spaced apart from the side edges of the main body, with only dielectric material disposed between the external terminals and the side edges of the main body.

[0007] Other features and embodiments of the present invention are described in more detail below.

[0008] A complete and implementable disclosure of the present invention (including its best mode for those skilled in the art) is described more specifically in the remainder of the specification (including by reference to the accompanying drawings). [Brief explanation of the drawing]

[0009] [Figure 1A] This is an external perspective view of the generally top and side of one embodiment of a capacitor including two external terminals according to the present invention. [Figure 1B] Figure 1A is a side view of the internal electrode layer of the capacitor. [Figure 1C] Figures 1A and 1B are three-dimensional external perspective views of the top and side of the internal electrode layer of the capacitor. [Figure 1D] Figures 1A and 1C show the upper external view of the capacitor. [Figure 2A] This is an external perspective view of the generally top and side of another embodiment of a capacitor including four external terminals according to the present invention. [Figure 2B] Figure 2A is a side view of the internal electrode layer of the capacitor. [Figure 2C] Figures 2A and 2B are three-dimensional external perspective views of the top and side of the internal electrode layer of the capacitor. [Figure 2D] Figures 2A and 2C show the upper external view of the capacitor. [Figure 3A] This is an external perspective view of the generally top and side of one embodiment of a capacitor including two external terminals according to the present invention. [Figure 3B] Figure 3A is a side view of the internal electrode layer of the capacitor. [Figure 3C] Figures 3A and 3B show the upper external view of the capacitor. [Figure 4] Figure 3A is a perspective view of a capacitor mounted on a mounting surface according to the present invention. [Figure 5]A side view of a printed circuit board and an integrated circuit package including a capacitor according to the present invention.

Embodiments for Carrying out the Invention

[0010] It should be understood by those skilled in the art that this discussion is merely an illustration of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0011] Generally speaking, the present invention is directed to multilayer capacitors. A multilayer capacitor (or simply a capacitor) includes a body portion having alternating dielectric layers and internal electrode layers. The body portion has at least a pair of end surfaces and a pair of side surfaces. External terminals are formed on the body portion of the capacitor and are spaced apart from at least a pair of side surfaces of the body portion. The external terminals are arranged in a linear manner in a single dimension such that only dielectric material is disposed between at least two sides of each external terminal and the adjacent edges of the capacitor surface on which the external terminals are disposed.

[0012] The specific arrangement of the capacitor elements can provide several advantages. For example, the capacitor of the present invention can be mounted on a circuit board as a surface mount capacitor and can provide a smaller footprint on the circuit board. And this can also enable a reduction in the size of the circuit board.

[0013] Additionally, in certain applications, it is desirable to maintain the lowest possible inductance (i.e., parasitic inductance). Using the capacitors of the present invention allows for a significant reduction in inductance. In particular, minimizing the distance or path for ground connections can help reduce inductance. Generally, using the capacitors of the present invention can enable a reduction in inductance of at least an order of magnitude compared to using multiple individual multilayer ceramic capacitors. For example, using the capacitors of the present invention can result in inductances on the order of picohrenries or even femtohenries compared to prior art capacitors exhibiting larger inductances. Generally, the inductance can be less than 1 nanohenry. In particular, the inductance can be 900 picohrenies or less, for example, 750 picohrenies or less, for example, 500 picohrenies or less, for example, 400 picohrenies or less, for example, 250 picohrenies or less, for example, 100 picohrenies or less, for example, 50 picohrenies or less, for example, 25 picohrenies or less, for example, 15 picohrenies or less, for example, 10 picohrenies or less. The inductance can be 1 femtohenry or more, for example, 25 femtohenries or more, for example, 50 femtohenries or more, for example, 100 femtohenries or more, for example, 250 femtohenries or more, for example, 500 femtohenries or more, for example, 750 femtohenries or more. Minimizing such inductance can contribute to good performance (especially good decoupling performance), especially under high-speed transient conditions.

[0014] In addition, the capacitor can provide the desired capacitance. In particular, the capacitance can be 1,000 μF or less, for example, 750 μF or less, for example, 500 μF or less, for example, 250 μF or less, for example, 100 μF or less, for example, 50 μF or less, for example, 25 μF or less, for example, 20 μF or less, for example, 15 μF or less, for example, 10 μF or less, for example, 5 μF or less, for example, 2.5 μF or less, for example, 1 μF or less, for example, 0.75 μF or less, for example, 0.5 μF or less, and so on. Capacitance can be 1 pF or greater, for example, 10 pF or greater, for example, 25 pF or greater, for example, 50 pF or greater, for example, 100 pF or greater, for example, 250 pF or greater, for example, 500 pF or greater, for example, 750 pF or greater, for example, 900 pF or greater, for example, 1 μF or greater, for example, 2 μF or greater, for example, 3 μF or greater, for example, 5 μF or greater, for example, 8 μF or greater, for example, 10 μF or greater. Capacitance can be measured using common techniques known in the art.

[0015] Furthermore, the capacitor can provide a desired resistance. In particular, the resistance can be 100 mOhm or less, for example, 75 mOhm or less, for example, 50 mOhm or less, for example, 40 mOhm or less, for example, 30 mOhm or less, for example, 25 mOhm or less, for example, 20 mOhm or less, for example, 15 mOhm or less, for example, 10 mOhm or less, for example, 5 mOhm or less. The resistance can be 0.01 mOhm or more, for example, 0.1 mOhm or more, for example, 0.25 mOhm or more, for example, 0.5 mOhm or more, for example, 1 mOhm or more, for example, 1.5 mOhm or more, for example, 2 mOhm or more, for example, 5 mOhm or more, for example, 10 mOhm or more. The resistance can be measured using common techniques known in the art.

[0016] As described above, the present invention includes a multilayer capacitor comprising a body having an upper surface and a bottom surface opposite the upper surface. The body of the capacitor also includes at least one side surface (in particular, at least two side surfaces) extending between the upper surface and the bottom surface. The capacitor may also include at least one end surface (in particular, at least two end surfaces) extending between the upper surface and the bottom surface. Generally, the side surfaces extend in the longitudinal or length (L) direction and are generally longer than the end surfaces, while the end surfaces extend in the transverse or width (W) direction and are generally shorter. In one embodiment, the capacitor includes at least six total surfaces (e.g., one top, one bottom, two side surfaces, and two ends). For example, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0017] In addition, the capacitor can have a desired height. For example, the height can be 10 microns or more, for example 25 microns or more, for example 50 microns or more, for example 100 microns or more, for example 200 microns or more, for example 250 microns or more, for example 300 microns or more, for example 350 microns or more, for example 400 microns or more, for example 450 microns or more, for example 500 microns or more, for example 1,000 microns or more, for example 2,000 microns or more. The height can be 5,000 microns or less, for example 4,000 microns or less, for example 2,500 microns or less, for example 2,000 microns or less, for example 1,000 microns or less, for example 750 microns or less, for example 600 microns or less, for example 500 microns or less, for example 450 microns or less. When surrounded by a ball grid array, the height of a capacitor can be within 10% of the height (or diameter) of the balls in the ball grid array, for example, within 7%, within 5%, within 3%, within 2%, within 1%, etc. For example, such a height can be the original height before any reflow.

[0018] Capacitors can have a desired length. For example, the length can be 10 microns or more, 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 400 microns or more, 450 microns or more, 500 microns or more, 1,000 microns or more, 1,500 microns or more, 2,000 microns or more, 2,500 microns or more, 3,000 microns or more, 3,500 microns or more, 4,000 microns or more, and so on. The length can be 10,000 microns or less, for example, 8,000 microns or less, for example, 6,000 microns or less, for example, 5,000 microns or less, for example, 4,000 microns or less, for example, 3,000 microns or less, for example, 2,500 microns or less, for example, 2,000 microns or less, for example, 1,000 microns or less, for example, 750 microns or less, for example, 600 microns or less, for example, 500 microns or less, for example, 450 microns or less, and so on.

[0019] Furthermore, the capacitor can have a desired width. For example, the width can be 10 microns or more, 25 microns or more, 50 microns or more, 100 microns or more, 200 microns or more, 250 microns or more, 300 microns or more, 350 microns or more, 400 microns or more, 450 microns or more, 500 microns or more, 750 microns or more, 1,000 microns or more, 1,500 microns or more, 2,000 microns or more, 2,500 microns or more, 3,000 microns or more, and so on. The width can be 5,000 microns or less, for example, 4,000 microns or less, for example, 3,000 microns or less, for example, 2,500 microns or less, for example, 2,000 microns or less, for example, 1,500 microns or less, for example, 1,000 microns or less, for example, 750 microns or less, for example, 600 microns or less, for example, 500 microns or less, for example, 450 microns or less.

[0020] Generally, a multilayer capacitor includes one set of alternating dielectric layers and internal electrode layers. Generally, a capacitor includes at least one set of alternating dielectric layers and internal electrode layers. It is also possible for a capacitor to include a second set of alternating dielectric layers and internal electrode layers. In this regard, a capacitor can include at least two sets of alternating dielectric layers and internal electrode layers, for example, at least three sets, for example, at least four sets, etc. However, it should be understood that the present invention can and is not necessarily limited to any number of sets of alternating dielectric layers and internal electrode layers. In addition, each set of alternating dielectric layers and internal electrode layers can be separated from adjacent sets by a certain distance. For example, the distance is greater than the thickness of the individual dielectric layers in the set. In particular, the distance can be at least twice the thickness of the dielectric layers in the set, for example, at least three times, for example, at least five times, for example, at least ten times, etc.

[0021] An alternating set of dielectric layers and internal electrode layers can form at least a portion of the main body of a capacitor. By arranging the dielectric layers and internal electrode layers in a stacked or laminated configuration, the capacitor can be referred to as a multilayer capacitor, and, for example, when the dielectric layers include ceramic, it can be referred to as a multilayer ceramic capacitor.

[0022] The capacitor also includes external terminals electrically connected to the internal electrode layer. The external terminals are formed on at least the upper surface of the capacitor and the bottom surface of the capacitor opposite the upper surface. In some embodiments, the external terminals may include a first end external terminal and a second end external terminal, and one or both of the first and second end external terminals may also be formed on the respective end surfaces adjacent to each end external terminal.

[0023] The alternating dielectric layers and internal electrode layers include dielectric layers arranged alternately with the internal electrode layers. In particular, the internal electrode layers include a first internal electrode layer and a second internal electrode layer that are interleaved, positioned opposite each other and spaced apart, such that the dielectric layers are located between each other's internal electrode layers.

[0024] Generally, the thickness of the dielectric layer and the internal electrode layer is not limited and can be any desired thickness depending on the performance characteristics. For example, the thickness of the internal electrode layer is not limited to approximately 500 nm or more, for example, approximately 1 μm or more, for example, approximately 2 μm or more, and can range from approximately 10 μm or less, for example, approximately 5 μm or less, for example, approximately 4 μm or less, for example, approximately 3 μm or less, for example, approximately 2 μm or less. For example, the internal electrode layer can have a thickness of approximately 1 μm to approximately 2 μm.

[0025] In addition, the present invention is not necessarily limited to the number of internal electrode layers in each set of alternating dielectric layers and internal electrode layers, or in the capacitor as a whole. For example, each set may include 10 or more, for example 25 or more, for example 50 or more, for example 100 or more, for example 200 or more, for example 300 or more, for example 500 or more, for example 600 or more, for example 750 or more, for example 1,000 or more internal electrode layers. Each set can have an internal electrode layer of 5,000 or less, for example, 4,000 or less, for example, 3,000 or less, for example, 2,000 or less, for example, 1,500 or less, for example, 1,000 or less, for example, 750 or less, for example, 500 or less, for example, 400 or less, for example, 300 or less, for example, 250 or less, for example, 200 or less, for example, 175 or less, for example, 150 or less, etc. Furthermore, the entire capacitor can contain the above number of electrode layers.

[0026] The internal electrode layer has an upper edge and a bottom edge opposite the upper edge. The internal electrode layer also has two side edges extending between the upper and bottom edges. In one embodiment, the side edges, upper edge, and bottom edge define the main body of the internal electrode layer. Generally, the main body of the internal electrode layer can have a rectangular configuration or shape.

[0027] Generally, the top and bottom edges can have the same dimensions (e.g., length - L direction). The side edges can have the same dimensions (e.g., height - T direction). Generally, the side edges can have shorter dimensions (e.g., height - T direction) than the dimensions (e.g., length - L direction) of the top and / or bottom edges. In this regard, the height of the side edges of the internal electrode layer when extending between the top and bottom surfaces of the capacitor can be smaller than the length of the top and / or bottom edges of the internal electrode layer when extending between the end surfaces of the capacitor. In other words, the internal electrode layer can have top and / or bottom edges with larger dimensions than side edges with smaller dimensions. In this regard, the "shorter" side of the layer can coincide with the height direction of the capacitor.

[0028] The internal electrode layers have lead tabs extending from the main body portion of each internal electrode layer. The lead tabs extend from the upper and bottom edges. In other words, the internal electrode layers may have lead tabs extending from the "longer" side or edge of the internal electrode layer. The lead tabs may extend to the edge of the dielectric layer and / or the surface of the capacitor. For example, in a stacked configuration, the leading edge of the lead tab may extend to the edge of the dielectric layer. Such leading edges may be used to form external terminals. In addition, the upper and bottom edges of the layers may have at least one lead tab extending from there, for example, at least two lead tabs, for example, at least three lead tabs, for example, at least four lead tabs, and so on.

[0029] Each upper and lower edge of the internal electrode layer may have an equal number of lead tabs extending from it. For example, each upper and lower edge may have at least one lead tab extending from it. In another embodiment, each upper and lower edge may have at least two lead tabs extending from it. However, it should be understood that the present invention may and may not necessarily include any number of lead tabs extending from the internal electrode layer.

[0030] In one embodiment, at least one lead tab extends from the upper and bottom edges of the main body of the internal electrode layer, and the edge of the lead tab aligns with the lateral edge of the main body of the internal electrode layer. For example, at least one lateral edge of the lead tab (i.e., an edge that coincides with the height direction) can be substantially aligned with the respective lateral edges of the main body of the internal electrode layer. In this regard, at least one lead tab does not have to be offset from the lateral edge of the internal electrode layer.

[0031] However, in some embodiments, at least one lead tab can be offset from the lateral edge of the internal electrode layer. For example, the edge of each lead tab is positioned parallel to, but spaced apart from, the lateral edge of the main body of the internal electrode layer along its length or L direction. For example, at least one lateral edge of a lead tab (i.e., an edge coincident with the height direction) can be substantially parallel to each of the lateral edges of the main body of the internal electrode layer, but offset from the lateral edge of the internal electrode layer along the length of the main body of the internal electrode layer.

[0032] When it is possible for more than one lead tab to be present along the edge, either additionally or alternatively, each lead tab may extend from the inner portions of the upper and bottom edges of the main body of the internal electrode layer. In this respect, the lead tabs do not necessarily have to extend immediately from the lateral edges of the internal electrode layer. In other words, the lead tabs may be offset from the lateral edges of the internal electrode layer, for example, in the longitudinal or L direction. The offset may be offset and positioned between the lateral edges of the internal electrode layer (in particular at a position that is at least 50% of the length of the internal electrode layer (for example, beyond the center of the internal electrode layer)).

[0033] Lead tabs extending from the upper edge and the bottom edge of each internal electrode layer can be offset by the same distance from the side edge. In this regard, at least one lateral edge of the lead tab (i.e., the edge that coincides with the height direction) can be substantially aligned. In one embodiment, both lateral edges of each lead tab can be substantially aligned.

[0034] Similarly, the length of a lead tab extending from the upper edge (i.e., extending longitudinally from one end surface to another) can be the same as the length of a corresponding lead tab extending from the bottom edge.

[0035] The length of each lead tab can be 0.3 mm or more, for example, 0.4 mm or more, for example, 0.5 mm or more, for example, 0.6 mm or more, for example, 0.7 mm or more. The length of each lead tab can be 1.1 mm or less, for example, 0.9 mm or less, for example, 0.8 mm or less, for example, 0.7 mm or less, for example, 0.6 mm or less, for example, 0.5 mm or less. When there are more than one lead tab along the edge, each lead tab can have the same length.

[0036] In another embodiment, each lead tab can have a different length. For example, with respect to an internal electrode layer having more than one lead tab extending from an upper or bottom edge, a lead tab substantially aligned with the side edge of the internal electrode layer can have a longer length than a lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer can be 0.3 or greater, for example 0.5 or greater, for example 0.7 or greater, for example 0.9 or greater, for example 1 or greater, for example 1 or greater, for example 1.1 or greater, for example 1.2 or greater, for example 1.3 or greater, for example 1.4 or greater, for example 1.5 or greater, and so on. The ratio can be 5 or less, for example, 4 or less, for example, 3 or less, for example, 2 or less, for example, 1.8 or less, for example, 1.7 or less, for example, 1.6 or less, for example, 1.5 or less, for example, 1.4 or less, and so on.

[0037] Being substantially aligned means that the offset of one lateral edge of the first lead tab and / or second lead tab at the upper edge from the lateral edge is within + / -10% of the offset of the corresponding lateral edge of the first lead tab and / or second lead tab at the bottom edge from the lateral edge, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc.

[0038] When the dielectric layer and the internal electrode layer are stacked together as described herein, the aligned lead tabs form what may be called a row of lead tabs or electrode tabs. The distance between adjacent exposed lead tabs of the internal electrode layer in a given row can be specifically designed to ensure guided formation of the terminations. Such a distance between exposed lead tabs of the internal electrode layer in a given row can be about 10 microns or less, for example, about 8 microns or less, for example, about 5 microns or less, for example, about 4 microns or less, for example, about 2 microns or less, for example, about 1.5 microns or less, for example, about 1 micron or less, etc. The distance can be about 0.25 microns or more, for example, about 0.5 microns or more, for example, about 1 micron or more, for example, about 1.5 microns or more, for example, about 2 microns or more, for example, about 3 microns or more, etc. However, it should be understood that such a distance may not necessarily be limited.

[0039] Additionally, the distance between adjacent columnar stacks of electrode tabs can be at least twice the distance between adjacent lead tabs in a given column, but is not limited to this, to ensure that individual terminations do not mix. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances can vary depending on the desired capacitance performance and circuit board configuration.

[0040] The distance can be 0.1 mm or more, for example, 0.2 mm or more, for example, 0.3 mm or more, for example, 0.4 mm or more, for example, 0.5 mm or more, for example, 0.6 mm or more. The distance can be 1.5 mm or less, for example, 1.3 mm or less, for example, 1 mm or less, for example, 0.9 mm or less, for example, 0.7 mm or less, for example, 0.6 mm or less, for example, 0.5 mm or less, for example, 0.4 mm or less. In one embodiment, such a distance can be determined based on the center point of each lead tab. In another embodiment, such a distance can be based on the distance between adjacent lateral edges of the lead tabs. In addition, such a distance can correspond to the separation distance of balls on a ball grid array.

[0041] In a set of alternating dielectric and internal electrode layers, the lead tabs of the first and second internal electrode layers are offset from each other longitudinally or in the lengthwise direction. That is, the lead tabs of each internal electrode layer can be symmetrically offset by a certain distance from the centerline of the internal electrode layer and / or dielectric layer (for example, from the longitudinal centerline or with respect to the perpendicular line). That is, the lead tabs of each internal electrode layer can be symmetrically offset with respect to the perpendicular line of the internal electrode layer and / or dielectric layer. Nevertheless, a gap region is formed between the lead tabs of each internal electrode layer.

[0042] In addition, the internal electrode layer can be symmetrical in a given direction, regardless of the number of lead tabs extending from it. For example, the lead tabs can be symmetrical with respect to a horizontal line passing through the center of the main body of the internal electrode layer (i.e., a line extending from the center of one side edge of the internal electrode layer to the center of the other side edge).

[0043] Furthermore, as shown herein, each internal electrode layer includes at least two side edges. When stacked to form the body of the capacitor, such side edges of alternating internal electrode layers do not have to be substantially aligned with each other. For example, the side edges can be offset from each other. Moreover, in at least some embodiments, the side edges can be offset from the side surfaces of the body of the capacitor.

[0044] Furthermore, the capacitor of the present invention includes external terminals on the upper and bottom surfaces of the capacitor body. The external terminals are spaced apart from the side surfaces of the capacitor body, and only dielectric material is disposed between the external terminals and the side surfaces of the body. In some embodiments, the capacitor also includes external terminals on opposing end surfaces of the capacitor body, but in other embodiments, in addition to being spaced apart from the side surfaces, the external terminals are spaced apart from at least one of the opposing end surfaces, and only dielectric material is disposed between the external terminals and at least one end surface.

[0045] The external terminals include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitor may include at least one, for example, at least two, for example, at least four, for example, at least six, for example, at least eight, first polarity terminals and / or second and opposite polarity terminals on the upper surface of the capacitor body. In addition, the capacitor may include the above-mentioned number of terminals on the bottom surface of the capacitor body.

[0046] A capacitor may have an equal number of first polarity terminals and / or second polarity terminals on its top and bottom surfaces. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the top surface. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the bottom surface. The total number of terminals present on the top surface of the capacitor may be equal to the total number of terminals present on the bottom surface of the capacitor. The total number of first polarity terminals present on the top and bottom surfaces of the capacitor may be equal to the total number of second and opposite polarity terminals present on the top and bottom surfaces of the capacitor.

[0047] Generally, similar polarity terminals on the bottom surface of a capacitor, corresponding to a particular set of alternating dielectric and internal electrode layers, are electrically connected to similar polarity terminals on the top surface of the capacitor. Similar polarity terminals located on the top and bottom surfaces of a capacitor do not necessarily have to mesh with each other. In this regard, corresponding similar polarity terminals on the top and bottom surfaces may not be offset by their terminal position, but instead may be positioned directly above or below another similar polarity terminal on the opposite top or bottom surface. In other words, corresponding similar polarity terminals, corresponding to a particular set of lead tabs, can be substantially aligned. The substantial alignment means that the offset of one lateral edge of a polarity terminal on the upper surface from the side edge is within + / -10% of the offset of the corresponding polarity terminal on the bottom surface from the side edge, for example, within + / -5%, within + / -4%, within + / -3%, within + / -2%, within + / -1%, within + / -0.5%, etc.

[0048] Generally, the pitch of external terminals (i.e., the nominal distance between centers, also called the center-to-center spacing) can be determined by a particular circuit board configuration. The pitch between external terminals in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals.

[0049] The pitch can be approximately 0.1 mm or more, for example, approximately 0.2 mm or more, for example, approximately 0.3 mm or more, for example, 0.4 mm or more, for example, approximately 0.5 mm or more, for example, approximately 0.6 mm or more, for example, approximately 0.7 mm or more, for example, approximately 0.8 mm or more, for example, approximately 0.9 mm or more, for example, approximately 1.0 mm or more. The pitch can be approximately 2.0 mm or less, for example, approximately 1.5 mm or less, for example, approximately 1.4 mm or less, for example, approximately 1.3 mm or less, for example, approximately 1.2 mm or less, for example, approximately 1.1 mm or less, for example, approximately 1.0 mm or less. For example, the pitch can be approximately 0.2 mm, approximately 0.4 mm, approximately 0.6 mm, approximately 0.8 mm, approximately 1.0 mm, approximately 1.2 mm, etc. In particular, the pitch can be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch can be about 0.6 mm, for example, 0.6 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc. In another embodiment, the pitch can be about 0.8 mm, for example, 0.8 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc. In a further embodiment, the pitch can be about 1 mm, for example, 1 mm + / - 10%, for example, + / - 5%, for example, + / - 2%, for example, + / - 1%, etc.

[0050] The ratio of the length of the capacitor body to the pitch can be 1.1 or greater, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the length of the capacitor body to the pitch can be in the range of 1.1 to 1,000, for example, in the range of 2 to 500, in the range of 5 to 100, or in the range of 10 to 50.

[0051] As shown above, the extension of the leading edge of the lead tab can assist in the formation of external terminals. In this regard, the pitch between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be the same as that described above. That is, the pitch between the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer can be substantially the same as the pitch between the corresponding external terminals from which the lead tab is used during formation.

[0052] In addition, external terminals can be positioned in a manner similar to that of a ball grid array. For example, external terminals can be provided to make contact in a manner typically used by a ball grid array (particularly a surrounding ball grid array). In this regard, the pitch of the external terminals can be the same as the pitch of the surrounding ball grid array. That is, the pitch can be within 10% of the pitch of the surrounding ball grid array, for example, within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc.

[0053] In addition, external terminals can be provided in a single row having multiple columns, which can be referred to as a 1 × n configuration of external terminals in the row × column specification, where n is the number of columns. For example, external terminals can be provided such that they exist in a single row and at least two columns. For example, external terminals can be provided with at least two columns, for example, at least three columns, for example, at least four columns, for example. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0054] Furthermore, the length of an external terminal extending along the upper surface in the longitudinal direction or in the direction of length L can be the same as the length of a corresponding external terminal extending along the bottom surface. The length of the external terminals can be measured from one terminal end surface to another, and these terminals face each other in the longitudinal direction.

[0055] The length of the external terminals can be 0.3 mm or more, for example, 0.4 mm or more, for example, 0.5 mm or more, for example, 0.6 mm or more, for example, 0.7 mm or more. The length of the external terminals can be 1.1 mm or less, for example, 0.9 mm or less, for example, 0.8 mm or less, for example, 0.7 mm or less, for example, 0.6 mm or less, for example, 0.5 mm or less. When there is more than one external terminal along the surface, each external terminal can have the same length. Furthermore, the length of the external terminals can be less than the length of the capacitor, for example, 50% or less of the length of the capacitor, for example, 40% or less, for example, 30% or less, for example, 25% or less, for example, 20% or less, for example, 15% or less.

[0056] In another embodiment, each external terminal can have a different length. For example, an external terminal adjacent to an end surface can have a longer length than an external terminal offset from the end surface. In this regard, the ratio of the length of an external terminal adjacent to an end surface to the length of an external terminal offset from the end surface can be 0.3 or greater, for example, 0.5 or greater, for example, 0.7 or greater, for example, 0.9 or greater, for example, 1 or greater, for example, 1 or greater, for example, 1.1 or greater, for example, 1.2 or greater, for example, 1.3 or greater, for example, 1.4 or greater, for example, 1.5 or greater. The ratio can be 5 or less, for example, 4 or less, for example, 3 or less, for example, 2 or less, for example, 1.8 or less, for example, 1.7 or less, for example, 1.6 or less, for example, 1.5 or less, for example, 1.4 or less.

[0057] Furthermore, the width of external terminals extending laterally or in the width W direction can be the same on the top and bottom surfaces. The width of external terminals can be measured from one terminal side surface to another, where they face each other laterally.

[0058] The width of the external terminals can be 0.3 mm or more, for example, 0.4 mm or more, for example, 0.5 mm or more, for example, 0.6 mm or more, for example, 0.7 mm or more. The width of the external terminals can be 1.1 mm or less, for example, 0.9 mm or less, for example, 0.8 mm or less, for example, 0.7 mm or less, for example, 0.6 mm or less, for example, 0.5 mm or less. When there are more than one external terminal along the surface, each external terminal can have the same width. Furthermore, the width of the external terminals can be smaller than the width of the capacitor.

[0059] Furthermore, the external terminals can be located not only on the sides and / or ends of the capacitor, but also spaced apart from each other, with dielectric material disposed between adjacent external terminals. The external terminals may include a first end external terminal and a second end external terminal, the first end external terminal being located adjacent to or closest to the first end surface of the capacitor body, and the second end external terminal being located adjacent to or closest to the second end surface of the capacitor body. The first and second end external terminals can be spaced apart from each other longitudinally by the distance between the end external terminals. The ratio of the length of the capacitor body to the distance between the end external terminals can be 1.1 or greater, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the length of the capacitor body to the distance between the external terminals can be in the range of 1.1 to 1,000, and can be in the range of 2 to 500, 5 to 100, or 10 to 50, for example.

[0060] Furthermore, adjacent external terminals can be spaced apart from each other longitudinally on the upper surface of the capacitor by the distance between adjacent external terminals, for example, between adjacent lateral sides of external terminals. For example, when a pair of adjacent external terminals has a lateral side facing the other of the pair of adjacent external terminals, the lateral side of one external terminal of the pair is spaced apart from the lateral side of the other external terminal of the pair by the distance between adjacent external terminals. The ratio of the length of the capacitor body to the distance between adjacent external terminals can be 1.1 or greater, and can be, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater. For example, the ratio of the length of the capacitor body to the distance between adjacent external terminals can be in the range of 1.1 to 1,000, and can be, for example, in the range of 2 to 500, in the range of 5 to 100, or in the range of 10 to 50.

[0061] The capacitor of the present invention can be further described according to embodiments as illustrated in Figures 1A to 1D, Figures 2A to 2D, and Figures 3A to 3C.

[0062] Figure 1A illustrates a capacitor 100 in a 1x2 configuration. That is, the capacitor 100 includes two external terminals arranged in a linear manner in a single dimension on the top and bottom surfaces of the capacitor. In the embodiment depicted, the capacitor 100 includes external terminals arranged in a linear manner or in a single row along the longitudinal direction L, which can be referred to as a linear terminal arrangement.

[0063] In this regard, the capacitor 100 includes a main body 116 having external terminals 112 and 114, the external terminals 112 and 114 including a first external terminal 112 and a second external terminal 114, the first external terminal 112 being disposed on at least one of the upper surface 118 or the bottom surface 120 and electrically connected to a first internal electrode layer 1005 (Figures 1B and 1C), and the second external terminal 114 being disposed on at least one of the upper surface 118 or the bottom surface 120 and electrically connected to a second internal electrode layer 1015 (Figures 1B and 1C). More specifically, in the embodiment depicted, the capacitor 100 includes a first external terminal 112 and a second external terminal 114 disposed on the upper surface 118 of the main body 116, and two corresponding external terminals 112, 114 (not shown) on the bottom surface 120 of the main body 116 (they may be referred to as a third external terminal 112 and a fourth external terminal 114).

[0064] External terminals 112 and 114 on the upper surface 118 are electrically connected to the corresponding external terminals 112 and 114 on the bottom surface 120. Thus, as shown in Figure 1A, the capacitor 100 includes at least one first polarity terminal and at least one second and opposite polarity terminal on the upper surface 118, and the bottom surface 120 also includes at least one first polarity terminal and a second and opposite polarity terminal, although not shown. Furthermore, the first and third external terminals 112 are electrically connected to the first internal electrode layer 1005 (Figures 1B and 1C), and the second and fourth external terminals 114 are electrically connected to the second internal electrode layer 1015 (Figures 1B and 1C).

[0065] The main body portion 116 includes an upper surface 118 and a bottom surface 120 that faces the upper surface 118 along the height direction T. The main body portion also includes a first side surface 122 and a second side surface 124, the first side surface 122 extending between the upper surface 118 and the bottom surface 120 along the height direction T, and the second side surface 124 facing the first side surface 122 along the lateral or width direction W and extending between the upper surface 118 and the bottom surface 120. The main body further includes a first end surface 126 and a second end surface 128, the first end surface 126 extending between the upper surface 118 and the bottom surface 120 along the height direction T, and the second end surface 128 facing the first end surface 126 along the longitudinal direction or length direction L, and extending between the upper surface 118 and the bottom surface 120. The main body 116 has a main body length 115 and a main body width 125.

[0066] As further illustrated in Figure 1A, the main body 116 includes end edges 130, 132 that define the longitudinal boundaries of the upper and lower surfaces 118, 120, and side edges 134, 136 that define the lateral boundaries of the upper and lower surfaces 118, 120. For example, the upper surface 118 has a first upper end edge 130a and a second upper end edge 132a that extend along the lateral direction W between a pair of side surfaces 122, 124. The first upper end edge 130a and the second upper end edge 132a face each other along the longitudinal direction L. The upper surface 118 also has a first upper side edge 134a and a second upper side edge 136a that extend along the longitudinal direction L between a pair of end surfaces 126, 128. The first upper side edge 134a and the second upper side edge 136a face each other along the lateral direction W. The upper end edges 130a and 132a define the longitudinal boundary of the upper surface 118, and the upper side edges 134a and 136a define the lateral boundary of the upper surface 118.

[0067] Similarly, the bottom surface 120 has a first bottom end edge 130b and a second bottom end edge 132b that extend along the lateral direction W between a pair of side surfaces 122 and 124. The first bottom end edge 130b and the second bottom end edge 132b face each other along the longitudinal direction L. The bottom surface 120 also has a first bottom side edge 134b and a second bottom side edge 136b that extend along the longitudinal direction L between a pair of end surfaces 126 and 128. The first bottom side edge 134b and the second bottom side edge 136b face each other along the lateral direction W. The bottom edge portions 130b and 132b define the longitudinal boundary of the bottom surface 120, and the bottom side edges 134b and 136b define the lateral boundary of the bottom surface 120.

[0068] Although not shown in the figure, it will be recognized that the bottom surface 120 can be configured in the same way as the top surface 118. That is, the bottom surface 120 can also have a first end edge and a second end edge, the first and second end edges extending along the lateral direction W between a pair of side surfaces 122, 124 and facing each other along the longitudinal direction L. Furthermore, the bottom surface 120 can also have a first side edge and a second side edge, the first and second side edges extending along the longitudinal direction L between a pair of end surfaces 126, 128 and facing each other along the lateral direction W. The end edges and side edges can define the longitudinal boundary and the lateral boundary of the bottom surface 120, respectively.

[0069] The external terminals 112 and 114 of the capacitor 100 are offset from the sides and ends of the capacitor 100. As shown in Figures 1A and 1D, the external terminals 112 and 114 are spaced apart from the first and second side edges 134 and 136 of both the upper surface 118 and the bottom surface 120, respectively, so that only dielectric material is disposed between the side edges 134 and 136 and the external terminals 112 and 114. For example, the external terminals 112 and 114 are spaced apart from the first side edge 134a on the upper surface 118 and the first side edge 134b on the bottom surface 120, defining a first edge gap 138 between the external terminals 112 and 114 and the first side edges 134a and 134b, respectively. Furthermore, the external terminals 112 and 114 are positioned at a distance from the second side edge 136a on the upper surface 118 and the second side edge 136b on the bottom surface 120, defining a second edge gap 140 between the external terminals 112 and 114 and the second side edges 136a and 136b, respectively.

[0070] The edge gaps 138 and 140 can be larger than the thickness of the individual layers, for example, larger than the thickness of the individual dielectric layers or individual internal electrode layers 1010 (Figures 1B and 1C). For example, each edge gap 138 or 140 can be at least twice the thickness of the individual dielectric layer or individual internal electrode layer, for example, at least three times, for example, at least five times, for example, at least ten times, etc. In some embodiments, the first edge gap 138 and the second edge gap 140 can be the same (for example, with respect to a given surface 118, 120, the external electrodes 112, 114 can be at the same distance or equidistant from the respective first side edge 134 to the respective second side edge 136), but in other embodiments, the first edge gap 138 and the second edge gap 140 can be different (for example, with respect to a given surface 118, 120, the external electrodes 112, 114 can be closer to one of the respective first side edge 134 or the respective second side edge 136 than to the other side edge of the respective surface 118, 120).

[0071] Similarly, the external terminals 112 and 114 of the capacitor 100 are spaced apart from the end edges 130 and 132 of the upper and lower surfaces 118 and 120. As shown in Figures 1A and 1D, the external terminals 112 and 114 are spaced apart from the first end edges 130 and second end edges 132 of the upper surface 118 and lower surface 120, respectively, defining a first end gap 142 between the external terminal 112 and the first end edges 130a and 130b, and a second end gap 144 between the external terminal 114 and the second end edges 132a and 132b.

[0072] The end gaps 142 and 144 can be larger than the thickness of the individual layers, for example, larger than the thickness of the individual dielectric layers or individual internal electrode layers 1010 (Figures 1B and 1C). For example, each end gap 142 or 144 can be at least twice the thickness of the individual dielectric layer or individual internal electrode layer, for example, at least three times, for example, at least five times, for example, at least ten times, etc. In some embodiments, the first end gap 142 and the second end gap 144 can be the same (for example, with respect to a given surface 118, 120, the external terminal 112 can be at the same distance from each first end edge 130 as the external terminal 114 is at the same distance from each second end edge 132), but in other embodiments, the first end gap 142 and the second end gap 144 can be different (for example, with respect to a given surface 118, 120, one of the external terminals 112, 114 can be closer to its adjacent end edge 130, 132 than the other external electrode 112, 114 is closer to its adjacent end edge 130, 132).

[0073] Referring to Figures 1A and 1B, the capacitor 100 in Figure 1A includes external terminals 112 and 114 and a set of alternating dielectric layers and internal electrode layers 1010. Referring in particular to Figure 1B, the set of alternating dielectric layers and internal electrode layers 1010 includes internal electrode layers 1005 and 1015 and dielectric layers (not shown) in an alternating arrangement.

[0074] Generally, the internal electrode layers 1005, 1015 include at least one lead tab 1020, 1030, 1040, 1050 extending from the upper and bottom edges of the main body of the internal electrode layer. Generally, the lead tabs 1020, 1030, 1040, 1050 of the internal electrode layers 1005, 1015 extend to the upper and bottom surfaces of the capacitor and help form the external terminals 112, 114. In this regard, the lead tabs 1020, 1030, 1040, 1050 are exposed on the upper surface 118 and bottom surface 120 of the capacitor, allowing for connections between the main body of the internal electrode layer and the external terminals 112, 114. For example, lead tabs 1020, 1030, 1040, and 1050 may include leading edges 1023, 1033, 1043, and 1053, which extend to the edge of the dielectric layer, enabling the formation of external terminals 112 and 114 on the upper surface 118 and the bottom surface 120.

[0075] As illustrated in Figures 1B and 1C, the first internal electrode layer 1005 includes one lead tab 1020 extending from the main body 1035 along the upper edge 1005c and one lead tab 1030 extending from the main body 1035 along the bottom edge 1005d. The second internal electrode layer 1015 includes one lead tab 1040 extending from the main body 145 along the upper edge and one lead tab 1050 extending from the main body 145 along the bottom edge.

[0076] The lead tabs 1020 and 1030 located at the upper edge 1005c and bottom edge 1005d of the first internal electrode layer 1005 can be aligned in the vertical or height direction T. That is, the lateral edges 1021 and 1022 of the first lead tab 1020 along the upper edge 1005c can be aligned with the lateral edges 1031 and 1032 of the first lead tab 1030 along the bottom edge 1005d opposite the upper edge 1005c. In other words, the lateral edges 1021 and 1022 of the first lead tab 1020 along the upper edge 1005c can be offset from the lateral edges 1005a and 1032 of the first lead tab 1030 along the bottom edge 1005d opposite the upper edge 1005c by the same distance (indicated by "O").

[0077] However, it should be understood that both lateral edges 1021 and 1022 of the first lead tab 1020 along the upper edge 1005c can be aligned with the lateral edges 1031 and 1032 of the first lead tab 1030 along the bottom edge 1005d opposite the upper edge 1005c. In other words, both lateral edges 1021 and 1022 of the first lead tab 1020 along the upper edge 1005c can be offset from the lateral edges 1005a and 1032 of the first lead tab 1030 along the bottom edge 1005d opposite the upper edge 1005c by the same distance.

[0078] Similarly, the lead tabs 1040 and 1050 at the upper and lower edges of the second internal electrode layer 1015 can be aligned vertically. That is, the lateral edges 1041 and 1042 of the first lead tab 1040 along the upper edge can be aligned with the lateral edges 1051 and 1052 of the first lead tab 1050 along the lower edge opposite the upper edge. In one embodiment, both lateral edges 1041 and 1042 of the first lead tab 1040 along the upper edge can be aligned with the lateral edges 1051 and 1052 of the first lead tab 1050 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tabs at the upper edge and the lateral edges of the first lead tabs at the lower edge, as described with respect to the internal electrode layer 1005, can also be applied to the internal electrode layer 1015.

[0079] Such an arrangement allows a tab gap 1016 to be formed between the lead tab 1020 of the first internal electrode layer 1005 and the lead tab 1040 of the second internal electrode layer 1015. Similarly, a tab gap 1018 can be formed between the lead tab 1030 of the first internal electrode layer 1005 and the lead tab 1050 of the second internal electrode layer 1015. The sizes of the respective tab gaps 1016 and 1018 can be substantially the same.

[0080] The lead tabs 1020 and 1040 can be arranged in parallel with the lead tabs 1030 and 1050 extending from the internal electrode layers 1005 and 1015, respectively, so that the lead tabs extending from the alternating electrode layers 1005 and 1015 can be aligned in their respective rows. For example, the lead tabs 1020 and 1030 of the internal electrode layer 1005 can be arranged in their respective stacked configurations, while the lead tabs 1040 and 1050 of the internal electrode layer 1015 can be arranged in their respective stacked configurations.

[0081] It is understood that lead tab 1020 is connected to external terminal 112, while lead tab 1040 is connected to external terminal 114. Thus, each lead tab 1020 interlocks with each other with each other with each other with respect to external terminals 112 and 114. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0082] Referring to Figure 1D, a top view of the upper surface 118 of the capacitor 100 is provided. It will be recognized that the bottom surface 120 can be configured substantially similarly to the upper surface 118, and that the description of the upper surface 118 can similarly describe the bottom surface 120.

[0083] As shown in Figure 1D, the external terminals 112 and 114 can be spaced apart from each other, not only on the sides and ends of the upper surface 118 and bottom surface 120 of the capacitor 100. As one example, the external terminals 112 and 114 may include a first end external terminal 112 and a second end external terminal 114, where the first end external terminal 112 is located on the upper surface 118 adjacent to the first end surface 126 and the first end edge 130a, and the second end external terminal 114 is located on the upper surface 118 adjacent to the second end surface 128 and the second end edge 132a. The first end external terminal 112 and the second end external terminal 114 are spaced apart in the longitudinal direction L by an end external terminal spacing distance 150.

[0084] As previously described, the main body 116 has a main body length 115 in the longitudinal direction L. The ratio of the main body length 115 to the distance 150 between end external terminals is 1.1 or greater. For example, the ratio of the main body length 115 to the distance 150 between end external terminals can be 1.1 or greater, and can be, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0085] As further illustrated in Figure 1D, a pitch 152 is defined between adjacent external terminals 112, 114. As previously described, the pitch 152 is the nominal distance between the centers of adjacent external terminals, and the pitch 152 can also be referred to as the distance between the centers of the external terminals. The ratio of the body length 115 to the pitch 152 is 1.1 or greater, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0086] As illustrated in Figures 1A to 1D, the capacitor 100 includes two external terminals 112, 114 on each surface, and each internal electrode layer 1010 includes at least one lead tab extending from the upper and bottom edges. However, as shown above, the present invention is not limited by the number of external terminals, and / or the number of lead tabs extending from the upper and / or bottom edges.

[0087] For example, Figure 2A illustrates a capacitor 200 that includes four external terminals on each surface and two lead tabs extending from the upper and bottom surfaces of each internal electrode layer.

[0088] As illustrated in Figure 2A, the capacitor 200 has a 1×4 configuration. That is, the capacitor 200 includes four external terminals arranged in a linear manner in a single dimension on the top and bottom surfaces of the capacitor. In the embodiment depicted, the capacitor 200 includes external terminals arranged in a linear manner or in a single row along the longitudinal direction L, which can be referred to as a linear terminal arrangement.

[0089] In this regard, the capacitor 200 includes a main body 216 having external terminals 212a, 212b, 214a, and 214b, the external terminals 212a, 212b, 214a, and 214b include a first external terminal 212a and a second external terminal 214a, the first external terminal 212a being disposed on at least one of the upper surface 218 or the bottom surface 220 and electrically connected to a first internal electrode layer 2005 (Figures 2B and 2C), and the second external terminal 214a being disposed on at least one of the upper surface 218 or the bottom surface 220 and electrically connected to a second internal electrode layer 2015 (Figures 2B and 2C). More specifically, in the embodiment depicted, the capacitor 200 includes a first external terminal 212a, a second external terminal 214a, a third external terminal 212b, and a fourth external terminal 214b disposed on the upper surface 218 of the main body 216, as well as four corresponding external terminals 212a, 212b, 214a, and 214b (not shown) on the bottom surface 220 of the main body 216 (they may be referred to as a fifth external terminal 212a, a sixth external terminal 214a, a seventh external terminal 212b, and an eighth external terminal 214b).

[0090] External terminals 212a, 212b, 214a, and 214b on the upper surface 218 are electrically connected to the corresponding external terminals 212a, 212b, 214a, and 214b on the bottom surface 220. Thus, as shown in Figure 2A, the capacitor 200 includes at least two first polarity terminals and at least two second and opposite polarity terminals on the upper surface 218, and the bottom surface 220 also includes at least two first polarity terminals and two second and opposite polarity terminals, although not shown. Furthermore, the first, third, fifth, and seventh external terminals 212a, 212b are electrically connected to the first internal electrode layer 2005 (Figures 2B and 2C), and the second, fourth, sixth, and eighth external terminals 214a, 214b are electrically connected to the second internal electrode layer 2015 (Figures 2B and 2C).

[0091] The same reference numbers used in Figures 1A to 1D are used in Figures 2A to 2D. Generally, the same reference numbers in a figure refer to the same or similar features or components. Therefore, it can be recognized that the body 216 of capacitor 200 is configured in the same way as the body 116 of capacitor 100. For example, the main body portion 216 includes an upper surface 218, a bottom surface 220 facing the upper surface 218 along the height direction T, a first side surface 222 extending between the upper surface 218 and the bottom surface 220 along the height direction T, a second side surface 224 facing the first side surface 222 along the lateral or width direction W and extending between the upper surface 218 and the bottom surface 220, a first end surface 226 extending between the upper surface 218 and the bottom surface 220 along the height direction T, and a second end surface 228 facing the first end surface 226 along the longitudinal or length direction L and extending between the upper surface 218 and the bottom surface 220. The main body portion 216 has a main body length 215 and a main body width 225.

[0092] Furthermore, the upper surface 218 has first and second end edges 230, 232 extending along the lateral direction W between a pair of side surfaces 222, 224. The upper surface 218 also includes first and second side edges 234, 236 extending along the longitudinal direction L between a pair of end surfaces 226, 228. Although not shown in the figure, the bottom surface 220 can be configured similarly to the upper surface 218 and will be recognized as having first and second end edges and first and second side edges.

[0093] The external terminals 212 and 214 of the capacitor 200 are offset from the sides and ends of the capacitor 200. As shown in Figures 2A and 2D, the external terminals 212a, 212b, 214a, and 214b are spaced apart from the first and second side edges 234 and 236 of both the upper surface 218 and the bottom surface 220, respectively, so that only dielectric material is disposed between the external terminals 212a, 212b, 214a, and 214b and the side edges 234 and 236. For example, with respect to the upper surface 218 and the bottom surface 220, the external terminals 212a, 212b, 214a, and 214b are spaced apart from the first side edges 234a, 234b and the second side edges 236a, 236b, respectively, defining a first edge gap 238 between the external terminals 212a, 212b, 214a, and 214b and the first side edges 234a, 234b, and defining a second edge gap 240 between the external terminals 212a, 212b, 214a, and 214b and the second side edges 236a, 236b. Similarly, the external terminals 212a and 214b are positioned at a distance from the first end edges 230a, 230b and the second end edges 232a, 232b of the upper surface 218 and the bottom surface 220, respectively, defining a first end gap 242 between the external terminal 212a and the first end edges 230a, 230b, and a second end gap 244 between the external terminal 214b and the second end edges 232a, 232b.

[0094] The edge gaps 238, 240 and end gaps 242, 244 can be larger than the thickness of the individual layers, for example, larger than the thickness of the individual dielectric layers or individual internal electrode layers 1010 (Figures 1B, 1C). For example, each edge gap 238, 240 and each end gap 242, 244 can be at least twice the thickness of the individual dielectric layer or individual internal electrode layer, for example, at least three times, for example, at least five times, for example, at least ten times, etc. In some embodiments, the first edge gap 238 and the second edge gap 240 can be the same (for example, with respect to a given surface 218, 220, the external electrodes 212a, 212b, 214a, 214b can be at the same distance or equidistant from their respective first side edges 234a, 234b to their respective second side edges 236a, 236b), but in other embodiments, the first edge gap 238 and the second edge gap 240 can be different (for example, with respect to a given surface 218, 220, the external electrodes 212a, 212b, 214a, 214b can be closer to one of the first side edges 234 or the second side edge 236 than to the other side edge of their respective surfaces 218, 220). Similarly, in some embodiments, the first end gap 242 and the second end gap 244 can be the same (for example, with respect to a given surface 218, 220, the external terminal 212a can be at the same distance from the respective first end edges 230a, 230b as the external terminal 214b is at the same distance from the respective second end edges 232a, 232b), but in other embodiments, the first end gap 242 and the second end gap 244 can be different (for example, with respect to a given surface 218, 220, one of the external terminals 212a, 214b can be closer to its adjacent end edges 230, 232 than the other external terminal 212a, 214b is closer to its adjacent end edges 230, 232).

[0095] The capacitor 200 in Figure 2A includes external terminals 212a, 212b, 214a, and 214b, and a set of alternating dielectric layers and internal electrode layers 2010 as shown in Figure 2B. As shown in Figure 2B, the set of alternating dielectric layers and internal electrode layers 2010 includes internal electrode layers 2005, 2015 and dielectric layers (not shown) in an alternating arrangement.

[0096] Generally, the internal electrode layers 2005 and 2015 include at least one lead tab 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, and 2050b extending from the upper and bottom edges of the main body of the internal electrode layer. Generally, the lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, and 2050b of the internal electrode layers 2005 and 2015 extend to the upper and bottom surfaces of the capacitor and help form the external terminals. In this regard, lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, and 2050b are exposed on the upper and lower surfaces of the capacitor, enabling connection between the main body of the internal electrode layer and the external terminals. For example, lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, and 2050b may include leading edges 2023a~b, 2033a~b, 2043a~b, and 2053a~b, and these leading edges extend to the edge of the dielectric layer, enabling the formation of external terminals.

[0097] As illustrated in Figures 2B and 2C, the internal electrode layers 2005 and 2015 include at least two lead tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, and 2050b along their upper and bottom edges, respectively. As illustrated in Figures 2B and 2C, the first internal electrode layer 2005 includes two lead tabs 2020a, 2020b, 2030a, and 2030b along their respective upper and bottom edges 2005c and 2005d, extending from the main body 235. The second internal electrode layer 2015 includes two lead tabs 2040a, 2040b, 2050a, and 2050b along their respective upper and bottom edges, extending from the main body 245.

[0098] The lead tabs 2020a, 2020b, 2030a, and 2030b located at the upper edge 2005c and bottom edge 2005d of the first internal electrode layer 2005 can be aligned vertically. That is, the lateral edges 2021a and 2022a of the first lead tab 2020a along the upper edge 2005c can be aligned with the lateral edges 231a and 232a of the first lead tab 2030a along the bottom edge 2005d on the opposite side of the upper edge 2005c. In other words, the lateral edges 2021a and 2022a of the first lead tab 2020a along the upper edge 2005c can be offset from the side edges 2005a-b by the same distance as the lateral edges 231a and 232a of the first lead tab 2030a along the bottom edge 2005d opposite the upper edge 2005c (indicated by "O"). Also, both lateral edges 2021a and 2022a of the first lead tab 2020a along the upper edge 2005c can be aligned with the lateral edges 231a and 232a of the first lead tab 2030a along the bottom edge 2005d opposite the upper edge 2005c. That is, both lateral edges can be offset from the side edges 2005a-b by the same distance.

[0099] When the upper edge 2005c and the bottom edge 2005d include at least two lead tabs 2020a, 2020b, 2030a, and 2030b, at least one lateral edge of each lead tab on the upper edge 2005c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 2005d. Also, both lateral edges of each lead tab on the upper edge 2005c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 2005d.

[0100] Similarly, the lead tabs 2040a, 2040b, 2050a, and 2050b located at the upper and lower edges of the second internal electrode layer 2015 can be aligned vertically. That is, the lateral edges 2041a and 2042a of the first lead tab 2040a along the upper edge can be aligned with the lateral edges 2051a and 2052a of the first lead tab 2050a along the lower edge opposite the upper edge. Both lateral edges 2041a and 2042a of the first lead tab 2040a along the upper edge can be aligned with the lateral edges 2051a and 2052a of the first lead tab 2050a along the lower edge opposite the upper edge. The relationship between the lateral edge of the first lead tab at the upper edge and the lateral edge of the first lead tab at the bottom edge, as described for the internal electrode layer 2005, can also be applied to the internal electrode layer 2015.

[0101] Such arrangements allow tab gaps to be formed between any of the lead tabs along the upper edge 2005c of the first internal electrode layer 2005, the second internal electrode layer 2015, or both. For example, tab gaps can be formed between any of the lead tabs 2020a-b, 2040a-b extending from the upper edge of each internal electrode layer. Additionally, tab gaps can be formed between any of the lead tabs along the bottom edge 2005d of the first internal electrode layer 2005, the second internal electrode layer 2015, or both. For example, tab gaps can be formed between any of the lead tabs 2030a-b, 2050a-b extending from the bottom edge of each internal electrode layer. Furthermore, the size of the tab gap between each pair of tabs extending from the upper edge (whether from the same internal electrode layer or from adjacent internal electrode layers) can be substantially the same as the size of the tab gap between each of the corresponding tabs extending from the bottom edge. For example, the first tab gap 2016a between lead tab 2020a and lead tab 2020b can be substantially the same as the first tab gap 2018a between lead tab 2030a and lead tab 2030b. Similarly, the second tab gap 2016b between lead tab 2020a and lead tab 2040a can be substantially the same as the second tab gap 2018b between lead tab 2030 and lead tab 2050a.

[0102] Any or all of the lead tabs 2020a, 2020b, 2040a, and 2040b can be arranged in parallel with the lead tabs 2030a, 2030b, 2050a, and 2050b extending from layers 2005 and 2015, respectively, so that the lead tabs extending from the alternating electrode layers 2005 and 2015 can be aligned in their respective columns. For example, the lead tabs 2020a, 2020b and 2030a, 2030b of the internal electrode layer 2005 can be arranged in their respective stacked configurations, while the lead tabs 2040a, 2040b and 2050a, 2050b of the internal electrode layer 2015 can be arranged in their respective stacked configurations.

[0103] It is understood that lead tabs 2020a and 2020b are connected to external terminals 22a and 22b, respectively, while lead tabs 2040a and 2040b are connected to external terminals 24a and 24b, respectively. Therefore, each lead tab 2020a and 2020b will interlock with each other in the same manner as external terminals 22a and 22b and 24a and 24b, respectively. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0104] As shown in Figure 2D, the external terminals 212a, 212b, 214a, and 214b can be positioned at intervals from each other, not only on the sides and ends of the upper surface 218 and bottom surface 220 of the capacitor 200. The external terminals 212a, 212b, 214a, and 214b may include a first end external terminal 212a and a second end external terminal 214a, the first end external terminal 212a being positioned adjacent to the first end surface 226 and the first end edge 230, and the second end external terminal 214a being positioned adjacent to the second end surface 228 and the second end edge 232. The first end external terminal 212a and the second end external terminal 214a are positioned at a distance of 250 in the longitudinal direction L from each other.

[0105] As previously described, the main body portion 216 has a main body portion length 215 in the longitudinal direction L. The ratio of the main body portion length 215 to the end external terminal spacing distance 250 can be 1.1 or greater, and can be, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0106] As further illustrated in Figure 2D, the pitch 252 is defined between adjacent external terminals 212a, 212b, 214a, 214b, for example, between adjacent terminals 212a and 214b, between adjacent terminals 214b and 212b, or between adjacent terminals 212b and 214a. As previously described, the pitch 252 is the nominal distance between the centers of adjacent external terminals, and the pitch 252 can also be referred to as the spacing between the centers of the external terminals. The ratio of the body length 215 to the pitch 252 is 1.1 or greater, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0107] Furthermore, adjacent external terminals 212a, 212b, 214a, and 214b are spaced apart from each other in the longitudinal direction L on the upper surface 228 by the adjacent external terminal spacing distance 254 between adjacent lateral sides of the external terminals. For example, as shown in Figure 2D, the first lateral side 201a of external terminal 212b (the first lateral side 201a facing external terminal 214a) is spaced apart from the first lateral side 201b of external terminal 214a (the first lateral side 201b facing external terminal 212b) by the adjacent external terminal spacing distance 254. The ratio of the main body length 215 to the adjacent external terminal spacing distance 254 is 1.1 or greater, for example, 2 or greater, 5 or greater, 10 or greater, 20 or greater, 100 or greater, or 500 or greater.

[0108] Additionally, as shown in Figure 2A, the capacitor 200 in Figures 2A to 2D includes at least one first polarity terminal and at least one second and opposite polarity terminal on the top surface. Although not shown, the bottom surface includes at least one first polarity terminal and the second and opposite terminals. In particular, Figure 2A includes two positive terminals 212a-b and two negative terminals 214a-b on the top surface.

[0109] As illustrated in Figures 2A to 2D, the capacitor includes four external terminals on each surface, and each internal electrode layer of the capacitor includes two lead tabs extending from the upper and bottom edges of the internal electrode layer, respectively. However, as stated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs in the internal electrode layer.

[0110] Looking at Figures 3A to 3C, a capacitor 300 having a 1x2 configuration is illustrated. That is, the capacitor 300 includes two external terminals arranged in a linear manner in a single dimension on the upper and bottom surfaces of the capacitor. In the embodiment depicted, the capacitor 300 includes external terminals arranged in a linear manner or in a single row along the longitudinal direction L, which can be referred to as a linear terminal arrangement.

[0111] In this regard, the capacitor 300 includes a main body 316 having external terminals 312 and 314, the external terminals 312 and 314 including a first external terminal 312 and a second external terminal 314, the first external terminal 312 being disposed on at least one of the upper surface 318 or the bottom surface 320 and electrically connected to a first internal electrode layer 3005 (Figures 3B and 3C), and the second external terminal 314 being disposed on at least one of the upper surface 318 or the bottom surface 320 and electrically connected to a second internal electrode layer 3015 (Figures 3B and 3C).

[0112] The capacitor 300 illustrated in Figures 3A to 3C is substantially the same as the capacitor 100 in Figures 1A to 1D, and it will be recognized that the same reference numerals as in Figures 1A to 1D are used in Figures 3A to 3C to indicate the same or similar characteristics. However, unlike the external terminals 112 and 114 of capacitor 100, the external terminals 312 and 314 of capacitor 300 are not spaced apart from the end surfaces 326 and 328 of the capacitor body 316. Instead, the external terminal 312 is formed along the first end of the body 316 from the upper surface 318 to the bottom surface 320, with a portion of the external terminal 312 extending along the first end surface 326. Similarly, the external terminal 314 is formed along the second end of the body 316 from the upper surface 318 to the bottom surface 320, with a portion of the external terminal 314 extending along the second end surface 328. Therefore, rather than external terminals formed separately on the upper and lower surfaces as shown in Figures 1A and 1D, the first external electrode 312 is wrapped around from the upper surface 318 to the lower surface 320, and the first external electrode 312 is positioned on the upper surface 318, the first end surface 326, and the lower surface 320, and the second external electrode 314 is wrapped around from the upper surface 318 to the lower surface 320, and the second external electrode 314 is positioned on the upper surface 318, the second end surface 328, and the lower surface 320.

[0113] Furthermore, unlike the lead tabs 1020, 1030, 1040, and 1050 of electrode layers 1005 and 1015, which are offset from the side edge 100a (as indicated by "O" in Figure 1B), the lead tabs 3020, 3030, 3040, and 3050 of electrode layers 3005 and 3015 are not offset from the side edge 3005a. Thus, the lateral edges 3021, 3031, 3042, and 3052 of the lead tabs 3020, 3030, 3040, and 3052, and the side edge 3005a of electrode layers 3005 and 3015 extend to the ends 326 and 328 of the capacitor body 316, making it possible to assist in the formation of external electrodes 312 and 314 along, for example, the end surfaces 326 and 328.

[0114] Additionally, the embodiment shown in the figure uses only two internal electrode layers in a stack of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention can and is not necessarily limited to any number of internal electrode layers as shown herein.

[0115] Generally, the present invention provides a capacitor having a unique configuration that offers various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and can be any materials commonly used in the art, and can be formed using any methods commonly used in the art.

[0116] Generally, dielectric layers are typically formed from materials having a relatively high dielectric constant (K), such as about 10 to about 40,000 in some embodiments, about 50 to about 30,000 in some embodiments, and about 100 to about 20,000 in some embodiments.

[0117] In this regard, the dielectric material can be a ceramic. Ceramics can be provided in various forms, such as wafers (e.g., pre-sintered) or as dielectric materials co-sintered within the device itself.

[0118] Specific examples of high dielectric material types include, for example, NPO(COG) (up to about 100), X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be noted that the materials described above are described by their industry-recognized definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and therefore should be recognized by those skilled in the art. For example, such materials may include ceramics. Such materials may include perovskites, for example, barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate, etc. In one particular embodiment, for example, chemical formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 can be used, where x is from 0 to 1, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO3 (where x is approximately 0.2 to approximately 0.8, and in some embodiments approximately 0.4 to approximately 0.6), Pb x Zr 1-xTiO3("PZT") (where x ranges from about 0.05 to about 0.4), lead lanthanum zirconate titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconate titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Additionally, further composite perovskites are A[B1 1 / 3 B2 2 / 3 O3 materials (where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), and B2 is Ta z Nb 1-z (z can be a value from 0 to 1)). In one particular embodiment, the dielectric layer can include titanate.

[0119] The internal electrode layer can be formed from any of a variety of different metals as known in the art. The internal electrode layer can be made from metals such as conductive metals. The materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold respectively, may also be suitable. In one particular embodiment, the internal electrode layer can include nickel or its alloy.

[0120] The external terminals can be formed from any of a variety of different metals as known in the art. The external terminals can be made from metals such as conductive metals. The materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In one particular embodiment, the external terminals can include copper or its alloys.

[0121] The external terminals can be formed using any method generally known in the art. The external terminals can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying / airbrushing, etc.

[0122] The external terminals can be formed such that the external terminals are a thin film plating of metal. Such a thin film plating can be formed by depositing a conductive material (e.g., a conductive metal, etc.) on an exposed portion of the internal electrode layer. For example, the leading edge of the internal electrode layer can be exposed such that it can enable the formation of plated terminations.

[0123] The external terminals can have an average thickness from about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less, such as about 20 μm or less, to about 5 μm or more, such as about 10 μm or more, such as about 15 μm or more. For example, the external terminals can have an average thickness from about 5 μm to about 50 μm, such as from about 10 μm to about 40 μm, such as from about 15 μm to about 30 μm, such as from about 15 μm to about 25 μm.

[0124] Generally, external terminals can include plated terminals. For example, external terminals can include electroplated terminals, electroless plated terminals, or a combination thereof. For example, electroplated terminals can be formed via electroplating. Electroless plated terminals can be formed via electroless plating.

[0125] When multiple layers constitute an external terminal, the external terminal can include electroplated and electroless plated terminals. For example, electroless plating can be used first to deposit the initial layer of material. The plating technique can then be switched to an electrochemical plating system, which can enable faster accumulation of the material.

[0126] When forming terminals plated by any of the plating methods, the leading edges of the lead tabs of the internal electrode layer exposed from the body of the capacitor are exposed to the plating solution. By exposure, in one embodiment, the capacitor can be immersed in the plating solution.

[0127] The plating solution contains a conductive material (e.g., a conductive metal) and is used to form a plated end. Such a conductive material can be any of the materials described above or any that is commonly known in the art. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solution, so that the plated layer and the outer terminal contain nickel. Alternatively, the plating solution can be a copper acid bath or other suitable copper solution, so that the plated layer and the outer terminal contain copper.

[0128] Additionally, it should be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. Furthermore, the additives may be used to use the plating solution at a desired pH. In one embodiment, a resistance-reducing additive may be used in the solution to assist in complete plating, as well as in the bonding of the plating material to the exposed leading edges of the lead tabs of the capacitor and internal electrode layers.

[0129] The capacitor can be exposed, submerged, or immersed in a plating solution for a predetermined amount of time. Such exposure time is not necessarily limited, but can be long enough to allow sufficient plating material to deposit to form plated terminals. In this regard, the time should be sufficient to allow the formation of continuous connections between the desired exposed adjacent leading edges of the lead tabs of a given polarity in each internal electrode layer within a set of alternating dielectric and internal electrode layers.

[0130] Generally, the difference between electrolytic and electroless plating is that electrolytic plating uses an electrical bias (for example, by using an external power supply). Electrolytic plating solutions typically have a high current density range, e.g., 10 to 15 amp / ft. 2 It may be exposed to (rated 9.4 volts). The connection can be formed by a negative connection to the capacitor, which requires the formation of plated terminals, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite to the polarity of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the internal electrode layer.

[0131] Various pretreatment steps can be used before immersing or exposing the capacitors to the plating solution. Such steps can be performed for a variety of purposes, including catalytically accelerating, and / or improving, the adhesion of the plating material to the leading edge of the lead tabs.

[0132] Additionally, an initial cleaning step may be used prior to plating or any other pretreatment step. Such a step may be used to remove any oxide buildup that may form on the exposed lead tabs of the internal electrode layer. This cleaning step may be particularly useful in assisting the removal of any nickel oxide buildup when the internal electrode or other conductive element is formed from nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning tank (e.g., one containing an acid cleaner). In one embodiment, the exposure can be over a predetermined time (e.g., on the order of about 10 minutes). Alternatively, cleaning can be achieved by a chemical polishing or hyper-rising step.

[0133] In addition, to promote the deposition of conductive materials, a step may be performed to activate the exposed metal leading edge of the lead tab of the internal electrode layer. Activation can be achieved by immersion in a palladium salt, a photo-patterned palladium organometallic precursor (via a mask or laser), a screen-printed or inkjet-deposited palladium compound, or an electrophoretic palladium deposit. It should be recognized that the palladium-based activation is disclosed merely as an example of an activating solution, which often works well for activating exposed tab portions formed from nickel or its alloys. However, it should be understood that other activating solutions may be used and are therefore not necessarily limited.

[0134] Furthermore, instead of or in addition to the activation step described above, the activating dopant can be introduced into the conductive material when forming the internal electrode layer of the capacitor. For example, when the internal electrode layer contains nickel and the activating dopant contains palladium, the palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layer. Doing so makes it possible to eliminate the palladium activation step. It should be further understood that some of the above activation methods, such as organometallic precursors, are also useful for co-deposition of glass-forming agents to improve adhesion to the generally ceramic body of the capacitor. When the activation step is performed as described above, traces of the activating material may often remain on the exposed conductive portion before and after terminal plating.

[0135] Additionally, post-plating treatment steps may be used as desired or as needed. Such steps may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step may be used after the plating step has been carried out. Such heating may be performed via baking, laser subjecting, UV exposure, microwave exposure, arc welding, etc.

[0136] As shown herein, the external terminal includes at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may include a third plating layer. Furthermore, the materials of these plating layers may be any of those described above, or may be those commonly known in the art.

[0137] For example, one plating layer (e.g., a first plating layer) may contain copper or an alloy thereof. Another plating layer (e.g., a second plating layer) may contain nickel or an alloy thereof. Alternatively, another plating layer (e.g., a second plating layer) may contain copper or an alloy thereof. Another plating layer (e.g., a third plating layer) may contain tin, lead, gold, or a combination thereof (e.g., an alloy). Alternatively, the initial plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, an initial copper plating layer may be formed, followed by a nickel layer.

[0138] In one embodiment, the initial plating layer or first plating layer can be a conductive metal (e.g., copper). This area can then be covered by a second layer containing a resistive polymer material for sealing. The area can then be polished to selectively remove the resistive polymer material and then re-plated with a third layer containing a conductive metallic material (e.g., copper).

[0139] The aforementioned second layer above the initial plating layer can correspond to a solder barrier layer (e.g., a nickel-solder barrier layer). In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel or copper) onto the initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for the layer (the aforementioned solder barrier layer) include nickel-phosphorus, gold, and silver. In some embodiments, the aforementioned third layer above the solder barrier layer can correspond to a conductive layer (e.g., plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder).

[0140] In addition, a layer of metal plating may be formed, followed by an electroplating step to provide a resistive alloy or a higher resistive metal alloy coating (e.g., electroless Ni-P alloy) on such metal plating. However, it should be understood that any metal coating is possible, as will be understood by those skilled in the art from the full disclosure herein.

[0141] It should be recognized that any of the steps described above can occur as a bulk process, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes (all of which are commonly known in the art). Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminations, which requires processing of individual components).

[0142] As described herein, the formation of external terminals is generally guided by the position of the exposed leading edge of the lead tab of the internal electrode layer. Such a phenomenon can be referred to as "self-determinism" because the formation of the externally plated terminals is determined by the configuration of the exposed conductive metal of the internal electrode layer at selected peripheral locations on the capacitor.

[0143] Additional aspects of the above techniques for forming thin-film plated terminations are described in U.S. Patents 7,177,137 and 7,463,474 by Ritter et al., which are incorporated herein by reference for all purposes. It should be recognized that additional techniques for forming capacitor terminals may also be within the scope of this technique. Exemplary alternatives, but not limited to, include forming terminations by plating, magnetization, masking, electrophoresis / static, sputtering, vacuum deposition, printing, or other techniques for forming either a thick or thin conductive layer.

[0144] Furthermore, the capacitor can then be exposed to a solder mask. For example, this can allow the capacitor to be coated. Although not intended to be limiting, such a mask can help prevent oxidation of plated layers (e.g., copper-plated layers, etc.) (especially when such layers are the final plating layers for external terminals). Such solder mask materials may not necessarily be limited by the present invention. For example, such materials may include any of the materials described above with respect to the solder barrier layer. In addition or alternatively, such materials may include epoxy (e.g., liquid epoxy that is then cured, etc.).

[0145] When providing such a material on a capacitor, it may be necessary to access the plating layer and external terminals to form electrical connections. In this regard, a laser can be used to form holes through the mask layer. Such holes can then be filled with a conductive material (e.g., copper). This can then be used to form electrical connections with the capacitor.

[0146] Referring to Figures 4 and 5, capacitors such as those disclosed herein can be mounted using a variety of means. For example, a capacitor can be mounted on a circuit board including a substrate (e.g., an insulating layer) having an upper surface and a lower surface. Referring to Figure 4, a capacitor 300 as shown in Figure 3A is mounted on a circuit board 450 having an upper surface 452 and a lower surface 454. The circuit board 450 has a number of defined current paths therein. The external terminals 312 and 314 of the capacitor 300 are electrically in communication with the predetermined current paths of the circuit board 450, respectively. In addition, the external terminals 312 and 314 of the capacitor 300 can be physically connected to the circuit board 450 using any method commonly known in the art, such as a general soldering technique. It will be recognized that capacitor 300 is used merely as an example, and in other embodiments, capacitors 100 and / or capacitor 200 can be mounted on mounting surfaces such as the circuit board 450.

[0147] As illustrated in Figure 5, the integrated circuit package 560 may also be supplied on a circuit board 550. The integrated circuit package 560 may be connected to the circuit board 550 using a ball grid array 562. The circuit board may further include a processor 564. The processor 564 may similarly be connected to the integrated circuit package 560 using a ball grid array 566.

[0148] Generally, the ball grid array 562 can be configured such that the pitch is 1.5 mm or less, for example 1.25 mm or less, for example 1 mm or less, for example 0.8 mm or less, for example 0.6 mm or less, and 0.4 mm or more, for example 0.5 mm or more, for example 0.6 mm or more.

[0149] In addition, the integrated circuit package 560 can also be connected to the circuit board 550 using capacitors 100 / 200 / 300 as defined herein. In this regard, the internal electrode layers of the capacitors 100 / 200 / 300 can be positioned so that they are orthogonal to the horizontal plane of the circuit board 550 and the integrated circuit package 560. In other words, the internal electrode layers of the capacitors 100 / 200 / 300 can be positioned so that they are substantially non-parallel to the circuit board 550. For example, the capacitors 100 / 200 / 300 can be positioned between the integrated circuit package 560 and the circuit board 550, such that the capacitor 608 is "sandwiched" between the two components. In this regard, the capacitors 100 / 200 / 300 are directly connected to the integrated circuit package 560 and the circuit board 550. For example, capacitors 100 / 200 / 300 can be connected (e.g., physically and / or electrically) to the circuit board 550 and / or the circuit package 560 using any method commonly known in the art, such as general soldering techniques.

[0150] By using capacitors in the arrangement described above, capacitors 100 / 200 / 300 can be removed from the original ball grid array 562. However, capacitors 100 / 200 / 300 can still be surrounded by the ball grid array 562, as illustrated in Figure 5.

[0151] Therefore, as shown in Figure 5, the capacitors 100 / 200 / 300 of the present invention can be directly connected to the integrated circuit package 560 and the circuit board 550 (e.g., a printed circuit board). This direct connection allows current 568 to flow through the capacitor, thereby providing a direct power-ground connection.

[0152] In addition to the above, although not illustrated herein, in one embodiment the integrated circuit package itself can include a multilayer capacitor. In this regard, the capacitor can be directly embedded within the package. Such incorporation of the capacitor can allow for size reduction, which may be beneficial for a variety of electronic applications.

[0153] The foregoing provides one example of a means for mounting capacitors as disclosed herein, but it should be understood that other methods may also be available. For example, capacitors can be mounted via a land grid array configuration. Alternatively, capacitors can be embedded within another substrate or component.

[0154] In the embodiments referenced above, the internal electrode layer is generally oriented in a vertical configuration. Of course, this is not always necessary, and it is equally appropriate to use other geometric configurations (e.g., a horizontal configuration).

[0155] These and other modifications and variations of the present invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the aspects of the various embodiments can be interchanged, both in whole and in part. Furthermore, those skilled in the art will understand that the foregoing description is merely illustrative and not intended to limit the invention, and that the invention is further described in such appended claims. [Explanation of Symbols]

[0156] 100 multilayer capacitors 112 First external terminal 114 Second external terminal 115 Main body length 116 Main body 118 Upper surface 120 Bottom surface 122 First side surface 124 Second side surface 125 Main body width 126 First end surface 128 Second end surface 130a First end edge 130b First end edge 130 First end edge 130a First upper end edge 130b First bottom edge 132 Second end edge 132a Second upper end edge 132b Second bottom edge 134 First lateral edge 134a First upper side edge 134b First bottom side edge 136 Second lateral edge 136a Second upper side edge 136b Second bottom side edge 138 First edge gap 140 Second edge gap 142 First end gap 144 Second end gap 150 End external terminal spacing distance 152 pitch 200 Capacitors 201a First lateral side of external terminal 212b 201b First lateral side of external terminal 214a 212a First external terminal 212b Third external terminal 214a Second external terminal 214b Fourth external terminal 215 Main body length 216 Main body 218 Upper surface 220 Bottom surface 222 First side surface 224 Second side surface 225 Main body width 226 First end surface 228 Second end surface 230a First end edge 230b First end edge 230 First end edge 230a First upper end edge 230b First bottom edge 232 Second end edge 232a Second upper end edge 232b Second bottom edge 234 First lateral edge 234a First upper side edge 234b First bottom side edge 235 Main body 236 Second lateral edge 236a Second upper side edge 236b Second bottom side edge 238 First edge gap 240 Second edge gap 242 First end gap 244 Second end gap 250 End external terminal spacing distance 252 pitch 254 Distance between adjacent external terminals 300 Capacitors 312 First external terminal 314 Second external terminal 315 Main body length 316 Main body 318 Upper surface 320 bottom surface 322 First side surface 324 Second side surface 325 Main body width 326 First end surface 328 Second end surface 330a First end edge 330b First end edge 330 First end edge 330a First upper end edge 330b First bottom edge 332 Second end edge 332a Second upper end edge 332b Second bottom edge 334 First lateral edge 334a First upper side edge 334b First bottom side edge 336 Second lateral edge 336a Second upper side edge 336b Second bottom side edge 338 First edge gap 340 Second edge gap 450 Circuit Boards 452 Upper surface 454 Lower surface 550 Circuit Board 560 Integrated Circuit Package 562 Ball Grid Array 564 processors 566 Ball Grid Array 568 Current 1005 First internal electrode layer 1005a Side edge 1005b Side edge 1005c Upper edge 1005d bottom edge 1010 Internal electrode layer 1015 Second internal electrode layer 1016 Tab Gap 1018 Tab Gap 1020 Lead Tabs 1021 Lateral edge 1022 Lateral edge 1023 Front edge 1030 Lead Tab 1031 Lateral edge 1032 Lateral edge 1033 Front edge 1035 Main body 1040 Lead Tabs 1041 Lateral edge 1042 Lateral edge 1043 Front edge 1050 Lead Tabs 1051 Lateral edge 1052 Lateral edge 1053 Front edge 2005 First internal electrode layer 2005a Side edge 2005b Side edge 2005c Upper edge 2005d bottom edge 2010 Internal electrode layer 2015 Second internal electrode layer 2016a First tab gap 2016b Second tab gap 2018a First tab gap 2018b Second tab gap 2020a Lead Tab 2020b Lead Tab 2021a Lateral edge 2021b Lateral edge 2022a Lateral edge 2022b Lateral edge 2023a Leading edge 2023b Leading edge 2030a Lead Tab 2030b Lead Tab 2031a Lateral edge 2031b Lateral edge 2032a Lateral edge 2032b Lateral edge 2033a Leading edge 2033b Leading edge 2035 Main body 2040a Lead Tab 2040b Lead Tab 2041a Lateral edge 2041b Lateral edge 2042a Lateral edge 2042b Lateral edge 2043a Leading edge 2043b Leading edge 2050a Lead Tab 2050b Lead Tab 2051a Lateral edge 2051b Lateral edge 2052a Lateral edge 2052b Lateral edge 2053a Leading edge 2053b Leading edge 3005 First internal electrode layer 3005a Side edge 3005b Side edge 3005c Upper edge 3005d bottom edge 3010 Internal electrode layer 3015 Second internal electrode layer 3020 Lead Tab 3021 Lateral edge 3022 Lateral edge 3023 Front edge 3030 Lead Tab 3031 Lateral edge 3032 Lateral edge 3033 Front edge 3035 Main body 3040 Lead Tab 3041 Lateral edge 3042 Lateral edge 3043 Front edge 3050 Lead Tab 3051 Lateral edge 3052 Lateral edge 3053 Front edge L Longitudinal direction, length direction O Offset T Vertical direction, height direction W (horizontal direction, width direction)

Claims

1. A multilayer capacitor, wherein the multilayer capacitor is The main body comprises an upper surface, a bottom surface opposite the upper surface, a pair of side surfaces facing each other along the lateral direction, and a pair of end surfaces facing each other along the longitudinal direction, and the main body also comprises a side edge defining the lateral boundary of the upper surface and the bottom surface, the side edge comprising a first upper side edge, a second upper side edge, a first bottom side edge, and a second bottom side edge, each extending along the longitudinal direction between the pair of end surfaces, the first upper side edge and the second upper side edge facing each other along the lateral direction, the main body comprises alternating dielectric layers and internal electrode layers, the internal electrode layers comprising a first internal electrode layer and a second internal electrode layer, each internal electrode layer is A main body having an upper edge, a bottom edge opposite the upper edge, and two side edges extending between the upper edge and the bottom edge, The internal electrode layer comprises at least one lead tab extending from the upper edge of the main body portion, and at least one lead tab extending from the bottom edge of the main body portion. The main body, An external terminal comprising a first external terminal and a second external terminal, wherein the first external terminal is disposed on at least one of the upper surface or the bottom surface and is electrically connected to the first internal electrode layer, and the second external terminal is disposed on at least one of the upper surface or the bottom surface and is electrically connected to the second internal electrode layer, and Includes, A multilayer capacitor in which the external terminals are arranged in a linear manner on at least one of the upper surface or the bottom surface of the main body, spaced apart from the side edge of the main body, and only dielectric material is disposed between the external terminals and the side edge of the main body.

2. The first external terminal is disposed adjacent to the first end surface of the pair of end surfaces of the main body, and the second external terminal is disposed adjacent to the second end surface of the pair of end surfaces of the main body. The first external terminal and the second external terminal are arranged on the upper surface at a distance equal to the end external terminal spacing distance in the longitudinal direction. The main body portion has a length in the longitudinal direction, The multilayer capacitor according to claim 1, wherein the ratio of the length of the main body to the distance between the end external terminals is 1.1 or more.

3. The multilayer capacitor according to claim 2, wherein the ratio of the length of the main body to the distance between the end external terminals is within the range of 2 to 500.

4. The multilayer capacitor according to claim 2, wherein the ratio of the length of the main body to the distance between the end external terminals is within the range of 10 to 100.

5. The first external terminal is disposed adjacent to the first end surface of the pair of end surfaces of the main body, and the second external terminal is disposed adjacent to the second end surface of the pair of end surfaces of the main body. The first external terminal is formed on the upper surface, the bottom surface, and the first end surface, extending from the upper surface to the bottom surface, and the first external terminal is disposed on the upper surface, the bottom surface, and the first end surface. The multilayer capacitor according to claim 1, wherein the second external terminal is formed on the upper surface, the bottom surface, and the second end surface, extending from the upper surface to the bottom surface, and the second external terminal is disposed on the upper surface, the bottom surface, and the second end surface.

6. The multilayer capacitor according to claim 1, wherein the external terminals are arranged in at least two rows, and the at least two rows are spaced apart from each other along the longitudinal direction.

7. The multilayer capacitor according to claim 6, wherein the number of rows of external terminals is equal to the number of lead tabs extending from the upper edge of the main body portion of one internal electrode layer.

8. The main body portion has end edges that define the longitudinal boundary of the upper surface and the bottom surface, and the end edges include a first upper end edge, a second upper end edge, a first bottom end edge, and a second bottom end edge that extend along the transverse direction between the pair of side surfaces, the first upper end edge and the second upper end edge face each other along the longitudinal direction, and the first bottom end edge and the second bottom end edge face each other along the longitudinal direction. The multilayer capacitor according to claim 1, wherein the external terminals are arranged at a distance from the end edge of the main body, and only the dielectric material is disposed between the external terminals and the end edge of the main body.

9. The external terminals include adjacent terminals that are spaced apart from each other in the longitudinal direction on the upper surface by a distance equal to the distance between adjacent external terminals. The main body portion has a length in the longitudinal direction, The multilayer capacitor according to claim 1, wherein the ratio of the length of the main body to the distance between adjacent external terminals is 1.1 or more.

10. The multilayer capacitor according to claim 9, wherein the ratio of the length of the main body to the distance between adjacent external terminals is within the range of 2 to 500.

11. The multilayer capacitor according to claim 9, wherein the ratio of the length of the main body to the distance between adjacent external terminals is in the range of 10 to 100.

12. The external terminals include adjacent terminals located adjacent to the first external terminal on the same surface of the main body, and the first external terminal and the adjacent terminals are arranged on the same surface at a distance equal to the distance between adjacent external terminals, separated from each other in the longitudinal direction. The multilayer capacitor according to claim 2, wherein the ratio of the distance between end external terminals to the distance between adjacent external terminals is 1.1 or more.

13. The multilayer capacitor according to claim 12, wherein the ratio of the distance between end external terminals to the distance between adjacent external terminals is in the range of 2 to 500.

14. The multilayer capacitor according to claim 12, wherein the ratio of the distance between end external terminals to the distance between adjacent external terminals is in the range of 10 to 100.

15. The pitch is defined between adjacent external terminals. The main body portion has a length in the longitudinal direction, The multilayer capacitor according to claim 1, wherein the ratio of the length of the main body to the pitch is 1.1 or more.

16. The multilayer capacitor according to claim 15, wherein the ratio of the length of the main body to the pitch is within the range of 2 to 500.

17. The multilayer capacitor according to claim 15, wherein the ratio of the length of the main body to the pitch is in the range of 10 to 100.

18. The multilayer capacitor according to claim 1, wherein the first external terminal is disposed on the upper surface of the main body, the second external terminal is disposed on the upper surface of the main body, the external terminal further includes a third external terminal and a fourth external terminal, the third external terminal is disposed on the bottom surface and electrically connected to the first internal electrode layer, and the fourth external terminal is disposed on the bottom surface and electrically connected to the second internal electrode layer.

19. The multilayer capacitor according to claim 1, wherein the first internal electrode layer and the second internal electrode layer are interleaved in a facing relationship, and the dielectric layer is positioned between the first internal electrode layer and the second internal electrode layer, respectively.

20. The multilayer capacitor according to claim 19, wherein the dielectric layer includes ceramic.

21. The multilayer capacitor according to claim 1, wherein each internal electrode layer includes at least two lead tabs, the at least two lead tabs extending from the upper edge of the main body, the bottom edge of the main body, or both the upper edge and the bottom edge of the main body, and the two lead tabs include a first lead tab and a second lead tab.

22. The first lead tab extends from the upper edge, and the second lead tab extends from the bottom edge. The multilayer capacitor according to claim 21, wherein at least one lateral edge of the first lead tab is substantially aligned with at least one lateral edge of the second lead tab.

23. The first lead tab extends from the upper edge, and the second lead tab extends from the bottom edge. Each of the first lead tab and the second lead tab includes two lateral edges, The multilayer capacitor according to claim 21, wherein both lateral edges of the first lead tab are substantially aligned with the respective lateral edges of the second lead tab.

24. The multilayer capacitor according to claim 1, wherein at least one lateral edge of the lead tab located at the upper edge is substantially aligned with at least one lateral edge of the lead tab located at the bottom edge.

25. The multilayer capacitor according to claim 1, wherein both lateral edges of the lead tabs on the upper edge are substantially aligned with the respective lateral edges of the lead tabs on the bottom edge.

26. The multilayer capacitor according to claim 1, wherein the at least one lead tab extending from the upper edge of the main body portion of the internal electrode layer and the at least one lead tab extending from the bottom edge of the main body portion of the internal electrode layer include a lateral edge aligned with the side edge of the main body portion of the internal electrode layer.

27. The multilayer capacitor according to claim 1, wherein the internal electrode layer includes a conductive metal.

28. The multilayer capacitor according to claim 1, wherein the external terminal includes an electroplated layer.

29. The multilayer capacitor according to claim 1, wherein the external terminal includes an electroless plated layer.

30. The multilayer capacitor according to claim 1, wherein the external terminal includes an electroless plated layer and an electroplated layer.

31. The multilayer capacitor according to claim 1, wherein the external terminal includes a first electroless plated layer, a second electroplated layer, and a third electroplated layer.

32. The multilayer capacitor according to claim 31, wherein the first electroless plated layer contains copper, the second electroplated layer contains nickel, and the third electroplated layer contains tin.

33. The multilayer capacitor according to claim 1, wherein the capacitor comprises at least three sets of alternating dielectric layers and internal electrode layers.

34. A circuit board comprising a multilayer capacitor as described in claim 1, wherein the multilayer capacitor is positioned on the circuit board.

35. The circuit board according to claim 34, wherein the substrate further includes an integrated circuit package, the multilayer capacitor is positioned vertically between the circuit board and the integrated circuit package, and the circuit board, the multilayer capacitor, and the integrated circuit package are in a stacked arrangement.

36. The circuit board according to claim 35, wherein the multilayer capacitor is directly connected to the circuit board and the integrated circuit package.

37. An integrated circuit package comprising a multilayer capacitor as described in claim 1.

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