Display boards and display devices

Abstract

The display board comprises a substrate substrate, a bottom metal layer 10, and a gate drive circuit. The substrate substrate comprises a display area AA and a peripheral area BB located around the display area AA. The bottom metal layer 10 and the gate drive circuit are located in the peripheral area BB, and the bottom metal layer 10 is electrically connected to at least one type of signal line. The gate drive circuit is located on the side of the bottom metal layer 10 away from the substrate substrate. The gate drive circuit comprises a plurality of first circuit units. The orthographic projection of the bottom metal layer 10 on the substrate substrate and the orthographic projection of at least one first circuit unit on the substrate substrate overlap at least partially.

Description

Technical Field

[0001] This article relates to the display technology field, but is not limited thereto, and particularly relates to a display substrate and a display device.

Background Art

[0002] With the development of display technology, the market's requirements for the screens of display products are becoming increasingly high. Not only the display effect of display products is required, but also it is required that display products maintain a normal display effect under more adverse conditions. For example, it is required that display products operate normally in environments such as high temperature, low temperature, or high static electricity.

Summary of the Invention

[0003] The following is an overview of the themes that will be described in detail in this article. This overview is not for limiting the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In one aspect, embodiments of the present disclosure provide a display substrate, which includes a substrate substrate, a bottom metal layer, and a gate driving circuit. The substrate substrate includes a display area and a peripheral area located around the display area. The bottom metal layer is located in the peripheral area and is electrically connected to at least one type of signal line. The gate driving circuit is located in the peripheral area and is located on the side of the bottom metal layer away from the substrate substrate. The gate driving circuit includes a plurality of first circuit units. The orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of at least one first circuit unit on the substrate substrate at least partially overlap.

[0006] In some exemplary embodiments, the at least one first circuit unit comprises at least one transistor. The orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the active layer of the at least one transistor of the at least one first circuit unit on the substrate substrate overlap at least partially.

[0007] In some exemplary embodiments, the active layer of the at least one transistor comprises at least one channel region, and the orthogonal projection of the bottom metal layer on the substrate substrate covers the orthogonal projection of the channel region of the active layer of the at least one transistor on the substrate substrate.

[0008] In some exemplary embodiments, the at least one first circuit unit comprises a plurality of transistors. The orthographic projection of the bottom metal layer on the substrate substrate covers the orthographic projection of the active layer of the plurality of transistors of the at least one first circuit unit on the substrate substrate.

[0009] In some exemplary embodiments, the at least one first circuit unit comprises an input subcircuit and a first control subcircuit, the input subcircuit configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line, and the first control subcircuit configured to control the potential of a second shift node under the control of the first clock signal line and the first shift node. The first control subcircuit is electrically connected to the second shift node via a node relay electrode. The orthographic projection of the bottom metal layer on the substrate and the orthographic projection of the node relay electrode on the substrate overlap at least partially.

[0010] In some exemplary embodiments, the at least one first circuit unit comprises an input subcircuit, a first control subcircuit, and a second control subcircuit, wherein the input subcircuit is configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line, the first control subcircuit is configured to control the potential of a second shift node under the control of the first clock signal line and the first shift node, and the second control subcircuit is configured to conduct the first shift node and the third shift node under the control of a second power line. The input subcircuit, the first control subcircuit, and the second control subcircuit are electrically connected to the first shift node via a first connecting electrode. The orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the first connecting electrode on the substrate substrate overlap at least partially.

[0011] In some exemplary embodiments, the at least one first circuit unit comprises a second control subcircuit and an output subcircuit, the second control subcircuit configured to conduct a first shift node and a third shift node under the control of a second power line, and the output subcircuit configured to control the output signals at the shift output terminals under the control of the second shift node and the third shift node. The second control subcircuit and the output subcircuit are electrically connected to the third shift node via a seventh connecting electrode. The orthogonal projection of the bottom metal layer on the substrate covers the orthogonal projection of the seventh connecting electrode on the substrate.

[0012] In some exemplary embodiments, the at least one first circuit unit comprises at least one capacitor, and the orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the at least one capacitor of the at least one first circuit unit on the substrate substrate overlap at least partially.

[0013] In some exemplary embodiments, the bottom metal layer comprises a plurality of first metal blocks, the orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate overlap at least partially, the plurality of first metal blocks form a single structure, and are electrically connected to the same type of signal lines.

[0014] In some exemplary embodiments, the integral structure formed from the plurality of first metal blocks is a planar metal block and does not have any cavities.

[0015] In some exemplary embodiments, the at least one first metal block has a first cavity, the at least one first circuit unit comprises an output transistor, and the orthographic projection of the first cavity of the at least one first metal block on the substrate substrate and the orthographic projection of the doping region of the active layer of the output transistor on the substrate substrate partially overlap.

[0016] In some exemplary embodiments, a cavity region is provided between at least two adjacent first metal blocks.

[0017] In some exemplary embodiments, the gate drive circuit further comprises a plurality of cascaded second circuit units, the plurality of cascaded second circuit units located on the side of the plurality of first circuit units away from the display area, at least one second circuit unit being electrically connected to a first output connection line, the first output connection line extending toward the display area, and the orthographic projection of the first output connection line on the substrate substrate and the orthographic projection of the cavity area between adjacent first metal blocks on the substrate substrate partially overlap.

[0018] In some exemplary embodiments, the gate drive circuit further comprises a plurality of cascaded second circuit units, the plurality of cascaded second circuit units located away from the display area of ​​the plurality of first circuit units, the bottom metal layer further comprises a plurality of second metal blocks, the plurality of second metal blocks located away from the display area of ​​the plurality of first metal blocks, and the orthographic projection of at least one of the plurality of second metal blocks on the substrate substrate overlaps at least partially with the orthographic projection of one or more second circuit units on the substrate substrate. The plurality of second metal blocks are integrally constructed and are electrically connected to different types of signal lines than the plurality of first metal blocks.

[0019] In some exemplary embodiments, the bottom metal layer comprises a plurality of first metal blocks, wherein the orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate overlap at least partially. At least two of the plurality of first metal blocks are electrically connected to different types of signal lines.

[0020] In some exemplary embodiments, the gate drive circuit comprises a plurality of cascaded first circuit units and a plurality of cascaded second circuit units, wherein the plurality of cascaded second circuit units are located on the side of the plurality of cascaded first circuit units away from the display area, and the bottom metal layer comprises a plurality of first metal blocks and a plurality of second metal blocks, wherein the plurality of second metal blocks are located on the side of the plurality of first metal blocks away from the display area. The orthographic projection of at least one first metal block on the substrate board and the orthographic projection of one or more first circuit units on the substrate board overlap at least partially. The orthographic projection of at least one second metal block among the plurality of second metal blocks on the substrate board and the orthographic projection of one or more second circuit units on the substrate board overlap at least partially. At least one second metal block is connected to the same type of signal lines as at least one first metal block.

[0021] In some exemplary embodiments, the plurality of second metal blocks and the plurality of first metal blocks are integrally structured.

[0022] In some exemplary embodiments, the at least one type of signal line includes at least one of peripheral power lines, clock signal lines, and first pixel power lines.

[0023] In some exemplary embodiments, the display area is provided with a plurality of pixel circuits and a plurality of pixel metal blocks, the plurality of pixel circuits being electrically connected to the first pixel power supply wiring. At least one pixel circuit includes a drive transistor, and the orthographic projection of at least one pixel metal block on the substrate substrate and the orthographic projection of the active layer of the drive transistor of at least one pixel circuit on the substrate substrate overlap at least partially. The first metal block of the bottom metal layer is electrically connected to the first pixel power supply wiring via the at least one pixel metal block.

[0024] In some exemplary embodiments, an edge of the bottom metal layer includes at least one of a convex angle and a concave angle, and at least one of the convex angle and the concave angle is a rounded angle.

[0025] In another aspect, embodiments of the present disclosure provide a display device, which includes the above-mentioned display substrate.

[0026] After reading and understanding the accompanying drawings and the detailed description, other aspects can be understood.

Brief Description of the Drawings

[0027] The drawings are for better understanding the technical solutions of the present disclosure, and form a part of the specification. They are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, rather than to limit the technical solutions of the present disclosure. The shapes and sizes of one or more components in the drawings do not reflect the actual scale, and are only intended to schematically illustrate the content of the present disclosure.

[0028] [Figure 1] FIG. 1 is a schematic plan view of a display substrate. [Figure 2] FIG. 2 is a schematic operating view of a display substrate under an electrostatic field. [Figure 3] FIG. 3 is an equivalent circuit diagram of a scanning driving sub-circuit in at least one embodiment of the present disclosure. [Figure 4] FIG. 4 is an operating timing diagram of the scanning driving sub-circuit of the scanning driving circuit shown in FIG. 3. [Figure 5] FIG. 5 is a partial schematic plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 6A] FIG. 6A is a partial schematic plan view of a peripheral region after the bottom metal layer is formed in FIG. 5. [Figure 6B] FIG. 6B is a partial schematic plan view of a peripheral region after the semiconductor layer is formed in FIG. 5. [Figure 6C] FIG. 6C is a partial schematic plan view of a peripheral region after the first conductive layer is formed in FIG. 5. [Figure 6D] Figure 6D is a schematic partial plan view of the peripheral region after the second conductive layer has been formed in Figure 5. [Figure 6E] Figure 6E is a schematic partial plan view of the surrounding region after the fourth insulating layer has been formed in Figure 5. [Figure 6F] Figure 6F is a schematic partial plan view of the peripheral region after the third conductive layer has been formed in Figure 5. [Figure 7] Figure 7 is a partial schematic diagram of the display area and surrounding area in at least one embodiment of the present disclosure. [Figure 8] Figure 8 is an equivalent circuit diagram of a pixel circuit of a display area in at least one embodiment of the present disclosure. [Figure 9] Figure 9 is an operation timing diagram of the pixel circuit shown in Figure 8. [Figure 10] Figure 10 is a schematic partial plan view of a display area in at least one embodiment of the present disclosure. [Figure 11] Figure 11 is another partial plan schematic view of a peripheral region in at least one embodiment of the present disclosure. [Figure 12A] Figure 12A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 11. [Figure 12B] Figure 12B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 11. [Figure 12C] Figure 12C is a schematic partial plan view of the bottom metal layer in at least one embodiment of the present disclosure. [Figure 12D] Figure 12D is another partial plan schematic view of the bottom metal layer in at least one embodiment of the present disclosure. [Figure 13] Figure 13 is another partial plan schematic view of a peripheral region in at least one embodiment of the present disclosure. [Figure 14A] Figure 14A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 13. [Figure 14B] Figure 14B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 13. [Figure 15] Figure 15 is another partial plan schematic view of a peripheral region in at least one embodiment of the present disclosure. [Figure 16A] Figure 16A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 15. [Figure 16B] Figure 16B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 15. [Figure 17] Figure 17 is another partial plan schematic view of a peripheral region in at least one embodiment of the present disclosure. [Figure 18] Figure 18 is another partial plan schematic view of a peripheral region in at least one embodiment of the present disclosure. [Figure 19] Figure 19 is an equivalent circuit diagram of a light-emitting drive subcircuit in at least one embodiment of the present disclosure. [Figure 20] Figure 20 is an operation timing diagram of the light-emitting drive sub-circuit shown in Figure 19. [Figure 21] Figure 21 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 22A] Figure 22A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 21. [Figure 22B] Figure 22B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 21. [Figure 23] Figure 23 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 24A] Figure 24A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 23. [Figure 24B] Figure 24B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 23. [Figure 25] Figure 25 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 26] Figure 26 is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 25. [Figure 27] Figure 27 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 28] Figure 28 is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 27. [Figure 29] Figure 29 is a partial schematic diagram of the bottom metal layer in the peripheral region of at least one embodiment of the present disclosure. [Figure 30] Figure 30 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. [Figure 31A] Figure 31A is a schematic partial plan view of the surrounding region after the bottom metal layer has been formed in Figure 30. [Figure 31B] Figure 31B is a schematic partial plan view of the peripheral region after the semiconductor layer has been formed in Figure 30. [Figure 31C] Figure 31C is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 30. [Figure 32] Figure 32 is a schematic diagram of a display device in at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0029] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments may be carried out in several different forms. The forms and content may be transformed into other forms without departing from the spirit and scope of this disclosure, so as can be easily understood by those skilled in the art. Therefore, this disclosure should not be construed as being limited to the embodiments described below. The embodiments and features in this disclosure can be combined in any way, as long as they do not conflict.

[0030] In the drawings, the size, layer thickness, or area of ​​one or more components may be exaggerated for clarity. Therefore, one method of this disclosure is not necessarily limited to such sizes, and the shape and size of one or more components in the drawings do not reflect the actual scale. Furthermore, while the drawings schematically show ideal examples, one method of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," and "third" are established to avoid confusion of constituent elements and are not intended to limit them in terms of quantity. In this disclosure, "multiple" refers to two or more numbers.

[0032] In this specification, for convenience, descriptions indicating directional or positional relationships, such as “center,” “top,” “bottom,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to describe the positional relationships of components with reference to the drawings. However, this is merely for the sake of simplicity in describing this specification and does not express or imply that the indicated devices or elements necessarily have a specific orientation or are configured and operated in a specific orientation, and should therefore not be considered a limitation of this disclosure. The positional relationships of components are appropriately modified depending on the direction in which each component is described. Therefore, the terminology used in this specification is not limited and can be appropriately substituted as appropriate depending on the context.

[0033] In this specification, unless otherwise explicitly stated or limited, the terms “attachment” and “connection” should be understood in a broad sense. For example, this could mean being permanently connected, or detachably connected, or integrally connected; it could be a mechanical connection or an electrical connection; it could be a direct connection, an indirect connection via an intermediate member, or internal communication between two elements. Those skilled in the art will be able to understand the meaning of these terms in this disclosure depending on the context.

[0034] In this specification, "electrically connected" includes cases where components are connected via an element having some electrical function. An "element having some electrical function" is not particularly limited and can be any element capable of transmitting electrical signals between connected components. Examples of "elements having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements having different functions.

[0035] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0036] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When transistors with opposite polarity are used, or when the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be swapped. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped. The gate electrode may also be called the control electrode.

[0037] In this specification, "parallel" refers to a state in which the angle between two straight lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0038] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not in the strict sense, and may be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, such as chamfers, arcs, and other deformations.

[0039] In this disclosure, "approximately" and "about" mean that the limits are not strictly defined and that errors within the process and measurement range are acceptable. In this disclosure, "about the same" means that the difference in numerical values ​​is within 10%.

[0040] In this disclosure, "A extends along direction B" means that A may comprise a main body portion and a non-main body portion connected to the main body portion, the main body portion being a line, line segment, or strip, the main body portion extending along direction B, and the length of the main body portion extending along direction B being greater than the length of the non-main body portion extending in the other direction. In this disclosure, "A extends along direction B" always means "the main body portion of A extends along direction B."

[0041] Figure 1 is a schematic plan view of a display board. In some examples, as shown in Figure 1, the display board of this embodiment may comprise a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB may include a first bezel area located on one side of the display area AA and a second bezel area located on the other side of the display area. The second bezel area may be located on at least both sides of the first bezel area. For example, the first bezel area may include the lower bezel B1 of the display board, and the second bezel area may include the upper bezel B2, left bezel B3, and right bezel B4 of the display board. The upper bezel B2 and lower bezel B1 face each other, and the left bezel B3 and right bezel B4 face each other.

[0042] In some examples, the display area AA may be a flat area comprising a plurality of subpixels PX constituting a pixel array, and the plurality of subpixels PX may be configured to display a dynamic or still image. The display area AA may also be called the effective area. In some examples, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, for example, by winding, bending, folding, or rolling up.

[0043] In some examples, the second bezel region may comprise a circuit region, a power line region, a crack dam region, and a cut region, arranged sequentially along the direction of the display region AA. The circuit region may be connected to the display region AA and may comprise a gate drive circuit, for example, comprising a plurality of cascaded shift registers, which may be electrically connected to a plurality of gate lines in the display region AA. The power line region is connected to the circuit region and may comprise at least peripheral power wiring (e.g., low-level power lines), which may extend along a direction parallel to the edge of the display region and be connected to the cathode of the display region AA. The crack dam region may be connected to the power line region and may comprise at least a plurality of cracks located on the composite insulating layer. The cut region may be connected to the crack dam region and may comprise at least cut slots located on the composite insulating layer, which may be configured so that a cutting device can cut along each cut slot after the manufacturing of all film layers of the display substrate is complete.

[0044] In some examples, a first separation dam and a second separation dam may be installed in a first bezel region and a second bezel region, and the first and second separation dams may extend along a direction parallel to the edge of the display region, forming an annular structure surrounding the display region AA, and the edge of the display region is the edge of the display region that is closer to the first bezel region or the second bezel region.

[0045] In some examples, as shown in Figure 1, the display area AA may comprise at least a plurality of subpixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X and be arranged along a second direction Y, and the plurality of data lines DL may extend along the second direction Y and be arranged along the first direction X. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate intersect to form a plurality of subpixel regions, with one subpixel PX located within each subpixel region. The plurality of data lines DL may be electrically connected to the plurality of subpixels PX and configured to provide data signals to the plurality of subpixels PX. The plurality of data lines DL may extend to the bind area B1. The plurality of gate lines GL may be electrically connected to the plurality of subpixels PX and configured to provide gate control signals to the plurality of subpixels PX. In some examples, the gate control signal may include a scanning signal, or include a scanning signal and an illumination control signal. Alternatively, for example, the gate control signal may include a scanning signal, an illumination control signal, and a reset control signal.

[0046] In some examples, as shown in Figure 1, the first direction X may be the extension direction (row direction) of the gate line GL in the display area AA, and the second direction Y may be the extension direction (column direction) of the data line DL in the display area AA. The first direction X and the second direction Y may intersect, or for example, they may be perpendicular to each other.

[0047] In some examples, a single pixel unit in display area AA may have three subpixels, where the three subpixels are a red subpixel, a green subpixel, and a blue subpixel, respectively. However, this embodiment is not limited to this. In some examples, a single pixel unit may have four subpixels, where the four subpixels are a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, respectively.

[0048] In some examples, the shape of the subpixels may be rectangular, rhombus, pentagonal, or hexagonal. If a pixel unit has three subpixels, the three subpixels may be arranged in a horizontal parallel, vertical parallel, or U-shape, and if a pixel unit has four subpixels, the four subpixels may be arranged in a horizontal parallel, vertical parallel, or square. However, this embodiment is not limited to these arrangements.

[0049] In some examples, a subpixel may comprise a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may comprise multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0050] In some examples, the multiple transistors in a pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the difficulty of the display board manufacturing process, and improves the product yield. In some other examples, the multiple transistors in a pixel circuit may include both P-type and N-type transistors.

[0051] In some examples, multiple transistors in a pixel circuit may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors into a single display substrate, i.e., an LTPS+Oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display properties.

[0052] In some examples, the light-emitting element may be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element may be an OLED, which can emit red, green, blue, or white light by driving the corresponding pixel circuit. The color emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may comprise an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0053] In some implementation methods, taking portable electronic products such as mobile phones as an example, when a user uses a mobile phone, their body becomes charged. If the mobile phone screen is touched with high-frequency current for a long time, charge accumulates on the screen. If the charge cannot be released from the mobile phone in a timely manner, the screen will operate under an electric field, and if the screen itself does not have strong electrostatic resistance, the screen will malfunction. This will lead to a decrease in customer satisfaction and affect the user experience. Therefore, when designing display products, it is necessary to consider how to achieve normal display under more stringent conditions, such as high electrostatic fields.

[0054] Figure 2 is a schematic diagram of the operation of a display board under an electrostatic field. As shown in Figure 2, when a display board operates under high electrostatic field conditions, the charge on the display board tends to accumulate from the center to the periphery. As electrostatic charge accumulates, the gate drive circuit located in the peripheral region will operate in a high electrostatic field environment. If the electrostatic discharge tolerance of the gate drive circuit is insufficient, the accumulated charge will positively bias the transistor characteristics of the gate drive circuit, thereby affecting the operating state of the gate drive circuit and causing the display board to malfunction.

[0055] This embodiment provides a display substrate comprising a substrate, a bottom shielding metal (BSM) layer, and a gate drive circuit. The substrate comprises a display area and a peripheral area located around the display area. The bottom shielding metal layer is located in the peripheral area and is electrically connected to at least one type of signal line. The gate drive circuit is located in the peripheral area and on the side of the bottom shielding metal layer away from the substrate. The gate drive circuit comprises a plurality of first circuit units. The orthographic projection of the bottom shielding metal layer on the substrate and the orthographic projection of at least one first circuit unit on the substrate overlap at least partially. For example, the orthographic projection of the bottom shielding metal layer on the substrate may cover the orthographic projection of one or more first circuit units on the substrate, or the orthographic projection of the bottom shielding metal layer on the substrate and the orthographic projection of one or more first circuit units on the substrate may partially overlap.

[0056] In some examples, at least one type of signal line may include at least one of peripheral power lines, clock signal lines, and first pixel power lines. For example, the first pixel power line may be located in the display area and is configured to transmit a stable first voltage signal at a constant voltage. The peripheral power line may be located on the side of the gate drive circuit away from the display area and is configured to transmit a stable second voltage signal at a constant voltage. The clock signal line may be located in the peripheral area and is configured to transmit a pulse signal. In this example, by installing a bottom metal layer to receive a stable electrical or pulse signal at a constant voltage, a path for static electricity release can be provided, preventing static electricity buildup, which is advantageous for improving the electrostatic discharge immunity of the gate drive circuit.

[0057] In some examples, the bottom metal layer may comprise a plurality of first metal blocks, which may be electrically connected to the same type of signal line, or at least two of the first metal blocks may be electrically connected to different types of signal lines. Alternatively, for example, the bottom metal layer may comprise a plurality of first metal blocks and a plurality of second metal blocks, which may be electrically connected to the same type of signal line, which may be electrically connected to the same type of signal line, and which may be electrically connected to different types of signal lines. Alternatively, for example, the bottom metal layer may comprise a plurality of first metal blocks and a plurality of second metal blocks, which may be electrically connected to the same type of signal line. In this example, the same type of signal line may be configured to transmit the same signal, and different types of signal lines may be configured to transmit different signals.

[0058] In the display board according to this embodiment, a bottom metal layer is installed in the peripheral area, and the gate drive circuit is protected by the bottom metal layer, thereby improving the stability of the gate drive circuit under electrostatic discharge (ESD) conditions. As a result, the gate drive circuit can operate normally even when the display board is in a high electrostatic field, thereby increasing the ESD resistance of the display board. Furthermore, the bottom metal layer is electrically connected to the signal lines, providing a release path for electrostatic discharge and preventing the accumulation of electrostatic discharge, which is advantageous for improving the ESD resistance of the gate drive circuit.

[0059] In some exemplary embodiments, at least one first circuit unit may comprise at least one transistor. The orthographic projection of the bottom metal layer on the substrate and the orthographic projection of the active layer of at least one transistor of the at least one first circuit unit on the substrate may at least partially overlap. In some examples, the active layer of at least one transistor comprises at least one channel region, and the orthographic projection of the bottom metal layer on the substrate may cover the orthographic projection of the channel region of the active layer of at least one transistor on the substrate. In some other examples, the orthographic projection of the bottom metal layer on the substrate may cover the orthographic projection of the active layers of multiple transistors of at least one first circuit unit on the substrate. In this example, by using the bottom metal layer to shield the active layer of the transistors of the gate drive circuit, electrostatic discharge can be blocked, improving the stability of the transistor characteristics of the gate drive circuit under electrostatic conditions and increasing the electrostatic discharge resistance of the display substrate.

[0060] In some exemplary embodiments, at least one first circuit unit may comprise at least an input subcircuit and a first control subcircuit. The input subcircuit may be configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line. The first control subcircuit may be configured to control the potential of a second shift stage under the control of the first clock signal line and the first shift node. The first control subcircuit may be electrically connected to a second shift node via a node relay electrode. The orthographic projection of the bottom metal layer on the substrate and the orthographic projection of the node relay electrode on the substrate overlap at least partially. In this example, the circuit nodes of the gate drive circuit can be protected by utilizing the bottom metal layer to at least partially shield the second shift node, thereby increasing the electrostatic discharge immunity of the gate drive circuit.

[0061] In some exemplary embodiments, at least one first circuit unit may comprise at least an input subcircuit, a first control subcircuit, and a second control subcircuit. The input subcircuit may be configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line. The first control subcircuit may be configured to control the potential of a second shift node under the control of the first clock signal line and the first shift node. The second control subcircuit may be configured to conduct the first shift node and the third shift node under the control of a second power line. The input subcircuit, the first control subcircuit, and the second control subcircuit may be electrically connected to the first shift node via a first connecting electrode. The orthographic projection of the bottom metal layer on the substrate and the orthographic projection of the first connecting electrode on the substrate may at least partially overlap. In this example, the circuit nodes of the gate drive circuit can be protected by at least partially shielding the first shift node using the bottom metal layer, thereby increasing the electrostatic discharge immunity of the gate drive circuit.

[0062] In some exemplary embodiments, at least one first circuit unit may comprise at least a second control subcircuit and an output subcircuit. The second control subcircuit may be configured to conduct the first and third shift nodes under the control of a second power line. The output subcircuit may be configured to control the output signals at the shift output terminals under the control of the second and third shift nodes. The second control subcircuit and the output subcircuit may be electrically connected to the third shift node via a seventh connecting electrode. The orthographic projection of the bottom metal layer on the substrate may cover the orthographic projection of the seventh connecting electrode on the substrate. In this example, the circuit nodes of the gate drive circuit can be protected by shielding the third shift node using the bottom metal layer, thereby increasing the electrostatic discharge immunity of the gate drive circuit.

[0063] In some exemplary embodiments, at least one first circuit unit may comprise at least one capacitor. The orthographic projection of the bottom metal layer on the substrate and the orthographic projection of at least one capacitor of the at least one first circuit unit on the substrate may overlap at least partially. In this example, utilizing the bottom metal layer to at least partially shield the capacitor of the gate drive circuit helps to increase the node capacitance of the circuit node to which the capacitor is connected, thereby improving the stability of the circuit node, and the increased capacitance due to the overlap between the bottom metal layer and the capacitor can be used to reduce the space occupied by the capacitor, thus helping to reduce the size of the capacitor.

[0064] In some exemplary embodiments, the bottom metal layer may comprise a plurality of first metal blocks, and the orthographic projection of at least one first metal block on the substrate substrate may at least partially overlap with the orthographic projection of one or more first circuit units on the substrate substrate. The plurality of first metal blocks may form a single structure and be electrically connected to the same type of signal lines. In some examples, the single structure formed from the plurality of first metal blocks may be a planar metal block and have no cavities. In this example, the electrostatic discharge resistance of the gate drive circuit can be increased by shielding the gate drive circuit over a large area, and the manufacturing process can be simplified. In this example, the integral structure of A and B refers to a structure in which A and B are connected to each other and formed integrally.

[0065] In some exemplary embodiments, the gate drive circuit may comprise a plurality of cascaded first circuit units and a plurality of cascaded second circuit units. The plurality of cascaded second circuit units may be located on the side away from the display area of ​​the plurality of first circuit units. The orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of at least one second circuit unit on the substrate substrate may overlap at least partially. For example, the bottom metal layer may comprise a plurality of first metal blocks and a plurality of second metal blocks, the plurality of second metal blocks may be located on the side away from the display area of ​​the plurality of first metal blocks. The orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate may overlap at least partially. The orthographic projection of at least one of the plurality of second metal blocks on the substrate substrate and the orthographic projection of one or more second circuit units on the substrate substrate may overlap at least partially. Multiple second metal blocks may be a single integrated structure, and multiple second metal blocks and multiple first metal blocks may be electrically connected to different types of signal lines. For example, multiple second metal blocks may be electrically connected to the same type of signal line, and multiple first metal blocks may be electrically connected to the same type of signal line. The second metal blocks and first metal blocks may be configured to receive different signals. For example, the orthographic projection of one second metal block on the substrate may cover the orthographic projection of the active layer of at least one second circuit unit of multiple transistors on the substrate. In this example, the second metal blocks of the bottom metal layer can be used to shield the second circuit unit of the gate drive circuit, thereby blocking electrostatic discharge and increasing the electrostatic discharge immunity of the gate drive circuit.

[0066] In some exemplary embodiments, multiple pixel circuits may be installed in the display area, each of which is electrically connected to at least one first pixel power supply line, and at least one first metal block may be electrically connected to a first power supply line closer to the peripheral area. In some examples, multiple pixel metal blocks may be installed in the display area, and the multiple pixel metal blocks and the first metal block may be in the same layer structure. At least one pixel metal block may be electrically connected to the first pixel power supply line, and at least one first metal block may be electrically connected to the first pixel power supply line via at least one pixel metal block, thereby receiving a constant-voltage, stable first voltage signal transmitted from the first pixel power supply line. In this example, the first metal block receiving a constant-voltage, stable first voltage signal provides a static discharge path, avoids static discharge buildup, and is advantageous for improving the electrostatic discharge immunity of the gate drive circuit.

[0067] In some exemplary embodiments, the edge of the bottom metal layer comprises at least one of a convex angle and a concave angle. At least one of the convex and concave angles may be rounded. In this example, designing the edge of the bottom metal layer to be rounded can reduce the risk of static electricity occurring during the manufacturing process.

[0068] The technical proposal of this embodiment will be explained below with several examples.

[0069] In some examples, the gate drive circuit in the peripheral region may include a scan drive circuit. The scan drive circuit may be configured to generate scan signals supplied to the scan lines in the display region. For example, the scan drive circuit may sequentially supply scan signals having on-level pulses to the scan lines. The scan drive circuit may comprise a plurality of cascaded scan drive subcircuits. The input terminal of the first stage scan drive subcircuit may be electrically connected to the scan start signal line GSTV, and the output terminal of the i-th stage scan drive subcircuit may be electrically connected to the input terminal of the i+1-th stage scan drive subcircuit, where i is a positive integer. In some examples, the plurality of cascaded first circuit units comprising the gate drive circuit may comprise a plurality of cascaded scan drive subcircuits.

[0070] In the following description, we will use the example that the first circuit unit is a scanning drive subcircuit. Figure 3 is an equivalent circuit diagram of a scanning drive subcircuit in at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the scanning drive subcircuit may include an input subcircuit 51, a first control subcircuit 52, a second control subcircuit 54, and an output subcircuit 53. The input subcircuit 51 is electrically connected to a first clock signal line GCK, a shift input terminal GIN, and a first shift node GN1, and is configured to provide the signal from the shift input terminal GIN to the first shift node GN1 under the control of the first clock signal line GCK. The first control subcircuit 52 is electrically connected to a first clock signal line GCK, a first shift node GN1, and a second shift node GN2, and is configured to control the potential of the second shift node GN2 under the control of the first clock signal line GCK and the first shift node GN1. The second control subcircuit 54 is electrically connected to the second power line VGLg, the first shift node GN1, and the third shift node GN3, and is configured to conduct to the first shift node GN1 and the third shift node GN3 under the control of the second power line VGLg. The output subcircuit 53 is electrically connected to the second shift node GN2, the third shift node GN3, and the shift output terminal GOUT, and is configured to control the output signal of the shift output terminal GOUT under the control of the second shift node GN2 and the third shift node GN3.

[0071] In some examples, as shown in Figure 3, the input subcircuit 51 may include a first shift transistor GT1, the first control subcircuit 52 may include a second shift transistor GT2, a third shift transistor GT3, a sixth shift transistor GT6, and a seventh shift transistor GT7, the second control subcircuit 54 may include an eighth shift transistor GT8, and the output subcircuit 53 may include a fourth shift transistor GT4, a fifth shift transistor GT5, a first shift memory capacitor GC1, and a second shift memory capacitor GC2. The fourth shift transistor GT4 and the fifth shift transistor GT5 are output transistors of the scanning drive subcircuit.

[0072] In some examples, as shown in Figure 3, the control electrode of the first shift transistor GT1 is electrically connected to the first clock signal line GCK, the first electrode of the first shift transistor GT1 is electrically connected to the shift input terminal GIN, and the second electrode of the first shift transistor GT1 is electrically connected to the first shift node GN1. The control electrode of the second shift transistor GT2 is electrically connected to the first shift node GN1, the first electrode of the second shift transistor GT2 is electrically connected to the first clock signal line GCK, and the second electrode of the second shift transistor GT2 is electrically connected to the second shift node GN2. The control electrode of the third shift transistor GT3 is electrically connected to the first clock signal line GCK, the first electrode of the third shift transistor GT3 is electrically connected to the second power line VGLg, and the second electrode of the third shift transistor GT3 is electrically connected to the second shift node GN2. The control electrode of the fourth shift transistor GT4 is electrically connected to the second shift node GN2, the first electrode of the fourth shift transistor GT4 is electrically connected to the first power line VGHg, and the second electrode of the fourth shift transistor GT4 is electrically connected to the shift output terminal GOUT. The control electrode of the fifth shift transistor GT5 is electrically connected to the third shift node GN3, the first electrode of the fifth shift transistor GT5 is electrically connected to the second clock signal line GCB, and the second electrode of the fifth shift transistor GT5 is electrically connected to the shift output terminal GOUT. The control electrode of the sixth shift transistor GT6 is electrically connected to the second shift node GN2, the first electrode of the sixth shift transistor GT6 is electrically connected to the first power line VGHg, and the second electrode of the sixth shift transistor GT6 is electrically connected to the first electrode of the seventh shift transistor GT7. The control electrode of the seventh shift transistor GT7 is electrically connected to the second clock signal line GCB, and the second electrode of the seventh shift transistor GT7 is electrically connected to the first shift node GN1. The control electrode of the 8th shift transistor GT8 is electrically connected to the 2nd power line VGLg, the 1st electrode of the 8th shift transistor GT8 is electrically connected to the 1st shift node GN1, and the 2nd electrode of the 8th shift transistor GT8 is electrically connected to the 3rd shift node GN3.The second electrode of the first shift memory capacitor GC1 is electrically connected to the first power line VGHg, and the first electrode of the first shift memory capacitor GC1 is electrically connected to the second shift node GN2. The second electrode of the second shift memory capacitor GC2 is electrically connected to the shift output terminal GOUT, and the first electrode of the second shift memory capacitor GC2 is electrically connected to the third shift node GN3.

[0073] In this example, as shown in Figure 3, the first shift node GN1 is the connection point between the first shift transistor GT1, the second shift transistor GT2, the seventh shift transistor GT7, and the eighth shift transistor GT8. The second shift node GN2 is the connection point between the second shift transistor GT2, the third shift transistor GT3, the fourth shift transistor GT4, the sixth shift transistor GT6, and the first shift memory capacitor GC1. The third shift node GN3 is the connection point between the eighth shift transistor GT8, the fifth shift transistor GT5, and the second shift memory capacitor GC2.

[0074] In some examples, the first shift transistor GT1 to the eighth shift transistor GT8 in the scanning drive subcircuit shown in Figure 3 may all be P-type or N-type transistors. However, this embodiment is not limited to this.

[0075] In some examples, we will explain using the case where the first shift transistor GT1 to the eighth shift transistor GT8 of the scan drive subcircuit shown in Figure 3 are all P-type transistors. We will take the example where the shift input terminal GIN of the first stage scan drive subcircuit is electrically connected to the scan start signal line GSTV. Figure 4 is an operation timing diagram of the scan drive subcircuit of the scan drive circuit shown in Figure 3. As shown in Figures 3 and 4, the scan drive subcircuit according to this exemplary embodiment may include eight transistor units (i.e., the first shift transistor GT1 to the eighth shift transistor GT8), two capacitor units (i.e., the first shift memory capacitor GC1 and the second shift memory capacitor GC2), three input terminals (i.e., the first clock signal line GCK, the second clock signal line GCB, and the shift input terminal GIN), one output terminal (i.e., the shift output terminal GOUT), and two power supply terminals (i.e., the first power supply line VGHg and the second power supply line VGLg). The first power line VGHg may be configured to continuously provide a high-level signal, and the second power line VGLg may be configured to continuously provide a low-level signal.

[0076] In some examples, as shown in Figures 3 and 4, the operation process of the scanning drive subcircuit of the scanning drive circuit in this example may include the following four steps.

[0077] In the first stage S11, the first clock signal line GCK provides a low-level first clock signal, and the shift input terminal GIN receives a low-level trigger signal, which causes the first shift transistor GT1 and the third shift transistor GT3 to conduct. The conducted first shift transistor GT1 transmits a low-level trigger signal to the first shift node GN1, which causes the level of the first shift node GN1 to become low, which causes the second shift transistor GT2 and the fifth shift transistor GT5 to conduct. Since the eighth shift transistor GT8 remains in a conducting state in response to the second voltage (persistently low level) provided from the second power supply line VGLg, the level of the third shift node GN3 and the level of the first shift node GN1 may be the same, i.e., low level, and at the same time, this low level is stored in the second shift memory capacitor GC2. Furthermore, the conductive third shift transistor GT3 transmits a low level second voltage to the second shift node GN2, and the conductive second shift transistor GT2 transmits a low level of the first clock signal to the second shift node GN2, thereby causing the level of the second shift node GN2 to become low and to be stored in the first shift memory capacitor GC1. As a result, the fourth shift transistor GT4 conducts in response to the low level of the second shift node GN2 and outputs a high level first voltage provided from the first power line VGHg to the shift output terminal GOUT. Simultaneously, the fifth shift transistor GT5 conducts in response to the low level of the third shift node GN3 and transmits a high level second clock signal provided from the second clock signal line GCB to the shift output terminal GOUT, thereby causing the first circuit unit to output a high level signal at this stage.

[0078] In the second stage S12, the second clock signal line GCB provides a low level second clock signal, thereby conducting the seventh shift transistor GT7, and the first clock signal line GCK provides a high level first clock signal, thereby cutting off the first shift transistor GT1 and the third shift transistor GT3. Due to the memory function of the second shift memory capacitor GC2, the first shift node GN1 can continue to maintain the low level from the previous stage, thereby conducting the second shift transistor GT2 and the fifth shift transistor GT5. Because the second shift transistor GT2 is conducting, the high level first clock signal from the first clock signal line GCK is transmitted to the second shift node GN2, thereby causing the second shift node GN2 to become high level, and consequently cutting off the sixth shift transistor GT6 and the fourth shift transistor GT4, thereby preventing the high level provided from the first power line VGHg from being output to the shift output terminal GOUT and the first shift node GN1. At the same time, the fifth shift transistor GT5 is activated, so at this stage, the shift output terminal GOUT outputs a low-level signal transmitted from the second clock signal line GGB.

[0079] In the third stage S13, the first clock signal line GCK provides a low-level third clock signal, which causes the first shift transistor GT1 and the third shift transistor GT3 to conduct. At this time, the high level provided from the initial scan signal line GSTV is transmitted from the shift input terminal GIN to the first shift node GN1 and the third shift node GN3, which cuts off the fifth shift transistor GT5 and the second shift transistor GT2. The second clock signal line GCB receives a high-level second clock signal, which cuts off the seventh shift transistor GT7. Because the third shift transistor GT3 is now conduction, the low-level signal provided from the second power line VGLg is transmitted to the second shift node GN2 and stored in the first shift memory capacitor GC1. Consequently, the fourth shift transistor GT4 and the sixth shift transistor GT6 conduction occur, and at this stage, the shift output terminal GOUT outputs a high-level signal provided from the first power line VGHg.

[0080] In the fourth stage S14, the first clock signal line GCK provides a high-level first clock signal, which cuts off the first shift transistor GT1 and the third shift transistor GT3. The second clock signal line GCB provides a low-level second clock signal, which conducts the seventh shift transistor GT7. Due to the memory function of the second shift memory capacitor GC2, the level of the first shift node GN1 remains at the high level from the previous stage, which cuts off the second shift transistor GT2 and the fifth shift transistor GT5. In this stage, the shift output terminal GOUT outputs a high-level signal provided from the first power supply line VGHg. Due to the memory function of the first shift memory capacitor GC1, the second shift node GN2 continues to maintain the low level of the previous stage, thereby the sixth shift transistor GT6 conducts, and thereby the high level supplied from the first power line VGHg is transmitted to the first shift node GN1 and the third shift node GN3 via the conducted sixth shift transistor GT6 and the seventh shift transistor GT7, thereby the first shift node GN1 and the third shift node GN3 continue to maintain a high level, effectively preventing the fifth shift transistor GT5 from conducting, and thereby avoiding false output.

[0081] In some examples, the scan drive subcircuit may repeat the third stage S13 and the fourth stage S14 until the shift input terminal GIN receives a low-level signal again.

[0082] Figure 5 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. Figure 5 shows a schematic diagram of the planar structure of one scanning drive subcircuit as an example.

[0083] In some examples, as shown in Figure 5, the first clock signal line GCK, the second clock signal line GCB, the first power line VGHg, and the second power line VGLg may all extend along the second direction Y in a plane parallel to the display board. The first clock signal line GCK, the second clock signal line GCB, and the second power line VGLg may be located on the side away from the display area of ​​the scanning drive subcircuit, while the first power line VGHg may be located on the side closer to the display area of ​​the scanning drive subcircuit. The first clock signal line GCK may be located between the second clock signal line GCB and the second power line VGLg. The first clock signal line GCK may be located on the side of the second clock signal line GCB closer to the display area.

[0084] In some examples, as shown in Figure 5, the scanning drive subcircuit may be located between the first power line VGHg and the second power line VGLg. The first shift memory capacitor GC1 may be located on the side of the fourth shift transistor GT4 closer to the first power line VGHg, and the orthographic projections of the first shift memory capacitor GC1 and the first power line VGHg on the substrate may partially overlap. The second shift memory capacitor GC2 may be located on the side of the fifth shift transistor GT5 closer to the first power line VGHg, and the orthographic projections of the second shift memory capacitor GC2 and the first power line VGHg on the substrate may partially overlap. The second shift memory capacitor GC2 and the first shift memory capacitor GC1 may be arranged sequentially along the second direction Y. The fifth shift transistor GT5 and the fourth shift transistor GT4 may be arranged sequentially along the second direction Y. The third shift transistor GT3 may be located on the side of the eighth shift transistor GT8 closer to the second power line VGLg, and the third shift transistor GT3 and the second shift transistor GT2 may be arranged sequentially along the second direction Y. The first shift transistor GT1 may be located on the side of the second shift transistor GT2 away from the second power line VGLg. The seventh shift transistor GT7 may be located on the side of the eighth shift transistor GT8 away from the second power line VGLg, and the sixth shift transistor GT6 may be located between the seventh shift transistor GT7 and the first shift transistor GT1 in the second direction Y.

[0085] In some examples, in a direction perpendicular to the display substrate, the peripheral region of the display substrate may comprise a substrate substrate and a bottom metal layer and a circuit structure layer sequentially installed on the substrate substrate, and the peripheral region circuit structure layer may comprise a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially installed. In some examples, a first insulating layer may be installed between the bottom metal layer and the semiconductor layer, a second insulating layer may be installed between the semiconductor layer and the first conductive layer, a third insulating layer may be installed between the first conductive layer and the second conductive layer, and a fourth insulating layer may be installed between the second conductive layer and the third conductive layer. The first conductive layer may further be referred to as the first gate metal layer, the second conductive layer may further be referred to as the second gate metal layer, and the third conductive layer may further be referred to as the first source-drain metal layer. In some examples, the first to fourth insulating layers may all be made of inorganic materials. However, this embodiment is not limited to this. In some examples, a planar layer, anode layer, pixel definition layer, organic light-emitting layer, cathode layer, and package layer may be sequentially placed on the side of the display area of ​​the display substrate away from the substrate of the third conductive layer.

[0086] Figure 6A is a partial planar schematic diagram of the peripheral region after the bottom metal layer has been formed in Figure 5. Figure 6B is a partial planar schematic diagram of the peripheral region after the semiconductor layer has been formed in Figure 5. Figure 6C is a partial planar schematic diagram of the peripheral region after the first conductive layer has been formed in Figure 5. Figure 6D is a partial planar schematic diagram of the peripheral region after the second conductive layer has been formed in Figure 5. Figure 6E is a partial planar schematic diagram of the peripheral region after the fourth insulating layer has been formed in Figure 5. Figure 6F is a partial planar schematic diagram of the peripheral region after the third conductive layer has been formed in Figure 5.

[0087] In some examples, as shown in Figure 6A, the bottom metal layer 10 of the peripheral region may comprise a plurality of first metal blocks 101 (figure 6A schematically shows one first metal block 101 as an example) and a first connection structure 102. The plurality of first metal blocks 101 and the first connection structure 102 may be an integral structure. The plurality of first metal blocks 101 may be arranged sequentially along the second direction Y, and adjacent first metal blocks 101 may be electrically connected, for example, as an integral structure. The first metal blocks 101 may be located on the side of the first connection structure 102 away from the display area. For example, one first metal block 101 may correspond to one scan drive subcircuit, and one first metal block 101 may be located below the corresponding scan drive subcircuit to provide protection to the corresponding scan drive subcircuit and increase its electrostatic discharge resistance. However, this embodiment is not limited thereto. In some other examples, one first metal block may correspond to multiple scan drive subcircuits.

[0088] In some examples, as shown in Figure 6A, a first metal block 101 may comprise a first body portion 1010, a first extension portion 1011, a second extension portion 1012, a third extension portion 1013, a fourth extension portion 1014, and a plurality of fifth extension portions (e.g., four fifth extension portions 1015a, 1015b, 1015c, 1015d). The orthographic projection of the first body portion 1010 on a substrate may be, for example, substantially rectangular. The first extension portion 1011 and the second extension portion 1012 may extend from opposing sides of the first body portion 1010 along a second direction Y, and the third extension portion 1013 and the fourth extension portion 1014 may extend from opposing sides of the first body portion 1010 along the second direction Y. The first extension 1011 and the third extension 1013 may be adjacent in the first direction X and protrude from the upper edge of the first main body 1010, and the second extension 1012 and the fourth extension 1014 may be adjacent in the first direction X and protrude from the lower edge of the first main body 1010. For example, the third extension 1013 of one first metal block 101 may be connected to the fourth extension of an adjacent first metal block in the second direction Y to form an integrated structure, and the fourth extension 1014 of the first metal block 101 may be connected to the third extension of another adjacent first metal block in the second direction Y to form an integrated structure. The four fifth extensions 1015a, 1015b, 1015c, and 1015d may extend along the first direction X from the first main body 1010 toward the display area side, or they may protrude from the right edge of the first main body 1010. There may be a first cavity between adjacent fifth extensions, for example, a first cavity 1016a between fifth extensions 1015a and 1015b, a first cavity 1016b between fifth extensions 1015b and 1015c, and a first cavity 1016c between fifth extensions 1015c and 1015d. In some examples, the edges of the first cavities 1016a, 1016b, and 1016c may have concave angles (e.g., angles J3 and J4), and these concave angles may be designed to be rounded, thereby reducing the risk of static electricity generated during the manufacturing process.

[0089] In some examples, a cavity region 110 may be provided between two adjacent first metal blocks 101, as shown in Figure 6A. The cavity region 110 may be formed by being surrounded by the second extension 1012, fourth extension 1014, and fifth extension 1015d of one first metal block 101, and the third extension, first extension, and one fifth extension of the other first metal block. In this example, the formation of a cavity region between adjacent first metal blocks can reduce the area of ​​the first metal blocks, thereby reducing the risk of electrostatic discharge (ESD) generated during the manufacturing process.

[0090] In some examples, as shown in Figure 6A, the first connection structure 102 may be located on the side of the plurality of first metal blocks 101 closer to the display area. The first connection structure 102 is connected to a plurality of fifth extensions of the first metal block 101 to form an integrated structure. The first connection structure 102 may include a first connection part 1021, a second connection part 1022, a third connection part 1023, and a fourth connection part 1024. The first connection part 1021 may be connected to a plurality of fifth extensions of the first metal block 101. Both the first connection part 1021 and the third connection part 1023 may extend substantially along the second direction Y, and both the second connection part 1022 and the fourth connection part 1024 may extend substantially along the first direction X toward the display area. The first connection part 1021 may be connected to a plurality of first metal blocks 101, for example, to adjacent first metal blocks 101. Multiple second connection portions 1022 may be connected between the first connection portion 1021 and the third connection portion 1023. The fourth connection portion 1024 may be connected to the third connection portion 1023 and extend toward the display area along the first direction X. There may be a misalignment between the second connection portion 1022 and the fourth connection portion 1024 in the first direction X. For example, the second connection portion 1022 and the fourth connection portion 1024 may be misaligned in the first direction X and connected to opposite sides of the third connection portion 1023. The orthographic projection of the first connection structure 102 on the substrate board in this example may be a substantially mesh structure. Making the first connection structure 102 a mesh structure in this example is advantageous for reducing the impedance of the first connection structure 102. However, this embodiment is not limited to this. In some other examples, the first connection structure 102 may consist only of a first extension portion extending along the first direction X.

[0091] In some examples, as shown in Figure 6A, the edges of the first metal block 101 may have convex corners (e.g., corner J1) and concave corners (e.g., corner J2). The edges of the first connecting structure 102 may have concave corners (e.g., corners J5, J6, J7). The corners of the edges of the first metal block 101 and the first connecting structure 102 may both be designed as rounded corners, thereby reducing the risk of static electricity generated during the manufacturing process. In this example, the edges of the bottom metal layer 10 may include the edges of the first metal block 101, the edges of the first cavity of the first metal block 101, and the connection corners between the connections of the first connecting structure. In this example, the corners of the edges of the bottom metal layer may both be designed as rounded corners, thereby reducing the risk of static electricity generated during the manufacturing process.

[0092] In some examples, as shown in Figure 6B, the semiconductor layer in the peripheral region may include at least the active layers of multiple transistors in the scanning drive subcircuit (for example, the active layer GT10 of the first shift transistor, the active layer GT20 of the second shift transistor, the active layer GT30 of the third shift transistor, the active layer GT40 of the fourth shift transistor, the active layer GT50 of the fifth shift transistor, the active layer GT60 of the sixth shift transistor, the active layer GT70 of the seventh shift transistor, and the active layer GT80 of the eighth shift transistor). The active layer GT20 of the second shift transistor and the active layer GT30 of the third shift transistor may be an integrated structure. The active layer GT60 of the sixth shift transistor and the active layer GT70 of the seventh shift transistor may be an integrated structure. The active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor may be an integrated structure. However, this embodiment is not limited to these.

[0093] In some examples, as shown in Figures 6A and 6B, the orthographic projections of the active layers of multiple transistors in the scanning drive subcircuit and the first metal block 101 on the substrate may overlap at least partially. The orthographic projections of the active layer GT60 of the sixth shift transistor, the active layer GT70 of the seventh shift transistor, and the active layer GT80 of the eighth shift transistor on the substrate may be located within the range of the orthographic projection of the first metal block 101 on the substrate, and the orthographic projections of the active layers of the remaining shift transistors on the substrate may partially overlap with the orthographic projection of the first metal block 101 on the substrate. For example, the orthographic projection of the active layer GT10 of the first shift transistor on the substrate and the orthographic projection of the first extension portion 1011 of the first metal block 101 on the substrate partially overlap; the orthographic projections of the active layer GT20 of the second shift transistor and the active layer GT30 of the third shift transistor on the substrate partially overlap and the orthographic projection of the first main body portion 1010 on the substrate partially overlap; the orthographic projections of the active layer GT60 of the sixth shift transistor, the active layer GT70 of the seventh shift transistor and the active layer GT80 of the eighth shift transistor on the substrate are located within the range of the orthographic projection of the first main body portion 1010 on the substrate; and the orthographic projections of the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor on the substrate partially overlap and the orthographic projections of the four fifth extension portions on the substrate. The shape of the first metal block in this example may correspond to the shapes of multiple transistors in the scanning drive subcircuit.

[0094] In some examples, as shown in Figure 6C, the first conductive layer in the peripheral region may include at least the control electrodes of a plurality of transistors of the scanning drive subcircuit (e.g., the control electrode GT13 of the first shift transistor, the control electrode GT23 of the second shift transistor, the control electrode GT33 of the third shift transistor, the control electrode GT43 of the fourth shift transistor, the control electrode GT53 of the fifth shift transistor, the control electrode GT63 of the sixth shift transistor, the control electrode GT73 of the seventh shift transistor, and the control electrode GT83 of the eighth shift transistor), the first electrode GC1-1 of the first shift memory capacitor, the first electrode GC2-1 of the second shift memory capacitor, and the input connection line 201. The input connection line 201 may extend along the first direction X and be located on the side away from the active layer GT40 of the fourth shift transistor and away from the active layer GT50 of the fifth shift transistor. The control electrode GT63 of the sixth shift transistor, the control electrode GT43 of the fourth shift transistor, and the first electrode GC1-1 of the first shift memory capacitor may be an integrated structure. The control electrode GT53 of the fifth shift transistor and the first electrode GC2-1 of the second shift memory capacitor may be integrated into a single structure.

[0095] In some examples, the active layer may comprise at least one channel region and multiple doping regions. For example, the doping regions may be located on opposite sides of the channel region. The orthographic projections of the channel region of the transistor's active layer and the control electrodes of the transistor on the substrate may overlap. For example, the orthographic projection of the channel region of the transistor's active layer on the substrate may be located within the range of the orthographic projection of the control electrodes of the transistor on the substrate. As shown in Figures 6A to 6C, the orthographic projections of the channel regions of the active layers of multiple transistors in the scanning drive subcircuit on the substrate may be located within the range of the orthographic projection of the first metal block 101 on the substrate. In other words, the orthographic projection of the first metal block 101 on the substrate may cover the orthographic projections of the channel regions of the active layers of the first to eighth shift transistors in the scanning drive subcircuit on the substrate. In some examples, the orthographic projection of the first metal block 101 on the substrate may partially overlap with the doping region of the active layer of the output transistor. For example, the orthographic projections of the doping regions of the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor on the substrate partially overlap with the orthographic projection of the first metal block 101 on the substrate, while the orthographic projections of the three first cavities of the first metal block 101 on the substrate do not overlap with the orthographic projections of the channel regions of the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor on the substrate. The orthographic projections of the first cavities of the first metal block 101 on the substrate may partially overlap with the orthographic projections of the doping regions of the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor on the substrate.In this example, by shielding the channel regions of the active layers of multiple transistors in the scanning drive subcircuit with a first metal block, the electrostatic discharge on the substrate side is prevented from affecting the transistor characteristics of the scanning drive subcircuit, thereby improving the stability of the scanning drive subcircuit under electrostatic conditions. Furthermore, by installing a first cavity in the first metal block, the transistor characteristics are protected while simultaneously reducing the area of ​​the first metal block, thereby reducing the electrostatic discharge risk that occurs during the manufacturing process.

[0096] In some examples, as shown in Figure 6D, the second conductive layer in the peripheral region may comprise at least the second electrode GC1-2 of the first shift memory capacitor of the scanning drive subcircuit, the second electrode GC2-2 of the second shift memory capacitor, a node relay electrode 202, and a first output connection line 35. The node relay electrode 202 may be located between the control electrode GT23 of the second shift transistor and the control electrode GT63 of the sixth shift transistor. The orthographic projection of the second electrode GC1-2 of the first shift memory capacitor on the substrate may be located within the orthographic projection of the first electrode GC1-1 of the first shift memory capacitor on the substrate. The orthographic projection of the second electrode GC2-2 of the second shift memory capacitor on the substrate and the orthographic projection of the first electrode GC2-1 of the second shift memory capacitor on the substrate may overlap at least partially. The first output connection line 35 may extend along the first direction X and be located on the side away from the active layer GT40 of the fourth shift transistor on the active layer GT50 of the fifth shift transistor.

[0097] In some examples, as shown in Figures 6A to 6D, the orthographic projections of the first shift memory capacitor and the second shift memory capacitor on the substrate substrate may partially overlap with the orthographic projection of the bottom metal layer 10 on the substrate substrate. For example, the orthographic projections of the first shift memory capacitor and the second shift memory capacitor on the substrate substrate do not have to overlap with the orthographic projection of the first metal block 101 on the substrate substrate, but may partially overlap with the orthographic projection of the first connection portion 1021 of the first connection structure 102 on the substrate substrate. Parts of the first shift memory capacitor and parts of the second shift memory capacitor may be located within a region formed by being surrounded by the first connection portion 1021, the second connection portion 1022, and the third connection portion 1023 of the first connection structure 102.

[0098] In some examples, as shown in Figure 6E, multiple vias may be provided in the fourth insulating layer in the peripheral region, for example, the first via V1 to the 30th via V30. The fourth insulating layer, the third insulating layer, and the second insulating layer in the first via V1 to the 13th via V13 may be etched to expose a portion of the surface of the semiconductor layer, the fourth insulating layer and the third insulating layer in the 14th via V14 to the 24th via V24 may be etched to expose a portion of the surface of the first conductive layer, and the fourth insulating layer in the 25th via V25 to the 30th via V30 may be etched to expose a portion of the surface of the second conductive layer.

[0099] In some examples, as shown in Figure 6F, the third conductive layer in the peripheral region may include at least a plurality of connecting electrodes (e.g., first connecting electrode 301 to thirteenth connecting electrode 313), a first clock signal line GCK, a second clock signal line GCB, a first power line VGHg, and a second power line VGLg. The first clock signal line GCK, the second clock signal line GCB, the first power line VGHg, and the second power line VGLg may all extend substantially along the second direction Y.

[0100] In some examples, as shown in Figures 5 to 6F, the first connecting electrode 301 may be electrically connected to one doping region of the active layer GT10 of the first shift transistor via the first via V1, or to the control electrode GT23 of the second shift transistor via the 16th via V16, or to one doping region of the active layer GT80 of the eighth shift transistor via the 8th via V8, or to one doping region of the active layer GT70 of the seventh shift transistor via the 7th via V7. The second connecting electrode 302 may be electrically connected to another doping region of the active layer GT10 of the first shift transistor via the second via V2, or to one end of the input connection line 201 via two 22nd vias V22 placed side by side. The other end of the input connection line 201 may be electrically connected to the 11th connection electrode 311 via two 24th vias V24 arranged side by side, and the 11th connection electrode 311 may be electrically connected to the shift output terminal of the preceding scan drive subcircuit. In some examples, the input connection line 201 may be configured to extend toward the display area and be electrically connected to the scan line or reset control line of the display area via a connection line located in the third conductive layer. The third connection electrode 303 may be electrically connected to one doping region of the active layer GT20 of the second shift transistor via a third via V3, or to the control electrode GT13 of the first shift transistor via a 15th via V15. The control electrode GT13 of the first shift transistor may be electrically connected to the first clock signal line GCK via two 14th vias V14 arranged vertically. The fourth connecting electrode 304 may be electrically connected to the control electrode GT63 of the sixth shift transistor via the 20th via V20, or to the node relay electrode 202 via the 26th via V26. The fifth connecting electrode 305 may be electrically connected to another doping region of the active layer GT20 of the second shift transistor via the fourth via V4, or to the node relay electrode 202 via the 25th via V25.The sixth connection electrode 306 may be electrically connected to one doping region of the active layer GT30 of the third shift transistor via the fifth via V5, or to the control electrode GT83 of the eighth shift transistor via the 19th via V19. The sixth connection electrode 306 and the second power line VGLg may be an integrated structure. The control electrode of the third shift transistor may be electrically connected to the first clock signal line GCK via two vertically arranged 17th vias V17. The seventh connection electrode 307 may be electrically connected to another doping region of the active layer GT80 of the eighth shift transistor via the 9th via V9, or to the control electrode GT53 of the fifth shift transistor via the 23rd via V23. The eighth connection electrode 308 may be electrically connected to the doping region of the active layer GT40 of the fourth shift transistor via a plurality of horizontally arranged 10th vias V10, or to one doping region of the active layer GT60 of the sixth shift transistor via the sixth via V6. The eighth connection electrode 308 and the first power line VGHg may be an integrated structure. The first power line VGHg may be electrically connected to the second electrode GC1-2 of the first shift memory capacitor via a plurality of 27th vias V27. The ninth connection electrode 309 may be electrically connected to the doping region of the active layer GT40 of the fourth shift transistor via a plurality of 11th vias V11, or to the doping region of the active layer GT50 of the fifth shift transistor via a plurality of 13th vias V13, or to the second electrode GC2-2 of the second shift memory capacitor via three vertically arranged 28th vias V28. The ninth connection electrode 309 may be electrically connected to the 11th connection electrode 311 and input connection line 201 of the next stage's scan drive subcircuit as the shift output terminal of the scan drive subcircuit of this stage. The 10th connecting electrode 310 may be electrically connected to the doping region of the active layer GT50 of the 5th shift transistor via a plurality of 12th vias V12, or it may be electrically connected to the control electrode GT73 of the 7th shift transistor via two vertically arranged 21st vias V21.The control electrode GT73 of the seventh shift transistor may be electrically connected to the second clock signal line GCB via two vertically aligned eighteenth vias V18. The twelfth connection electrode 312 may be electrically connected to the second electrode GC2-2 of the second shift memory capacitor via two vertically aligned twenty-nine vias V29. The twelfth connection electrode 312 may extend toward the display area, thereby being electrically connected to the scan lines of the display area and configured to provide scan signals to a row of pixel circuits. The thirteenth connection electrode 313 may be electrically connected to the first output connection line 35 via two vertically aligned thirty vias V30. The thirteenth connection electrode 313 may extend toward the display area, for example, being electrically connected to the light emission control lines of the display area and configured to provide light emission control signals to a row of pixel circuits. For example, the first output connection line 35 may be electrically connected to a light emission control subcircuit located on the side of the scan drive subcircuit away from the display area. The orthographic projection of the first output connection line 35 on the substrate substrate and the orthographic projection of the cavity region 110 between adjacent first metal blocks 101 on the substrate substrate may partially overlap. In this example, the cavity region can reduce the overlap area between the first output connection line and the first metal block, thereby reducing the influence of parasitic capacitance between the first output connection line and the first metal block on the signal transmission of the first output connection line, ensuring the stability of the signal transmission of the first output connection line, while simultaneously reducing the area of ​​the first metal block and lowering the risk of electrostatic discharge (ESD) generated during the manufacturing process.

[0101] In some examples, the node relay electrode 202 can provide electrical connections between the control electrode GT63 of the sixth shift transistor GT6 and the second shift transistor GT2 and the third shift transistor GT3, i.e., electrical connections with the second shift node GN2. The orthographic projection of the node relay electrode 202 on the substrate may be located within the range of the orthographic projection of the first metal block 101 on the substrate. This allows the first metal block 101 to cover the second shift node GN2 in the scanning drive subcircuit, thereby blocking electrostatic effects on the second shift node GN2. Furthermore, the capacitance formed between the first metal block 101 and the node relay electrode 202 increases the node capacitance, improving the stability of the second shift node GN2. The first connecting electrode 301 enables electrical connections between the first shift transistor GT1, the second shift transistor GT2, the seventh shift transistor GT7, and the eighth shift transistor GT8, that is, it enables electrical connections with the first shift node GN1. The orthographic projection of the first connecting electrode 301 on the substrate may be located within the range of the orthographic projection of the first metal block 101 on the substrate. This allows the first metal block 101 to cover the first shift node GN1 in the scanning drive subcircuit, thereby blocking electrostatic effects on the first shift node GN1. The seventh connecting electrode 307 enables electrical connection between the eighth shift transistor GT8, the fifth shift transistor GT5, and the second shift memory capacitor GC2, that is, it enables electrical connection with the third shift node GN3. The orthographic projection of the seventh connecting electrode 307 on the substrate may be located within the range of the orthographic projection of the first metal block 101 on the substrate, thereby allowing the first metal block 101 to cover the third shift node GN3 in the scanning drive subcircuit and block electrostatic effects on the third shift node GN3.

[0102] In some examples, multiple pixel circuits may be installed in the display area, and at least one pixel circuit may be electrically connected to the first pixel circuit wiring. The first metal block in the peripheral area may be electrically connected to the first pixel power wiring in the display area, thereby configured to receive a first voltage signal. For example, the first connection structure of the bottom metal layer of the peripheral area may extend to the display area and be electrically connected directly to at least one first pixel power wiring close to the peripheral area within the display area. Alternatively, for example, multiple pixel metal blocks may be installed in the display area, and the pixel metal blocks may have the same layer structure as the first metal block in the peripheral area, and the first metal blocks may be electrically connected to the first pixel power wiring via the pixel metal blocks. This embodiment is not limited thereto.

[0103] Figure 7 is a schematic partial diagram of the display area and peripheral area in at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the bottom metal layer 10 of the display substrate may include at least a plurality of first metal blocks 101 (two first metal blocks 101 are shown as an example in Figure 7) located in the peripheral area BB, a first connection structure 102, and a plurality of pixel metal blocks 103 located in the display area AA. The plurality of pixel metal blocks 103 may be arranged in an array and connected to form a single structure. The first connection structure 102 in the peripheral area BB may be directly connected to the pixel metal blocks 103 in the display area AA to form a single structure. For example, the fourth connection portion 1024 of the first connection structure 102 is directly connected to the pixel metal block 103.

[0104] In some examples, the pixel metal block 103 of the display area may extend to the upper and lower bezels of the peripheral area of ​​the display substrate and be electrically connected to a fifth power line PL1 or a sixth power line PL2. In some examples, the first pixel power wiring may be the fifth power line PL1, and the first metal block 101 may be electrically connected to the pixel metal block 103 via the first connection structure 102, and the pixel metal block 103 may be electrically connected to the fifth power line PL1, thereby enabling the first metal block 101 to receive a stable first voltage signal at a constant voltage provided from the fifth power line PL1. However, this embodiment is not limited thereto. In some other examples, the first connection structure 102 may be electrically connected to a first power line VGHg located in the peripheral area, for example, the second connection portion 1022 of the first connection structure 102 may be electrically connected to the first power line VGHg, thereby enabling the first metal block to receive a stable electrical signal at a constant voltage transmitted from the first power line VGHg and providing a static discharge path. However, this embodiment is not limited to this.

[0105] In some examples, as shown in Figure 7, the first connection structure 102 in the peripheral region BB may be a substantially mesh structure, which can reduce the impedance of the bottom metal layer.

[0106] Figure 8 is an equivalent circuit diagram of a pixel circuit of a display area in at least one embodiment of the present disclosure. The pixel circuit in this example may have a 7T1C structure. In some examples, as shown in Figure 8, the pixel circuit may include six switching transistors (PT1, PT2, PT4~PT7), one drive transistor PT3, and one pixel memory capacitor Cst. The six switching transistors are, respectively, a data writing transistor PT4, a threshold compensation transistor PT2, a first light emission control transistor PT5, a second light emission control transistor PT6, a first reset transistor PT1, and a second reset transistor PT7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0107] In some examples, the drive transistor and the six switching transistors may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the difficulty of the display board manufacturing process, and improves the product yield. In some possible implementations, the drive transistor and the six switching transistors may include both P-type and N-type transistors.

[0108] In some examples, as shown in Figure 8, the pixel circuit is electrically connected to a scan line GL, a data line DL, a fifth power line PL1, a sixth power line PL2, a light emission control line EML, a first initial voltage line INIT1, a second initial voltage line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the fifth power line PL1 is configured to provide the pixel circuit with a stable first voltage signal VDD, the sixth power line PL2 is configured to provide the pixel circuit with a stable second voltage signal VSS, and the first voltage signal VDD may be greater than the second voltage signal VSS. The scan line GL may be configured to provide the pixel circuit with a scan signal SCAN, the data line DL may be configured to provide the pixel circuit with a data signal DATA, the light emission control line EML may be configured to provide the pixel circuit with a light emission control signal EM, the first reset control line RST1 is configured to provide the pixel circuit with a first reset control signal RESET1, and the second reset control line RST2 is configured to provide the pixel circuit with a second reset control signal RESET2. In some examples, the second reset signal RESET2(i) received by the i-th row pixel circuit is the same as the scan signal SCAN(i) received by the i-th row pixel circuit. However, this embodiment is not limited to this.

[0109] In some examples, the i-th stage scanning drive subcircuit in the above embodiment may provide a scanning signal to the i-th row pixel circuit via the scanning line GL, a second reset control signal to the i-th row pixel circuit via the second reset control line, or a first reset control signal to the i-th row pixel circuit via the first reset control line. The light emission drive circuit may provide light emission control signals to at least one row of pixel circuits in the display area via the light emission control line EML. However, this embodiment is not limited thereto.

[0110] In some examples, as shown in Figure 8, the control electrode of the data writing transistor PT4 is electrically connected to the scan line GL, the first electrode of the data writing transistor PT4 is electrically connected to the data line DL, and the second electrode of the data writing transistor PT4 is electrically connected to the first electrode of the drive transistor PT3. The control electrode of the threshold compensation transistor PT2 is electrically connected to the scan line GL, the first electrode of the threshold compensation transistor PT2 is electrically connected to the control electrode of the drive transistor PT3, and the second electrode of the threshold compensation transistor PT2 is electrically connected to the second electrode of the drive transistor PT3. The control electrode of the first light emission control transistor PT5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor PT5 is electrically connected to the fifth power line PL1, and the second electrode of the first light emission control transistor PT5 is electrically connected to the first electrode of the drive transistor PT3. The control electrode of the second light emission control transistor PT6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor PT6 is electrically connected to the second electrode of the drive transistor PT3, and the second electrode of the second light emission control transistor PT6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor PT1 is electrically connected to the control electrode of the drive transistor PT3 and configured to reset the control electrode of the drive transistor PT3, and the second reset transistor PT7 is electrically connected to the anode of the light-emitting element EL and configured to reset the anode of the light-emitting element EL. The control electrode of the first reset transistor PT1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor PT1 is electrically connected to the first initial voltage line INIT1, and the second electrode of the first reset transistor PT1 is electrically connected to the control electrode of the drive transistor PT3. The control electrode of the second reset transistor PT7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor PT7 is electrically connected to the second initial voltage line INIT2, and the second electrode of the second reset transistor PT7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the pixel memory capacitor Cst is electrically connected to the control electrode of the drive transistor PT3, and the second electrode of the pixel memory capacitor Cst is electrically connected to the fifth power line PL1.

[0111] In this example, as shown in Figure 8, the first pixel node PN1 is the connection point between the pixel memory capacitor Cst, the first reset transistor PT1, the drive transistor PT3, and the threshold compensation transistor PT2; the second pixel node PN2 is the connection point between the first light emission control transistor PT5, the data writing transistor PT4, and the drive transistor PT3; the third pixel node PN3 is the connection point between the drive transistor PT3, the threshold compensation transistor PT2, and the second light emission control transistor PT6; and the fourth pixel node PN4 is the connection point between the second light emission control transistor PT6, the second reset transistor PT7, and the light-emitting element EL.

[0112] Figure 9 is an operation timing diagram of the pixel circuit shown in Figure 8. Next, the operation process of the pixel circuit shown in Figure 8 will be explained with reference to Figure 9. The explanation will be given as an example where the multiple transistors in the pixel circuit shown in Figure 8 are P-type transistors.

[0113] In some examples, as shown in Figures 8 and 9, the operation process of the pixel circuit during the display period of one frame may include a reset stage S31, a data writing stage S32, and a light emission stage S33.

[0114] In the reset phase S31, the first reset control signal RESET1 provided from the first reset control line RST1 is a low-level signal that conducts the first reset transistor PT1, and the first initial voltage Vinit1 provided from the first initial voltage line INIT1 is supplied to the first pixel node PN1, initializing the first pixel node PN1 and erasing the original data voltage in the pixel memory capacitor Cst. The scan signal SCAN provided from the scan line GL is a high-level signal, and the light emission control signal EM provided from the light emission control line EML is a high-level signal that cuts off the data write transistor PT4, threshold compensation transistor PT2, first light emission control transistor PT5, second light emission control transistor PT6, and second reset transistor PT7. The light-emitting element EL does not emit light at this stage.

[0115] The data writing stage S32 may also be called the threshold compensation stage. The scan signal SCAN provided from the scan line GL is a low-level signal, the first reset control signal RESET1 provided from the first reset control line RST1 and the light emission control signal EM provided from the light emission control line EML are both high-level signals, and the data line DL outputs the data signal DATA. At this stage, the first electrode of the pixel memory capacitor Cst is at a low level, so the drive transistor PT3 is conductive. The scan signal SCAN is a low-level signal, which conducts the threshold compensation transistor PT2, the data writing transistor PT4, and the second reset transistor PT7. The threshold compensation transistor PT2 and the data writing transistor PT4 are connected, and the data voltage Vdata output from the data line DL is supplied to the first pixel node PN1 via the second pixel node PN2, the connected drive transistor PT3, the third pixel node PN3, and the connected threshold compensation transistor PT2. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the drive transistor PT3 is charged to the pixel memory capacitor Cst, and the voltage at the first electrode of the pixel memory capacitor Cst (i.e., the first pixel node PN1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL and Vth is the threshold voltage of the drive transistor PT3. The second reset transistor PT7 is connected, and the second initial voltage Vinit2 provided from the second initial voltage line INIT2 is supplied to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL, clearing the previously stored voltage inside it, completing the initialization, and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1, provided by the first reset control line RST1, is a high-level signal that cuts off the first reset transistor PT1. The light emission control signal EM, provided by the light emission control line EML, is a high-level signal that cuts off the first light emission control transistor PT5 and the second light emission control transistor PT6.

[0116] In the light emission stage S33, the light emission control signal EM provided from the light emission control line EML is a low-level signal, while the scan signal SCAN provided from the scan line GL and the first reset control signal RESET1 provided from the first reset control line RST1 are high-level signals. The light emission control signal EM provided from the light emission control line EML is a low-level signal that conducts the first light emission control transistor PT5 and the second light emission control transistor PT6, and the first voltage signal VDD output from the fifth power line PL1 provides a drive voltage to the anode of the light-emitting element EL via the conducted first light emission control transistor PT5, drive transistor PT3, and second light emission control transistor PT6, driving the light-emitting element EL to emit light.

[0117] In the pixel circuit driving process, the drive current flowing through the drive transistor PT3 is determined by the voltage difference between its control electrode and the first electrode. Since the voltage at the first pixel node PN1 is Vdata - |Vth|, the drive current of the drive transistor PT3 is: I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K × [(VDD - Vdata)] 2 Here, I is the drive current flowing through the drive transistor PT3, i.e., the drive current that drives the light-emitting element EL; K is a constant; Vgs is the voltage difference between the control electrode and the first electrode of the drive transistor PT3; Vth is the threshold voltage of the drive transistor PT3; Vdata is the data voltage output from the data line D; and VDD is the first voltage signal output from the fifth power supply line PL1.

[0118] As can be seen from the above equation, the current flowing through the light-emitting element EL is independent of the threshold voltage of the drive transistor PT3. Therefore, the pixel circuit of this embodiment can compensate for the threshold voltage of the drive transistor PT3 relatively well.

[0119] Figure 10 is a schematic partial plan view of a display area in at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, the display substrate of the display area may comprise at least a substrate, a bottom metal layer and a circuit structure layer sequentially placed on the substrate, in a direction perpendicular to the display substrate. The circuit structure layer of the display area may comprise sequentially placed semiconductor layers, a first conductive layer, a second conductive layer and a third conductive layer. The semiconductor layers may comprise at least the active layers of a plurality of transistors of the pixel circuit; for example, the active layers of seven transistors of the pixel circuit may be an integrated structure. The first conductive layer may comprise at least control electrodes of a plurality of transistors of the pixel circuit, a first electrode of a pixel memory capacitor Cst, a first reset control line RST1, a scan line GL, and a light emission control line EML. The first electrode of the pixel memory capacitor Cst and the control electrode of the drive transistor PT3 may be an integrated structure, the control electrode of the first anode reset transistor PT1 and the control electrode of the second anode reset transistor PT7 of the preceding pixel circuit and the first reset control line RST1 may be an integrated structure, the control electrode of the threshold compensation transistor PT2 and the data writing transistor PT4 and the scan line GL may be an integrated structure, and the control electrode of the first light emission control transistor PT5 and the second light emission control transistor PT6 and the light emission control line EML may be an integrated structure. The second conductive layer may comprise at least the second electrode of the pixel memory capacitor and the first initial signal line INIT1. The second electrode of the pixel memory capacitor of a plurality of pixel circuits arranged along the first direction X may be an integrated structure, enabling the transmission of the first voltage signal along the first direction X and ensuring uniformity of the first voltage signal in the display area. The third conductive layer may comprise at least a plurality of pixel connection electrodes, a data line DL and a fifth power line PL1. Both the data line DL and the fifth power line PL1 may extend along the second direction Y.

[0120] In some examples, as shown in Figures 7 and 10, the orthographic projection of the pixel metal block 103 on the substrate and the orthographic projection of the active layer of at least one transistor in the pixel circuit on the substrate may overlap at least partially. For example, the orthographic projection of the pixel metal block 103 on the substrate may cover the orthographic projection of the channel region of the active layer of the drive transistor PT3 on the substrate. In this example, the pixel metal block 103 can be placed in the display area to isolate the pixel circuit from static electricity. However, this embodiment is not limited to this. In some other examples, the pixel metal block may not be placed in the display area. For example, the first connection structure may extend to the display area and be electrically connected to the second electrode of the pixel memory capacitor of the pixel circuit at the edge of the display area, and electrically connected to the fifth power line PL1 via the second electrode of the pixel memory capacitor, thereby enabling the first metal block 101 to receive a stable first voltage signal at a constant voltage.

[0121] Next, the manufacturing process for display substrates will be described illustratively. In this embodiment, the “patterning process” includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. For deposition, one or more of sputtering, vapor deposition, and chemical vapor deposition may be employed; for coating, one or more of spray coating, spin coating, and inkjet printing may be employed; and for etching, one or more of dry etching and wet etching may be employed; however, this disclosure is not limited. A “thin film” refers to a thin film of a single layer produced on a substrate by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may further be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. Each "layer" after going through the patterning process contains at least one "pattern".

[0122] In embodiments of this disclosure, "A and B are of the same layer structure" or "A and B are placed on the same layer" means that A and B are formed simultaneously by the same patterning process, or that the distance between the surface of A and B closest to the substrate is approximately the same, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A and the boundary of the orthographic projection of B overlap.

[0123] In some cases, the manufacturing process for the display board may include the following steps (1) to (7).

[0124] (1) A bottom metal layer is formed. In some examples, a bottom metal thin film is deposited on a substrate, and the bottom metal thin film is patterned by a patterning process to form a bottom metal layer. The bottom metal layer may include a first metal block 101 and a first connecting structure 102 located in the peripheral region BB, and a pixel metal block 103 located in the display region AA, as shown in Figures 6A and 7.

[0125] In some examples, the substrate may be a flexible base substrate or a rigid base substrate. For example, a rigid base substrate may be made of a material such as glass or quartz. A flexible base substrate may be made of a material such as polyimide (PI), and the flexible base substrate may be a single-layer structure or a laminated structure consisting of an inorganic material layer and a flexible material layer. However, this embodiment is not limited to these.

[0126] (2) Forming a semiconductor layer. In some examples, as shown in Figures 6B and 10, a first insulating thin film and a semiconductor thin film are sequentially deposited on a substrate on which the above structure is formed, and the semiconductor thin film is patterned by a patterning process to form a first insulating layer that covers the bottom metal layer and a semiconductor layer placed on the first insulating layer.

[0127] In some examples, the semiconductor layer material may include, for example, polysilicon. The active layer may comprise at least one channel region and multiple doping regions. The channel region may be undoped with impurities and have semiconductor properties. The multiple doping regions are located on both sides of the channel region and may be doped with impurities and therefore conductive. The impurities may vary depending on the type of transistor. In some examples, the doping regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as impurity-doped wiring and may be used to electrically connect to the transistors.

[0128] (3) Forming the first conductive layer. In some examples, as shown in Figures 6C and 10, the second insulating thin film and the first conductive thin film are sequentially deposited on a substrate on which the above structure is formed, and the first conductive thin film is patterned by a patterning process to form a second insulating layer that covers the semiconductor layer and a first conductive layer that is placed on the second insulating layer.

[0129] (4) Forming the second conductive layer. In some examples, as shown in Figures 6D and 10, the third insulating thin film and the second conductive thin film are sequentially deposited on a substrate on which the above structure is formed, and the second conductive thin film is patterned by a patterning process to form a third insulating layer covering the first conductive layer and a second conductive layer placed on the third insulating layer.

[0130] (5) Forming the fourth insulating layer. In some examples, as shown in Figures 6E and 10, the fourth insulating thin film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth insulating thin film is patterned by a patterning process to form the fourth insulating layer.

[0131] (6) Forming a third conductive layer. In some examples, as shown in Figures 6F and 10, a third conductive thin film is deposited on a substrate on which the aforementioned pattern is formed, and the third conductive thin film is patterned by a patterning process to form a third conductive layer on the fourth insulating layer.

[0132] This completes the manufacturing of the circuit structure layer of the display board.

[0133] (7) A flat layer, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer are formed in sequence.

[0134] In some examples, a flat thin film is coated onto a substrate substrate on which the aforementioned pattern is formed, and the flat thin film is patterned by a patterning process to form a flat layer. Multiple pixel connection holes may be formed in the flat layer of the display area. Subsequently, an anode thin film is deposited on the substrate substrate on which the aforementioned pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer. The anode of the anode layer may be electrically connected to the corresponding pixel circuit via the pixel connection holes. Subsequently, a pixel definition thin film is coated onto the substrate substrate on which the aforementioned pattern is formed, and a pixel definition layer is formed by a masking, exposure, and development process. Multiple pixel apertures that expose the anode layer are formed in the pixel definition layer. Subsequently, an organic light-emitting layer is formed within the aforementioned formed pixel apertures, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer and the second power line, respectively. In some examples, a package layer is formed on the cathode layer, and the package layer may have a laminated structure of inorganic material / organic material / inorganic material.

[0135] In some examples, the bottom metal layer, the first conductive layer, the second conductive layer, and the third conductive layer may be made of one or more metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of one or more silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiON), and may be a single layer, multilayer, or composite layer. The second and third insulating layers may be called gate insulating (GI) layers, and the fourth insulating layer may be called interlayer insulating (ILD) layers. The flat layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited to these materials.

[0136] The structure and manufacturing process of the display substrate in this embodiment are merely illustrative. In some examples, the structure can be modified and the patterning process can be increased or decreased as required by actual circumstances. For example, if the display substrate is an LTPO display substrate, the circuit structure layers of the display substrate may include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. This embodiment is not limited thereto.

[0137] The manufacturing process of this exemplary embodiment can be implemented using existing mature manufacturing equipment, has good compatibility with existing manufacturing processes, is easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0138] Figure 11 is another partial plan schematic diagram of a peripheral region in at least one embodiment of the present disclosure. Figure 12A is a partial plan schematic diagram of the peripheral region after the bottom metal layer has been formed in Figure 11. Figure 12B is a partial plan schematic diagram of the peripheral region after the first conductive layer has been formed in Figure 11. Figure 12C is a partial plan schematic diagram of the bottom metal layer in at least one embodiment of the present disclosure. Figure 12D is another partial plan schematic diagram of the bottom metal layer in at least one embodiment of the present disclosure. Figures 12C and 12D schematically show three first metal blocks as examples.

[0139] In some examples, as shown in Figure 12A, the bottom metal layer 10 of the peripheral region may comprise a first metal block 101 and a first connecting structure 102. The first connecting structure 102 may be located on the side of the first metal block 101 closer to the display area. The first metal block 101 and the first connecting structure 102 may be an integrated structure. One first metal block 101 may correspond to one scanning drive subcircuit.

[0140] In some examples, as shown in Figure 12C, adjacent first metal blocks 101 may be installed independently, and the first connection structures 102 to which adjacent first metal blocks 101 are connected may be installed independently of each other. Different first metal blocks 101 may be electrically connected to different signal lines. For example, the first and third first metal blocks may be electrically connected to the first pixel power supply wiring, and the second first metal block may be electrically connected to the clock signal line or the peripheral power supply wiring. Alternatively, for example, the first first metal block may be electrically connected to the first pixel power supply wiring, the second first metal block may be electrically connected to the peripheral power supply wiring, and the third first metal block may be electrically connected to the clock signal line. This embodiment is not limited thereto.

[0141] In some other examples, as shown in Figure 12D, multiple first metal blocks 101 may be connected by a first connecting structure 102 and form an integrated structure. Multiple first metal blocks 101 may be electrically connected to the same signal line via the first connecting structure 102, for example, all of them may be electrically connected to a first pixel power supply wiring.

[0142] In some examples, as shown in Figure 12A, the first metal block 101 may comprise a first body portion 1010, a first extension portion 1011, and a plurality of fifth extension portions (e.g., four fifth extension portions 1015a, 1015b, 1015c, 1015d). The orthographic projection of the first body portion 1010 on the substrate may be substantially hook-shaped. The first body portion 1010 may have a second cavity portion 1017, the orthographic projection of the second cavity portion 1017 on the substrate may be substantially rectangular, and the first body portion 1010 partially encloses the second cavity portion 1017. For example, the edge of the second cavity portion 1017 may have a concave corner (e.g., corner J8), and the concave corner may be designed to be rounded, thereby reducing the risk of electrostatic discharge during the manufacturing process.

[0143] In some examples, as shown in Figure 12A, the first extension 1011 may extend from the upper edge of the first body 1010 along the second direction Y. The four fifth extensions 1015a, 1015b, 1015c, and 1015d may extend from the first body 1010 towards the display area along the first direction X, and may protrude from the right edge of the first body 1010. There may be a first cavity between adjacent fifth extensions, for example, a first cavity 1016a between fifth extensions 1015a and 1015b, a first cavity 1016b between fifth extensions 1015b and 1015c, and a first cavity 1016c between fifth extensions 1015c and 1015d. The edges of the first cavity may have rounded concave corners, thereby reducing the risk of static electricity during the manufacturing process.

[0144] In some examples, as shown in Figure 12A, the first connection structure 102 may include a first connection portion 1021 extending along a second direction Y and a second connection portion 1022 extending along a first direction X. The connection position between the second connection portion 1022 and the first connection portion 1021 may substantially correspond to the boundary position of two adjacent first metal blocks 101. In this example, the two adjacent first metal blocks 101 may be connected by the first connection portion 1021 and receive a constant voltage electrical signal from the display area via the second connection portion 1022. For example, the second connection portion 1022 receives a first voltage signal transmitted from a first pixel power line by being electrically connected to the pixel metal block of the display area. However, this embodiment is not limited thereto. In some other examples, at least two adjacent first metal blocks may not be connected via the first connection portion 1021 of the first connection structure, and may directly receive a constant voltage electrical signal via the second connection portion 1022.

[0145] In some examples, as shown in Figures 11 to 12B, one first metal block 101 may correspond to one scanning drive subcircuit. The orthographic projection of a single first metal block 101 on the substrate may cover the orthographic projection of the channel region of the active layer of multiple shift transistors (i.e., the first shift transistor GT1 to the eighth shift transistor GT8) of a single scanning drive subcircuit on the substrate. The orthographic projection of the first metal block 101 on the substrate and the orthographic projection of the doping region of the active layer of multiple shift transistors (e.g., including the output transistor) on the substrate may partially overlap. The orthographic projection of the first metal block 101 on the substrate may partially overlap with the orthographic projection of the node relay electrode on the substrate, and may partially overlap with the orthographic projection of the first connection electrode on the substrate. The orthographic projections of the node relay electrode and the first connection electrode on the substrate and the orthographic projection of the second cavity 1017 of the first metal block 101 on the substrate may partially overlap. The orthographic projection of the first metal block 101 on the substrate substrate and the orthographic projection of the seventh connecting electrode on the substrate substrate do not need to overlap. In this example, the first metal block 101 may partially cover the shift node or may not cover the shift node, providing an electrostatic discharge shielding effect while simultaneously reducing the area of ​​the first metal block and lowering the electrostatic discharge risk that occurs during the manufacturing process.

[0146] The shape of the first metal block 101 in this example is adapted to the arrangement and shape of the first shift transistor GT1 and the eighth shift transistor GT8. In this example, by using the first metal block 101 to protect the scanning drive subcircuit from below, the effects of electrostatic discharge on the transistor characteristics of the scanning drive subcircuit can be blocked, thereby allowing the scanning drive subcircuit to operate more stably even in conditions where static electricity accumulates. Furthermore, the edges of the first metal block 101 are designed to be rounded, thereby reducing the risk of electrostatic discharge that may occur during the manufacturing process. In some other examples, one first metal block may accommodate multiple scanning drive subcircuits.

[0147] The remaining details regarding the display board of this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0148] Figure 13 is another partial plan schematic diagram of a peripheral region in at least one embodiment of the present disclosure. Figure 14A is a partial plan schematic diagram of the peripheral region after the bottom metal layer has been formed in Figure 13. Figure 14B is a partial plan schematic diagram of the peripheral region after the first conductive layer has been formed in Figure 13.

[0149] In some examples, as shown in Figures 13 to 14B, the bottom metal layer 10 of the peripheral region may comprise a first metal block 101 and a first connecting structure 102. In this example, the first metal block 101 may be a planar metal block, and no void is provided in the first metal block 101. Two adjacent first metal blocks 101 may be a single integrated structure, and no void is provided between the adjacent first metal blocks 101. The first connecting structure 102 may be located on the side of the first metal block 101 closer to the display area. The first connecting structure 102 may comprise a first connecting portion 1021 extending along a second direction Y, and a second connecting portion 1022 extending along a first direction X. The first connecting portion 1021 and the second connecting portion 1022 may have a stripe structure. The connection positions of the first connecting portion 1021 and the second connecting portion 1022 may correspond to the boundary positions of two adjacent first metal blocks 101. For example, the second connection section 1022 may extend until it is electrically connected to a pixel metal block in the display area, thereby being configured to receive a stable first voltage signal at a constant voltage. In some examples, one first metal block corresponds to one scanning drive subcircuit.

[0150] In some examples, as shown in Figures 13 to 14B, the orthographic projection of one first metal block 101 on the substrate may cover the orthographic projection of the channel region of the active layer of multiple shift transistors (e.g., first shift transistor GT1 to eighth shift transistor GT8) of a scanning drive subcircuit on the substrate. For example, the orthographic projection of the first metal block 101 on the substrate may cover the orthographic projection of the active layer of all the shift transistors of the corresponding scanning drive subcircuit on the substrate. The orthographic projection of the first metal block 101 on the substrate and the orthographic projection of the first and second shift memory capacitors on the substrate may partially overlap. For example, the increased capacitance due to the overlap between the bottom metal layer and the first and second shift memory capacitors can be used to reduce the capacitor area of ​​the first and second shift memory capacitors, thereby reducing the space occupied by the first and second shift memory capacitors, which is advantageous for reducing the space occupied by the scanning drive subcircuit. Furthermore, the overlap between the bottom metal layer and the first shift memory capacitor can increase the node capacitance of the second shift node, thereby improving the stability of the second shift node, and the overlap between the bottom metal layer and the second shift memory capacitor can increase the node capacitance of the third shift node, thereby improving the stability of the third shift node. In some other examples, the orthographic projection of the bottom metal layer on the substrate may cover the orthographic projection of the first and second shift memory capacitors on the substrate. The first metal block 101 in this example may be located below the scanning drive subcircuit, shielding the scanning drive subcircuit over a large area, thereby blocking static electricity and increasing the static electricity resistance of the scanning drive subcircuit. Furthermore, the first metal block 101 in this example does not require the creation of a cavity, thus simplifying the process.

[0151] In some examples, as shown in Figure 14A, the orthographic projection of the first metal block 101 on the substrate may be rectangular. Adjacent first metal blocks 101 may be a single integrated structure. The connection angle (e.g., corner J5) between the first connection portion 1021 and the second connection portion 1022 of the first connection structure 102 may be designed as a rounded corner, thereby reducing the risk of electrostatic discharge during the manufacturing process.

[0152] The remaining details regarding the display board of this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0153] Figure 15 is another partial plan schematic diagram of a peripheral region in at least one embodiment of the present disclosure. Figure 16A is a partial plan schematic diagram of the peripheral region after the bottom metal layer has been formed in Figure 15. Figure 16B is a partial plan schematic diagram of the peripheral region after the first conductive layer has been formed in Figure 15.

[0154] In some examples, as shown in Figure 16A, the bottom metal layer 10 of the peripheral region may comprise a first metal block 101 and a second connection structure 104. The second connection structure 104 may be located on the side of the first metal block 101 away from the display area. The second connection structure 104 may comprise a fifth connection portion 1041 extending along a first direction X. The fifth connection portion 1041 may be connected to the boundary position of two adjacent first metal blocks 101. The fifth connection portion 1041 may be a stripe structure extending from the first metal block 101 away from the display area along the first direction X. For example, the fifth extension portion 1041 may extend below the peripheral power lines. The peripheral power lines may be located in the peripheral region and on the side of the gate drive circuit away from the display area. The peripheral power lines may be configured to transmit constant voltage electrical signals, such as a second voltage signal. In some examples, the peripheral power lines may be located in a third conductive layer. The fifth extension 1041 may be electrically connected to the surrounding power lines via vias opened from the fourth insulating layer to the first insulating layer, enabling the first metal block 101 to receive a constant voltage electrical signal.

[0155] In some examples, as shown in Figure 16A, the orthographic projection of the first metal block 101 on the substrate may be rectangular. Adjacent first metal blocks 101 may be a single integrated structure, and the orthographic projection of the integrated structure on the substrate may be substantially rectangular. As shown in Figures 15 to 16B, the orthographic projection of the first metal block 101 on the substrate and the orthographic projection of the active layers of multiple transistors of the scanning drive subcircuit on the substrate overlap at least partially. For example, the orthographic projection of the active layer of the third shift transistor on the substrate and the orthographic projection of the first metal block 101 on the substrate partially overlap. In some other examples, the orthographic projection of the first metal block 101 on the substrate may cover the orthographic projection of the active layers of all shift transistors of the scanning drive subcircuit on the substrate. However, this embodiment is not limited to this.

[0156] In some examples, as shown in Figure 16A, the connection angle (e.g., corner J9) between the first metal block 101 and the fifth connection portion 1041 of the second connecting structure 104 may be designed as a rounded corner, thereby reducing the risk of static electricity during the manufacturing process.

[0157] The remaining details regarding the display board of this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0158] Figure 17 is another partial plan schematic of a peripheral region in at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the fifth connection portion 1041 of the second connection structure 104 of the bottom metal layer may be electrically connected to a second clock signal line GCB via vias opened from the first to the fourth insulating layer, so that the first metal block 101 receives the second clock signal provided from the second clock signal line GCB, thereby achieving electrostatic isolation to the scanning drive subcircuit. The fifth connection portion 1041 is a stripe structure extending along the first direction X. In this example, the connection of the fifth connection portion to the second clock signal line GCB can reduce the impact on other wiring. However, this embodiment is not limited thereto. In some other examples, the fifth connection portion 1041 of the second connection structure 104 may be electrically connected to a first clock signal line GCK, or to a second power line VGLg. In some other examples, the first metal block may be electrically connected to the first power line VGHg via a first connection structure. The remaining description of the display board in this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0159] Figure 18 is another partial plan schematic of a peripheral region in at least one embodiment of the present disclosure. In some examples, as shown in Figure 18, the first metal block 101 of the bottom metal layer may be rectangular, and the first metal block 101 may extend below the second clock signal line GCB and be electrically connected directly to the second clock signal line GCB via vias opened from the first insulating layer to the fourth insulating layer. In some examples, the orthographic projection of the first metal block 101 on the substrate may cover the orthographic projection of the first shift memory capacitor and the second shift memory capacitor on the substrate. The capacitance generated by the overlap between the first metal block 101 and the first shift memory capacitor can be used to reduce the capacitor area of ​​the first shift memory capacitor, thereby reducing the space occupied by the first shift memory capacitor and thus advantageous in reducing the space occupied by the scanning drive subcircuit. The capacitance generated by the overlap between the first metal block 101 and the second shift memory capacitor can be used to reduce the capacitor area of ​​the second shift memory capacitor, thereby reducing the space occupied by the second shift memory capacitor and thus advantageous in reducing the space occupied by the scanning drive subcircuit. Furthermore, the overlap between the first metal block 101 and the first shift memory capacitor can increase the node capacitance of the second shift node, thereby improving the stability of the second shift node. The overlap between the first metal block 101 and the second shift memory capacitor can increase the node capacitance of the third shift node, thereby improving the stability of the third shift node. The remaining description of the display board of this embodiment can be found in the description of the above embodiment and will not be repeated here.

[0160] In some examples, the gate drive circuit in the peripheral region may comprise a scanning drive circuit and a light emission drive circuit. The light emission drive circuit may be located on the side of the scanning drive circuit away from the display area. The light emission drive circuit may be configured to generate a light emission control signal that is supplied to the light emission control line of the display area. The light emission drive circuit may comprise a plurality of cascaded light emission drive subcircuits. The input terminal of the first stage light emission drive circuit may be electrically connected to the light emission start signal line ESTV, and the output terminal of the i-th stage light emission drive subcircuit may be electrically connected to the input terminal of the i+1-th stage light emission drive subcircuit, where i is a positive integer. In some examples, the plurality of cascaded second circuit units comprising the gate drive circuit may comprise a plurality of cascaded light emission drive subcircuits. The following explanation will use the example where the second circuit unit is a light emission drive subcircuit.

[0161] Figure 19 is an equivalent circuit diagram of a light-emitting drive subcircuit in at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the light-emitting drive subcircuit of this example may include a first control transistor ET1 to a tenth control transistor ET10, a first control memory capacitor EC1, a second control memory capacitor EC2, and a third control memory capacitor EC3. The ninth control transistor ET9 and the tenth control transistor ET10 are output transistors of the light-emitting drive subcircuit. The first control transistor ET1 is an input transistor of the light-emitting drive subcircuit.

[0162] In some examples, as shown in Figure 19, the control electrode of the first control transistor ET1 is electrically connected to the third clock signal line ECK, the first electrode of the first control transistor ET1 is electrically connected to the control input terminal EIN, and the second electrode of the first control transistor ET1 is electrically connected to the first control node EN1. The control electrode of the second control transistor ET2 is electrically connected to the first control node EN1, the first electrode of the second control transistor ET2 is electrically connected to the third clock signal line ECK, and the second electrode of the second control transistor ET2 is electrically connected to the second control node EN2. The control electrode of the third control transistor ET3 is electrically connected to the third clock signal line ECK, the first electrode of the third control transistor ET3 is electrically connected to the fourth power line VGLe, and the second electrode of the third control transistor ET3 is electrically connected to the second control node EN2. The control electrode of the fourth control transistor ET4 is electrically connected to the fourth clock signal line ECB, the first electrode of the fourth control transistor ET4 is electrically connected to the second electrode of the fifth control transistor ET5, and the second electrode of the fourth control transistor ET4 is electrically connected to the first control node EN1. The control electrode of the fifth control transistor ET5 is electrically connected to the second control node EN2, and the first electrode of the fifth control transistor ET5 is electrically connected to the third power line VGHe. The control electrode of the sixth control transistor ET6 is electrically connected to the second control node EN2, the first electrode of the sixth control transistor ET6 is electrically connected to the fourth clock signal line ECB, and the second electrode of the sixth control transistor ET6 is electrically connected to the third control node EN3. The control electrode of the seventh control transistor ET7 is electrically connected to the fourth clock signal line ECB, the first electrode of the seventh control transistor ET7 is electrically connected to the third control node EN3, and the second electrode of the seventh control transistor ET7 is electrically connected to the fourth control node EN4. The control electrode of the 8th control transistor ET8 is electrically connected to the 1st control node EN1, the 1st electrode of the 8th control transistor ET8 is electrically connected to the 3rd power line VGHe, and the 2nd electrode of the 8th control transistor ET8 is electrically connected to the 4th control node EN4.The control electrode of the ninth control transistor ET9 is electrically connected to the fourth control node EN4, the first electrode of the ninth control transistor ET9 is electrically connected to the third power line VGHe, and the second electrode of the ninth control transistor ET9 is electrically connected to the control output terminal EOUT. The control electrode of the tenth control transistor ET10 is electrically connected to the first control node EN1, the first electrode of the tenth control transistor ET10 is electrically connected to the fourth power line VGLe, and the second electrode of the tenth control transistor ET10 is electrically connected to the control output terminal EOUT. The first electrode of the first control memory capacitor EC1 is electrically connected to the control electrode of the sixth control transistor ET6, and the second electrode of the first control memory capacitor EC1 is electrically connected to the third control node EN3. The first electrode of the second control memory capacitor EC2 is electrically connected to the control electrode of the tenth control transistor ET10, and the second electrode of the second control memory capacitor EC2 is electrically connected to the fourth clock signal line ECB. The first electrode of the third control memory capacitor EC3 is electrically connected to the control electrode of the ninth control transistor ET9, and the second electrode of the third control memory capacitor EC3 is electrically connected to the third power line VGHe.

[0163] In this exemplary embodiment, as shown in Figure 19, the first control node EN1 is the connection point between the first control transistor ET1, the second control transistor ET2, the fourth control transistor ET4, the eighth control transistor ET8, the tenth control transistor ET10, and the second control memory capacitor EC2. The second control node EN2 is the connection point between the third control transistor ET3, the second control transistor ET2, the fifth control transistor ET5, the sixth control transistor ET6, and the first control memory capacitor EC1. The third control node EN3 is the connection point between the sixth control transistor ET6, the seventh control transistor ET7, and the first control memory capacitor EC1. The fourth control node EN4 is the connection point between the seventh control transistor ET7, the eighth control transistor ET8, the ninth control transistor ET9, and the third control memory capacitor EC3.

[0164] Next, we will explain using the example where the first control transistor ET1 to the tenth control transistor ET10 are all P-type transistors. We will explain using the first stage light-emitting drive subcircuit as an example. The control input terminal EIN of the first stage light-emitting drive subcircuit is electrically connected to the light-emitting start signal line ESTV. Figure 20 is an operation timing diagram of the light-emitting drive subcircuit shown in Figure 19. As shown in Figures 19 and 20, the light-emitting drive subcircuit according to this exemplary embodiment comprises 10 transistor units (i.e., the first control transistor ET1 to the tenth control transistor ET10), 3 capacitor units (i.e., the first control memory capacitor EC1 to the third control memory capacitor EC3), 3 input terminals (i.e., the third clock signal line ECK, the fourth clock signal line ECB, and the control input terminal EIN), 1 output terminal (i.e., the control output terminal EOUT), and 2 power supply terminals (i.e., the third power supply line VGHe and the fourth power supply line VGLe). The third power line VGHe can continuously supply high-level signals, and the fourth power line VGLe can continuously supply low-level signals.

[0165] In some examples, as shown in Figures 19 and 20, the operation process of the light-emitting drive subcircuit in this example includes the following five steps.

[0166] In the first stage S21, the third clock signal provided from the third clock signal line ECK is at a low level, causing the first control transistor ET1 and the third control transistor ET3 to conduct. The conducted first control transistor ET1 transmits the high-level signal from the control input terminal EIN to the first control node EN1, thereby raising the level of the first control node EN1, which cuts off the second control transistor ET2, the eighth control transistor ET8, and the tenth control transistor ET10. The conducted third control transistor ET3 also transmits the low-level signal from the fourth power line VGLe to the second control node EN2, thereby lowering the level of the second control node EN2, which causes the fifth control transistor ET5 and the sixth control transistor ET6 to conduct. The fourth clock signal provided from the fourth clock signal line ECB is at a high level, which cuts off the seventh control transistor ET7 and the fourth control transistor ET4. Additionally, the memory function of the third control memory capacitor EC3 cuts off the ninth control transistor ET9. In the first stage S21, both the ninth control transistor ET9 and the tenth control transistor ET10 were cut off, so the signal at the control output terminal EOUT remained at the previous low level.

[0167] In the second stage S22, the fourth clock signal supplied from the fourth clock signal line ECB is at a low level, thereby conducting the fourth control transistor ET4 and the seventh control transistor ET7. The signal from the third clock signal line ECK is at a high level, thereby cutting off the first control transistor ET1 and the third control transistor ET3. Due to the memory function of the first control memory capacitor EC1, the second control node EN2 can continue to maintain the low level from the previous stage, thereby conducting the fifth control transistor ET5 and the sixth control transistor ET6. The high-level signal from the third power line VGHe is transmitted to the first control node EN1 via the conducted fifth control transistor ET5 and the fourth control transistor ET4, thereby causing the level of the first control node EN1 to continue to maintain the high level from the previous stage, thereby cutting off the second control transistor ET2, the eighth control transistor ET8, and the tenth control transistor ET10. Furthermore, the low-level signal of the fourth clock signal line ECB is transmitted to the control electrode of the ninth control transistor ET9 via the conductive sixth control transistor ET6 and the seventh control transistor ET7, causing the ninth control transistor ET9 to conduct. The conductive ninth control transistor ET9 outputs the high-level signal of the third power line VGHe, resulting in a high-level signal at the control output terminal EOUT.

[0168] In the third stage S23, the third clock signal on the third clock signal line ECK is at a low level, causing the first control transistor ET1 and the third control transistor ET3 to conduct. The signal on the fourth clock signal line ECB is at a high level, causing the fourth control transistor ET4 and the seventh control transistor ET7 to cut off. Due to the memory function of the third control memory capacitor EC3, the ninth control transistor ET9 remains in a conduction state, and the conducted ninth control transistor ET9 outputs a high-level signal on the third power line VGHe, causing the signal at the control output terminal EOUT to remain at a high level. In the fourth stage S24, the third clock signal on the third clock signal line ECK is at a high level, which cuts off the first control transistor ET1 and the third control transistor ET3. The signal on the fourth clock signal line ECB is at a low level, which causes the fourth control transistor ET4 and the seventh control transistor ET7 to conduct. Due to the memory function of the second control memory capacitor EC2, the level of the first control node EN1 remains at the high level from the previous stage, which cuts off the second control transistor ET2, the eighth control transistor ET8, and the tenth control transistor ET10. Due to the memory function of the first control memory capacitor EC1, the second control node EN2 continues to maintain the low level from the previous stage, which causes the fifth control transistor ET5 and the sixth control transistor ET6 to conduct. Furthermore, the low-level signal of the fourth clock signal line ECB is transmitted to the control electrode of the ninth control transistor ET9 via the conductive sixth control transistor ET6 and the seventh control transistor ET7, thereby causing the ninth control transistor ET9 to conduct. The conductive ninth control transistor ET9 outputs the high-level signal of the third power line VGHe, and as a result, the signal at the control output terminal EOUT remains at a high level.

[0169] In the fifth stage S25, the signal on the third clock signal line ECK is at a low level, which causes the first control transistor ET1 and the third control transistor ET3 to conduct. The signal on the fourth clock signal line ECB is at a high level, which causes the fourth control transistor ET4 and the seventh control transistor ET7 to be cut off. The conducted first control transistor ET1 transmits the low-level signal from its control input terminal EMIN to the first control node EN1, thereby lowering the level of the first control node EN1, which causes the second control transistor ET2, the eighth control transistor ET8, and the tenth control transistor ET10 to conduct. The conducted second control transistor ET2 transmits the low-level signal from the third clock signal line ECK to the second control node EN2, which further lowers the level of the second control node EN2, causing it to continue at the low level of the previous stage, thereby causing the fifth control transistor ET5 and the sixth control transistor ET6 to conduct. Furthermore, the conductive eighth control transistor ET8 transmits the high-level signal from the third power line VGHe to the control electrode of the ninth control transistor ET9, thereby cutting off the ninth control transistor ET9. The conductive tenth control transistor ET10 outputs the low-level signal from the fourth power line VGLe, causing the signal at the control output terminal EOUT to become low level.

[0170] In this example, the control output terminal EOUT of the light-emitting drive subcircuit can provide a light-emitting control signal to the pixel circuit of the display area via the light-emitting control line.

[0171] Figure 21 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. Figure 22A is a schematic partial plan view of the peripheral region after the bottom metal layer has been formed in Figure 21. Figure 22B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 21.

[0172] In some examples, as shown in Figure 21, the third power line VGHe, the third clock signal line ECK, and the fourth clock signal line ECB may be located on the side of the light-emitting drive subcircuit away from the display area along the first direction X, and may be arranged sequentially along the direction away from the display area. The fourth power line VGLe and the light-emitting start signal line ESTV may be located on the side of the light-emitting drive subcircuit closer to the display area along the first direction X. The scanning drive circuit may be installed on the side of the fourth power line VGLe and the light-emitting start signal line ESTV closer to the display area. The third power line VGHe, the third clock signal line ECK, the fourth clock signal line ECB, the fourth power line VGLe, and the light-emitting start signal line ESTV may all extend along the second direction Y.

[0173] In some examples, as shown in Figure 21, the light-emitting drive subcircuit may be located between the fourth power line VGLe and the third power line VGHe. The seventh control transistor ET7, the fifth control transistor ET5, the fourth control transistor ET4, and the first control transistor ET1 may be arranged sequentially along the second direction Y and located on the side closer to the display area of ​​the third power line VGHe. The eighth control transistor ET8 may be located between the seventh control transistor ET7 and the ninth control transistor ET9 in the first direction X. The sixth control transistor ET6 may be located on the side of the fifth control transistor ET5 away from the third power line VGHe. The first control transistor ET1, the second control transistor ET2, and the third control transistor ET3 may be arranged sequentially along the first direction X and located between the third power line VGLe and the second control memory capacitor EC2. The tenth control transistor ET10 may be located between the second control memory capacitor EC2 and the fourth power line VGLe. The ninth control transistor ET9 and the tenth control transistor ET10 may be arranged sequentially along the second direction Y. The third control memory capacitor EC3, the first control memory capacitor EC1, and the second control memory capacitor EC2 may be arranged sequentially in the second direction Y. The third control memory capacitor EC3 may be located on the side away from the first control memory capacitor EC1 of the seventh control transistor ET7 and the eighth control transistor ET8. The first control memory capacitor EC1 may be located between the seventh control transistor ET7 and the sixth control transistor ET6. The first control transistor ET1 may be located on the side away from the display area of ​​the tenth control transistor ET10.

[0174] In some examples, as shown in Figures 21 to 22B, the semiconductor layer in the peripheral region may include at least the active layers of multiple transistors in the light-emitting drive subcircuit (for example, the active layer ET10 of the first control transistor, the active layer ET20 of the second control transistor, the active layer ET30 of the third control transistor, the active layer ET40 of the fourth control transistor, the active layer ET50 of the fifth control transistor, the active layer ET60 of the sixth control transistor, the active layer ET70 of the seventh control transistor, the active layer ET80 of the eighth control transistor, the active layer ET90 of the ninth control transistor, and the active layer ET100 of the tenth control transistor). In some examples, the active layer ET40 of the fourth control transistor and the active layer ET50 of the fifth control transistor may be a single integrated structure. The active layer ET90 of the ninth control transistor and the active layer ET100 of the tenth control transistor may also be a single integrated structure.

[0175] In some examples, as shown in Figure 22B, the first conductive layer in the peripheral region may include at least control electrodes for multiple transistors of the light-emitting drive subcircuit (for example, control electrodes ET13 for the first control transistor, ET23 for the second control transistor, ET33 for the third control transistor, ET43 for the fourth control transistor, ET53 for the fifth control transistor, ET63 for the sixth control transistor, ET73 for the seventh control transistor, ET83 for the eighth control transistor, ET93 for the ninth control transistor, and ET103 for the tenth control transistor), as well as the first electrode EC1-1 of the first control memory capacitor of the light-emitting drive subcircuit, the first electrode EC2-1 of the second control memory capacitor, and the first electrode EC3-1 of the third control memory capacitor.

[0176] In some examples, as shown in Figure 22B, the control electrode ET53 of the fifth control transistor, the control electrode ET63 of the sixth control transistor, and the first electrode EC1-1 of the first control memory capacitor may be integrated into a single structure. The control electrode ET23 of the second control transistor, the control electrode ET83 of the eighth control transistor, the control electrode ET103 of the tenth control transistor, and the first electrode EC2-1 of the second control memory capacitor may be integrated into a single structure. The control electrode ET13 of the first control transistor and the control electrode ET33 of the third control transistor may be integrated into a single structure. The control electrode ET93 of the ninth control transistor and the first electrode EC3-1 of the third control memory capacitor may be integrated into a single structure.

[0177] In some examples, as shown in Figure 21, the second conductive layer in the peripheral region may include at least the second electrode of the first control memory capacitor EC2 of the light-emitting drive subcircuit, the second electrode of the second control memory capacitor EC2, the second electrode of the third control memory capacitor EC3, and the control output terminal EOUT. The orthographic projection of the second electrode of the first control memory capacitor EC2 on the substrate may be located within the range of the orthographic projection of the first electrode EC1-1 on the substrate. The orthographic projection of the second electrode of the second control memory capacitor EC2 on the substrate may be located within the range of the orthographic projection of the first electrode EC2-1 on the substrate. The orthographic projection of the second electrode of the third control memory capacitor EC3 on the substrate may be located within the range of the orthographic projection of the first electrode EC3-1 on the substrate. The control output terminal EOUT may be located on the side closer to the display area of ​​the active layer ET90 of the ninth control transistor and the active layer ET100 of the tenth control transistor. The orthographic projection of the control output terminal EOUT on the substrate may be F-shaped. The control output terminal EOUT may be extended until it is electrically connected to the first output connection line 35 in the above embodiment, thereby providing a light emission control signal to the pixel circuit of the display area.

[0178] In some examples, as shown in Figure 21, the third conductive layer in the peripheral region may include at least a plurality of connection electrodes for the light-emitting drive subcircuit, a third clock signal line ECK, a fourth clock signal line ECB, a third power supply line VGHe, a fourth power supply line VGLe, and a control input terminal EIN.

[0179] In some examples, as shown in Figure 22A, the bottom metal layer 10 of the peripheral region may comprise a second metal block 105 and a third connecting structure 106. The third connecting structure 106 may be located on the side of the second metal block 105 closer to the display area. The third connecting structure 106 may comprise a sixth connecting portion 1061 extending along a first direction X. The sixth connecting portion 1061 may be a stripe structure extending along the first direction X closer to the display area. For example, the sixth connecting portion 1061 may be electrically connected to the fifth connecting portion of the second connecting structure in the above-described embodiment. For example, one sixth connecting portion and one fifth connecting portion may be an integral structure. The electrical connection between the sixth connecting portion and the fifth connecting portion enables the electrical connection between the first metal block and the second metal block. The second metal block 105 may be configured to receive a constant voltage electrical signal via the first metal block. However, this embodiment is not limited thereto. In some other examples, the bottom metal layer 10 may be a planar metal structure, that is, the third connecting structure and the second connecting structure may be a single planar metal block rather than a striped structure.

[0180] In some examples, one second metal block 105 may correspond to one light-emitting drive subcircuit. Adjacent second metal blocks 105 may be a single integrated structure. However, this embodiment is not limited to this. In some other examples, one second metal block 105 may correspond to multiple light-emitting drive subcircuits. In some other examples, at least two adjacent second metal blocks may be installed individually and not connected.

[0181] In some examples, as shown in Figure 22A, the orthographic projection of one second metal block 105 on the substrate may cover the orthographic projection of the channel region of the active layer of multiple control transistors of one light-emitting drive subcircuit on the substrate. For example, the orthographic projection of the second metal block 105 on the substrate may cover the orthographic projection of the active layer of all control transistors (e.g., including the first control transistor ET1 to the tenth control transistor ET10) of the corresponding light-emitting drive subcircuit on the substrate. The orthographic projection of the second metal block 105 on the substrate may also cover the orthographic projection of multiple control nodes of the light-emitting drive subcircuit on the substrate, thereby using the second metal block 105 to block electrostatic effects on the multiple control nodes. The orthographic projection of the second metal block 105 on the substrate and the orthographic projection of the three control memory capacitors of the light-emitting drive subcircuit on the substrate may overlap at least partially, which is advantageous for improving the stability of the corresponding control node, and the capacitance resulting from the overlap between the second metal block and the control memory capacitors can be used to reduce the area of ​​the control memory capacitors, thereby reducing the space occupied by the control memory capacitors. In this example, the second metal block 105 may be located below the light-emitting drive subcircuit, shielding the light-emitting drive subcircuit over a large area, thereby blocking static electricity and improving the electrostatic discharge resistance of the light-emitting drive subcircuit.

[0182] In some examples, as shown in Figure 22A, the orthographic projection of the second metal block 105 on the substrate may be rectangular. Adjacent second metal blocks 105 may be a single integrated structure. The connection angle (e.g., corner 1051) between the second metal block 105 and the sixth extension 1061 of the third connecting structure 106 may be designed as a rounded corner, thereby reducing the risk of electrostatic discharge during the manufacturing process.

[0183] In some examples, the bottom metal layer of the peripheral region may shield the scanning drive subcircuit and the light emission drive subcircuit over a large area, that is, it may cover the orthographic projection on the substrate substrate of the channel region of the active layer of at least all transistors in the scanning drive subcircuit and the light emission drive subcircuit, thereby protecting the scanning drive subcircuit and the light emission drive subcircuit, which allows the gate drive circuit to operate stably even under conditions where static electricity accumulates, and the electrostatic discharge immunity of the gate drive circuit is enhanced.

[0184] The remaining details regarding the display board of this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0185] Figure 23 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. Figure 24A is a schematic partial plan view of the peripheral region after the bottom metal layer has been formed in Figure 23. Figure 24B is a schematic partial plan view of the peripheral region after the first conductive layer has been formed in Figure 23.

[0186] In some examples, as shown in Figures 23 to 24B, the bottom metal layer 10 of the peripheral region may comprise a second metal block 105 and a third connecting structure 106. The orthographic projection of one second metal block 105 on the substrate may cover the orthographic projection on the substrate of the channel region of the active layer of a plurality of control transistors (e.g., the first control transistor ET1 to the tenth control transistor ET10) of a single light-emitting drive subcircuit. For example, the orthographic projection of the second metal block 105 on the substrate and the orthographic projection on the substrate of the doping region of the active layer of the corresponding plurality of control transistors (e.g., output transistors) of the light-emitting drive subcircuit may partially overlap. The shape of the second metal block 105 in this example may correspond to the shape and arrangement of the control transistors of the light-emitting drive subcircuit. In this example, the second metal block of the bottom metal layer can shield the channel region of the active layer of the transistor in the light-emitting drive subcircuit, thereby blocking static electricity and protecting the light-emitting drive subcircuit. This allows the gate drive circuit to operate stably even under conditions where static electricity accumulates, thereby increasing the electrostatic discharge resistance of the gate drive circuit. The remaining description of the display substrate in this embodiment can be found in the description of the previously mentioned embodiment and will not be repeated here.

[0187] Figure 25 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. Figure 26 is a schematic partial plan view of the peripheral region in Figure 25 after the bottom metal layer has been formed.

[0188] In some examples, as shown in Figures 25-26, the bottom metal layer 10 of the peripheral region may comprise a second metal block 105 and a fourth connecting structure 107. The fourth connecting structure 107 may be located on the side of the second metal block 105 away from the display area. The fourth connecting structure 107 may comprise a seventh connecting portion 1071 extending along a first direction X. The seventh connecting portion 1071 may be a stripe structure extending along the first direction X away from the display area. The seventh connecting portion 1071 may extend below the peripheral power lines and be electrically connected to the peripheral power lines via vias opened in the insulating layer, thereby enabling the second metal block 105 to receive a constant voltage electrical signal, for example, a second voltage signal.

[0189] In this example, the bottom metal layer 10 may be configured to be electrically connected to two constant voltage electrical signals. Multiple second metal blocks 105 may be a single integrated structure and may be electrically connected to peripheral power lines via a fourth connection structure 107, thereby receiving a stable second voltage signal at a constant voltage. Multiple first metal blocks may be a single integrated structure and may be electrically connected to the pixel metal blocks of the display area via a first connection structure, thereby being electrically connected to the first pixel power lines via the pixel metal blocks, and receiving a stable first voltage signal at a constant voltage.

[0190] In some examples, as shown in Figures 25 and 26, the orthographic projection of one second metal block 105 on the substrate may cover the orthographic projection of the channel region of the active layer of multiple control transistors of one light-emitting drive subcircuit on the substrate. For example, the orthographic projection of the second metal block 105 on the substrate may cover the orthographic projection of the active layer of multiple control transistors of the corresponding light-emitting drive subcircuit on the substrate. For example, the orthographic projection of the second metal block 105 on the substrate may be rectangular. Adjacent second metal blocks 105 may be a single integrated structure. The connection angle (e.g., corner 1052) between the second metal block 105 and the seventh connection portion 1071 of the fourth connection structure 107 may be designed as a rounded corner, thereby reducing the risk of electrostatic discharge during the manufacturing process. The remaining structure of the display substrate in this embodiment can be found in the description of the embodiments above and will not be repeated here.

[0191] Figure 27 is a schematic partial plan view of the peripheral region in at least one embodiment of the present disclosure. Figure 28 is a schematic partial plan view of the peripheral region after the bottom metal layer has been formed in Figure 27. Figure 29 is a schematic partial view of the bottom metal layer in the peripheral region in at least one embodiment of the present disclosure.

[0192] In some examples, as shown in Figures 27 to 29, the bottom metal layer 10 of the peripheral region may comprise a second metal block 105, a third connecting structure 106, and a fourth connecting structure 107. The third connecting structure 106 may be located on the side of the second metal block 105 closer to the display area. The third connecting structure 106 may comprise a sixth connecting portion 1061 extending along a first direction X. The sixth connecting portion 1061 may be a stripe structure extending along the first direction X closer to the display area. The sixth connecting portion 1061 may be electrically connected to the fifth connecting portion 1041 of the second connecting structure 104, and may be, for example, an integrated structure. The electrical connection between the sixth connecting portion 1061 and the fifth connecting portion 1041 enables the electrical connection between the first metal block 101 and the second metal block 105. The fourth connecting structure 107 may be located on the side of the second metal block 105 away from the display area. The fourth connection structure 107 may include a seventh connection portion 1071 extending along a first direction X. The seventh connection portion 1071 may be a stripe structure extending along the first direction X away from the display area. The seventh connection portion 1071 may extend below the peripheral power lines and be electrically connected to the peripheral power lines via vias opened in the insulating layer, thereby enabling the second metal block 105 to receive a constant voltage electrical signal, for example, a second voltage signal. In some examples, the second metal block 105 and the first metal block 101 of the bottom metal layer 10 may be a single structure and may be configured to be electrically connected to the same constant voltage electrical signal (e.g., a second voltage signal). In some other examples, the seventh connection portion 1071 of the fourth connection structure 107 may be electrically connected to a clock signal line (e.g., a fourth clock signal line ECB or a third clock signal line ECK), thereby configured to receive a clock signal. In some other examples, the sixth connection portion 1061 of the third connection structure 106 may be electrically connected to a clock signal line (for example, a first clock signal line or a second clock signal line). The remaining structure of the display board in this embodiment can be found in the description of the above embodiment and will not be repeated here.

[0193] Figure 30 is a schematic partial plan view of a peripheral region in at least one embodiment of the present disclosure. Figure 31A is a schematic partial plan view of the peripheral region in Figure 30 after the bottom metal layer has been formed. Figure 31B is a schematic partial plan view of the peripheral region in Figure 30 after the semiconductor layer has been formed. Figure 31C is a schematic partial plan view of the peripheral region in Figure 30 after the first conductive layer has been formed. In this example, a bottom metal layer corresponding to one scanning drive subcircuit is described as an example, where one first circuit unit may comprise one transistor or one capacitor of the scanning drive subcircuit. In Figure 31A, the connection lines of the first metal block of the bottom metal layer are schematically shown, while in Figures 30, 31B, and 31C, the connection lines of the first metal block are omitted from the illustration.

[0194] In some examples, as shown in Figures 30 to 31C, the bottom metal layer 10 of the peripheral region may comprise a plurality of first metal blocks (e.g., including first metal blocks 101a to 101g). For example, one first metal block may correspond to one first circuit unit (e.g., one transistor). In some examples, the first metal block 101a may correspond to the first shift transistor, for example, covering the channel region of the active layer GT10 of the first shift transistor; the first metal block 101b may correspond to the second shift transistor, for example, covering the channel region of the active layer GT20 of the second shift transistor; the first metal block 101c may correspond to the third shift transistor, for example, covering the channel region of the active layer GT30 of the third shift transistor; the first metal block 101d may correspond to the sixth and seventh shift transistors, for example, covering the channel regions of the active layer GT60 of the sixth shift transistor and the active layer GT70 of the seventh shift transistor; and the first metal block 101e may correspond to the eighth shift transistor, for example, covering the channel region of the active layer GT80 of the eighth shift transistor. The first metal block 101f may correspond to a fourth shift transistor, for example, by covering the channel region of the active layer GT40 of the fourth shift transistor, and the first metal block 101g may correspond to a fifth shift transistor, for example, by covering the channel region of the active layer GT50 of the fifth shift transistor. In some other examples, at least two first metal blocks in Figure 30A may form an integrated structure connected to each other.

[0195] In some examples, as shown in Figure 31A, multiple first metal blocks 101a to 101g may be installed independently. The first metal block 101a may be electrically connected to the first signal line L1 via a first connecting line, the first metal block 101b may be electrically connected to the second signal line L2 via a second connecting line, the first metal block 101c may be electrically connected to the third signal line L3 via a third connecting line, the first metal block 101d may be electrically connected to the fourth signal line L4 via a fourth connecting line, the first metal block 101e may be electrically connected to the fifth signal line L5 via a fifth connecting line, the first metal block 101f may be electrically connected to the sixth signal line L6 via a sixth connecting line, and the first metal block 101g may be electrically connected to the seventh signal line L7 via a seventh connecting line. The first signal lines L1 to the seventh signal lines L7 may be of different types, that is, they may transmit different signals, or at least two of the first signal lines L1 to the seventh signal lines L7 may transmit the same signal. For example, the first signal lines L1 to the seventh signal lines L7 may all be of the same type, that is, they may transmit the same signal. In some examples, the first signal lines L1 to the seventh signal lines L7 may all be configured to transmit the same signal as the first pixel power supply wiring. In some other examples, the first signal lines L1 to the fifth signal lines L5 may all be configured to transmit the same signal as the peripheral power supply wiring, and the sixth signal line L6 and the seventh signal line L7 may all be configured to transmit the same signal as the first pixel power supply wiring. However, this embodiment is not limited to this. The remaining structure of the display board in this embodiment can be described in the above-mentioned embodiment and will not be repeated here.

[0196] In some other examples, the gate drive circuit in the peripheral region may further include a reset control drive circuit, which may be configured to provide a reset control signal to the reset control line in the display region. For example, the reset control drive circuit may be located between the scanning drive circuit and the light emission control drive circuit. The bottom metal layer may include a metal block corresponding to the reset control drive circuit, thereby providing electrostatic isolation to the reset control drive circuit, and the signal line connected to the metal block that isolates the reset control drive circuit may be the same type of signal line as the signal line connected to the first metal block, or the same type of signal line as the signal line connected to the second metal block, or a different type of signal line than the signal lines connected to the first and second metal blocks. This embodiment does not limit the structure of the gate drive circuit.

[0197] In some other examples, the above embodiments may be combined with each other. In some examples, the bottom metal layer may be a planar metal layer, and the first and second metal blocks may both be planar metal blocks and may be integral structures, and no cavities or cavities are provided. In some other examples, cavities or cavities may be provided in at least one of the first and second metal blocks of the bottom metal layer. In some other examples, the bottom metal layer may be electrically connected to a clock signal line (e.g., at least one of the first to fourth clock signal lines) via the first or second metal block, thereby receiving pulse signals.

[0198] Figure 32 is a schematic diagram of a display device in at least one embodiment of the present disclosure. In some examples, as shown in Figure 32, this embodiment provides a display device 91 comprising a display board 910. The display board 910 may be an OLED display board, a QLED display board, a Micro-LED display board, or a Mini-LED display board. The display device 91 may be any product or component having a display function, such as an OLED display device, a wristwatch, a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, or a navigator. However, this embodiment is not limited thereto.

[0199] In the drawings of this disclosure, only structures relating to this disclosure are shown; for other structures, conventional designs can be referenced. Unless they conflict, embodiments of this disclosure, i.e., features in the embodiments, can be combined to form new embodiments. Modifications or equivalent substitutions to the invention of this disclosure can be made without departing from the spirit and scope of the invention, as will be understood by those skilled in the art, and such modifications or substitutions should be included within the claims of this application. [Explanation of Symbols]

[0200] 10 Bottom metal layer 35. First output connection line 51 Input Sub-circuit 52 First control subcircuit 53 Output sub-circuit 54 Second control sub-circuit 91 Display device 101 First Metal Block 101a~g First metal block 102 First connection structure 103-pixel metal block 104 Second connection structure 105 Second Metal Block 106 Third Connection Structure 107 Fourth connection structure 110 Cavity area 201 Input Connection Cable 202 node relay electrodes 301-313 1st-13th connecting electrodes 910 Display board 1010 First main body 1011~1014 1st~4th extension section 1015a~d 5th stretching section 1016a~c 1st cavity 1017 Second cavity 1021 First connection section 1022 Second connection section 1023 Third connection section 1024 Fourth connection section 1041 Fifth connection section 1051 Corner 1052 corner 1061 Sixth connection section 1071 Seventh Connection Section AA display area B1 Lower bezel B2 Upper Bezel B3 Left Bezel B4 Right Bezel BB surrounding area

Claims

1. A display board comprising a substrate board, a bottom metal layer, and a gate drive circuit, The substrate board comprises a display area and a peripheral area located around the display area. The bottom metal layer is located at least in the peripheral region and is electrically connected to at least one type of signal line. The gate drive circuit is located in the peripheral region and on the side of the bottom metal layer away from the substrate, and the gate drive circuit comprises a plurality of first circuit units. A display board in which the orthographic projection of the bottom metal layer on the substrate board and the orthographic projection of at least one first circuit unit on the substrate board overlap at least partially.

2. The display substrate according to claim 1, wherein the at least one first circuit unit comprises at least one transistor, and the orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the active layer of the at least one transistor of the at least one first circuit unit on the substrate substrate overlap at least partially.

3. The display substrate according to claim 2, wherein the active layer of the at least one transistor comprises at least one channel region, and the orthographic projection of the bottom metal layer on the substrate covers the orthographic projection of the channel region of the active layer of the at least one transistor on the substrate.

4. The display substrate according to claim 2, wherein the at least one first circuit unit comprises a plurality of transistors, and the orthographic projection of the bottom metal layer on the substrate substrate covers the orthographic projection of the active layer of the plurality of transistors of the at least one first circuit unit on the substrate substrate.

5. The at least one first circuit unit comprises an input subcircuit and a first control subcircuit, wherein the input subcircuit is configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line, and the first control subcircuit is configured to control the potential of a second shift node under the control of the first clock signal line and the first shift node. The first control subcircuit is electrically connected to the second shift node via a node relay electrode. The display substrate according to any one of claims 1 to 4, wherein the orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the node relay electrode on the substrate substrate overlap at least partially.

6. The at least one first circuit unit comprises an input subcircuit, a first control subcircuit, and a second control subcircuit, wherein the input subcircuit is configured to provide a shift input terminal signal to a first shift node under the control of a first clock signal line, the first control subcircuit is configured to control the potential of a second shift node under the control of the first clock signal line and the first shift node, and the second control subcircuit is configured to conduct the first shift node and the third shift node under the control of a second power line. The input subcircuit, the first control subcircuit, and the second control subcircuit are electrically connected to the first shift node via the first connecting electrode. The display substrate according to any one of claims 1 to 4, wherein the orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the first connecting electrode on the substrate substrate overlap at least partially.

7. The at least one first circuit unit comprises a second control subcircuit and an output subcircuit, wherein the second control subcircuit is configured to conduct the first shift node and the third shift node under the control of a second power line, and the output subcircuit is configured to control the output signals at the shift output terminals under the control of the second shift node and the third shift node, and the second control subcircuit and the output subcircuit are electrically connected to the third shift node via a seventh connecting electrode. The display substrate according to any one of claims 1 to 4, wherein the orthographic projection of the bottom metal layer on the substrate substrate covers the orthographic projection of the seventh connecting electrode on the substrate substrate.

8. The display board according to claim 1, wherein the at least one first circuit unit comprises at least one capacitor, and the orthographic projection of the bottom metal layer on the substrate substrate and the orthographic projection of the at least one capacitor of the at least one first circuit unit on the substrate substrate overlap at least partially.

9. The bottom metal layer comprises a plurality of first metal blocks, and the orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate overlap at least partially. The display board according to any one of claims 1 to 8, wherein the plurality of first metal blocks are integrally structured and electrically connected to signal lines of the same type.

10. The display substrate according to claim 9, wherein the integral structure formed from the plurality of first metal blocks is a planar metal block and does not have any cavities.

11. The display substrate according to claim 9, wherein the at least one first metal block has a first cavity, the at least one first circuit unit comprises an output transistor, and the orthographic projection of the first cavity of the at least one first metal block on the substrate substrate and the orthographic projection of the doping region of the active layer of the output transistor on the substrate substrate partially overlap.

12. The display substrate according to claim 9, wherein a cavity region is provided between at least two adjacent first metal blocks.

13. The gate drive circuit further comprises a plurality of cascaded second circuit units, the plurality of cascaded second circuit units located on the side of the plurality of first circuit units away from the display area, at least one second circuit unit is electrically connected to a first output connection line, the first output connection line extends toward the display area, The display board according to claim 12, wherein the orthographic projection of the first output connection line on the substrate board and the orthographic projection of the cavity region between adjacent first metal blocks on the substrate board partially overlap.

14. The gate drive circuit further comprises a plurality of cascaded second circuit units, the plurality of cascaded second circuit units located on the side of the plurality of first circuit units away from the display area, the bottom metal layer further comprises a plurality of second metal blocks, the plurality of second metal blocks located on the side of the plurality of first metal blocks away from the display area, and the orthographic projection of at least one of the plurality of second metal blocks on the substrate substrate and the orthographic projection of one or more second circuit units on the substrate substrate overlap at least partially. The display board according to claim 9, wherein the plurality of second metal blocks are integrally structured and are electrically connected to signal lines of a different type from the plurality of second metal blocks and the plurality of first metal blocks.

15. The bottom metal layer comprises a plurality of first metal blocks, and the orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate overlap at least partially. The display board according to any one of claims 1 to 8, wherein at least two of the plurality of first metal blocks are electrically connected to different types of signal lines.

16. The gate drive circuit comprises a plurality of cascaded first circuit units and a plurality of cascaded second circuit units, wherein the plurality of cascaded second circuit units are located on the side of the plurality of cascaded first circuit units away from the display area, the bottom metal layer comprises a plurality of first metal blocks and a plurality of second metal blocks, wherein the plurality of second metal blocks are located on the side of the plurality of first metal blocks away from the display area, the orthographic projection of at least one first metal block on the substrate substrate and the orthographic projection of one or more first circuit units on the substrate substrate overlap at least partially, the orthographic projection of at least one second metal block among the plurality of second metal blocks on the substrate substrate and the orthographic projection of one or more second circuit units on the substrate substrate overlap at least partially, The display board according to claim 1, wherein at least one second metal block is connected to the same type of signal line as at least one first metal block.

17. The display substrate according to claim 16, wherein the plurality of second metal blocks and the plurality of first metal blocks are integrally structured.

18. The display board according to any one of claims 1 to 17, wherein the at least one type of signal line includes at least one of peripheral power supply wiring, clock signal lines, and first pixel power supply wiring.

19. Multiple pixel circuits and multiple pixel metal blocks are installed in the display area, and the multiple pixel circuits are electrically connected to the first pixel power supply wiring. At least one pixel circuit comprises a drive transistor, and the orthographic projection of at least one pixel metal block on the substrate substrate and the orthographic projection of the active layer of the drive transistor of at least one pixel circuit on the substrate substrate overlap at least partially. The display board according to claim 18, wherein the first metal block of the bottom metal layer is electrically connected to the first pixel power wiring via the at least one pixel metal block.

20. The display substrate according to any one of claims 1 to 19, wherein the edge of the bottom metal layer has at least one of a convex angle and a concave angle, and at least one of the convex angle and the concave angle is rounded.

21. A display device comprising a display board according to any one of claims 1 to 20.

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