Indication device

Abstract

A display device is provided. The display device includes a display panel and an input sensor disposed on the display panel. The input sensor may include an insulating layer, a sensing pattern, and a dummy pattern disposed between the sensing pattern and the insulating layer. The dummy pattern may be superimposed on a broken region of the line component of the sensing pattern or on a separated region of the line pattern of the sensing pattern.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device including an input sensor.

Background Art

[0002] A variety of display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, game machines, etc. have been developed. The input devices of the display device include a keyboard or a mouse. Also, the display device includes an input sensor as an input device.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a display device including an input sensor with reduced visibility.

Means for Solving the Problems

[0004] A display device according to an embodiment of the present invention includes a display panel including a plurality of light-emitting regions and non-light-emitting regions adjacent to the plurality of light-emitting regions, and an input sensor disposed on the display panel. The input sensor may include an insulating layer, a first sensing electrode, a second sensing electrode including a sensing pattern spaced apart from the first sensing electrode in a plan view, and a dummy pattern, wherein the insulating layer is disposed between the dummy pattern and the first sensing electrode, and between the sensing pattern of the second sensing electrode and the dummy pattern. Each of the first sensing electrode and the second sensing electrode defines a plurality of opening regions overlapping corresponding light-emitting regions among the plurality of light-emitting regions, and includes a line component overlapping the non-light-emitting region. The line component of the first sensing electrode and the line component of the second sensing electrode are spaced apart to define a boundary region, and at least a part of the dummy pattern may overlap the boundary region.

Advantages of the Invention

[0005] According to the present invention, a dummy pattern can increase the amount of external light reflected in the disconnected region or boundary region. The dummy pattern reduces the difference between the amount of external light reflected in the region where the line component is located and the amount of external light reflected in the region corresponding to the disconnected region or boundary region. This may reduce the visibility of the input sensor. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective view of a display device according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view of a display device according to one embodiment of the present invention. [Figure 3] This is a plan view of a display panel according to one embodiment of the present invention. [Figure 4a] This is an enlarged plan view of the display area according to one embodiment of the present invention. [Figure 4b] This is an enlarged plan view of the display area according to one embodiment of the present invention. [Figure 4c] This is an enlarged plan view of the display area according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of the display device corresponding to I-I' in Figure 4a. [Figure 6a] This is a plan view of an input sensor according to one embodiment of the present invention. [Figure 6b] This is a cross-sectional view of the input sensor corresponding to line II-II' in Figure 6a. [Figure 7a] This is an enlarged plan view of the second conductive layer corresponding to the first region in Figure 6a. [Figure 7b] This is an enlarged plan view of the first conductive layer corresponding to the first region in Figure 6a. [Figure 7c] This is a plan view of the first region in Figure 6a, with a portion of it enlarged. [Figure 7d] This is a cross-sectional view corresponding to line III-III' in Figure 7c. [Figure 7e] Figure 7c is a perspective view showing the reflection of external light occurring in a specific region. [Figure 8a] This is an enlarged plan view of the second conductive layer corresponding to the second region in Figure 6a. [Figure 8b] This is an enlarged plan view of the first conductive layer corresponding to the second region in Figure 6a. [Figure 9a] This is an enlarged plan view of a portion of the first region of an input sensor according to one embodiment of the present invention. [Figure 9b] This is an enlarged plan view of a portion of the first region of an input sensor according to one embodiment of the present invention. [Figure 9c] This is an enlarged plan view of a portion of the first region of an input sensor according to one embodiment of the present invention. [Figure 9d] This is a cross-sectional view of an input sensor according to one embodiment of the present invention. [Modes for carrying out the invention]

[0007] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on top of" or "combined with" another component, it means that it can be directly placed on top of, connected to, or combined with the other component, or that a third component can be placed between them.

[0008] The same drawing symbol refers to the same component. Furthermore, in drawings, the thickness, proportions, and dimensions of components are exaggerated for the sake of effective explanation of the technical content. "and / or" includes all combinations of one or more components defined by the relevant component.

[0009] Terms such as "first," "second," etc., are used to describe a variety of components, but the components are not limited to those defined by these terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may also be named the first component. A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0010] Also, terms such as "downward", "lower side", "upward", "upper side" are used to explain the association relationship of the components shown in the drawings. The above terms are relative concepts and are explained based on the directions shown in the drawings.

[0011] Terms such as "include" or "have" specify the existence of features, numbers, steps, operations, components, parts described above in the specification or combinations thereof, and it should be understood that the existence or addition possibility of one or more other features, numbers, steps, operations, components, parts or combinations thereof is not precluded in advance.

[0012] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as those generally understood by those skilled in the technical field to which the present invention pertains. Also, terms the same as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings in the context of the related technology, and should not be interpreted in an overly ideal or formal meaning unless explicitly defined here.

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0014] FIG. 1 is a perspective view of a display device DD according to an embodiment of the present invention. As shown in FIG. 1, the display device DD can display an image through a display surface DD-IS. The display surface DD-IS is parallel to the surface defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display surface DD-IS, that is, the thickness direction of the display device DD is indicated by the third direction axis DR3.

[0015] The front (or upper surface) and the back (or lower surface) of each member or unit described below are divided by the third direction axis DR3. However, in this embodiment, the first to third direction axes DR1, DR2, DR3 are merely examples. Hereinafter, the first to third directions are the directions indicated by the first to third direction axes DR1, DR2, DR3 respectively, and the same drawing reference numerals are referred to.

[0016] In one embodiment of the present invention, a display device DD having a planar display surface is shown, but the invention is not limited thereto. The display device DD may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas that indicate different directions from each other, and may include, for example, a folded display surface. The display device DD according to this embodiment may be a flexible display device DD. The flexible display device DD may be a collapsible display device that can be folded.

[0017] In this embodiment, a display device DD that can be applied to a tablet terminal is shown as an example. Electronic modules, camera modules, power supply modules, etc., mounted on the main board can be arranged together with the display device DD in a bracket / casing to constitute a tablet terminal. The display device DD according to the present invention can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, car navigation systems, game consoles, and smartwatches.

[0018] As shown in Figure 1, the display surface DD-IS includes an image area DD-AA where the image is displayed, and a bezel area DD-NDA adjacent to the image area DD-AA. The bezel area DD-NDA is an area where no image is displayed. Figure 1 shows an icon image as an example of an image.

[0019] As shown in Figure 1, the image region DD-AA can be substantially quadrilateral. "Substantially quadrilateral" includes not only quadrilaterals in a mathematical sense, but also quadrilaterals in which no vertices are defined in the vertex region (or corner region) but curved boundaries are defined.

[0020] The bezel region DD-NDA may surround the image region DD-AA. However, the shape of the bezel region DD-NDA can be modified, not limited to this. For example, the bezel region DD-NDA may be located on only one side of the image region DD-AA.

[0021] Figure 2 is a cross-sectional view of a display device DD according to one embodiment of the present invention.

[0022] The display device DD may include a display module DM and a window WM positioned on the display module DM. The display module DM and the window WM may be bonded together by an adhesive layer PSA. According to one embodiment of the present invention, the window WM may be formed by a coating method, and the window WM may be in contact with the display module DM, in which case the adhesive layer PSA may be omitted.

[0023] The display panel DM may include a display panel 100, an input sensor 200, and an anti-reflective layer 300. The display panel 100 may include a base layer 110, a drive element layer 120, a light-emitting element layer 130, and a sealing layer 140.

[0024] A drive element layer 120 is placed on the upper surface of the base layer 110. The base layer 110 may be a flexible substrate that can be bent, folded, rolled, etc. The base layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiments of the present invention are not limited to these, and the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer. The base layer 110 has substantially the same shape as the display panel 100.

[0025] The base layer 110 may have a multilayer structure. For example, the base layer 110 may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed between them. The first and second synthetic resin layers may, but are not limited to, a polyimide resin.

[0026] The driving element layer 120 may be placed on top of the base layer 110. The driving element layer 120 may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and signal lines. The driving element layer 120 may include a pixel driving circuit.

[0027] The light-emitting element layer 130 may be placed on top of the driving element layer 120. The light-emitting element layer 130 may include light-emitting elements. For example, the light-emitting elements may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro-LEDs, or nano-LEDs.

[0028] The sealing layer 140 may be placed on top of the light-emitting element layer 130. The sealing layer 140 can protect the light-emitting element layer 130, i.e., the light-emitting element, from foreign matter such as moisture, oxygen, and dust particles. The sealing layer 140 may include at least one sealing inorganic layer. The sealing layer 140 may include a laminated structure of a first sealing inorganic layer / sealing organic layer / second sealing inorganic layer.

[0029] The input sensor 200 may be directly mounted on the display panel 100. The input sensor 200 may sense user input, for example, by electromagnetic induction and / or capacitance. The display panel 100 and the input sensor 200 may be formed by a continuous process. Here, "directly mounted" may mean that no third component is placed between the input sensor 200 and the display panel 100. For example, no separate adhesive layer may be placed between the input sensor 200 and the display panel 100.

[0030] The anti-reflective layer 200 reduces the reflectance of external light incident from above the window WM. An anti-reflective layer 300 according to one embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be of film type or liquid crystal coating type and may include a λ / 2 phase retarder or a λ / 4 phase retarder. The polarizer may also be of film type or liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement. The phase retarder and polarizer may further include a protective film. The phase retarder and polarizer themselves or the protective film may be defined as the base layer of the anti-reflective layer 300.

[0031] An anti-reflective layer 300 according to one embodiment of the present invention may include a color filter. The color filter has a predetermined arrangement. The arrangement of the color filter may be determined by considering the light-emitting color of the pixels included in the display panel 100. The anti-reflective layer 300 may further include a black matrix adjacent to the color filter. The anti-reflective layer 300 including the color filter may be placed directly on the display panel 100.

[0032] A window WM according to one embodiment of the present invention may include a base layer and a light-shielding pattern. The base layer may include a glass substrate and / or a synthetic resin film. The light-shielding pattern is partially superimposed on the base layer. The light-shielding pattern is located on the back of the base layer and may substantially define the bezel area DD-NDA of the display device DD (see Figure 1). Areas where the light-shielding pattern is not located may define the image area DD-DA of the display device DD (see Figure 1).

[0033] Figure 3 is a plan view of a display panel 100 according to one embodiment of the present invention.

[0034] Referring to Figure 3, the display panel 100 may include a plurality of pixels PX, a scan drive circuit SDV, a light emission drive circuit EDV, a plurality of signal lines, and a plurality of pads PD. The plurality of pixels PX are arranged in the display panel 100-DA. The drive chip DIC implemented in the non-display area 100-NDA may include a data drive circuit. The display panel 100-DA may correspond to the image area DD-DA in Figure 1, and the non-display area 100-NDA may correspond to the bezel area DD-NDA. In this specification, "areas or parts corresponding to each other" means superimposed, and means, but is not necessarily limited to, two different areas or parts having the same area. In one embodiment of the present invention, the data drive circuit may also be integrated into the display panel 100, like the scan drive circuit SDV and the light emission drive circuit EDV.

[0035] Multiple signal lines may include multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple light-emitting lines EL1 to ELm, first and second control lines SL-C1 and SL-C2, and first and second power lines PL1 and PL2. m and n are natural numbers greater than or equal to 2.

[0036] Scan lines SL1 to SLm can be extended in the first direction DR1 and electrically connected to the pixel PX and the scan drive unit SDV. Data lines DL1 to DLn can be extended in the second direction DR2 and electrically connected to the pixel PX and the drive chip DIC. Light emission lines EL1 to ELm can be extended in the first direction DR1 and electrically connected to the pixel PX and the light emission drive circuit EDV.

[0037] The first power supply line PL1 receives the first power supply voltage, and the second power supply line PL2 receives the second power supply voltage, which is at a lower level than the first power supply voltage. Although not shown in the diagram, the second electrode (e.g., cathode) of the light-emitting element is connected to the third power supply line PL2.

[0038] The first control line SL-C1 is connected to the scan drive circuit SDV and may extend toward the lower edge of the display panel 100. The second control line SL-C2 is connected to the light-emitting drive circuit EDV and may extend toward the lower edge of the display panel 100. The pad PD is located in the non-display area 100-NDA adjacent to the lower edge of the display panel 100 and may be even closer to the lower edge of the display panel 100 than the drive chip DIC. The pad PD may be connected to some of the signal lines of the drive chip DIC.

[0039] The scan drive unit SDV generates multiple scan signals, which can be applied to the pixel PX via scan lines SL1 to SLm. The drive chip DIC generates multiple data voltages, which can be applied to the pixel PX via data lines DL1 to DLn. The light emission drive circuit EDV generates multiple light emission signals, which can be applied to the pixel PX via light emission lines EL1 to ELm. The pixel PX may be supplied with data voltages in response to the scan signals. In response to the light emission signals, the pixel PX can emit light with a brightness corresponding to the data voltage to display an image.

[0040] Figures 4a to 4c are enlarged plan views of the display area 100-DA according to one embodiment of the present invention.

[0041] Referring to Figure 4a, the display area 100-DA includes multiple light-emitting areas LA1, LA2, and LA3, and may include a non-light-emitting area NLA adjacent to the multiple light-emitting areas LA1, LA2, and LA3. The non-light-emitting area NLA sets the boundary between the light-emitting areas LA1, LA2, and LA3.

[0042] The light-emitting regions LA1, LA2, and LA3 can be arranged in a 1:1 correspondence with the pixels PX in Figure 3. Each pixel PX contains a light-emitting element, and the light-emitting regions LA1, LA2, and LA3 can be regions from which light formed by the light-emitting element is emitted. The arrangement relationship between the light-emitting regions LA1, LA2, and LA3 and the non-light-emitting region NLA will be described later with reference to Figure 5.

[0043] The light-emitting regions LA1, LA2, and LA3 may include a first light-emitting region LA1 (or first color light-emitting region) that forms a first color of light, a second light-emitting region LA2 (or second color light-emitting region) that forms a second color of light, and a third light-emitting region LA3 (or third color light-emitting region) that forms a third color of light. In this embodiment, the first color of light may be red light, the second color of light may be green light, and the third color of light may be blue light.

[0044] The areas of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 may differ from each other, but are not necessarily limited to this. In this embodiment, the area of ​​the first light-emitting region LA1 may be the smallest among the areas of the first light-emitting region LA1, the second light-emitting region LA2, and the area of ​​the third light-emitting region LA3 may be the largest among the areas of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3.

[0045] The first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 may define a single unit light-emitting region UA. The unit light-emitting region UA ​​is a repeating arrangement unit of light-emitting regions placed in the display area 100-DA. In this embodiment, the unit light-emitting region UA ​​may include the first unit light-emitting region UA1 and the second unit light-emitting region UA2.

[0046] Referring to the first unit light-emitting region UA1 and the second unit light-emitting region UA2, the first light-emitting region LA1 and the second light-emitting region LA2 are positioned on one side (the left side in Figure 4a) of the third light-emitting region LA3 in the first direction DR1. The second light-emitting region LA2 of the first unit light-emitting region UA1 and the second unit light-emitting region UA2 are 2 Direction DR 2 It is positioned on one side (the lower side in Figure 4a) of the first light-emitting region LA1.

[0047] In the first unit light-emitting region UA1 and the second unit light-emitting region UA2, the positions of the third light-emitting region LA3 relative to the first light-emitting region LA1 and the second light-emitting region LA2 differ from each other within the second direction DR2. Referring to the first unit light-emitting region UA1, the position of the third light-emitting region LA3 relative to the first light-emitting region LA1 and the second light-emitting region LA2 is located relatively lower within the second direction DR2. Referring to the second unit light-emitting region UA2, the position of the third light-emitting region LA3 relative to the first light-emitting region LA1 and the second light-emitting region LA2 is located relatively higher within the second direction DR2. The degree to which the third light-emitting region LA3 is shifted relative to the first light-emitting region LA1 and the second light-emitting region LA2 may differ between the first unit light-emitting region UA1 and the second unit light-emitting region UA2 within the second direction DR2. In this embodiment, the third light-emitting region LA3 of the second unit light-emitting region UA2 may be shifted even further relative to each other. However, this is not limited to the above; the first unit light-emitting region UA1 and the second unit light-emitting region UA2 may have the same degree of shift of the third light-emitting region LA3 relative to the first light-emitting region LA1 and the second light-emitting region LA2 within the second direction DR2.

[0048] The first unit light-emitting region UA1 and the second unit light-emitting region UA2 can be arranged alternately along the first direction DR1 within the pixel row PXR. The first unit light-emitting region UA1 and the second unit light-emitting region UA2 can be arranged alternately along the second direction DR2 within the pixel column PXC. With this arrangement of the first unit light-emitting region UA1 and the second unit light-emitting region UA2, the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA2 are arranged according to a predetermined rule. Two adjacent third light-emitting regions LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA2 are separated by a first interval DT1 and are arranged relatively close together. The third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA2, separated by a first interval DT1, define a pair of light-emitting regions UP. The pair of light-emitting regions UP are separated by a second interval DT2 within their respective pixel column PXC. The second interval DT2 is greater than the first interval DT1.

[0049] The reason why pairs of UP (upper emission regions) are formed is due to the mask used during deposition. The light-emitting element located in the third light-emitting region LA3 of the first unit light-emitting region UA1 and the light-emitting element located in the third light-emitting region LA3 of the second unit light-emitting region UA2 each contain a light-emitting layer with a single shape. In other words, the light-emitting layer located in the third light-emitting region LA3 of the first unit light-emitting region UA1 and the light-emitting layer located in the third light-emitting region LA3 of the second unit light-emitting region UA2 have a single shape and are deposited using a single mask. Openings corresponding to pairs of UP of light-emitting regions are defined in the mask. The area between the openings of the mask corresponds to the mask's blocking region. Defining openings corresponding to pairs of UP of light-emitting regions reduces the number of openings, and the width of the mask's blocking region located between the openings in the second direction DR2 can be secured. If the width of the mask's blocking region is not secured in the second direction DR2 for a thin film mask, it is not possible to suppress defects such as mask stretching during the deposition process.

[0050] This can be seen by comparing the third spacing DT3 between the third light-emitting regions LA3 shown in Figure 4b. Referring to Figure 4b, one type of unit light-emitting region UA ​​is arranged in the display area 100-DA. The third spacing DT3 between the third light-emitting regions LA3 of adjacent unit light-emitting regions UA of the pixel row PXC is smaller than the second spacing DT2 in Figure 4b. The mask used to form the third light-emitting regions LA3 in Figure 4b has a larger number of openings, and the width of the mask's blocking area is relatively reduced. This is because the mask that forms the light-emitting layer in the third light-emitting regions LA3 shown in Figure 4b has openings defined that correspond to each of the third light-emitting regions LA3.

[0051] Referring to Figure 4c, one type of unit light-emitting region UA0 is arranged in the display area 100-DA. The unit light-emitting region UA0 includes a second light-emitting region LA2 separated in a first direction DR1, and a first light-emitting region LA1 and a third light-emitting region LA3 separated in a second direction DR2. The four light-emitting regions LA1, LA2, and LA3 of the unit light-emitting region UA0 are arranged in a diamond shape. The unit light-emitting regions UA0 of a pixel row PXR are aligned along the first direction DR1. The unit light-emitting regions UA0 of adjacent pixel rows PXR may be arranged to intersect along the first direction DR1. The unit light-emitting regions UA0 of adjacent pixel rows PXR may be arranged to intersect along the second direction DR2.

[0052] Figure 5 is a cross-sectional view of the display device DD corresponding to I-I' in Figure 4a. In Figure 5, some components of the display device DD, such as the anti-reflective layer 300 to window WM in Figure 2, are not shown.

[0053] The pixel driving circuit PC that drives the light-emitting element may include multiple pixel driving elements. The pixel driving circuit PC may include multiple transistors S-TFT, O-TFT and capacitor Cst. Figure 5 shows silicon transistor S-TFT and oxide transistor O-TFT as examples of transistors. The pixel driving circuit PC in Figure 5 is merely one embodiment, and the configuration of the pixel driving circuit PC is not necessarily limited to this. The pixel circuit PC may include only one type of transistor from silicon transistor S-TFT and oxide transistor O-TFT.

[0054] Referring to Figure 5, the base layer 110 is shown as a single layer. The base layer 110 may contain a synthetic resin such as polyimide. The base layer 110 can be formed by coating a synthetic resin layer onto a work substrate (or carrier substrate). After the display module DM is completed by performing subsequent processes, the work substrate can be removed. In one embodiment of the present invention, the base layer 110 may have a multilayer structure comprising a first synthetic resin layer, at least one inorganic layer, and a second synthetic resin layer.

[0055] Referring further to Figure 5, a barrier layer 10br may be placed on the base layer 110. The barrier layer 10br prevents foreign matter from entering from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. These may be provided in multiples, and the silicon oxide layers and silicon nitride layers may be stacked alternately.

[0056] The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. A first shielding electrode BMLa may be placed between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLb may be positioned to correspond to a silicon transistor S-TFT. The first shielding electrode BMLa may contain a metal, such as molybdenum.

[0057] The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive a first power supply voltage. The first shielding electrode BMLa may block the electrical potential due to polarization from affecting the silicon transistor S-TFT. The first shielding electrode BMLa may block external light from reaching the silicon transistor S-TFT. In one embodiment of the present invention, the first shielding electrode BMLa may be a floating electrode in an isolated form from other electrodes or wiring.

[0058] A buffer layer 10bf may be placed above the barrier layer 10br. The buffer layer 10bf can prevent metal atoms and impurities from diffusing from the base layer 110 to the upper first semiconductor pattern SC1. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0059] A first semiconductor pattern SC1 can be placed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low-temperature polyol silicon.

[0060] The electrical properties of the first semiconductor pattern SC1 may differ depending on whether or not it is doped. The first semiconductor pattern SC1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. The source region SE1, channel region AC1 (or active region), and drain region DE1 of a silicon transistor S-TFT may include the first semiconductor pattern SC1. The source region SE and drain region DE may extend in opposite directions from the channel region AC1 in cross-section.

[0061] A first insulating layer 10 may be placed on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the inorganic layer of the driving element layer 120 described later may have a single-layer or multilayer structure and may contain at least one of the materials described above, but is not limited to that.

[0062] The gate GT1 of a silicon transistor S-TFT is placed on the first insulating layer 10. The gate GT1 may be part of a metal pattern. The gate GT1 is superimposed on the channel region AC1. In the process of doping the first semiconductor pattern SC1, the gate GT1 may be a mask. The first electrode CE10 of a storage capacitor Cst is placed on the first insulating layer 10. Unlike the illustration in Figure 5, the first electrode CE10 may have a shape that is integrated with the gate GT1.

[0063] A second insulating layer 20 can be placed on top of the first insulating layer 10 to cover the gate GT1. In one embodiment of the present invention, an upper electrode superimposed on the gate GT1 may be further placed on top of the second insulating layer 20. A second electrode CE20 superimposed on the first electrode CE10 may be placed on top of the second insulating layer 20. The upper electrode may have a shape that is integral with the second electrode CE20 in a plan view.

[0064] A second shielding electrode BMLb is placed on the second insulating layer 20. The second shielding electrode BMLb may be positioned to correspond to the oxide transistor O-TFT. In one embodiment of the present invention, the second shielding electrode BMLb may be omitted. In one embodiment of the present invention, the first shielding electrode BMLa may be extended to the bottom of the oxide transistor O-TFT and replace the second shielding electrode BMLb.

[0065] A third insulating layer 30 may be placed on top of the second insulating layer 20. The second semiconductor pattern SC2 may be placed above the third insulating layer 30. The second semiconductor pattern SC2 may include the channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) x ), or may include transparent conductive oxides (TCOs) such as indium oxide (In2O3).

[0066] The metal oxide semiconductor may include multiple regions SE2, AC2, and DE2, which are divided by whether the transparent conductive oxide is reducible or not. The region where the transparent conductive oxide is reduced (hereinafter referred to as the reduced region) has greater conductivity than the region where it is not reduced (hereinafter referred to as the unreduced region). The reduced region substantially functions as the source / drain or signal line of the transistor. The unreduced region substantially corresponds to the semiconductor region (or channel) of the transistor. A fourth insulating layer 40 may be placed on top of the third insulating layer 30. As shown in Figure 5, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In one embodiment of the present invention, the fourth insulating layer 40 may be an insulating pattern superimposed on the gate GT2 of the oxide transistor O-TFT, exposing the source region SE2 and drain region DE2 of the oxide transistor O-TFT.

[0067] The gate GT2 of the oxide transistor O-TFT is placed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT is superimposed on the channel region AC2. A fifth insulating layer 50 is placed on the r insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first insulating layer 10 to the fifth insulating layer 50 may be an inorganic layer.

[0068] The first linkage pattern CNP1 and the second linkage pattern CNP2 may be placed on the fifth insulating layer 50. Since the first linkage pattern CNP1 and the second linkage pattern CNP2 are formed by the same process, they may have the same material and the same layered structure. The first linkage pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 that penetrates the first to third insulating layers 10, 20, 30, 40, and 50. The second linkage pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 that penetrates the fourth and fifth insulating layers 40 and 50. The diameter of the connecting tube between the first linkage pattern CNP1 and the second linkage pattern CNP2 to the silicon transistor S-TFT and the oxide transistor O-TFT is not necessarily limited to this.

[0069] A sixth insulating layer 60 may be placed on top of the fifth insulating layer 50. A third connecting electrode CNP3 may be placed on top of the sixth insulating layer 60. The third connecting electrode CNP3 may be connected to a first connecting pattern CNP1 via a third pixel contact hole PCH3 that penetrates the sixth insulating layer 60. A data line DL may be placed on top of the sixth insulating layer 60. A seventh insulating layer 70 may be placed on top of the sixth insulating layer 60 and cover the third connecting pattern CNP3 and the data line DL. Since the third connecting pattern CNP3 and the data line DL are formed by the same process, they may have the same material and the same laminated structure. The sixth insulating layer 60 and the seventh insulating layer 70 may each be organic layers.

[0070] A light-emitting element (LD) may include an anode AE ​​(or first electrode), a light-emitting layer EL, and a cathode CE (or second electrode layer). The anode AE ​​of the light-emitting element (LD) may be located on a seventh insulating layer 70. The anode AE ​​may be a (semi)transparent electrode or a reflective electrode. The anode AE ​​may include a sequentially stacked ITO / Ag / ITO laminated structure. The positions of the anode AE ​​and cathode CE may be altered relative to each other.

[0071] The pixel definition film PDL may be placed on the seventh insulating layer 70. The pixel definition film PDL may be an organic layer. The pixel definition film PDL has light-absorbing properties, but for example, the pixel definition film PDL may have a block hue. The pixel definition film PDL may contain a black component (black coloring agent). The black component may contain a black dye or a black pigment. The black component may contain carbon black, a metal such as chromium, or an oxide thereof. The pixel definition film PDL may correspond to a shielding pattern having light-shielding properties.

[0072] The pixel definition film PDL may cover a portion of the anode AE. For example, an aperture PDL-OP may be defined in the pixel definition film PDL that exposes a portion of the anode AE. An emission region LA1 may be defined corresponding to the aperture PDL-OP. Figure 5 shows one emission region LA1 corresponding to the first emission region LA1 in Figure 4a. The cross-sections corresponding to the second emission region LA2 and the third emission region LA3 in Figure 4a may be substantially the same as those in Figure 5. However, an emission layer EL of a different material than that of the first emission region LA1 may be placed in the second emission region LA2 and the third emission region LA3. Also, referring to the pair of emission regions UP in Figure 4, the pixel definition film PDL is placed between the third emission region LA3 of the first unit emission region UA1 and the third emission region LA3 of the second unit emission region UA2. The light-emitting layer EL, which is located in the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA2, may be located on top of the pixel definition film PDL, which is located in the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA2.

[0073] In one embodiment of the present invention, a hole control layer may be disposed between the anode AE ​​and the light-emitting layer EL. The hole control layer includes a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer EL and the cathode CE. The electron control layer includes an electron transport layer and may further include an electron injection layer.

[0074] The sealing layer 140 can cover the light-emitting diode (LD). The sealing layer 140 may include sequentially stacked sealing inorganic layers 141, sealing organic layers 142, and sealing inorganic layers 143, but the layers constituting the sealing layer 140 are not necessarily limited to these. The sealing inorganic layers 141 and 143 may include silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, or aluminum oxide layers. Each of the sealing inorganic layers 141 and 143 may have a gypsum structure. The sealing organic layer 142 may include, but is not limited to, an acrylic organic layer.

[0075] The input sensor 200 may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensor 200 may include a first insulating layer 210 (or a first sensor insulating layer), a first conductive layer 220 (or a first sensor conductive layer), a second insulating layer 230 (or a second sensor insulating layer), a second conductive layer 240 (or a second sensor conductive layer), and a third insulating layer 250 (or a third sensor insulating layer). Figure 5 shows a simplified representation of the conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240.

[0076] The first insulating layer 210 may be placed on the display panel 100. The first insulating layer 210 may be an inorganic layer containing at least one of silicon nitride, silicon oxynitride, and silicon oxide. The first conductive layer 220 and the second conductive layer 240 may each have a single-layer structure or a multilayer structure stacked along a third direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive lines that define a mesh-like electrode. The conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 may or may not be connected via contact holes that penetrate the second insulating layer 230, depending on their position.

[0077] The single-layer structure of the first conductive layer 220 and the second conductive layer 240 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may be indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). x ), or may include transparent conductive oxides such as indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0078] Each of the multilayer conductive layers, the first conductive layer 220 and the second conductive layer 240, may include a metal layer. The metal layer may have, for example, a titanium / aluminum / titanium three-layer structure. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer. The second insulating layer 230 may be placed between the first conductive layer 220 and the second conductive layer 240. The third insulating layer 250 may cover the second conductive layer 240. In one embodiment of the present invention, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include inorganic or organic layers.

[0079] Figure 6a is a plan view of an input sensor 200 according to one embodiment of the present invention. Figure 6b is a cross-sectional view of the input sensor 200 corresponding to line II-II' in Figure 7.

[0080] As shown in Figure 6a, the input sensor 200 includes a sensing area 200-DA and a non-sensing area 200-NDA adjacent to the sensing area 200-DA. The sensing area 200-DA and the non-sensing area 200-NDA correspond to the display area 100-DA and the non-display area 100-NDA shown in Figure 5, respectively. The input sensor 200 includes first electrodes E1-1 to E1-4 (or first sensing electrodes), second electrodes E2-1 to E2-7 (or second sensing electrodes), first signal line SL1 (or first sensor signal line), and second signal line SL2 (or second sensor signal line).

[0081] First electrodes E1-1 to E1-4 and second electrodes E2-1 to E2-7 are arranged in the sensing region 200-DA, insulated from each other. A first signal line SL1 connected to the first electrodes E1-1 to E1-4 and a second signal line SL2 electrically connected to the second electrodes E2-1 to E2-7 are arranged in the non-sensing region 200-NDA. One of the first signal line SL1 and the second signal line SL2 transmits a drive signal from an external circuit to the corresponding electrode to sense an external input, while the other outputs a sensing signal. Based on the sensing signal, the change in capacitance between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 is measured. In this embodiment, a mutual cap type input sensor is shown as an example, but it is not limited to this. A self-cap type input sensor may also be applied. A self-cap type input sensor may include one type of sensing electrode.

[0082] Each of the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 may have a mesh-like structure with multiple defined aperture regions. These multiple aperture regions may superimpose on corresponding light-emitting regions among the multiple light-emitting regions LA1, LA2, and LA3 in Figure 4a. The second electrodes E2-1 to E2-7 are insulated from the first electrodes E1-1 to E1-4. Either the first electrodes E1-1 to E1-4 or the second electrodes E2-1 to E2-7 may have a single, integrated shape. In this embodiment, the second electrodes E2-1 to E2-7 having a single, integrated shape are shown as an example.

[0083] The second electrodes E2-1 to E2-7 may include a sensing portion SP2 and an intermediate portion CP2. The sensing portion SP2 has a larger area than the intermediate portion CP2 and may have a rhombic shape. Each intermediate portion CP2 is positioned between two adjacent sensing portions SP2. The length of the intermediate portion CP2 may be relatively short, and the intermediate portion CP2 may be omitted. In this case, the sensing portion SP2 may be directly extended from the adjacent sensing portion SP2.

[0084] Each of the first electrodes E1-1 to E1-4 may include a sensing portion SP1 and a bridge pattern CP1 (or a connecting pattern). Two adjacent sensing patterns SP1 may be connected to two bridge patterns CP1, but the number of bridge patterns is not limited.

[0085] Referring to Figures 6a and 6b, the bridge pattern CP1 includes a first conductive layer 220, and the plurality of first electrodes E1-1 to E1-4 and the sensing pattern SP1 may include a third conductive layer 240. The bridge pattern CP1 can be connected to the sensing pattern SP1 via contact holes TH-I formed in the second insulating layer 230. In one embodiment of the present invention, the bridge pattern CP1 may include a second conductive layer 240, and the plurality of first electrodes E1-1 to E1-4 and the sensing pattern SP1 may include a first conductive layer 220.

[0086] In this embodiment, the first signal line SL1 and the second signal line SL2 in Figure 6a may each include the first conductive layer 220 in Figure 6b. Therefore, the first signal line SL1 and the second signal line SL2 in Figure 6a may each be placed on the same layer as the bridge pattern conductive layer CP1 in Figure 6b. However, the embodiment is not limited to this, and the first signal line SL1 and the second signal line SL2 may each include the second conductive layer 240. The first signal line SL1 and the second signal line SL2 may each include either a line containing the first conductive layer 220 or a line containing the second conductive layer 240.

[0087] Figure 7a is an enlarged plan view of the second conductive layer 240 corresponding to the first region A1 in Figure 6a. Figure 7b is an enlarged plan view of the first conductive layer 220 corresponding to the first region A1 in Figure 6a. Figure 7c is an enlarged plan view of a portion of the first region A1 in Figure 6a. Figure 7d is a cross-sectional view corresponding to III-III' in Figure 7c. Figure 7e is a perspective view showing the reflection of external light occurring in a portion of the region shown in Figure 7c.

[0088] In Figures 7a to 7d, the second conductive layer 240 refers to the second conductive layer 240 in Figure 5, and the first conductive layer 220 refers to the first conductive layer 220 in Figure 5. Figure 7a shows an enlarged view of the sensing pattern SP1 including the second conductive layer 240. The sensing pattern SP1 is shown as representative of the first electrodes E1-1 to E1-4. In Figures 7a to 7b, the display area 100-DA shown in Figure 4a is shown together. Although not shown separately, the sensing portion SP2 may have the same structure as the sensing pattern SP1.

[0089] Referring to Figure 7a, the sensing pattern SP1 defines multiple aperture regions EOP1, EOP2, and EOP3. These multiple aperture regions EOP1, EOP2, and EOP3 may include a first aperture region EOP1 corresponding to (or superimposed on) the first light-emitting region LA1, a second aperture region EOP2 corresponding to the second light-emitting region LA2, and a third aperture region EOP3 corresponding to the pair UP of the light-emitting regions.

[0090] In this embodiment, a first light-emitting region LA1 is arranged inside a first aperture region EOP1, a second light-emitting region LA2 is arranged inside a second aperture region EOP2, and a pair of light-emitting regions UP is arranged inside a third aperture region EOP3. Inside the third aperture region EOP3, the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA1, as shown in Figure 4a, are commonly arranged. In one embodiment of the present invention, the third aperture region EOP3 may be formed separately for the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA1. In this case, a first line component L1, described later, may be arranged in the region between the third light-emitting region LA3 of the first unit light-emitting region UA1 and the third light-emitting region LA3 of the second unit light-emitting region UA1.

[0091] The sensing pattern SP1 may include multiple line components L1 and L2 that define multiple opening regions EOP1, EOP2, and EOP3. The multiple line components L1 and L2 may include a first line component L1 and a second line component L2 that extend in directions intersecting each other. In this embodiment, the first line component L1 may be extended in a first direction DR1, and the second line component L2 may be extended in a second direction DR2.

[0092] Each first line component L1 extends from one second line component L2 to another second line component L2 adjacent to the first second line component L2. The first line component L1 is located between two adjacent opening regions EOP1, EOP2, and EOP3 in the second direction DR2, and the second line component L2 may include multiple groups of line components separated by the width in the second direction DR2.

[0093] A disconnection region DCA may be defined for multiple line components L1 and L2. The disconnection region DCA is the region from which line components L1 and L2 have been removed. The disconnection region DCA reduces the visibility of the boundary region between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 shown in Figure 6a. When the disconnection region DCA is formed on the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 shown in Figure 6a according to a predetermined rule, both the boundary region between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7, and the disconnection region DCA of the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can be seen within the sensing region 200-DA shown in Figure 6a.

[0094] A step in which no disconnection region DCA is formed between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7, and only the boundary region is clearly visible, can be defined as visibility level 1. At level 1, the position and shape of the disconnection region DCA between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 can be easily recognized. A step in which a disconnection region DCA is formed between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7, and the visibility of the boundary region between the disconnection region DCA between the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 is reduced, can be defined as visibility level 2. According to Level 2, the existence of the disconnection region DCA between the first electrode E1-1~E1-4 and the second electrode E2-1~E2-7 can be recognized, but the position and shape of the disconnection region DCA between the first electrode E1-1~E1-4 and the second electrode E2-1~E2-7 cannot be accurately recognized. This is because the disconnection region DCA reduced the visibility of the boundary region.

[0095] In this embodiment, the disconnected region DCA may include the first to eighth disconnected regions C1 to C8. The first to eighth disconnected regions C1 to C8 form a unit (hereinafter referred to as a disconnected unit) and are repeatedly formed on the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7. In Figure 7a, the first to eighth disconnected regions C1 to C8 of the disconnected unit are shown bundled together.

[0096] The positions of the 1st to 8th disconnection regions C1 to C8 will be explained focusing on the regions where the (m-1)th pixel row PXRm-1, the mth pixel row PXRm, the (m+1)th pixel row PXRm+1, the (n-1)th pixel column PXCn-1, the nth pixel column PXCn, and the (n+1)th pixel column PXCn+1 are located. Here, m and n can each be natural numbers greater than or equal to 2. The first unit light emission region UA1 is located at each of the positions of the (m-1)th pixel row PXRm-1 and the (n-1)th pixel column PXCn-1, the (m+1)th pixel row PXRm+1 and the (n-1)th pixel column PXCn-1, the (m-1)th pixel row PXRm-1 and the (n+1)th pixel column PXCn+1, and the (m+1)th pixel row PXRm+1 and the (n+1)th pixel column PXCn+1. The second unit light-emitting region UA2 is positioned at the locations of the m-th pixel row PXRm and the (n-1)th pixel column PXCn-1, the (m-1)th pixel row PXRm-1 and the nth pixel column PXCn, the (m+1)th pixel row PXRm+1 and the nth pixel column PXCn, and the m-th pixel row PXRm and the (n+1)th pixel column PXCn+1, respectively.

[0097] The first to eighth disconnection regions C1 to C8 can be divided into four pairs (pairs of disconnection regions). Each pair of disconnection regions contains the two most adjacent disconnection regions from the first to eighth disconnection regions C1 to C8. The first disconnection region C1 and the second disconnection region C2 form a pair, the third disconnection region C3 and the fourth disconnection region C4 form a pair, the fifth disconnection region C5 and the sixth disconnection region C6 form a pair, and the seventh disconnection region C7 and the eighth disconnection region C8 form a pair. One disconnection region in a pair of disconnection regions is defined in the first line component L1, and the other disconnection region is defined in the second line component L2.

[0098] The first disconnected region C1 is located in the nth pixel row PXCn and is formed in the first line component L1, which is located between the first light-emitting region LA1 of the (m-1)th pixel row PXRm-1 and the second light-emitting region LA2 of the (m-1)th pixel row PXRm-1. The second disconnected region C2 is located in the (m-1)th pixel row PXRm-1 and is formed in the second line component L2, which is located between the second light-emitting region LA2 of the nth pixel row PXCn and the third light-emitting region LA3 of the nth pixel row PXCn. The third disconnected region C3 is located in the nth pixel row PXCn and is formed in the first line component L1, which is located between the first light-emitting region LA1 of the mth pixel row PXRm and the second light-emitting region LA2 of the mth pixel row PXRm. The fourth disconnected region C4 is located in the mth pixel row PXRm and is formed in the second line component L2, which is located between the third light-emitting region LA3 of the (n-1)th pixel row PXCn-1 and the second light-emitting region LA2 of the nth pixel row PXCn.

[0099] The fifth disconnection region C5 is located in the (n+1)th pixel row PXCn+1 and is formed in the second line component L2, which is located between the second light emission region LA2 of the (m-1)th pixel row PXRm-1 and the third light emission region LA3 of the (m-1)th pixel row PXRm-1. The sixth disconnection region C6 is located in the (n+1)th pixel row PXCn+1 and is located between the second light emission region LA2 of the (m-1)th pixel row PXRm-1 and the first light emission region LA1 of the m-th pixel row PXRm. 1 Line ingredient L 1 The seventh disconnected region C7 is located in the m-th pixel row PXRm and is formed in the second line component L2, which is located between the third light-emitting region LA3 of the n-th pixel column PXCn and the second light-emitting region LA2 of the (n+1)th pixel column PXCn+1. The eighth disconnected region C1 is located in the (n+1)th pixel column PXCn+1 and is formed in the first line component L1, which is located between the second light-emitting region LA2 of the m-th pixel row PXRm and the first light-emitting region LA1 of the (m+1)th pixel row PXRm+1.

[0100] The first disconnection region C1, the third disconnection region C3, the sixth disconnection region C6, and the eighth disconnection region C8 are formed in the first line component L1 and connect the first opening region EOP1 and the second opening region EOP2. The second disconnection region C2, the fourth disconnection region C4, the fifth disconnection region C5, and the seventh disconnection region C7 are formed in the second line component L2 and can connect the second opening region EOP2 and the third opening region EOP3.

[0101] Referring to Figure 7b, the first conductive layer 220 may include multiple dummy patterns MP. Each of the multiple dummy patterns MP is superimposed on one of the multiple disconnected regions DCA shown in Figure 7a. The multiple dummy patterns MP may include the first to eighth dummy patterns MP1 to MP8, corresponding to the first to eighth disconnected regions C1 to C8.

[0102] Figures 7c and 7d show enlarged views of the disconnection regions DCA formed in the first line component L1 and the second line component L2. A dummy pattern MP is positioned to correspond to the disconnection regions DCA.

[0103] The second insulating layer 230 is positioned between the disconnection region DCA of the first line component L1 and the second line component L2 and the dummy pattern MP. In this embodiment, the dummy pattern MP may, but is not limited to, be positioned below the second insulating layer 230.

[0104] The first line component L1 and the second line component L2 may have a multilayer laminated structure. The first line component L1 and the second line component L2 may each contain the same laminated structure. The first line component L1 and the second line component L2 may each include a first conductive layer CL10 (or first line conductive layer), a second conductive layer CL20 (or second line conductive layer) disposed above the first conductive layer CL10 and in contact with the first conductive layer CL10, and a third conductive layer CL30 (or third line conductive layer) disposed below the first conductive layer CL10 and in contact with the first conductive layer CL10. In this embodiment, the third conductive layer CL30 may be omitted.

[0105] The first conductive layer CL10 has a first reflectance, a first conductivity, and a first thickness. The second conductive layer CL10 has a second reflectance lower than the first reflectance, a second conductivity lower than the first conductivity, and a second thickness smaller than the first thickness. The first conductive layer CL10, with its low resistance, acts as a substantial signal transport path. By increasing its thickness, multiple signal lines SL1 and SL2 can be arranged within a narrow area in a plan view. The second conductive layer CL20, with its low reflectance, covers the first conductive layer CL10, reducing the reflectance of external light.

[0106] Medium-sized electronic devices, such as tablets or laptops shown in Figures 1 and 6a, have a larger input sensor area compared to small electronic devices such as mobile phones. The increased length of the first electrodes E1-1 to E1-4 and the second electrodes E2-1 to E2-7 increases their resistance, and to reduce this resistance, the thickness of low-resistance layers, such as the first conductive layer CL10, is increased.

[0107] The third conductive layer CL30 may have a greater bonding force to the first insulating layer 210 than the first conductive layer CL10. The first conductive layer CL10 may contain aluminum, copper, silver, etc., which have low resistance. The second conductive layer CL20 may contain titanium. The second conductive layer CL20 may have a thickness of 100 Å to 500 Å. By applying the titanium second conductive layer CL20 as the uppermost conductive layer, the reflectivity of external light is reduced, and the reflected light from the titanium layer produces a relatively small color shift. The third conductive layer CL30 may contain ZIO (Zinc Indium Oxide), InO (Indium Oxide), ZnO (Zinc Oxide), or the metals that make up the first conductive layer CL10, or alloys of those metals.

[0108] The dummy pattern MP may have substantially the same optical properties as the first line component L1 and the second line component L2. For example, the dummy pattern MP may have substantially the same reflectance as the first line component L1 and the second line component L2. The dummy pattern MP may contain substantially the same material as the first line component L1 and the second line component L2.

[0109] The dummy pattern MP may have the same laminated structure as the first line component L1 and the second line component L2. The dummy pattern MP may contain the same laminated structures as the first line component L1. Since the dummy pattern MP is arranged to compensate for the disconnection region DCA in optical properties, it is preferable that it has the same laminated structure as the first line component L1 and the second line component L2.

[0110] The first conductive layer CL1 (or first line conductive layer) of the dummy pattern MP may contain the same material and have the same thickness as the first conductive layer CL10 of the first line component L1. The second conductive layer CL2 (or second line conductive layer) of the dummy pattern MP may contain the same material and have the same thickness as the second conductive layer CL20 of the first line component L1. The third conductive layer CL3 (or first line conductive layer) of the dummy pattern MP may contain the same material and have the same thickness as the third conductive layer CL30 of the first line component L1.

[0111] Figure 7e shows the reflection path of external light. Essentially, external light is reflected from the side of the second conductive layer CL20, as described in Figure 7d. If the dummy pattern MP is not placed, external light is not reflected at the disconnected region DCA, making the disconnected region DCA visible. If the dummy pattern MP is placed corresponding to the disconnected region DCA, external light can be reflected by the dummy pattern MP corresponding to the disconnected region DCA. Therefore, the visibility of the disconnected region DCA may be reduced.

[0112] Figure 8a is an enlarged plan view of the second conductive layer 240 corresponding to the second region B1 in Figure 6a. Figure 8b is an enlarged plan view of the first conductive layer 220 corresponding to the second region B1 in Figure 6a.

[0113] Figure 8a shows the boundary region between the sensing pattern SP1 of the third first electrode E1-3 and the sensing portion SP2 of the fifth second electrode E2-5. By removing the first and second line components L1 and L2 according to a predetermined rule, the boundary region between the first electrode E1-3 and the second electrode E2-5, that is, the boundary region BA between the first and second line components L1 and L2 of the sensing pattern SP1 and the first and second line components L1 and L2 of the sensing portion SP2, is defined.

[0114] A boundary line BL is shown to clearly represent the boundary region between the first electrode E1-3 and the second electrode E2-5. The boundary region between the first electrode E1-3 and the second electrode E2-5 can be defined as the set of boundary regions BA between the first and second line components L1 and L2 of the sensing pattern SP1 and the first and second line components L1 and L2 of the sensing portion SP2. Twelve boundary regions BA are shown exemplarily in Figure 8a.

[0115] A portion of the boundary region BA may be located between the first aperture region EOP1 and the second aperture region EOP2, another portion between the first aperture region EOP1 and the third aperture region EOP3, and yet another portion between the third aperture region EOP3 and the second aperture region EOP2. A portion of the boundary region BA may be defined as a first line component L1 or a second line component L2 located in the first unit emission region UA1 and the second unit emission region UA2, respectively. Another portion of the boundary region BA may be defined as a first line component L1 or a second line component L2 located between the first unit emission region UA1 and the second unit emission region UA2, which are arranged in different pixel rows and / or different pixel columns.

[0116] Referring to Figure 8b, the first conductive layer 230 may include a plurality of dummy patterns MP-B positioned in the boundary region between the first electrode E1-3 and the second electrode E2-5. Although the reference numerals for the plurality of dummy patterns MP in Figure 7b are different, the plurality of dummy patterns MP-B in Figure 8b may be substantially the same as the plurality of dummy patterns MP in Figure 7b. The plurality of dummy patterns MP in Figure 7b and the plurality of dummy patterns MP-B in Figure 8b may be formed by the same process, have the same layered structure, and contain the same material.

[0117] Multiple dummy patterns MP-B can be superimposed on multiple boundary regions BA. The roles of the multiple dummy patterns MP-B placed in multiple boundary regions BA can be substantially the same as the roles of the multiple dummy patterns MP, as explained with reference to Figures 7a to 7e.

[0118] The placement of multiple dummy patterns MP-B may reduce the visibility of the boundary region between the first electrode E1-3 and the second electrode E2-5. The step in which the visibility of the boundary region between the first electrode E1-3 and the second electrode E2-5 is reduced by the placement of multiple dummy patterns MP-B may be defined as visibility level 3. The step in which the boundary region between the first electrode E1-3 and the second electrode E2-5 is substantially undetectable due to the optical substitution of multiple boundary regions BA by the multiple dummy patterns MP-B may be defined as visibility level 4. There may be a difference in the degree of optical compensation by the multiple dummy patterns MP-B between visibility level 3 and visibility level 4.

[0119] The placement of multiple dummy patterns MP-B reduces the reflectivity difference between the second line component L2 and the disconnected region DCA, as explained with reference to Figure 7e. This "reduction in reflectivity difference" itself can be defined as visibility level 3. Visibility level 4 can be defined when the reflectivity difference is within a predetermined range, for example, -5% to +5% or -10% to +10%. In other words, visibility level 4 is a greater reduction in reflectivity difference than visibility level 3.

[0120] In Figure 8a, the disconnection region DCA of the sensing pattern SP1 and sensing portion SP2 is not shown in order to highlight the boundary region BA. However, in this embodiment, the disconnection region DCA according to the rule described with reference to Figure 7a can be defined for the first electrodes E1-1 to E1-4 (see Figure 6a) and the second electrodes E2-1 to E2-7 (see Figure 6a). Also, although the dummy pattern MP is not shown in Figure 8b, a dummy pattern MP may be further arranged to correspond to the disconnection region DCA according to the rule described with reference to Figure 7a. The disconnection region DCA and the dummy pattern MP can ensure a visibility level of 3 or 4 in the inner region of the first electrode E1-3 and the second electrode E2-5.

[0121] In one embodiment of the present invention, a disconnection region DCA does not need to be defined between the first electrode E1-3 and the second electrode E2-5. The reason for forming a disconnection region DCA is, as described above, to lower the visibility level from level 1 to level 2. However, if a visibility level 4 can be secured in which the boundary region between the first electrode E1-3 and the second electrode E2-5 is not substantially perceived, then it is not a problem if a disconnection region DCA is not formed between the first electrode E1-3 and the second electrode E2-5. If a disconnection region DCA is not formed between the first electrode E1-3 and the second electrode E2-5, the resistance of the first electrode E1-3 and the second electrode E2-5 can be lowered, and the sensing intensity can be improved.

[0122] Figures 9a to 9c are enlarged plan views of a portion of the first region A1 of the input sensor 200 according to one embodiment of the present invention. Figure 9d is a cross-sectional view of the input sensor 200 according to one embodiment of the present invention. Figures 9a to 9c correspond to Figure 7c, and Figure 9d corresponds to Figure 7d. For a detailed explanation of the same configuration as described with reference to Figures 7a to 7e, please refer to the explanations of Figures 7a to 7e.

[0123] As shown in Figures 9a to 9c, the dummy pattern MP can have a variety of areas and shapes. The area and shape of the dummy pattern MP can be set to correspond to the reflection characteristics of the dummy pattern MP.

[0124] As shown in Figure 9a, the dummy pattern MP may have a smaller area than the disconnected region DCA and the same line width. As shown in Figure 9b, the dummy pattern MP may have a larger area than the disconnected region DCA and have a larger length and line width than the disconnected region DCA. As shown in Figure 9c, the dummy pattern MP may have a different shape from the disconnected region DCA. The dummy pattern MP may be circular. The shape of the dummy pattern MP is not particularly limited and may be deformed into an elliptical shape or the like.

[0125] As shown in Figure 9d, the dummy pattern MP may be placed on the second insulating layer 230, and the second line component L2 may be placed below the second insulating layer 230. In this case, the bridge pattern CP1, as described with reference to Figures 6a and 6b, may also include the second conductive layer 240.

[0126] Although preferred embodiments of the present invention have been described so far with reference, a person skilled in the art or a person with ordinary knowledge in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and technical domain of the invention as described in the claims below. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be determined by the claims. [Industrial applicability]

[0127] This invention relates to a display device including an input sensor. Because various input devices are used in various display devices, this invention has a high potential for application to products.

Claims

1. A display panel including multiple light-emitting regions and non-light-emitting regions adjacent to the multiple light-emitting regions, Includes an input sensor positioned on the display panel, The aforementioned input sensor is Insulating layer and, First sensing electrode and A second sensing electrode, which includes a sensing pattern that is separated from the first sensing electrode in a plan view, A dummy pattern, the insulating layer of which is disposed between the dummy pattern and the first sensing electrode, and between the sensing pattern of the second sensing electrode and the dummy pattern, Each of the sensing patterns of the first sensing electrode and the second sensing electrode includes a line component superimposed on the non-luminescent region. The line component defines a plurality of aperture regions that overlap with the corresponding light-emitting region among the plurality of light-emitting regions, The region separated from the line component of the first sensing electrode and the line component of the sensing pattern of the second sensing electrode is defined as a boundary region. A display device in which at least a portion of the dummy pattern is superimposed on the boundary region.

2. Disconnection regions are defined in the line component of the first sensing electrode and the line component of the sensing pattern of the second sensing electrode. Each of the dummy patterns is superimposed on the corresponding region among the disconnected region and the boundary region. The display device according to claim 1.

3. The aforementioned light-emitting region is Multiple first light-emitting regions that emit a first color of light, Multiple second light-emitting regions that emit second-color light, It includes a plurality of third light-emitting regions that emit third-color light, Two of the first light-emitting regions, two of the second light-emitting regions, and two of the third light-emitting regions define a unit light-emitting region. The aforementioned unit light-emitting region is On one side of one of the two third light-emitting regions, one first light-emitting region of the two first light-emitting regions and one second light-emitting region of the two second light-emitting regions are arranged, and the one third light-emitting region has a first unit light-emitting region positioned below the one first light-emitting region and the one second light-emitting region in the direction in which the one first light-emitting region and the one second light-emitting region are arranged side by side. On one side of the other third light-emitting region of the two third light-emitting regions, the other first light-emitting region of the two first light-emitting regions and the other second light-emitting region of the two second light-emitting regions are arranged, and the other third light-emitting region includes a second unit light-emitting region positioned above the other first light-emitting region and the other second light-emitting region in the direction in which the other first light-emitting region and the other second light-emitting region are arranged side by side. The display device according to claim 2.

4. The aforementioned plurality of opening regions are A first aperture region corresponding to one of the first light-emitting regions, A second aperture region corresponding to one of the second light-emitting regions, The first unit light-emitting region and the second unit light-emitting region are arranged adjacent to each other in the direction in which they are aligned, and the third aperture region of the first unit light-emitting region corresponds to the other third light-emitting region of the second unit light-emitting region, The display device according to claim 3.

5. One of the aforementioned boundary regions is located between one first light-emitting region and one second light-emitting region. The other is positioned between one first light-emitting region and one third light-emitting region. Another one is positioned between a second light-emitting region and a third light-emitting region. The display device according to claim 4.

6. One of the aforementioned disconnected regions is located between one first light-emitting region and one second light-emitting region, another is located between one first light-emitting region and one third light-emitting region, and yet another is located between one second light-emitting region and one third light-emitting region. The display device according to claim 4.

7. Multiple unit light-emitting regions are provided, and these multiple unit light-emitting regions define a pixel matrix, the pixel matrix including the (m-1)th pixel row, the mth pixel row, the (m+1)th pixel row, the (n-1)th pixel column, the nth pixel column, and the (n+1)th pixel column, where m and n are each natural numbers of 2 or greater. The first unit light-emitting region is arranged in each of the following locations: the (m-1)th pixel row and the (n-1)th pixel column, the (m+1)th pixel row and the (n-1)th pixel column, the (m-1)th pixel row and the (n+1)th pixel column, and the (m+1)th pixel row and the (n+1)th pixel column. The second unit light-emitting region is arranged in each of the following locations: the m-th pixel row and the (n-1)th pixel column, the (m-1)th pixel row and the nth pixel column, the (m+1)th pixel row and the nth pixel column, and the m-th pixel row and the (n+1)th pixel column. The display device according to claim 4.

8. The aforementioned line component is, A first line component extending in the first direction, A second line component extending in a second direction intersecting the first direction, The aforementioned disconnection region defines a plurality of disconnection units, and each of the plurality of disconnection units includes a first disconnection region to an eighth disconnection region. The first disconnected region is defined in the first line component located between the first light-emitting region of the second unit light-emitting region and the second light-emitting region of the second unit light-emitting region, which are located in the (m-1)th pixel row and the nth pixel column. The second disconnected region is defined in the second line component located between the second light-emitting region of the second unit light-emitting region, which is located in the (m-1)th pixel row and the nth pixel column, and the third light-emitting region of the second unit light-emitting region. The third disconnected region is defined in the first line component located between the second light-emitting region of the first unit light-emitting region and the third light-emitting region of the first unit light-emitting region, which are arranged in the m-th pixel row and the n-th pixel column. The fourth disconnected region is defined as the second line component located between the third light-emitting region of the second unit light-emitting region, which is arranged in the m-th pixel row and the (n-1)-th pixel column, and the second light-emitting region of the first unit light-emitting region, which is arranged in the m-th pixel row and the n-th pixel column. The display device according to claim 7.

9. The fifth disconnected region is defined as the second line component located between the second light-emitting region of the first unit light-emitting region, which is located in the (m-1)th pixel row and the (n+1)th pixel column, and the third light-emitting region of the first unit light-emitting region. The sixth disconnected region is defined as the first line component located between the second light-emitting region of the first unit light-emitting region, which is located in the (m-1)th pixel row and the (n+1)th pixel column, and the first light-emitting region of the second unit light-emitting region, which is located in the (m)th pixel row and the (n+1)th pixel column. The seventh disconnected region is defined as the second line component located between the third light-emitting region of the first unit light-emitting region, which is located in the m-th pixel row and the n-th pixel column, and the second light-emitting region of the second unit light-emitting region, which is located in the m-th pixel row and the (n+1)-th pixel column. The eighth disconnected region is defined as the first line component located between one second light-emitting region of the second unit light-emitting region arranged in the m-th pixel row and the (n+1)th pixel column, and one first light-emitting region of the first unit light-emitting region arranged in the (m+1)th pixel row and the (n+1)th pixel column. The display device according to claim 8.

10. The aforementioned line component is, A first line component extending in the first direction, A second line component extending in a second direction intersecting the first direction, The aforementioned disconnection region defines a plurality of disconnection units, and each of the plurality of disconnection units includes a first disconnection region to an eighth disconnection region. The first to eighth disconnection regions are divided into four pairs, each including two disconnection regions that are most adjacent to each other. Of the two disconnected regions in each of the four pairs, one is defined in the first line component, and the other is defined in the second line component. The display device according to claim 7.

11. The line component and the dummy pattern include the same laminated structure. The display device according to claim 1.

12. The line component and the dummy pattern include a first conductive layer and a second conductive layer disposed on the first conductive layer. The first conductive layer has higher electrical conductivity and greater reflectivity than the second conductive layer. The display device according to claim 11.

13. Multiple sensing patterns are arranged along the first direction, Each of the second sensing electrodes includes a bridge pattern that connects two adjacent sensing patterns from among a plurality of sensing patterns. The bridge pattern is placed on the same layer as the dummy pattern. The display device according to claim 1.

14. The bridge pattern and the dummy pattern include the same laminated structure. The display device according to claim 13.

15. The first sensing electrode extends in a second direction intersecting the first direction and has an integral shape. The display device according to claim 14.

16. A display panel including multiple light-emitting regions and non-light-emitting regions adjacent to the multiple light-emitting regions, Includes an input sensor positioned on the display panel, The aforementioned input sensor is Insulating layer and, Sensing electrode and, A dummy pattern, wherein the insulating layer is disposed between the sensing electrode and the dummy pattern, The sensing electrode includes a line component superimposed on the non-emitting region, and the line component defines a plurality of aperture regions superimposed on a corresponding emitting region among the plurality of emitting regions. A disconnected region is defined in the aforementioned line component. The dummy pattern is a display device superimposed on the disconnected area.

17. The aforementioned line component is, A first line component extending in the first direction, A second line component extending in a second direction intersecting the first direction, The aforementioned disconnected region is divided into a plurality of pairs of disconnected regions, each including two disconnected regions that are most adjacent to each other. Of the two disconnected regions in each pair of the plurality of disconnected regions, one is defined in the first line component and the other is defined in the second line component. The display device according to claim 16.

18. The line component and the dummy pattern include a first conductive layer and a second conductive layer disposed on the first conductive layer. The first conductive layer has higher electrical conductivity and greater reflectivity than the second conductive layer. The display device according to claim 16.

19. The line component and the dummy pattern have substantially the same reflectivity. The display device according to claim 16.

20. The line component and the dummy pattern contain substantially the same substance. The display device according to claim 16.

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