Quantum error correction decoder and method for synthesizing a Boolean circuit for a quantum error correction decoder chip using the same

Abstract

A method for synthesizing Boolean circuits for an error-correcting decoder. The method may include the steps of: providing one or more input binary variables derived from one or more syndrome measurements; providing a mapping representing a quantum error-correcting decoder; providing corresponding output binary variables for the one or more input binary variables, representing one or more recovery operations on a qubit, wherein the output binary variables are generated using the mapping; and using the one or more input binary variables and the corresponding output binary variables to synthesize at least one Boolean circuit. A quantum error-correcting decoder chip comprising one or more Boolean circuits.

Description

[Technical Field]

[0001] cross reference This application claims the interests of U.S. Provisional Patent Application No. 63 / 493,648, filed on March 31, 2023, which is incorporated herein by reference in its entirety. Technical Background

[0002] In digital computing and the transmission of digital signals or data in communication systems, the transmitted digital data can be subject to errors during transmission from the sender to the receiver. Error correction codes or error correcting codes (ECCs) can be used to encode the digital data to be transmitted over the communication channel from the sender to the receiver in order to control data errors. The sender can encode the message or data to be transmitted with redundant information, thereby enabling the detection and correction of errors that may occur during transmission without retransmission.

[0003] In quantum computing, a quantum system for performing quantum computations can be implemented by an ensemble of subsystems exhibiting different quantum states, either correlated or entangled due to quantum coherence. In various implementations, each subsystem within the ensemble may exhibit two or more different quantum states to function as a fundamental quantum device. Information can be represented, stored, processed, and transmitted through the superposition and correlation of quantum states of different fundamental quantum devices. Such a fundamental quantum device with two or more different quantum states may be called a "qubit," and a two-state device is often called a quantum bit ("qubit"). To realize the practical application of quantum computers, it is necessary to create logical qubits and quantum gates with sufficiently low error rates. One way to achieve these low error rates is through quantum error correction, a method for creating logical qubits and quantum gates that are more reliable than physical component parts. However, quantum error correction can induce overhead costs in terms of computation time and physical resources. [Overview of the project]

[0004] This disclosure provides a method and system for synthesizing Boolean circuits for an error correction decoder. This disclosure also provides a quantum error correction decoder chip comprising the synthesized Boolean circuits.

[0005] In quantum computing, in addition to errors that can occur during data transmission in digital computing, quantum information is susceptible to errors caused by quantum decoherence and other quantum noise or quantum interfaces. Quantum error correction may be useful in achieving fault-tolerant quantum computing.

[0006] The advantage of the methods and systems disclosed herein is that the resulting decoder architecture requires relatively simple information processing. This attribute is advantageous when implemented in hardware using CMOS, SFQ ASIC, or FPGA technology, resulting in benefits such as minimizing the hardware footprint, reducing power consumption, and increasing execution frequency.

[0007] Another advantage of the methods and systems disclosed herein is that this architectural design aligns seamlessly with Single-Instruction-Multiple-Data (SIMD) parallelization, thereby facilitating good integration with GPU / CPU chips.

[0008] Another advantage of the methods and systems provided herein is that a quantum error correction decoder chip with synthesized Boolean circuits can be co-located with a quantum processor at the same cryogenic temperature, thereby avoiding otherwise high communication costs.

[0009] In one embodiment, the Disclosure provides a method for synthesizing a Boolean circuit for a quantum error correction decoder. The method may include the steps of: (a) providing one or more input binary variables at least partially derived from one or more syndrome measurements; (b) providing a mapping representing the quantum error correction decoder; (c) generating corresponding output binary variables for the one or more input binary variables at least partially based on the mapping, wherein the output binary variables represent one or more recovery operations of a plurality of qubits; and (d) synthesizing at least one Boolean circuit at least partially based on the one or more input binary variables and the corresponding output binary variables.

[0010] In some embodiments, (d) includes constructing a look-up table of the mapping based at least partially on one or more input binary variables and the corresponding output binary variables. In some embodiments, (d) includes performing an optimization on the Boolean circuit to reduce the number of logic gates in the Boolean circuit. In some embodiments, the optimization is performed iteratively until a stopping criterion is met. In some embodiments, the optimization includes two-level logic optimization. In some embodiments, the optimization includes multi-level logic optimization. In some embodiments, the two-level logic optimization includes reducing the number of AND and OR gates. In some embodiments, the two-level logic optimization includes reducing the number of AND, OR, and NOT gates.

[0011] In some embodiments, (d) further includes converting the Boolean circuit into a netlist. In some embodiments, the netlist includes a directed graph, which is configured to define the flow and sequence of the logic gates and one or more non-Boolean circuit elements of the Boolean circuit. In some embodiments, the one or more recovery operations are on a logic qubit or a physical qubit. In some embodiments, the method further includes the step of performing the one or more recovery operations on the logic qubit or the physical qubit.

[0012] In some embodiments, the mapping in (b) is at least partially based on a recurrent neural network (RNN). In some embodiments, (b) comprises (i) constructing a deterministic finite automaton (DFA) of the RNN, and (ii) constructing one or more lookup tables, at least partially based on a classifier, wherein the classifier is configured to associate labels with each state of the DFA, and the classifier includes a transition function configured to associate each state of the DFA with an input state of the DFA. In some embodiments, the RNN includes a clustering layer to reduce the size of the DFA. In some embodiments, constructing the DFA in (i) comprises performing a merging procedure in the space of hidden states of the RNN, wherein the merging procedure is configured to reduce the complexity of the DFA. In some embodiments, the method further includes reducing the complexity of the DFA based at least in part on the Hopcroft algorithm. In some embodiments, the method further includes constructing a binary state encoding of the DFA. In some embodiments, (d) further includes converting the Boolean circuits into a netlist and optimizing the netlist by relabeling the DFA at least in part.

[0013] In some embodiments, the one or more syndrome measurements are from a quantum error correction code comprising one or more members selected from the group consisting of a Surface code, a color code, a toric code, and a Bacon-Shor code. In some embodiments, the method further comprises the step of implementing the quantum error correction code before (a). In some embodiments, the quantum error correction code comprises one or more members selected from the group consisting of a Surface code, a color code, a toric code, and a Bacon-Shor code. In some embodiments, the quantum error correction decoder comprises one or more members selected from the group consisting of a Minimum-Weight Perfect Matching decoder, a Union Find decoder, a Belief Matching decoder, a Tensor-Network decoder, and a renormalization group decoder.

[0014] In another embodiment, the Disclosure provides a quantum error correction decoder chip, which may include one or more Boolean circuits, each configured to receive one or more input binary variables derived from one or more syndrome measurements from syndrome qubits, each configured to process the one or more input binary variables to generate an output binary variable, the output binary variable being operable to generate one or more recovery operations.

[0015] In some embodiments, the one or more Boolean circuits include at least one element from the group consisting of a field programmable gate array (FPGA), ASIC, CMOS, and SFQ. In some embodiments, the chip is communicatively coupled to a quantum processor, the quantum processor is operably coupled to a cryogenic device and cooled to extremely low temperatures by the cryogenic device, the cryogenic device having different cryogenic stages at different extremely low temperatures, and the one or more Boolean circuits are operably coupled to the cryogenic device and cooled to different cryogenic stages by the cryogenic device. In some embodiments, the one or more Boolean circuits are operably coupled to a circuit cooled by the cryogenic device. In some embodiments, the one or more Boolean circuits are operably coupled to a circuit at room temperature. In some embodiments, the chip is communicatively coupled to a controller.

[0016] In some embodiments, the recovery operation includes updating the Pauli frame or updating data qubits to reduce errors in quantum computing. In some embodiments, the quantum processor includes one or more members selected from the group consisting of superconducting quantum processors, semiconductor quantum processors, trapped ion quantum processors, and neutral atom quantum processors. In some embodiments, one or more Boolean circuits are at least partially based on a lookup table, and the lookup table is at least partially based on one or more input binary variables and corresponding output binary variables.

[0017] In some embodiments, the one or more Boolean circuits are generated by performing optimizations on the one or more Boolean circuits, at least partially, in order to reduce the number of logic gates in the one or more Boolean circuits.

[0018] In some embodiments, the optimization is performed iteratively until a stopping criterion is met. In some embodiments, the optimization includes a two-level logic optimization. In some embodiments, the optimization includes a multi-level logic optimization. In some embodiments, the two-level logic optimization includes reducing the number of AND and OR gates. In some embodiments, the two-level logic optimization includes reducing the number of AND, OR, and NOT gates.

[0019] In some embodiments, the one or more Boolean circuits include a corresponding netlist. In some embodiments, the netlist includes a directed graph, which is configured to define the flow and sequence of the logic gates of the Boolean circuits and one or more non-Boolean circuit elements. In some embodiments, the one or more Boolean circuits are configured to provide the one or more recovery operations performed on the logic qubits or physical qubits of the quantum processor.

[0020] In some embodiments, the one or more Boolean circuits described above are generated at least partially based on a recurrent neural network (RNN). In some embodiments, the RNN includes a clustering layer to reduce the size of the deterministic finite automaton (DFA).

[0021] In some embodiments, the one or more syndrome measurements are from a quantum error correction code that includes one or more members selected from the group consisting of a Surface code, a color code, a toric code, and a Bacon-Shor code. In some embodiments, the chip further includes a quantum error correction code associated with the chip. In some embodiments, the quantum error correction code includes one or more members selected from the group consisting of a Surface code, a color code, a toric code, and a Bacon-Shor code. In some embodiments, the chip is configured to implement a quantum error correction decoder. In some embodiments, the one or more recovery operations are configured to update one or more data qubits to reduce errors in quantum computing. In some embodiments, the quantum error correction decoder includes one or more members selected from the group consisting of a minimum weight perfect matching decoder, a union find decoder, a belief matching decoder, a tensor network decoder, and a folding group decoder.

[0022] In another aspect, the present disclosure provides a processor communicatively coupled to a quantum computer, the processor being configured to: (a) provide one or more input binary variables derived at least in part from one or more syndrome measurements from the quantum computer; (b) provide a mapping representing a quantum error correction decoder; (c) generate corresponding output binary variables for the one or more input binary variables based at least in part on the mapping, the output binary variables representing one or more recovery operations of a plurality of qubits; and (d) synthesize at least one Boolean circuit based at least in part on the one or more input binary variables and the corresponding output binary variables.

[0023] In some embodiments, in (d), the processor is configured to construct a lookup table of the mappings based at least partially on the one or more input binary variables and the corresponding output binary variables. In some embodiments, in (d), the processor is configured to perform an optimization on the Boolean circuit to reduce the number of logic gates in the Boolean circuit. In some embodiments, the optimization is performed iteratively and until a stopping criterion is met. In some embodiments, the optimization includes a two-level logic optimization. In some embodiments, the optimization includes a multi-level logic optimization. In some embodiments, the two-level logic optimization includes reducing the number of AND and OR gates. In some embodiments, the two-level logic optimization includes reducing the number of AND, OR, and NOT gates. In some embodiments, in (d), the processor is configured to convert the Boolean circuit into a netlist. In some embodiments, the netlist includes a directed graph that defines the flow and sequence of the logic gates of the Boolean circuit and one or more non-Boolean circuit elements. In some embodiments, the one or more recovery operations are for logic qubits or physical qubits. In some embodiments, the processor is configured to perform one or more recovery operations on the logical qubit or the physical qubit.

[0024] In some embodiments, in (b), the mapping is at least partially based on a Recurrent Neural Network (RNN). In some embodiments, in (b), the processor is configured to (i) construct a Deterministic Finite Automaton (DFA) of the RNN, and (ii) construct one or more lookup tables at least partially based on a classifier, the classifier being configured to associate labels with each state of the DFA, the classifier including a transition function configured to associate each state of the DFA with an input of the states of the DFA. In some embodiments, the RNN includes a clustering layer for reducing the DFA size. In some embodiments, in (i), the processor performs a merge procedure in the hidden state space of the RNN, the merge procedure being configured to reduce the complexity of the DFA. In some embodiments, the processor is configured to reduce the DFA complexity at least partially based on the Hopcroft algorithm. In some embodiments, the processor is configured to construct a binary state encoding of the DFA. In some embodiments, in (d), the processor converts the Boolean circuit into a netlist. In some embodiments, the processor is configured to optimize the netlist by at least partially relabeling the DFA.

[0025] In some embodiments, the one or more syndrome measurements are from a quantum error correction code that includes one or more members selected from the group consisting of Surface codes, color codes, toric codes, and Bacon-Shor codes. In some embodiments, prior to (a), the processor is configured to implement the quantum error correction code. In some embodiments, the quantum error correction code includes one or more members selected from the group consisting of Surface codes, color codes, toric codes, and Bacon-Shor codes. In some embodiments, the quantum error correction decoder includes one or more members selected from the group consisting of minimum-weight perfect matching decoders, union-find decoders, belief-matching decoders, tensor network decoders, and renormalization group decoders.

[0026] While only exemplary embodiments of this disclosure have been shown and described, further aspects and advantages of this disclosure will be readily apparent to those skilled in the art from the following detailed description. As will be understood, other different embodiments of this disclosure are possible, and some of their details can be modified in various obvious ways without departing from this disclosure. Accordingly, the drawings and description should be considered illustrative and not restrictive.

[0027] Reference All publications, patents, and patent applications referenced herein are incorporated by reference to the same extent that each individual publication, patent, or patent application is specifically and individually indicated as being incorporated by reference. To the extent that any publications and patents or patent applications incorporated by reference are in conflict with the disclosures contained herein, this Specified is intended to supersede and / or take precedence over any such incongruous material. [Brief explanation of the drawing]

[0028] Novel features of the present invention are described in detail in the appended claims. A better understanding of the features and advantages of the present invention will be obtained by referring to the following detailed description, which describes exemplary embodiments in which the principles of the present invention are utilized, and to the appended drawings (hereinafter also referred to as "Figure" and "FIG"). [Figure 1] This is a diagram of a quantum error correction decoder chip that includes one or more Boolean circuits. [Figure 2] This is a flowchart illustrating an exemplary method for synthesizing a Boolean circuit for an error correction decoder. Detailed description of the invention

[0029] While various embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided only as examples. Numerous variations, modifications, and substitutions can be conceived by those skilled in the art without departing from the present invention. It should be understood that various alternatives to the embodiments of the present invention described herein may be adopted.

[0030] Whenever the terms “at least,” “greater than,” or “greater than or equal to” precede a first number in a set of two or more numbers, the terms “at least,” “greater than,” or “greater than or equal to” apply to each number in the set. For example, 1, 2, or 3 or more corresponds to 1 or more, 2 or more, or 3 or more.

[0031] Whenever the terms “no more than,” “less than,” or “less than or equal to” precede a first number in a set of two or more numbers, the terms “no more than,” “less than,” or “less than or equal to” apply to each number in the set. For example, 3, 2, or 1 or less corresponds to 3 or less, 2 or less, or 1 or less.

[0032] Certain embodiments of the invention described herein involve numerical ranges. Where a range exists, the range includes its endpoints. Furthermore, any subrange and the values ​​within that range exist as if explicitly described. The terms “about” or “approximately” may mean within an acceptable margin of error for a particular value, which depends in part on how that value is measured or determined, for example, on the limitations of the measuring system. For example, “about” may mean within one standard deviation or more than one standard deviation, according to convention in the art. Alternatively, “about” may mean a range of up to 20%, up to 10%, up to 5%, or up to 1% of a given value. Where a particular value is described in this application and claims, unless otherwise specified, the term “about” may be assumed to mean within an acceptable margin of error for that particular value.

[0033] Classical computer In some cases, the systems, media, networks, and methods described herein include classical computers (e.g., digital computers) or the use thereof. In some cases, a classical computer may include a digital computer. In some cases, a classical computer includes one or more hardware central processing units (CPUs) that perform the functions of a classical computer. In some cases, a classical computer further includes an operating system (OS) configured to execute executable instructions. In some cases, a classical computer is connected to a computer network. In some cases, a classical computer is connected to the Internet to access the World Wide Web. In some cases, a classical computer is connected to a cloud computing infrastructure. In some cases, a classical computer is connected to an intranet. In some cases, a classical computer is connected to a data storage device.

[0034] In some cases, a classic computer is connected to a computer network. In some cases, a classic computer is connected to the Internet to access the World Wide Web. In some cases, a classic computer is connected to one or more computer servers that can enable distributed computing, such as cloud computing infrastructure. In some cases, a classic computer is connected to an intranet and / or extranet, or to an intranet and / or extranet that communicates with the Internet. In some cases, a classic computer is connected to a data storage device. In some cases, the network is a telecommunications and / or data network. In some cases, the network is a peer-to-peer network, which can allow devices connected to a computer system to act as clients or servers.

[0035] According to the description herein, suitable classic computers may include, in non-limiting embodiments, server computers, desktop computers, laptop computers, notebook computers, subnotebook computers, netbook computers, netpad computers, set-top computers, media streaming devices, handheld computers, internet appliances, mobile smartphones, tablet computers, personal digital assistants, video game consoles, and vehicles. Smartphones may be suitable for use with the methods and systems described herein. In some cases having computer network connectivity, selections of televisions, video players, and digital music players may be suitable for use in the systems and methods described herein. Suitable tablet computers may include those having booklet, slate, and convertible configurations.

[0036] In some cases, a classic computer includes an operating system configured to execute executable instructions. An operating system can be, for example, software comprising programs and data that manages the device's hardware and provides services for running applications. Suitable server operating systems include, but are not limited to, FreeBSD, OpenBSD, NetBSD®, Linux®, Apple® Mac OS X Server®, Oracle® Solaris®, Windows Server®, and Novell® NetWare®. Suitable personal computer operating systems may include, but are not limited to, Microsoft® Windows®, Apple® Mac OS X®, Apple® macOS®, UNIX®, and UNIX®-like operating systems such as GNU / Linux®. In some cases, operating systems are provided through cloud computing. Appropriate mobile smartphone operating systems may include, but are not limited to, Nokia® Symbian® OS, Apple® iOS®, Research In Motion® BlackBerry OS®, Google® Android®, Microsoft® Windows Phone® OS, Microsoft® Windows Mobile® OS, Linux®, and Palm® WebOS®.Suitable media streaming device operating systems may include, but are not limited to, Apple TV®, Roku®, Boxee®, Google TV®, Google Chromecast®, Amazon Fire®, and Samsung® HomeSync®. Suitable video game console operating systems may include, but are not limited to, Sony® PS3®, Sony® PS4®, Microsoft® Xbox 360®, Microsoft®, Microsoft® Xbox One®, Nintendo® Wii®, Nintendo® Wii U®, and Ouya®.

[0037] In some cases, a classic computer includes storage devices and / or memory devices. In some cases, storage devices and / or memory devices are one or more physical devices used to temporarily or permanently store data or programs. In some cases, storage devices and / or memory devices may have one or more additional data storage units located outside the classic computer, for example, on a remote server communicating with the classic computer via an intranet or the internet. In some cases, the devices are volatile memory and require power to maintain the stored information. In some cases, the devices are non-volatile memory and retain the stored information when the classic computer is not powered. In some cases, non-volatile memory includes flash memory. In some cases, non-volatile memory includes dynamic random-access memory (DRAM). In some cases, non-volatile memory includes ferroelectric random-access memory (FRAM). In some cases, non-volatile memory includes phase-change random-access memory (PRAM). In some cases, the device is a storage device, including, in non-limiting examples, CD-ROMs, DVDs, flash memory devices, magnetic disk drives, magnetic tape drives, optical disk drives, and cloud computing-based storage. In some cases, the storage device and / or memory device is a combination of devices, such as those disclosed herein.

[0038] In some cases, a classical computer includes a display for transmitting visual information to the user. In some cases, the display is a cathode ray tube (CRT). In some cases, the display is a liquid crystal display (LCD). In some cases, the display is a thin-film transistor liquid crystal display (TFT-LCD). In some cases, the display is an organic light-emitting diode (OLED) display. In some cases, the OLED display is a passive-matrix OLED (PMOLED) display or an active-matrix OLED (AMOLED) display. In some cases, the display is a plasma display. In some cases, the display is a video projector. In some cases, the display is a combination of devices such as those disclosed herein.

[0039] In some cases, a classic computer includes an input device for receiving information from a user. In some cases, the input device is a keyboard. In some cases, the input device is a pointing device, including, in non-limiting examples, a mouse, trackball, trackpad, joystick, game controller, or stylus. In some cases, the input device is a touchscreen or multitouch screen. In some cases, the input device is a microphone for capturing voice input or other sound input. In some cases, the input device is a video camera or other sensor for capturing motion input or visual input. In some cases, the input device is Kinect®, Leap Motion®, etc. In some cases, the input device is a combination of devices such as those disclosed herein.

[0040] Quantum devices Any type of quantum computer may be suitable for the techniques disclosed herein. Quantum processors or quantum computers include one or more adiabatic quantum computers, quantum gate arrays, one-way quantum computers, topological quantum computers, quantum Turing machines, superconductor-based quantum computers, trapped ion quantum computers, trapped atom quantum computers, optical lattices, quantum dot computers, spin-based quantum computers, spatial-based quantum computers, Loss-DiVincenzo quantum computers, nuclear magnetic resonance (NMR)-based quantum computers, solution-state NMR quantum computers, solid-state NMR quantum computers, solid-state NMR Kane quantum computers, electrons-on-helium quantum computers, cavity-quantum-electrodynamics based quantum computers, molecular magnet quantum computersQuantum processors or quantum computers may include fullerene-based quantum computers, linear optical quantum computers, diamond-based quantum computers, nitrogen-vacancy (NV) diamond-based quantum computers, Bose-Einstein condensate-based quantum computers, transistor-based quantum computers, and rare-earth-metal-ion-doped inorganic crystal-based quantum computers. A quantum processor or quantum computer may include one or more of the following: quantum annealers, Ising solvers, optical parametric oscillators (OPOs), and gate model quantum computers.

[0041] A quantum processor or quantum computer may contain one or more qubits. One or more qubits include superconducting qubits, trapped ion qubits, trapped atom qubits, photon qubits, quantum dot qubits, electron spin-based qubits, nuclear spin-based qubits, molecular magnet qubits, fullerene-based qubits, diamond-based qubits, nitrogen-vacancy (NV) diamond-based qubits, Bose-Einstein condensate-based qubits, and transistor-based qubits. This may include qubits, or rare-earth-metal-ion-doped inorganic crystal-based qubits.

[0042] In accordance with the description herein, suitable quantum computers include, as non-limiting examples, superconducting quantum computers (qubits implemented as small superconducting circuits-Josephson junctions) (Clarke et al., “Superconducting quantum bits”, Nature 453, no.7198, pp.1031-1042, 2008), trapped ion quantum computers (qubits implemented as states of trapped ions) (Kielpinski et al., “Architecture for a large-scale ion-trap quantum computer”, Nature 417, no.6890, pp.709-711, 2002), and optical lattice quantum computers (qubits implemented as states of neutral atoms trapped in an optical lattice) (Deutsch et al., “Quantum computing with neutral atoms in an optical lattice”, Fortschritte der Physik: Progress of Physics 48, no.9-11, pp.925-943, 2000), spin-based quantum dot computers (qubits implemented as the spin states of trapped electrons) (Imamoglu et al., “Quantum information processing using quantum dot spins and cavity QED”, Physical Review Letters 83, no.20, p.4204, 1999), spatial-based quantum dot computers (qubits implemented as electron positions in double quantum dots) (Fedichkin et al.),“Novel coherent quantum bit using spatial quantization levels in semiconductor quantum dot”, arXiv:quant-ph / 0006097,2000), coupled quantum wires (qubits implemented as pairs of quantum wires coupled by quantum point contact) (Bertoni et al.,“Quantum logic gates based on coherent electron transport in quantum wires”, Physical Review Letters 84, no.25, p.5912,2000), nuclear magnetic resonance quantum computers (qubits implemented as nuclear spins and explored by radio waves) (Cory et al.,“Nuclear magnetic resonance spectroscopy: An experimentally accessible paradigm for quantum computing”, arXiv:quant-ph / 9709001,1997), solid-state NMR Kane quantum computer (qubits implemented as nuclear spin states of phosphorus donors in silicon) (Kane,“A silicon-based nuclear spin quantum ”,Nature 393,no.6681,pp.133-137, 1998), electrons-on-helium quantum computers (qubits implemented as electron spins) (Lyon, “Spin-based quantum computing using electrons on liquid helium”, arXiv:cond-mat / 0301581, 2006), cavity quantum electrodynamics-based quantum computers (qubits implemented as states of trapped atoms coupled to high-finesse cavities) (Burell, “An Introduction to Quantum Computing using Cavity QED concepts”, arXiv:1210.6512, 2012), molecular magnet-based quantum computers (qubits implemented as spin states) (Leuenberger et al., “Quantum Computing in Molecular Magnets”) ,arXiv:cond-mat / 0011415,2001), fullerene-based electron spin resonance (ESR) quantum computers (qubits implemented as electron spins of atoms or molecules encased in fullerenes) (Harneit, “Spin Quantum Computing with Endohedral Fullerenes”, arXiv:1708.09298,2017), linear optical quantum computers (qubits implemented as processing different modes of optical states through linear optical elements such as mirrors, beam splitters, and phase shifters) (Knill et al."Efficient linear optics quantum computation", rXiv:quant-ph / 0006088, 2000; diamond-based quantum computers (qubits implemented as electron or nuclear spins at nitrogen vacancy (NV) centers in diamond) (Nizovtsev et al., "A quantum computer based on NV centers in diamond: optically detected nutations of single electron and nuclear spins", Optics and Spectroscopy 99, no.2, pp.233-244, 2005); Bose-Einstein condensate-based quantum computers (qubits implemented as two-component Bose-Einstein condensates) (Byrnes et al., "Macroscopic quantum computation using Bose-Einstein condensates", arXiv:quantum-ph / 1103.5512, 2011); transistor-based quantum computers (nanophotonic cavity (Quantum bits implemented as semiconductors coupled to cavities) (Sun et al., “A single-photon switch and transistor enabled by a solid-state quantum memory”, arXiv:quant-ph / 1805.01964, 2018), rare-earth metal ion-doped inorganic crystal-based quantum computers (quantum bits implemented as hyperfine levels of the atomic ground state in rare-earth ion-doped inorganic crystals) (Ohlsson et al. “Quantum computer hardware based on rare-earth-ion-doped inorganic crystals”, Optics Communications 201, no.1-3, pp.This may include (71-77, 2002) and metal-like carbon nanosphere-based quantum computers (qubits implemented as electron spins in conducting carbon nanospheres) (Nafradi et al., “Room temperature manipulation of long lifetime spins in metallic-like carbon nanospheres”, arXiv:cond-mat / 1611.07690, 2016), each of which is incorporated herein by reference in its entirety.

[0043] Quantum error correction Quantum error correction involves methods for reducing the error rate in quantum computation. In some cases, quantum error correction may involve the process of using multiple physical qubits and gates to encode and use one or more resulting logical qubits with a lower error rate than that of the constituent physical qubits and gates. At the heart of quantum error correction is a quantum error correction code. A quantum error correction code may include several parameters: the number of data qubits (denoted by n), the number of logical qubits (denoted by k), and the minimum number of errors related to any two code states (called the code distance, denoted by d). Code states can form a distinct subspace of the complete Hilbert space of joint states of data qubits. Error correction may involve detecting and correcting errors, which moves the joint data qubit state out of the code space.

[0044] Quantum error correction code is an extension of the classic concept of error correction code, which allows one or more logical bits to be coded using many low-fidelity bits by correcting bit-flip errors.

[0045] In one example, the class of quantum error correction code is given by a stabilizer code. The form of the stabilizer is as follows: an abelian subgroup K of the n-qubit Pauli group is selected, which is called the stabilizer subgroup. For K, a set of generators A_1, A_2, ..., A_k is selected. The code space is the space of the eigenstates of the data qubits stabilized by A, i.e., the eigenvalue + 1. Thus, the code space encodes nk logical qubits. By simultaneously measuring each of the stabilizers A_1, A_2, ..., A_k, the data states are projected onto the code space. (For further details, see Gheorghiu, “Standard form of qudit stabilizer groups”, Physics Letters A 378, no. 5-6, pp. 505-5, 2014, and Gottesman, “An introduction to quantum error correction and fault-tolerant quantum computation”, In Quantum information science and its contributions to mathematics, Proceedings of Symposia in Applied Mathematics, 68, pp. 13-58, 2010, the respective publications which are incorporated herein by reference in their entirety.)

[0046] One example of a stabilizer code is the Calderbank-Shor-Steane (CSS) code. The CSS code is defined using a CSS construction that generates a single quantum error-correcting code from two nested linear error-correcting codes C’ < C that have the same number of data bits. Logical qubits are encoded within the quotient C / C’. The reason this construction generates a quantum error-correcting code is that (1) the ability to correct both Pauli X (bit-flip) errors and Pauli Z (phase-flip) errors enables full quantum error correction, and (2) the application of a Hadamard gate flips the code to its dual code and exchanges X errors with Z errors. In the case of the CSS code, each stabilizer generator is either of type X or of type Z (see, for example, Chapter 10 of “Quantum Computation and Quantum Information”, Cambridge University Press, New York, 2000, which is hereby incorporated by reference in its entirety).

[0047] In quantum error correction code, multiple physical data qubits may be kept in an entangled state. One or more logical qubits are represented as specific degrees of freedom in the Hilbert space of the data qubits, while perturbations along other degrees of freedom can be measured, decoded, and then corrected. In some cases, measurement, decoding, and correction can be performed substantially sequentially. The degrees of freedom are selected so that individual topologically isolated errors in the code can be detected and corrected. Decoding may include a diagnostic step of inferring which data qubits are likely to be erroneous based on the measured syndrome history. The process of measuring, decoding, and then applying correction to the syndrome qubits can be performed many times within a single quantum circuit, and therefore, speed and accuracy may be advantageous to minimize the accumulation of errors.

[0048] A key variable may be the distance of the quantum error correction code. The overhead related to the number of data qubits used and the time per quantum gate is a polynomial in code distance. However, theoretically, the error rate of logical components can be exponential in code distance, provided that the error rate of physical components is less than a fixed threshold value. Therefore, a lower logical error rate can be achieved by creating a code with a large code distance. However, the decoding process can become more difficult as the code distance increases, which can present a barrier to creating codes with large distances. To take advantage of larger code distances, a decoder may detect error strings up to half the length of the possible code distance. The algorithms used to do this can be complex. For example, the size and amount of training data used to create a successful neural network-based decoder can be exorbitant for large code distances.

[0049] In some examples, quantum error correction proceeds as follows: At regular time intervals, a syndrome extraction circuit containing data qubits and syndrome qubits is executed. Such a syndrome extraction circuit may include a sequence of physical qubit gates followed by measurements that generate readouts from the syndrome qubits and, in the absence of substantial errors, provide the measurement results to the corresponding stabilizers. This set of readouts may be called a syndrome. This process may be repeated several times to generate a syndrome history. This syndrome history may provide incomplete information about the errors that occurred and may be sent to a classical decoder, which may infer the most likely errors that could affect the data qubits. The decoder may return a candidate recovery operation, which is then applied to or stored in the data qubits. Depending on the code used, various classical algorithms have been developed to perform efficient and accurate decoding. (For further details, see Chamberland et al., “Triangular color codes on trivalent graphs with flag qubits”, New Journal of Physics 22, no.2, p.023019, 2020, Kubica et al., “Efficient color code decoders in d≧2 dimensions from toric code decoders”, arXiv:1905.07393, 2019, and Delfosse et al., “Almost-linear time decoding algorithm for topological codes”, arXiv:1709.06218, 2017, each of which is incorporated herein by reference in its entirety.)

[0050] Error correction in quantum computers can provide fault-tolerant quantum computing and may be useful for executing large-scale quantum algorithms to solve computational problems that may be difficult for classical computers.

[0051] Physical quantum devices, such as qubits within a quantum computer, can suffer sequential errors as a result of various causes, including natural decoherence or interaction with a control apparatus. One approach to overcome these errors is to use a quantum error correction scheme, in which a single logic qubit is coded using a combination of (1) several physical qubits to perform the quantum computation, (2) an additional syndrome qubit and error correction circuit to detect errors in the quantum state of the physical qubits performing the quantum computation, (3) a decoder that defines a recovery operation based on the observed syndrome, and (4) a controller to apply the recovery operation to the physical qubit and its subcombinations. Fault tolerance can be achieved when errors can be detected and corrected faster than they occur, thereby preventing errors from compounding over long computations.

[0052] However, engineering such quantum error correction systems presents challenges. Complexity increases exponentially with increasing numbers of possible errors to be corrected. It may be useful for decoding to be performed quickly in order to enable the action used to correct the error. By performing decoding rapidly in the decoder and placing the decoder as close to the qubit as possible, latency caused by the error correction operation can be reduced. The decoding process can be implemented by a classical coprocessor located adjacent to the quantum processor formed by the qubit, and the decoding process is executed within the same timeframe as the rate at which errors are generated. In the case of superconducting qubits that may have very short decoherence times and very fast gates, this fast decoding time may be difficult or challenging to achieve due to (1) the latency time required for transmitting readout information between the quantum processor and the classical coprocessor, and (2) the processing time required to make the decoding practical.

[0053] This specification recognizes the need for improved methods and systems that can overcome at least one of the shortcomings identified above.

[0054] The technology disclosed in this patent document can be implemented in a way that provides methods and systems to mitigate certain limitations related to the precision of physical qubits, communication lag between the quantum processor and the classical coprocessor, and the speed limit of error correction.

[0055] Referring to Figure 1, a diagram of a quantum error correction decoder chip is shown, which includes one or more Boolean circuits (100). The one or more Boolean circuits (100) can be of various types. The one or more Boolean circuits (100) may include at least one member of the group consisting of field programmable gate arrays (FPGA), ASICS, CMOS, and SFQ. The one or more Boolean circuits (100) receive one or more input binary variables derived from one or more syndrome measurements from syndrome qubits, and process the one or more input binary variables to generate output binary variables used to generate one or more recovery operations. The recovery operations can be of various types. In some cases, recovery operations include updating Pauli frames or updating data qubits to reduce errors in quantum computing. The binary variables may be derived from one or more syndrome measurements by a preprocessor (120). The one or more recovery operations may be generated by a postprocessor (130) using the output binary variables. The preprocessor (120) can be of various types. In some cases, the preprocessor (120) includes a timing module that synchronizes the reception of an input before it is delivered to one or more Boolean circuits (100). In some cases, the preprocessor (120) includes a module that takes the logical difference between the current measured data vector and a previous vector. The postprocessor (130) can be of various types. In some cases, the postprocessor (130) includes a dispatching module that determines whether a recovery operation is output in a given measurement round.

[0056] A quantum error correction decoder chip may be coupled to a quantum processor (not shown). The quantum processor can be of various types. The quantum processor may be any quantum processor disclosed elsewhere in this specification with respect to quantum devices. The quantum processor may be coupled to a cryogenic device and cooled to extremely low temperatures by the cryogenic device. The cryogenic device is not shown. In some cases, the cryogenic device has different cryogenic stages at different extremely low temperatures. One or more Boolean circuits may be coupled to a cryogenic device and cooled by the cryogenic device at different cryogenic stages. The cryogenic stages can efficiently dissipate various levels of heat and thus support various levels of complexity of the Boolean circuits implementing the decoder mapping. In some cases, one or more Boolean circuits may be held in the cryogenic device at extremely low temperatures, such as 100 mK, 600 mK, 3 K, or 4 K, which are higher than the quantum processor (1210). In some cases, one or more Boolean circuits can be held within a cryogenic apparatus at the same cryogenic stage and the same extremely low temperature (e.g., tens of mK) as the quantum processor.

[0057] Cryogenic devices can be of various types. In some cases, a cryogenic device includes a cryogenic platform capable of reaching the low temperatures required for qubit operation. In some cases, a cryogenic device includes a dilution refrigerator system having different cryogenic stages at different temperatures. In some cases, a cryogenic device includes a cryogenic cooling system. In other cases, a cryogenic device includes an adiabatic demagnetization refrigerator.

[0058] One or more Boolean circuits (100) may be coupled to a circuit cooled by a cryogenic device. One or more Boolean circuits (100) may be coupled to a circuit at room temperature.

[0059] In some cases, the quantum error correction decoder chip is coupled to a controller (110). The controller (110) can be of various types.

[0060] Referring here to Figure 2, a flowchart of an exemplary method for synthesizing a Boolean circuit for a quantum error-correcting decoder is shown. Error-correcting decoders can be of various types. In some cases, an error-correcting decoder includes at least one member of the group consisting of minimum-weight perfect matching decoders, union-find decoders, belief-matching decoders, tensor network decoders, and renormalization group decoders.

[0061] A processing operation (202) provides one or more input binary variables derived from one or more syndrome measurements. These one or more syndrome measurements may be provided using various types of quantum error correction codes. These one or more syndrome measurements may be provided from quantum error correction codes that include one or more members of the group consisting of Surface codes, color codes, toric codes, and Bacon-Shor codes.

[0062] Processing operation (204) provides a mapping representing a quantum error correction decoder. The mapping representing the quantum error correction decoder can be of various types. In some cases, the mapping of the quantum error correction decoder is based on a recurrent neural network (RNN). The quantum error correction decoder is a mapping.

[0063]

number

[0064] In some cases, the mapping represents a quantum error correction decoder.

[0065]

number

[0066] The extracted DFA is a tuple.

[0067]

number

[0068]

number

[0069]

number

[0070] In some cases, constructing a DFA may involve a merging procedure in the RNN's hidden state space. In some cases, the merging procedure can reduce the complexity of the DFA. A DFA can be extracted from an RNN following the procedure described in Merrill and Tsilivis, “Extracting Finite Automata from RNNs Using State Merging,” arXiv:2201.12451, which is incorporated herein by reference in its entirety. For illustrative purposes only and not limiting, each new RNN input bit string may be interpreted as a character allowed by the DFA, a prefix may be a complete or partial sequence of characters including a first character, and a word generally refers to a complete sequence of characters.

[0071] An uncompressed DFA, also called a prefix tree, can be constructed from a subset of words in a training set for an RNN. In one example, each word may be read sequentially character by character within a prefix, and a new DFA state may be introduced for each new prefix. Transitions between DFA states can be recorded by remembering the associated characters and responding to new characters. Each arrow may be associated with the character being created. Furthermore, each DFA state is associated with information about the hidden state h of a feeding RNN with the same prefix, along with a label g(h). In some cases, the information about the RNN's hidden state h is the vector h itself. Information associated with the hidden RNN state can be used to evaluate the distance between pairs of DFA states. In some cases, the distance can be evaluated using the cosine similarity between h1 and h2. A pair of states can be merged if the distance value is less than the value of the hyperparameter κ, or if the labels g(h1) and g(h2) are the same. To perform a state merge, states in the pair can be removed from the DFA. Instead, a new single state can be added to the DFA, inheriting at least some or all of the incident and outgoing arrows from the removed state. The new state can be associated with information derived from the information accompanying the merged state. In some cases, this information includes the label g(h1) and the vector h1. Following the merge process, a non-deterministic finite automaton (NFA) can be obtained. The NFA can then be transformed into a new DFA, for example, using powerset construction. The size of the resulting DFA can be minimized. In some cases, the construction of the DFA may involve using the Hopcroft algorithm to reduce the complexity of the above DFA.Minimization can be performed according to the procedure described in Hopcroft, “An n log n algorithm for minimizing states in a finite automaton,” Theory of Machines and Computations, pp. 189–196, Elsevier, 1971, which is incorporated herein by reference in its entirety.

[0072] The processing operation (206) provides corresponding output binary variables representing one or more recovery operations on qubits for one or more input binary variables. The output binary variables are generated using mappings representing quantum error correction decoders. The one or more recovery operations may be for logical qubits or for physical qubits.

[0073] Quantum error correction decoders are mapping

[0074]

number

[0075] In some cases, the input to a quantum error correction decoder is a sequential structure.

[0076]

number

[0077] Referring further to Figure 2, the processing operation (208) synthesizes at least one Boolean circuit using one or more input binary variables and corresponding output binary variables. In some cases, synthesizing at least one Boolean circuit involves using one or more input binary variables and corresponding output binary variables to construct a lookup table of mappings representing a quantum error correction decoder.

[0078] The disclosed methods and systems may aim to reduce the complexity of synthesized Boolean circuits. The disclosed methods and systems may use a simplification of the original problem of minimal Boolean circuit implementation for decoder d, by noting that different input bit strings may be associated with different probabilities. Thus, in practice, for sets of bit strings with small cumulative probabilities, it may suffice to generate an approximate version of the Boolean circuit for a decoder different from decoder d. In some cases, bit strings with small probabilities can be identified by their Hamming distance from bit strings with all zeros. A lookup table for the approximate decoder can be derived from the lookup table for the original decoder by inheriting the output values ​​of important bit strings and marking the remainder of bit strings whose exact output values ​​are less important as "don't care" terms.

[0079] A Boolean circuit representing a lookup table can be synthesized in various ways. In some cases, a Boolean circuit representing a lookup table is synthesized using the following procedure: Each input bit string that yields a non-zero output can be coded as a minterm. A minterm can be a logical conjunctive expression that evaluates to 1 only for its associated bit string. For example, the minterm of the bit string (1001) is AB'C'D, where the apostrophe, such as B', represents negation, and the product, such as AB, represents two-input AND operations. The sum of all minterms performed via an OR operation provides a typical Boolean circuit for the above lookup table. Such an expression is called a sum-of-products (SOP) expression.

[0080] The SOP representation of inputs / outputs in a lookup table can be compressed using two-level logic optimization. Such optimization may consider don't-care and don't-happen terms in the lookup table to reduce the complexity of the SOP representation in the lookup table.

[0081] In some cases, synthesizing at least one Boolean circuit involves performing optimizations on the Boolean circuit to reduce the number of logic gates, such as AND, OR, and NOT logic gates. In some cases, the Boolean circuit is iteratively optimized to reduce the number of logic gates until a threshold condition is met. The threshold condition can be the number of iterations, a threshold amount of reduction, or another convergence condition. In some cases, at least one Boolean circuit is synthesized while minimizing or reducing a figure-of-merit other than the number of AND and OR gates. In some cases, the figure-of-merit can be defined on a netlist derived from the Boolean circuit, which includes AND, OR, and NOT logic gates. Such a netlist may include a directed graph that defines the flow and sequence of the logic gates of the Boolean circuit and one or more non-Boolean circuit elements. In some cases, the netlist may include other primitive gates, such as XOR logic gates, as well as non-logic gates, such as SPLITTER. The figure of merit may relate to the physical resources required for the physical implementation of the netlist. In some cases, the figure of merit may include the depth of the netlist, the number of transistors required (in a CMOS implementation), or the number of Josephson junctions (in an SFQ implementation).

[0082] In some cases, the Quine-McCluskey algorithm in conjunction with Petrick’s method can be used to perform two-level logic optimization to minimize the SOP expression with respect to the total number of 2-input AND and OR gates. The minimized SOP expression can remain functionally equivalent to the original SOP expression. In some other cases, the heuristic Espresso algorithm can be used to perform this minimization, with the advantage of being scalable to larger input dimensions N s associated with it. Both the Quine-McCluskey and Espresso algorithms are generalized to the setting of approximate decoders. The SOP expression can be converted into a gate-level netlist, which can be further adapted to the underlying technological implementation before proceeding to the next step of integrated circuit generation. For example, an electronic technology restricted to 2-input gates may require converting multi-input minterms into a hierarchical sequence of two-level gates.

[0083] In some cases, the hardware resources used to implement the Boolean circuit associated with the two-level representation for the lookup table representing decoder d can be further improved by performing multilevel logic synthesis and optimization. One source of such potential improvement may be based on the observation that different minimum terms in the two-level representation may share the same subexpressions. Thus, by factoring out such subexpressions, the number of logic operations used to implement the lookup table can be reduced. In addition, these subexpressions can be evaluated before the rest of the circuit, which may lead to an increase in the depth of the associated Boolean circuit. In some cases, software packages such as ABC can be used to facilitate this process. A non-restrictive example of ABC can be found in Berkeley Logic Synthesis and Verification Group “A System for Sequential Synthesis and Verification,” available at https: / / people.eecs.berkeley.edu / ~alanmi / abc / , which is incorporated herein by reference in its entirety. Furthermore, ABC includes additional heuristics, which, when applied iteratively, can lead to further circuit minimization. As a step in this process, ABC can transform subcircuits that can be represented using a set of user-defined gates (such as 2-input AND, XOR, etc.), transform the resulting Boolean circuit into a netlist, and then directly optimize the figure of merit on the resulting netlist.

[0084] In some cases, the mapping represents a quantum error correction decoder.

[0085]

number

[0086] The extracted DFA is a tuple.

[0087]

number

[0088]

number

[0089]

number

[0090] In some cases, constructing a DFA may involve a merge procedure in the RNN's hidden state space. In some cases, the merge procedure can reduce the complexity of the DFA. A DFA can be extracted from an RNN according to the procedure described in Merrill and Tsilivis, “Extracting Finite Automata from RNNs Using State Merging”, arXiv:2201.12451, which is incorporated herein by reference in its entirety. For illustrative purposes only and not limiting, each new RNN input bit string may be interpreted as a character allowed by the DFA, a prefix may be a complete or partial sequence of characters containing a first character, and a word generally refers to a complete sequence of characters.

[0091] An uncompressed DFA, also called a prefix tree, can be constructed from a subset of words in the training set of an RNN. In one example, each word may be read sequentially character by character during the prefix, and a new DFA state may be introduced for each new prefix. Depending on the new character, transitions between DFA states are recorded, and the associated characters may be remembered. Each arrow may be associated with the character being created. Furthermore, each DFA state is associated with information about the hidden RNN state h, along with a label g(h), that was fed with the same prefix. In some cases, the information about the RNN's hidden state h is the vector h itself. Information related to the hidden RNN state can be used to evaluate the distance between pairs of DFA states. In some cases, the distance can be evaluated using the cosine similarity between h1 and h2. If the distance value is less than the value of the hyperparameter κ, or if the labels g(h1) and g(h2) are the same, the pair of states can be merged. To perform state merging, states in the pair can be removed from the DFA. Instead, a new single state may be added to the DFA, inheriting all incident and outgoing arrows from the deleted state. The new state may be associated with information derived from the information associated with the merged state. In some cases, this information includes the label g(h1) and the vector h1. At the end of the merge process, a nondeterministic finite automaton (NFA) may be obtained. The NFA may then be transformed into a new DFA, for example, using a powerset configuration. The size of the resulting DFA may be minimized. In some cases, the construction of the DFA may involve using the Hopcroft algorithm to reduce the complexity of the above DFA. Minimization may be performed according to the procedure described in Hopcroft, “An n log n algorithm for minimizing states in a finite automaton”, In Theory of Machines and Computations, pp. 189-196, Elsevier, 1971, which is incorporated herein by reference in its entirety.

[0092] In some cases, synthesizing at least one Boolean circuit may involve converting the Boolean circuit into a netlist and optimizing the netlist by relabeling the DFA. In some cases, the labeling of the DFA states Q may be binarized. For example, if Q contains three states {q0, q1, q2}, they may be labeled as {00, 01, 10}. For simplicity of presentation, without limitation, N b Assume that bits are required for encoding. A particular choice of state binary encoding strategy can affect the figure of merit evaluated on the resulting netlist. In some cases, a binary state encoding may be chosen that attempts to preserve the distance relationship between pairs of binary encodings and their corresponding RNN states. For example, the distance between binary encodings may be the Hamming distance, and the distance between RNN states may be the cosine similarity. In some cases, a heuristic discrete optimization algorithm may be used to optimize the binary state encoding, which is quantified by the evaluation of the figure of merit on the resulting netlist extracted from the DFA transition δ and the classifier F function.

[0093] Binary lookup table

[0094]

number

[0095] Binary lookup table

[0096]

number

[0097] δ b and F b Boolean circuits for both are generated using two-level or multi-level circuit synthesis and minimization as described elsewhere in this specification.

[0098] While preferred embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided only as examples. The present invention is not intended to be limited by any specific examples provided herein. While the description and illustration of embodiments herein have been made with reference to the preceding specification, they are not intended to be constrained. Numerous variations, alterations, and substitutions will be conceivable to those skilled in the art without departing from the present invention. Furthermore, it should be understood that all aspects of the present invention are not limited to any specific depictions, configurations, or relative proportions described herein, which will vary depending on various conditions and variables. It should be understood that various alternative forms of the embodiments of the present invention described herein may be employed when carrying out the present invention. Thus, it is intended that the present invention will further encompass any such alternatives, modifications, alterations, or equivalents. The following claims define the scope of the present invention, and the methods and structures within these claims, as well as their equivalents, are intended to be encompassed thereby.

Claims

1. A method for synthesizing a Boolean circuit for a quantum error correction decoder, wherein the method is (a) Providing one or more input binary variables that are at least partially derived from one or more syndrome measurements, (b) A step of providing a mapping representing the quantum error correction decoder, (c) A step of generating an output binary variable corresponding to one or more input binary variables based at least in part on the mapping, wherein the output binary variable represents one or more recovery operations of a plurality of qubits, (d) A step of synthesizing at least one Boolean circuit based at least partially on one or more input binary variables and the corresponding output binary variables. Methods that include...

2. The method according to claim 1, wherein (d) constructs a lookup table of the mapping based at least in part on one or more input binary variables and the corresponding output binary variables.

3. The method according to claim 1, wherein (d) an optimization is performed on the Boolean circuit in order to reduce the number of logic gates in the Boolean circuit.

4. The method according to claim 3, wherein the optimization is performed iteratively and until a stopping criterion is met.

5. The method according to claim 3, wherein the optimization includes two-level logic optimization.

6. The method according to claim 3, wherein the optimization includes multilevel logic optimization.

7. The method according to claim 5, wherein the two-level logic optimization includes reducing the number of AND gates and OR gates.

8. The method according to claim 7, wherein the two-level logic optimization includes reducing the number of AND gates, OR gates, and NOT gates.

9. The method according to claim 1, further comprising (d) converting the Boolean circuit into a netlist.

10. The method according to claim 9, wherein the netlist includes a directed graph, the directed graph is configured to define the flow and sequence of logic gates of the Boolean circuit and one or more non-Boolean circuit elements.

11. The method according to claim 1, wherein the one or more recovery operations are performed on a logical qubit or a physical qubit.

12. The method according to claim 11, further comprising the step of performing one or more recovery operations on the logical qubit or the physical qubit.

13. The method according to claim 1, wherein the mapping in (b) is at least partially based on a recurrent neural network (RNN).

14. The method according to claim 13, wherein (b) (i) constructs a deterministic finite automaton (DFA) of the RNN, and (ii) constructs one or more lookup tables at least in part on a classifier, the classifier being configured to associate labels with each state of the DFA, and the classifier including a transition function configured to associate each state of the DFA with an input of the states of the DFA.

15. The method according to claim 14, wherein the RNN includes a clustering layer for reducing the DFA size.

16. The method according to claim 14, wherein constructing the DFA in (i) includes performing a merge procedure in the hidden state space of the RNN, wherein the merge procedure is configured to reduce the complexity of the DFA.

17. The method according to claim 14, further comprising a step of reducing DFA complexity based at least in part on the Hopcroft algorithm.

18. The method according to claim 14, further comprising the step of constructing a binary state encoding of the DFA.

19. The method of claim 14, further comprising (d) converting the Boolean circuit into a netlist and optimizing the netlist by at least partially relabeling the DFA.

20. The method according to claim 1, wherein the one or more syndrome measurements are from a quantum error correction code comprising one or more members selected from the group consisting of Surface codes, color codes, toric codes, and Bacon-Shor codes.

21. The method according to claim 1, further comprising the step of performing a quantum error correction code before (a).

22. The method according to claim 21, wherein the quantum error correction code includes one or more members selected from the group consisting of a surface code, a color code, a toric code, and a Bacon-Shor code.

23. The method according to claim 1, wherein the quantum error correction decoder includes one or more members selected from the group consisting of a minimum weight perfect matching decoder, a union-find decoder, a belief-matching decoder, a tensor network decoder, and a renormalization group decoder.

24. A quantum error correction decoder chip, wherein the quantum error correction decoder chip is A quantum error correction decoder chip comprising one or more Boolean circuits, each configured to receive one or more input binary variables derived from one or more syndrome measurements from syndrome qubits, each configured to process the one or more input binary variables to generate output binary variables, and each output binary variable operable to generate one or more recovery operations.

25. The quantum error correction decoder chip according to claim 24, wherein the one or more Boolean circuits include at least one member of the group consisting of field-programmable gate arrays (FPGAs), ASICs, CMOSs, and SFQs.

26. The quantum error correction decoder chip according to claim 24, wherein the quantum error correction decoder chip is communicably coupled to a quantum processor, the quantum processor is operably coupled to a cryogenic device and cooled to an extremely low temperature by the cryogenic device, the cryogenic device has different cryogenic stages at different extremely low temperatures, and one or more Boolean circuits are operably coupled to the cryogenic device and cooled to different cryogenic stages by the cryogenic device.

27. The quantum error correction decoder chip according to claim 26, wherein one or more Boolean circuits are operably coupled to a circuit cooled by the cryogenic device.

28. The quantum error correction decoder chip according to claim 24, wherein one or more Boolean circuits are operably coupled to the circuits at room temperature.

29. A quantum error correction decoder chip according to claim 24, which is communicably coupled to a controller.

30. The quantum error correction decoder chip according to claim 24, wherein the recovery operation includes updating a Pauli frame or updating data qubits to reduce errors in quantum computing.

31. The quantum error correction decoder chip according to claim 26, wherein the quantum processor includes one or more members selected from the group consisting of a superconducting quantum processor, a semiconductor quantum processor, a trapped ion quantum processor, and a neutral atom quantum processor.

32. The quantum error correction decoder chip according to claim 24, wherein the one or more Boolean circuits are at least partially based on a lookup table, and the lookup table is at least partially based on the one or more input binary variables and the corresponding output binary variables.

33. The quantum error correction decoder chip according to claim 24, wherein the one or more Boolean circuits are generated by performing an optimization on the one or more Boolean circuits, at least partially, in order to reduce the number of logic gates in the one or more Boolean circuits.

34. The quantum error correction decoder chip according to claim 33, wherein the optimization is performed iteratively and until a stopping criterion is met.

35. The quantum error correction decoder chip according to claim 33, wherein the optimization includes two-level logic optimization.

36. The quantum error correction decoder chip according to claim 36, wherein the optimization includes multilevel logic optimization.

37. The quantum error correction decoder chip according to claim 35, wherein the two-level logic optimization includes reducing the number of AND gates and OR gates.

38. The quantum error correction decoder chip according to claim 37, wherein the two-level logic optimization includes reducing the number of AND gates, OR gates, and NOT gates.

39. The quantum error correction decoder chip according to claim 24, wherein one or more Boolean circuits include a corresponding netlist.

40. The quantum error correction decoder chip according to claim 39, wherein the netlist includes a directed graph, the directed graph is configured to define the flow and sequence of logic gates of the Boolean circuit and one or more non-Boolean circuit elements.

41. The quantum error correction decoder chip according to claim 26, wherein the one or more Boolean circuits are configured to provide the one or more recovery operations performed on the logic qubits or physical qubits of the quantum processor.

42. The quantum error correction decoder chip according to claim 24, wherein one or more Boolean circuits are generated at least partially based on a recurrent neural network (RNN).

43. The quantum error correction decoder chip according to claim 42, wherein the RNN includes a clustering layer for reducing the size of the deterministic finite automaton (DFA).

44. The quantum error correction decoder chip according to claim 24, wherein the one or more syndrome measurements are from a quantum error correction code that includes one or more members selected from the group consisting of a Surface code, a color code, a toric code, and a Bacon-Shor code.

45. The quantum error correction decoder chip according to claim 24, further comprising a quantum error correction code associated with the quantum error correction decoder chip.

46. The quantum error correction decoder chip according to claim 45, wherein the quantum error correction code includes one or more members selected from the group consisting of a surface code, a color code, a toric code, and a Bacon-Shor code.

47. A quantum error correction decoder chip according to claim 24, configured to perform quantum error correction decoding.

48. The quantum error correction decoder chip according to claim 24 or 47, wherein the one or more recovery operations are configured to update one or more data qubits in order to reduce errors in quantum computation.

49. The quantum error correction decoder chip according to claim 47 or 48, wherein the quantum error correction decoder includes one or more members selected from the group consisting of a minimum weight perfect matching decoder, a union-find decoder, a belief-matching decoder, a tensor network decoder, and a renormalization group decoder.

50. A processor that is communicatively coupled to a quantum computer, wherein the processor is (a) To provide one or more input binary variables that are at least partially derived from one or more syndrome measurements from the quantum computer, (b) To provide a mapping representing a quantum error correction decoder, (c) Generating corresponding output binary variables for one or more input binary variables based at least in part on the mapping, wherein the output binary variables represent one or more recovery operations of a plurality of qubits, (d) Synthesizing at least one Boolean circuit based at least partially on one or more input binary variables and the corresponding output binary variables. A processor configured to execute a set of instructions for performing a certain action.

51. The processor according to claim 50, wherein the processor is configured to construct a lookup table of the mapping based at least partially on the one or more input binary variables and the corresponding output binary variables.

52. The processor according to claim 50, wherein in (d), the processor is configured to perform optimization on the Boolean circuit in order to reduce the number of logic gates in the Boolean circuit.

53. The processor according to claim 52, wherein the optimization is performed iteratively and until a termination criterion is met.

54. The processor according to claim 50, wherein the optimization includes two-level logic optimization.

55. The processor according to claim 50, wherein the optimization includes multilevel logic optimization.

56. The processor according to claim 54, wherein the two-level logic optimization includes reducing the number of AND gates and OR gates.

57. The processor according to claim 56, wherein the two-level logic optimization includes reducing the number of AND gates, OR gates, and NOT gates.

58. The processor according to claim 56, wherein in (d), the processor is configured to convert the Boolean circuit into a netlist.

59. The processor according to claim 58, wherein the netlist includes a directed graph that defines the logic gates of the Boolean circuit and the flow and sequence of one or more non-Boolean circuit elements.

60. The processor according to claim 50, wherein the one or more recovery operations are performed on a logical qubit or a physical qubit.

61. The processor according to claim 60, wherein the processor is configured to perform one or more recovery operations on the logical qubit or the physical qubit.

62. The processor according to claim 50, wherein the mapping is at least partially based on a recurrent neural network (RNN).

63. The processor according to claim 62, wherein in (b), the processor is configured to (i) construct a deterministic finite automaton (DFA) of the RNN, and (ii) construct one or more lookup tables at least in part on a classifier, wherein the classifier is configured to associate labels with each state of the DFA, and the classifier includes a transition function configured to associate each state of the DFA with an input of the states of the DFA.

64. The method according to claim 63, wherein the RNN includes a clustering layer for reducing the DFA size.

65. The processor according to claim 63, wherein in (i), the processor performs a merge procedure in the hidden state space of the RNN, and the merge procedure is configured to reduce the complexity of the DFA.

66. The processor according to claim 63, configured to reduce the DFA complexity based at least in part on the Hopcroft algorithm.

67. The processor according to claim 63, configured to construct a binary state encoding of a DFA.

68. The processor according to claim 63, wherein in (d), the processor is configured to convert the Boolean circuit into a netlist.

69. The processor according to claim 68, configured to optimize the netlist by relabeling the DFA, at least partially.

70. The processor according to claim 50, wherein the one or more syndrome measurements are from a quantum error correction code that includes one or more members selected from the group consisting of Surface codes, color codes, toric codes, and Bacon-Shor codes.

71. The processor according to claim 50, wherein, prior to (a), the processor is configured to implement a quantum error correction code.

72. The processor according to claim 71, wherein the quantum error correction code includes one or more members selected from the group consisting of a surface code, a color code, a toric code, and a Bacon-Shor code.

73. The processor according to claim 50, wherein the quantum error correction decoder includes one or more members selected from the group consisting of a minimum weight perfect matching decoder, a union-find decoder, a belief-matching decoder, a tensor network decoder, and a renormalization group decoder.

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