Pixel circuit, driving method, display board, display panel, and display device

Abstract

The present invention relates to a pixel circuit, a driving method, a display board, a display panel, and a display device. The pixel circuit includes a light-emitting element (E0), a driving circuit (10), a first light-emitting control circuit (11), a first control circuit (12), a second control circuit (13), and a data writing circuit (32). The first control circuit (12) supplies a first control voltage to a second control node (N2) under the control of a first reset control signal, and controls the supply of a first light-emitting control signal to a first control node (N1) via a first light-emitting control line (E1) under the control of the potential of the second control node (N2). The second control circuit (13) writes a second control voltage to a third control node (N3) under the control of a second reset control signal, and controls the supply of a second light-emitting control signal to a first control node (N1) via a second light-emitting control line (Hf) under the control of the potential of the third control node (N3).

Description

Technical Field

[0003] , ,

[0001] Cross - reference to Related Applications This application claims priority to a PCT application with a filing date of March 31, 2023 and an application number of PCT / CN2023 / 085358. This disclosure relates to the technical field of displays, and particularly to pixel circuits, driving methods, display substrates, display panels, and display devices.

Background Art

[0002] Related pixel circuits including micro - light - emitting diodes or mini - light - emitting diodes use a first data line and a second data line. Among them, the first data line is for supplying a light - emitting time data voltage, and the second data line is for supplying a display data voltage. Since the first data line and the second data line are provided between two columns of pixel circuits, the number of side signals is large. Moreover, due to the coupling effect in the charging compensation stage between the signal on the first data line and the signal on the second data line, the voltage jump caused by the display data voltage in the charging compensation stage will cause column - direction defects in the related pixel circuits.

Summary of the Invention

[0003] In one aspect, an embodiment of the present disclosure is a pixel circuit including a light - emitting element and a pixel driving circuit. The pixel driving circuit includes a driving circuit, a first light - emitting control circuit, a first control circuit, a second control circuit, and a data writing circuit. The driving circuit is for generating a driving current to drive the light - emitting element. The first light - emitting control circuit is electrically connected to a first control node, a first end of the driving circuit, and the light - emitting element respectively, and is for controlling to conduct between the first end of the driving circuit and the light - emitting element under the control of the potential of the first control node. The first control circuit is electrically connected to the data line, the first reset control line, the first light emission control line, the first control node, and the second control node, respectively, and is for controlling the supply of the first control voltage supplied from the data line to the second control node under the control of the first reset control signal supplied from the first reset control line, and for controlling the supply of the first light emission control signal to the first control node by the first light emission control line under the control of the potential of the second control node. The second control circuit is electrically connected to the data line, the second reset control line, the second light emission control line, the first control node, and the third control node, respectively, and controls the second reset control signal supplied from the second reset control line to be written to the third control node, and the second light emission control signal to be supplied to the first control node by the second light emission control line, under the control of the potential of the third control node. The data writing circuit is electrically connected to the scan line, the data line, and the second end of the drive circuit, respectively, and is for writing the display data voltage supplied from the data line to the second end of the drive circuit under the control of the scan signal supplied from the scan line. The first control circuit, the second control circuit, and the data writing circuit are for receiving the corresponding voltage signal on the data line in a time-division manner. The present invention provides a pixel circuit in which the pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same, or at least two of the pulse widths of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are different.

[0004] Selectively, the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits within the same GOA module, and each receives a drive signal supplied from the different GOA circuits, or The scan line, the first reset control line, and the second reset control line are each electrically connected to one GOA circuit in a different GOA module, and each receives a drive signal supplied from one GOA circuit in a different GOA module, or Two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits within the first GOA module and receive drive signals supplied from the different GOA circuits within the first GOA module, while the remaining one of the scan line, the first reset control line, and the second reset control line is electrically connected to one GOA circuit within the second GOA module and receives a drive signal supplied from one GOA circuit within the second GOA module.

[0005] Selectively, the first control circuit includes a first write control circuit, a first energy storage circuit, and a second write control circuit. The first write control circuit is electrically connected to the first reset control line, the data line, and the second control node, respectively, and is for supplying the first control voltage supplied from the data line to the second control node under the control of the first reset control signal. The first energy storage circuit is electrically connected to the second control node and is for storing electrical energy. The second writing control circuit is electrically connected to the second control node, the first light emission control line, and the first control node, respectively, and controls the supply of the first light emission control signal to the first control node via the first light emission control line under the control of the potential of the second control node.

[0006] Selectively, the second control circuit includes a third write control circuit, a second energy storage circuit, and a fourth write control circuit. The third write control circuit is electrically connected to the second reset control line, the data line, and the third control node, respectively, and under the control of the second reset control signal, writes the second control voltage supplied from the data line to the third control node. The second energy storage circuit is electrically connected to the third control node and is for storing electrical energy. The fourth writing control circuit is electrically connected to the third control node, the second light emission control line, and the first control node, respectively, and controls the supply of the second light emission control signal to the first control node via the second light emission control line, under the control of the potential of the third control node.

[0007] Selectively, the first write control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second write control circuit includes a second transistor. The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node. The first electrode plate of the first capacitance is electrically connected to the second control node, and the second electrode plate of the first capacitance is electrically connected to the first initial voltage line. The gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light emission control line, and the second pole of the second transistor is electrically connected to the first control node.

[0008] Selectively, the third write control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth write control circuit includes a fourth transistor. The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node. The first electrode plate of the second capacitance is electrically connected to the third control node, and the second electrode plate of the second capacitance is electrically connected to the second initial voltage line. The gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

[0009] Selectively, the pixel circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control circuit. The second light emission control circuit is electrically connected to the first light emission control line, the power supply voltage line, and the second end of the drive circuit, respectively, and is used to control the power supply voltage line and the second end of the drive circuit to conduct electricity under the control of the first light emission control signal.

[0010] Selectively, the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit and a third energy storage circuit. The compensation control circuit is electrically connected to the scan line, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively, and is for controlling the control of the scan signal so that conductivity is established between the control terminal of the drive circuit and the first terminal of the drive circuit. The third energy storage circuit is electrically connected to the control terminal of the drive circuit and is for storing electrical energy.

[0011] Selectively, the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit, The first reset circuit is electrically connected to the third reset control line, the third initial voltage line, and the control terminal of the drive circuit, respectively, and is used to write the third initial voltage supplied from the third initial voltage line to the control terminal of the drive circuit under the control of the third reset control signal supplied from the third reset control line.

[0012] Selectively, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit, The second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line, and the first pole of the light-emitting element, respectively, and is used to write the fourth initial voltage supplied from the fourth initial voltage line to the first pole of the light-emitting element under the control of the fourth reset control signal supplied from the fourth reset control line. The second pole of the light-emitting element is electrically connected to the first voltage line.

[0013] Selectively, the third reset control line is either the first reset control line or the second reset control line. The fourth reset control line is either the first reset control line or the second reset control line.

[0014] Selectively, the second light-emitting control circuit includes a fifth transistor. The gate of the fifth transistor is electrically connected to the first light emission control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second terminal of the drive circuit.

[0015] Selectively, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor, and the drive circuit includes a drive transistor. The gate of the sixth transistor is electrically connected to the scan line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the drive transistor. The gate of the seventh transistor is electrically connected to the scan line, the first pole of the seventh transistor is electrically connected to the gate of the drive transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the drive transistor. The first electrode plate of the third capacitor is electrically connected to the gate of the drive transistor, and the second electrode plate of the third capacitor is electrically connected to the power supply voltage line.

[0016] Optionally, the first reset circuit includes an eighth transistor, a gate of the eighth transistor is electrically connected to the third reset control line, a first pole of the eighth transistor is electrically connected to a third initial voltage line, and a second pole of the eighth transistor is electrically connected to a control end of the driving circuit.

[0017] Optionally, the second reset circuit includes a ninth transistor, a gate of the ninth transistor is electrically connected to the fourth reset control line, a first pole of the ninth transistor is electrically connected to a fourth initial voltage line, and a second pole of the ninth transistor is electrically connected to a first pole of the light-emitting element.

[0018] Optionally, the pixel circuit according to at least one embodiment of the present disclosure includes a multiplexing control circuit, the multiplexing control circuit is electrically connected to a multiplexing control end, a voltage output end of a source driver, and the data line respectively, and is for controlling to conduct between the voltage output end and the data line under the control of a multiplexing control signal supplied from the multiplexing control end.

[0019] In a second aspect, an embodiment of the present disclosure is a driving method, which is applied to the above pixel circuit and includes a first writing stage and a second writing stage in a display stage. The driving method includes: In the first writing stage, a first control circuit supplies a first control voltage supplied from a data line to a second control node under the control of a first reset control signal, and the first control circuit controls whether to supply a first light-emitting control signal to a first control node under the control of the potential of the second control node; In the second writing stage, a second control circuit writes a second control voltage supplied from the data line to a third control node under the control of a second reset control signal, and the second control circuit controls whether to supply a second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0020] Selectively, the driving method described in at least one embodiment of the present disclosure is When performing medium-to-high gradation display, in the first writing stage, the first control circuit controls the supply of the first light emission control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the supply of the second light emission control signal to the first control node to be stopped under the control of the potential of the third control node. When performing low-gradation display, the first writing step includes controlling the supply of the first light emission control signal to the first control node to be stopped under the control of the potential of the second control node, and the second writing step includes controlling the supply of the second light emission control signal to the first control node under the control of the potential of the third control node.

[0021] In the third aspect, embodiments of the present disclosure provide a base substrate, a multi-row multi-column pixel circuit provided within a display area on the base substrate, and a display substrate.

[0022] Selectively, pixel circuits located in the same row are provided between two rows of data lines, and the data lines extend along the first direction. The pixel circuit of row a is provided between the scan line of row a and the first voltage line of row a, where a is a positive integer. The scan line of row a and the first voltage line of row a extend along the second direction, The first direction intersects with the second direction.

[0023] Selectively, the pixel circuit includes a light-emitting element and a pixel driving circuit. A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided within the gap. The orthographic projection of the light-emitting element on the base substrate does not overlap with the orthographic projection of the pixel driving circuit on the base substrate.

[0024] Selectively, the display board described in at least one embodiment of the present disclosure further includes a first signal line, the majority of which is included in the first signal line extends along a second direction. The first signal line is bent around the light-emitting element to form a first retraction space, and at least a portion of the light-emitting element is provided within the first retraction space.

[0025] Selectively, a display substrate described in at least one embodiment of the present disclosure includes a plurality of rows of light-emitting units, the light-emitting units including at least three of the light-emitting elements, At least one of the first signal lines is bent to the first side around at least one of the light-emitting elements in an odd-numbered row of light-emitting units to form a first retractable space. At least one of the first signal lines is bent to the second side around at least one of the light-emitting elements in an even row of light-emitting units to form another first retractable space. The first side and the second side are opposing sides.

[0026] Selectively, the pixel circuit includes a light-emitting element and a pixel driving circuit. The light-emitting element is provided on the side of the pixel driving circuit that is farther from the base substrate, The orthographic projection of the light-emitting element on the base substrate overlaps, at least partially, with the orthographic projection of the pixel driving circuit on the base substrate.

[0027] Selectively, a display board according to at least one embodiment of the present disclosure further includes a light-emitting control signal generation module and a second signal line, the light-emitting control signal generation module includes a plurality of stages of light-emitting control signal generation circuits, the light-emitting control signal generation circuits are provided in the display area, The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. At least one stage of the light emission control signal generation circuit is located between adjacent pixel drive groups, Most of the signal line portion included in the second signal line extends along the first direction, At least one of the second signal lines is bent around the at least one stage of the light emission control signal generation circuit to form a second retractable space, and a portion of the at least one stage of the light emission control signal generation circuit is provided within the second retractable space.

[0028] Selectively, the orthographic projection of the light emission control signal generation circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

[0029] Selectively, a display board according to at least one embodiment of the present disclosure further includes a gate drive module, the gate drive module includes a plurality of gate drive circuits, the gate drive circuits are provided in the display area, The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. At least one stage of the gate drive circuit is located between adjacent pixel drive groups.

[0030] Selectively, the display board described in at least one embodiment of the present disclosure further includes a second signal line, the majority of which is included in the second signal line extends along a first direction, At least one of the second signal lines is bent around the at least one stage of the gate drive circuit to form a third retraction space, and a portion of the at least one stage of the gate drive circuit is provided within the third retraction space.

[0031] Selectively, the orthographic projection of the gate drive circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

[0032] In the fourth aspect, embodiments of the present disclosure provide a display panel including the above-described display substrate.

[0033] Selectively, the display panel described in at least one embodiment of the present disclosure further includes a source driver, multiple rows of data lines, and a multiplexer circuit. Multiple pixel circuits located in the same row are all electrically connected to the data lines of the same row. The multiplexer circuit is electrically connected to the multiple voltage output terminals, multiple multiplexing control terminals, and multiple rows of data lines of the source driver, respectively, and is used to write voltage signals supplied from the source driver via its voltage output terminals to the data lines under the control of multiplexing control signals supplied from the multiplexing control terminals.

[0034] Selectively, the multiplexer circuit is electrically connected to N multiplexing control terminals, and the multiplexer circuit includes M multiplexing subcircuits, where N and M are integers greater than 1. Each of the aforementioned multiplexing subcircuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and the N rows of data lines, and is for controlling the voltage signal supplied from the voltage output terminal to be supplied to the nth data line of the N rows of data lines, under the control of the nth multiplexing control signal supplied from the Nth multiplexing control terminals. n is a positive integer less than or equal to N.

[0035] In the fifth aspect, an embodiment of the present disclosure is a driving method applied to the above-mentioned display panel, wherein the display cycle includes a first write period and a second write period, the first write period includes a first data write period and a second data write period, the second write period includes a third data write period and a fourth data write period, and the driving method is During the first data writing period, the multiplexer circuit writes the first control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. During the second data writing period, the first control circuit supplies a first control voltage supplied from the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether or not to supply a first light emission control signal to the first control node under the control of the potential of the second control node. During the third data writing period, the multiplexer circuit writes the second control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. The present invention provides a driving method that includes, during a fourth data writing period, a second control circuit writing a second control voltage supplied from the data line to a third control node under the control of a second reset control signal, and a second control circuit controlling whether or not to supply a second light emission control signal to the first control node under the control of the potential of the third control node.

[0036] Selectively, the first data writing period and the second data writing period may be set one after the other, and the third data writing period and the fourth data writing period may be set one after the other, or The first data writing period is included in the second data writing period, and the third data writing period is included in the fourth data writing period.

[0037] In the sixth aspect, embodiments of the present disclosure provide a display device including the above-described display panel. [Brief explanation of the drawing]

[0038] [Figure 1] Figure 1 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 2] Figure 2 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 3] Figure 3 is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 5] Figure 5 is an operation timing chart of at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure. [Figure 6] Figure 6 is an operation timing chart of at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure. [Figure 7] Figure 7 is an operation timing chart of at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure. [Figure 8A] Figure 8A is a schematic diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 8B] Figure 8B is a structural diagram of a pixel circuit described in at least one embodiment of the present disclosure. [Figure 9] Figure 9 is a layout diagram of at least one embodiment of the pixel circuit shown in Figure 4. [Figure 10] Figure 10 is a layout diagram of the first gate metal layer in Figure 9. [Figure 11] Figure 11 is a layout diagram of the semiconductor layer in Figure 9. [Figure 12] Figure 12 is a layout diagram of the second gate metal layer in Figure 9. [Figure 13] Figure 13 is a layout diagram of the source and drain metal layers in Figure 9. [Figure 14A] Figure 14A is a structural diagram of a display substrate described in at least one embodiment of the present disclosure. [Figure 14B] Figure 14B is a layout diagram of the first gate metal layer in Figure 14A. [Figure 14C] Figure 14C is a schematic diagram of the signal lines provided on the first gate metal layer and the positions of each light-emitting element in Figure 14A. [Figure 15] Figure 15 is a structural diagram of a display substrate described in at least one embodiment of the present disclosure. [Figure 16] Figure 16 is a structural diagram of a display substrate described in at least one embodiment of the present disclosure. [Figure 17] Figure 17 is a structural diagram of a display substrate described in at least one embodiment of the present disclosure. [Figure 18] Figure 18 is a structural diagram of a display substrate described in at least one embodiment of the present disclosure. [Figure 19] Figure 19 is a structural diagram of a display panel described in at least one embodiment of the present disclosure. [Figure 20]Figure 20 is a structural diagram of a display panel described in at least one embodiment of the present disclosure. [Figure 21] Figure 21 is a schematic diagram of a display panel described in at least one embodiment of the present disclosure. [Figure 22] Figure 22 is an operation timing chart of at least one embodiment of the display panel shown in Figure 21 of this disclosure. [Figure 23] Figure 23 is an operation timing chart of at least one embodiment of the display panel shown in Figure 21 of this disclosure. [Figure 24] Figure 24 is an operation timing chart of at least one embodiment of the display panel shown in Figure 21 of this disclosure. [Figure 25] Figure 25 is an operation timing chart of at least one embodiment of the display panel shown in Figure 21 of this disclosure. [Figure 26] Figure 26 is an operation timing chart of a display panel described in at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0039] The following describes the technical aspects of the embodiments of this disclosure clearly and completely, with reference to the drawings of the embodiments of this disclosure. It is clear that the embodiments described are only a selection of, and not all, embodiments of this disclosure. Any other embodiments obtained by those skilled in the art without creative work based on the embodiments of this disclosure are all covered by this disclosure.

[0040] The transistors used in all embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other devices having similar characteristics. In the embodiments of this disclosure, in order to distinguish between the two poles of a transistor other than the gate, one pole is referred to as the first pole and the other as the second pole.

[0041] In actual operation, if the transistor is a thin-film transistor or a field-effect transistor, the first pole may be the drain and the second pole may be the source, or the first pole may be the source and the second pole may be the drain.

[0042] As shown in Figure 1, the pixel circuit described in at least one embodiment of the present disclosure includes a light-emitting element E0 and a pixel driving circuit, the pixel driving circuit includes a driving circuit 10, a first light-emitting control circuit 11, a first control circuit 12, a second control circuit 13 and a data writing circuit 32, The aforementioned drive circuit 10 is for generating a drive current to drive the light-emitting element E0. The first light-emitting control circuit 11 is electrically connected to the first control node N1, the first end of the drive circuit 10, and the light-emitting element E0, respectively, and is used to control the connection between the first end of the drive circuit 10 and the light-emitting element E0 under the control of the potential of the first control node N1. The first control circuit 12 is electrically connected to the data line DT, the first reset control line RA, the first light emission control line E1, the first control node N1, and the second control node N2, respectively. It supplies the first control voltage supplied from the data line DT to the second control node N2 under the control of the first reset control signal supplied from the first reset control line RA, and controls the supply of the first light emission control signal to the first control node N1 via the first light emission control line E1 under the control of the potential of the second control node N2. The second control circuit 13 is electrically connected to the data line DT, the second reset control line RB, the second light emission control line Hf, the first control node N1, and the third control node N3, respectively. It is used to control the second reset control signal supplied from the second reset control line RB, write the second control voltage supplied from the data line DT to the third control node N3, and, under the control of the potential of the third control node N3, control the supply of the second light emission control signal to the first control node N1 via the second light emission control line Hf. The data writing circuit 32 is electrically connected to the scan line G1, the data line DT, and the second end of the drive circuit 10, respectively, and is for writing the display data voltage supplied from the data line DT to the second end of the drive circuit 10 under the control of the scan signal supplied from the scan line G1. The first control circuit 12, the second control circuit 13, and the data writing circuit 32 are for receiving the corresponding voltage signal on the data line DT in a time-division manner. The pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same, or at least two of the pulse widths of the scanning signal, the first reset control signal, and the second reset control signal are different.

[0043] In at least one embodiment of the pixel circuit shown in Figure 1 of this disclosure, the display data voltage Data_I and the light emission time control data voltage Data_T are supplied in a time-division manner using only one data line. This reduces the number of side signals and solves the problem of loss of grayscale signals when a multiplex transistor is added. Furthermore, the matching of the display data voltage Data_I and the light emission time control data voltage Data_T avoids coupling effects of both signals during the charge compensation stage, and reduces voltage jumps caused by the display data voltage Data_I during the charge compensation stage, thus resolving the column-direction defects of the original pixel circuit.

[0044] In at least one embodiment of the present disclosure, the scan line, the first reset control line, and the second reset control line are each electrically connected to different GOA circuits within the same GOA module and each receives a drive signal supplied from the different GOA circuits, or The scan line, the first reset control line, and the second reset control line are each electrically connected to one GOA circuit in a different GOA module, and each receives a drive signal supplied from one GOA circuit in a different GOA module, or Two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits within the first GOA module and receive drive signals supplied from the different GOA circuits within the first GOA module, while the remaining one of the scan line, the first reset control line, and the second reset control line is electrically connected to one GOA circuit within the second GOA module and receives a drive signal supplied from one GOA circuit within the second GOA module.

[0045] In actual implementation, the GOA module may include multiple GOA circuits cascaded together, with each stage of the GOA circuit supplying the corresponding drive signal. The drive signal output terminal of the a-1 stage GOA circuit may be electrically connected to the input terminal of the a stage GOA circuit and may be used to supply an input signal to the a stage GOA circuit. a is a positive integer.

[0046] In at least one embodiment of this disclosure, The pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be the same, and the corresponding drive signals may be supplied to the scanning line, the first reset control line, and the second reset control line, respectively, by GOA circuits in different stages within the same GOA module. In this way, the number of GOA modules used is reduced, making it easier to achieve a narrow bezel, or The pulse widths of the scanning signal, the first reset control signal, and the second reset control signal may be different from each other, and the corresponding drive signals may be supplied to the scanning line, the first reset control line, and the second reset control line, respectively, by any one stage of GOA circuitry within different GOA modules, or The pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be the same for two of them. Different stages of GOA circuits in the first GOA module may supply the corresponding drive signals to two of the scanning line, the first reset control line, and the second reset control line, while any one of the GOA circuits in the second GOA module may supply the corresponding drive signal to the remaining one of the scanning line, the first reset control line, and the second reset control line.

[0047] For example, the pulse width of the first reset control signal and the pulse width of the second reset control signal may be the same, and the pulse width of the scanning signal may be different from the pulse width of the first reset control signal. The first reset control signal and the second reset control signal may be supplied to the first reset control line and the second reset control line, respectively, by different stages of GOA circuits in the first GOA module, and the scanning signal may be supplied to the scanning line by any one stage of GOA circuit in the second GOA module.

[0048] In at least one embodiment of the present disclosure, the first control voltage and the second control voltage may be light emission time control data voltages.

[0049] Selectively, the light-emitting element may be a Mini LED or a Micro LED, but is not limited to these. In specific implementations, the light-emitting element may be an organic light-emitting diode.

[0050] During the operation of at least one embodiment of the pixel circuit shown in Figure 1 of this disclosure, When performing medium-to-high gradation display, the first light emission control line E1 controls the supply of the first light emission control signal to the first control node N1, and different light emission currents are generated depending on the voltage values ​​of the given different display data voltages. When performing low-gradation display, a control method of light emission current + light emission time is used, and the second light emission control signal on the second light emission control line Hf is supplied to the first control node N1. The second light emission control signal is a high-frequency signal, which reduces the flickering problem at low gradation.

[0051] In the operation of at least one embodiment of the pixel circuit shown in Figure 1 of this disclosure, the display stage may include a first writing stage and a second writing stage, and the driving method is In the first writing stage, the first control circuit 12, under the control of the first reset control signal, supplies a first control voltage supplied from the data line DT to the second control node N2, and the first control circuit 12, under the control of the potential of the second control node N2, controls whether or not to supply a first light emission control signal to the first control node N1. In the second writing stage, the second control circuit 13 writes the second control voltage supplied from the data line DT to the third control node N3 under the control of the second reset control signal, and the second control circuit 13 controls whether to supply the second light emission control signal to the first control node N1 under the control of the potential of the third control node N3.

[0052] During the operation of at least one embodiment of the pixel circuit shown in Figure 1 of this disclosure, When performing medium-to-high gradation display, in the first writing stage, the first control circuit 12 controls the supply of the first light emission control signal to the first control node N1 under the control of the potential of the second control node N2, and in the second writing stage, the second control circuit 13 controls the supply of the second light emission control signal to the first control node N1 to be stopped under the control of the potential of the third control node N3. When performing low-gradation display, in the first writing stage, the first control circuit 12 controls the supply of the first light emission control signal to the first control node N1 to be stopped under the control of the potential of the second control node N2, and in the second writing stage, the second control circuit 13 controls the supply of the second light emission control signal to the first control node N1 under the control of the potential of the third control node N3.

[0053] In at least one embodiment of the present disclosure, the first control circuit includes a first write control circuit, a first energy storage circuit, and a second write control circuit. The first write control circuit is electrically connected to the first reset control line, the data line, and the second control node, respectively, and is for supplying the first control voltage supplied from the data line to the second control node under the control of the first reset control signal. The first energy storage circuit is electrically connected to the second control node and is for storing electrical energy. The second writing control circuit is electrically connected to the second control node, the first light emission control line, and the first control node, respectively, and controls the supply of the first light emission control signal to the first control node via the first light emission control line under the control of the potential of the second control node.

[0054] In specific implementations, the first control circuit may include a first write control circuit, a first energy storage circuit, and a second write control circuit, the first write control circuit controlling so that a first control voltage is written to the second control node, and the second write control circuit controlling so that a first light emission control signal is written to the first control node.

[0055] In at least one embodiment of the present disclosure, the second control circuit includes a third write control circuit, a second energy storage circuit, and a fourth write control circuit. The third write control circuit is electrically connected to the second reset control line, the data line, and the third control node, respectively, and under the control of the second reset control signal, writes the second control voltage supplied from the data line to the third control node. The second energy storage circuit is electrically connected to the third control node and is for storing electrical energy. The fourth writing control circuit is electrically connected to the third control node, the second light emission control line, and the first control node, respectively, and controls the supply of the second light emission control signal to the first control node via the second light emission control line, under the control of the potential of the third control node.

[0056] In specific implementation, the second control circuit may include a third write control circuit, a second energy storage circuit, and a fourth write control circuit, the third write control circuit controlling so that the second control voltage is written to the third control node, and the fourth write control circuit controlling so that the second light emission control signal is supplied to the first control node.

[0057] As shown in Figure 2, in addition to at least one embodiment of the pixel circuit shown in Figure 1, The first control circuit includes a first write control circuit 21, a first energy storage circuit 22, and a second write control circuit 23. The first write control circuit 21 is electrically connected to the first reset control line RA, the data line DT, and the second control node N2, respectively, and is for supplying the first control voltage supplied from the data line DT to the second control node N2 under the control of the first reset control signal. The first energy storage circuit 22 is electrically connected to the second control node N2 and is for storing electrical energy. The second writing control circuit 23 is electrically connected to the second control node N2, the first light emission control line E1, and the first control node N1, respectively, and controls the supply of the first light emission control signal to the first control node N1 via the first light emission control line E1 under the control of the potential of the second control node N2. The second control circuit includes a third write control circuit 24, a second energy storage circuit 25, and a fourth write control circuit 26. The third write control circuit 24 is electrically connected to the second reset control line RB, the data line DT, and the third control node N3, respectively, and under the control of the second reset control signal, writes the second control voltage supplied from the data line DT to the third control node N3. The second energy storage circuit 25 is electrically connected to the third control node N3 and is for storing electrical energy. The fourth writing control circuit 26 is electrically connected to the third control node N3, the second light emission control line Hf, and the first control node N1, respectively, and controls the supply of the second light emission control signal to the first control node N1 via the second light emission control line Hf, under the control of the potential of the third control node N3.

[0058] Selectively, the first write control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second write control circuit includes a second transistor. The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node. The first electrode plate of the first capacitance is electrically connected to the second control node, and the second electrode plate of the first capacitance is electrically connected to the first initial voltage line. The gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light emission control line, and the second pole of the second transistor is electrically connected to the first control node.

[0059] Selectively, the third write control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth write control circuit includes a fourth transistor. The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node. The first electrode plate of the second capacitance is electrically connected to the third control node, and the second electrode plate of the second capacitance is electrically connected to the second initial voltage line. The gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

[0060] The pixel circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control circuit, The second light emission control circuit is electrically connected to the first light emission control line, the power supply voltage line, and the second end of the drive circuit, respectively, and is used to control the power supply voltage line and the second end of the drive circuit to conduct electricity under the control of the first light emission control signal.

[0061] In actual implementation, the pixel circuit may further include a second light emission control circuit, which controls the connection between the power supply voltage line and the second end of the drive circuit under the control of the first light emission control signal.

[0062] The pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit, and a third energy storage circuit. The data writing circuit is electrically connected to the scan line, the data line, and the second end of the drive circuit, respectively, and is for writing the display data voltage supplied from the data line to the second end of the drive circuit under the control of the scan signal supplied from the scan line. The compensation control circuit is electrically connected to the scan line, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively, and is for controlling the control of the scan signal so that conductivity is established between the control terminal of the drive circuit and the first terminal of the drive circuit. The third energy storage circuit is electrically connected to the control terminal of the drive circuit and is for storing electrical energy.

[0063] In specific implementations, the pixel circuit may further include a data writing circuit, a compensation control circuit, and a third energy storage circuit. The data writing circuit writes the display data voltage to the second end of the drive circuit under the control of a scanning signal, and the compensation control circuit performs threshold voltage compensation control by controlling the connection between the control end of the drive circuit and the first end of the drive circuit under the control of a scanning signal.

[0064] A pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit, The first reset circuit is electrically connected to the third reset control line, the third initial voltage line, and the control terminal of the drive circuit, respectively, and is used to write the third initial voltage supplied from the third initial voltage line to the control terminal of the drive circuit under the control of the third reset control signal supplied from the third reset control line.

[0065] In specific implementation, the pixel circuit may further include a first reset circuit. The first reset circuit, under the control of the third reset control signal, writes the third initial voltage to the control terminal of the drive circuit, thereby enabling the drive transistor included in the drive circuit to be turned on at the start of the charge compensation stage.

[0066] The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit, The second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line, and the first pole of the light-emitting element, respectively, and is used to write the fourth initial voltage supplied from the fourth initial voltage line to the first pole of the light-emitting element under the control of the fourth reset control signal supplied from the fourth reset control line. The second pole of the light-emitting element is electrically connected to the first voltage line.

[0067] Selectively, the first voltage line may be a low-voltage line, but is not limited to this.

[0068] In actual implementation, the pixel circuit may further include a second reset circuit, which, under the control of a fourth reset control signal, writes a fourth initial voltage to the first pole of the light-emitting element to control the light-emitting element so that it does not emit light and clears the residual charge of the first pole of the light-emitting element.

[0069] Selectively, the third reset control line is either the first reset control line or the second reset control line. The fourth reset control line is either the first reset control line or the second reset control line.

[0070] In at least one embodiment of the present disclosure, the third reset control line may be the first reset control line or the second reset control line, and the fourth reset control line may be the first reset control line or the second reset control line, thereby reducing the number of control lines used.

[0071] As shown in Figure 3, in addition to the at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit described in at least one embodiment of the present disclosure may further include a second light emission control circuit 31, a compensation control circuit 33, a third energy storage circuit 34, a first reset circuit 35, and a second reset circuit 36. The second light emission control circuit 31 is electrically connected to the first light emission control line E1, the power supply voltage line VDD, and the second end of the drive circuit 10, respectively, and controls the connection between the power supply voltage line VDD and the second end of the drive circuit 10 under the control of the first light emission control signal supplied from the first light emission control line E1. The compensation control circuit 33 is electrically connected to the scan line G1, the control terminal of the drive circuit 10, and the first terminal of the drive circuit 10, respectively, and is for controlling the control of the scan signal so that the control terminal of the drive circuit 10 and the first terminal of the drive circuit 10 are electrically connected. The third energy storage circuit 34 is electrically connected to the control terminal of the drive circuit 10 and is for storing electrical energy.

[0072] The first reset circuit 35 is electrically connected to the first reset control line RA, the third initial voltage line I3, and the control terminal of the drive circuit 10, respectively, and is used to write the third initial voltage supplied from the third initial voltage line I3 to the control terminal of the drive circuit 10 under the control of the first reset control signal supplied from the first reset control line RA. The second reset circuit 36 ​​is electrically connected to the first reset control line RA, the fourth initial voltage line I4, and the first pole of the light-emitting element E0, respectively, and is used to write the fourth initial voltage supplied from the fourth initial voltage line I4 to the first pole of the light-emitting element E0 under the control of the first reset control signal supplied from the first reset control line RA. The second pole of the light-emitting element E0 is electrically connected to the first voltage line.

[0073] In at least one embodiment shown in Figure 3, the third reset control line is the first reset control line, and the fourth reset control line is the first reset control line.

[0074] In actual implementation, the third reset control line and the fourth reset control line may both be the second reset control line, or the third reset control line may be the first reset control line and the fourth reset control line may be the second reset control line, or the third reset control line may be the second reset control line and the fourth reset control line may be the first reset control line.

[0075] In at least one embodiment of the present disclosure, the first initial voltage line, the second initial voltage line, the third initial voltage line, and the fourth initial voltage line may be the same initial voltage line, thereby reducing the number of initial voltage lines used.

[0076] Selectively, the second light-emitting control circuit includes a fifth transistor. The gate of the fifth transistor is electrically connected to the first light emission control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second terminal of the drive circuit.

[0077] Selectively, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor, and the drive circuit includes a drive transistor. The gate of the sixth transistor is electrically connected to the scan line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the drive transistor. The gate of the seventh transistor is electrically connected to the scan line, the first pole of the seventh transistor is electrically connected to the gate of the drive transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the drive transistor. The first electrode plate of the third capacitor is electrically connected to the gate of the drive transistor, and the second electrode plate of the third capacitor is electrically connected to the power supply voltage line.

[0078] Selectively, the first reset circuit includes an eighth transistor, The gate of the eighth transistor is electrically connected to the third reset control line, the first pole of the eighth transistor is electrically connected to the third initial voltage line, and the second pole of the eighth transistor is electrically connected to the control terminal of the drive circuit.

[0079] Selectively, the second reset circuit includes a ninth transistor, The gate of the ninth transistor is electrically connected to the fourth reset control line, the first pole of the ninth transistor is electrically connected to the fourth initial voltage line, and the second pole of the ninth transistor is electrically connected to the first pole of the light-emitting element.

[0080] As shown in Figure 4, in addition to at least one embodiment of the pixel circuit shown in Figure 3, the first write control circuit includes a first transistor M1, the first energy storage circuit includes a first capacitor C1, and the second write control circuit includes a second transistor M2. The gate of the first transistor M1 is electrically connected to the first reset control line RA, the source of the first transistor M1 is electrically connected to the data line DT, and the drain of the first transistor M1 is electrically connected to the second control node N2. The first plate of the first capacitor C1 is electrically connected to the second control node N2, and the second plate of the first capacitor C1 is electrically connected to the initial voltage line I0, which is for supplying the initial voltage Vinit. The gate of the second transistor M2 is electrically connected to the second control node N2, the source of the second transistor M2 is electrically connected to the first light emission control line E1, and the drain of the second transistor M2 is electrically connected to the first control node N1. The third write control circuit includes a third transistor M3, the second energy storage circuit includes a second capacitor C2, and the fourth write control circuit includes a fourth transistor M4. The gate of the third transistor M3 is electrically connected to the second reset control line RB, the source of the third transistor M3 is electrically connected to the data line DT, and the drain of the third transistor M3 is electrically connected to the third control node N3. The first plate of the second capacitor C2 is electrically connected to the third control node N3, and the second plate of the second capacitor C2 is electrically connected to the initial voltage line I0. The gate of the fourth transistor M4 is electrically connected to the third control node N3, the source of the fourth transistor M4 is electrically connected to the second light emission control line Hf, and the drain of the fourth transistor M4 is electrically connected to the first control node N1. The second light-emitting control circuit includes a fifth transistor M5, The gate of the fifth transistor M5 is electrically connected to the first light emission control line E1, the source of the fifth transistor M5 is electrically connected to the power supply voltage line VDD, and the drain of the fifth transistor M5 is electrically connected to the source of the drive transistor M0. The data writing circuit includes a sixth transistor M6, the compensation control circuit includes a seventh transistor M7, the third energy storage circuit includes a third capacitor C3, and the drive circuit includes a drive transistor M0. The gate of the sixth transistor M6 is electrically connected to the scan line G1, the source of the sixth transistor M6 is electrically connected to the data line DT, and the drain of the sixth transistor M6 is electrically connected to the drain of the drive transistor M0. The gate of the seventh transistor M7 is electrically connected to the scan line G1, the source of the seventh transistor M7 is electrically connected to the gate of the drive transistor M0, and the drain of the seventh transistor M7 is electrically connected to the drain of the drive transistor M0. The first plate of the third capacitor C3 is electrically connected to the gate of the drive transistor M0, and the second plate of the third capacitor C3 is electrically connected to the power supply voltage line VDD. The first reset circuit includes the eighth transistor M8, The gate of the eighth transistor M8 is electrically connected to the first reset control line RA, the source of the eighth transistor M8 is electrically connected to the initial voltage line I0, and the drain of the eighth transistor M8 is electrically connected to the gate of the drive transistor M0. The second reset circuit includes the ninth transistor M9, The gate of the ninth transistor M9 is electrically connected to the first reset control line RA, the source of the ninth transistor M9 is electrically connected to the initial voltage line I0, and the drain of the ninth transistor M9 is electrically connected to the anode of the microlight-emitting diode ML. The cathode of the microlight-emitting diode ML is electrically connected to the low-voltage line VSS. The first light-emitting control circuit includes a tenth transistor M10, The gate of M10 is electrically connected to the first control node N1, the source of M10 is electrically connected to the drain of M0, and the drain of M10 is electrically connected to the anode of ML.

[0081] In at least one embodiment of the pixel circuit shown in Figure 4, all transistors are p-type transistors, but are not limited to p-type transistors.

[0082] In at least one embodiment of the pixel circuit shown in Figure 4, the light-emitting element is a microlight-emitting diode ML, but is not limited thereto.

[0083] In at least one embodiment of the pixel circuit shown in Figure 4, the gate of M8 may be electrically connected to the second reset control line RB, in which case, during the second writing stage S2, the potential of the gate of M0 is initialized when M8 is turned on.

[0084] In at least one embodiment of the pixel circuit shown in Figure 4, time-division writing of the display data voltage, first control voltage, and second control voltage is realized by separating the gate signal of M6, the gate signal of M1, and the gate signal of M3, and the first control voltage and the second control voltage may be light emission time control data voltages.

[0085] As shown in Figure 5, during the operation of at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure, the display cycle includes a first write stage S1, a second write stage S2, a charge compensation stage S3, and a light emission stage S4, which are set in order. In the first writing stage S1, RA supplies a low voltage signal, RB supplies a high voltage signal, G1 supplies a high voltage signal, EM and Hf supply high voltage signals, DT supplies the first control voltage, and M1 is turned on, writing the first control voltage Data_T1 to the second control node N2. When performing medium-to-high grayscale display, the first control voltage is a low voltage signal, and M2 is turned on, controlling the circuit between E1 and the first control node N1 to conduct. When performing low grayscale display, the first control voltage is a high voltage signal, M2 is turned off, and the potential of the second control node N2 is maintained by C1. In the first writing stage S1, RA supplies a low voltage signal, M8 and M9 turn on, and I0 supplies the initial voltage Vinit to the gate of M0 and the anode of ML, so that at the start of the charge compensation stage, M0 can be turned on, ML is controlled not to emit light, and the residual charge on the anode of ML is cleared. In the second writing stage S2, RA supplies a high-voltage signal, RB supplies a low-voltage signal, G1 supplies a high-voltage signal, EM and Hf supply high-voltage signals, DT supplies the second control voltage, and M3 is turned on, writing the second control voltage Data_T2 to the third control node N3. When performing medium-to-high grayscale display, the second control voltage is a high-voltage signal and M4 is turned off. When performing low-grayscale display, the second control voltage is a low-voltage signal and M4 is turned on, controlling the connection between Hf and N1 to conduct, and C2 maintains the potential of the third control node N3. In charge compensation stage S3, RA supplies a high voltage signal, RB supplies a high voltage signal, G1 supplies a low voltage signal, EM and Hf supply high voltage signals, DT supplies the display data voltage Data_I, M6 and M7 are turned on, the display data voltage Data_I is written to the source of M0, and conduction is established between the gate and drain of M3. At the start of charge compensation stage S3, M0 is turned on, and C3 is charged via the turned-on M0 and M7 by the displayed data voltage Data_I until M0 is turned off. At this time, the gate potential of M0 becomes Data_I + Vth, where Vth is the threshold voltage of M0. During the light emission stage S4, EM supplies a low voltage signal, and for a portion of the period included in the light emission stage S4, Hf supplies a low voltage signal. When performing medium-to-high gradation display, N1 and EM are electrically connected, and in the light emission stage S4, M3 drives ML to emit light. When low-gradation display is performed, N1 and Hf are connected, and when Hf outputs a low-voltage signal, M3 drives ML to emit light.

[0086] As shown in Figure 5, the low-level pulse width of the first reset control signal supplied from RA, the low-level pulse width of the second reset control signal supplied from RB, and the low-level pulse width of the scanning signal supplied from G1 are all equal. Therefore, the first reset control signal, the second reset control signal, and the scanning signal can all be supplied by a single GOA (Gate On Array) circuit. As a result, the number of GOA circuits used is reduced, making it easier to achieve a narrow bezel.

[0087] In at least one embodiment of the present disclosure, the low-level pulse width of the first reset control signal supplied from RA, the low-level pulse width of the second reset control signal supplied from RB, and the low-level pulse width of the scan signal supplied from G1 are adjustable and do not have to match.

[0088] In at least one embodiment of the present disclosure, the low-level pulse width of the scanning signal supplied from G1 may be 2 μs or more in order to enable sufficient charge and threshold voltage compensation.

[0089] Figure 6 is an operation timing chart of at least one embodiment of the pixel circuit shown in Figure 4. Figure 6 differs from Figure 5 in that the low-level pulse width of the scan signal supplied from G1 is longer, the low-level pulse width of the scan signal supplied from G1 is greater than the low-level pulse width of the first reset control signal supplied from RSTA, and the low-level pulse width of the scan signal supplied from G1 is greater than the low-level pulse width of the second reset control signal supplied from RSTB. Thus, the charge compensation time is increased, enabling sufficient threshold voltage compensation.

[0090] As shown in Figure 6, the low-level pulse width of the first reset control signal is the same as the low-level pulse width of the second reset control signal, and the low-level pulse width of the scan signal is greater than the low-level pulse width of the first reset control signal. The nth stage GOA circuit of the first GOA module may supply the first reset control signal, the (n+1)th stage GOA circuit of the first GOA module may supply the second reset control signal, and the mth stage GOA circuit in the second GOA module may supply the scan signal. n and m are positive integers.

[0091] In at least one embodiment shown in Figure 6, the first reset control signal supplied from RA may be replaced with the second reset control signal supplied from RB.

[0092] As shown in Figure 7, during the operation of at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure, the display cycle includes a first write stage S1, a second write stage S2, a charge compensation stage S3, and a light emission stage S4, which are set in order. In the first writing stage S1, RA supplies a high-voltage signal, RB supplies a low-voltage signal, G1 supplies a high-voltage signal, EM and Hf supply high-voltage signals, DT supplies the first control voltage Data_T1, M1 is turned off, M3 is turned on, DT supplies the first control voltage Data_T1 to the third control node N3, C2 maintains the potential of the third control node N3, when performing medium-to-high grayscale display, the first control voltage Data_T1 is a high-voltage signal, when performing low-grayscale display, the first control voltage Data_T1 is a low-voltage signal, M4 is turned on, and conduction occurs between the first control node N1 and Hf. In the second writing stage S2, RA supplies a low voltage signal, RB supplies a high voltage signal, G1 supplies a high voltage signal, EM and Hf supply high voltage signals, DT supplies the second control voltage Data_T2, M1 turns on, M3 turns off, DT supplies the second control voltage Data_T2 to the second control node N2, C1 maintains the potential of the second control node N2, and when performing medium-to-high grayscale display, the second control voltage Data_T2 is a low voltage signal, M2 turns on, conduction occurs between the first control node N1 and E1, and when performing low grayscale display, the second control voltage Data_T2 is a high voltage signal. In charge compensation stage S3, RA supplies a high voltage signal, RB supplies a high voltage signal, G1 supplies a low voltage signal, EM and Hf supply high voltage signals, DT supplies the display data voltage Data_I, M6 and M7 are turned on, the display data voltage Data_I is written to the source of M0, and conduction is established between the gate and drain of M3. At the start of charge compensation stage S3, M0 is turned on, and C3 is charged via the turned-on M0 and M7 by the displayed data voltage Data_I until M0 is turned off. At this time, the gate potential of M0 becomes Data_I + Vth, where Vth is the threshold voltage of M0. During the light emission stage S4, EM supplies a low voltage signal, and for a portion of the period included in the light emission stage S4, Hf supplies a low voltage signal. When performing medium-to-high gradation display, N1 and EM are electrically connected, and in the light emission stage S4, M3 drives ML to emit light. When low-gradation display is performed, N1 and Hf are connected, and when Hf outputs a low-voltage signal, M3 drives ML to emit light.

[0093] In Figure 7, the low-level pulse width of the scan signal supplied from G1 is greater than the low-level pulse width of the first reset control signal, and is also greater than the low-level pulse width of the second reset control signal. As a result, the duration of the charge compensation phase is longer, allowing for sufficient compensation for the threshold voltage of the drive transistor. In actual operation, the low-level pulse width of the scan signal supplied from G1, the low-level pulse width of the first reset control signal, and the low-level pulse width of the second reset control signal may be equal.

[0094] In at least one embodiment of this design, the low-level pulse width of the scanning signal, the low-level pulse width of the first reset control signal, and the low-level pulse width of the second reset control signal may be equal. The second reset control signal may be supplied by the nth stage GOA circuit of the first GOA module, the first reset control signal may be supplied by the (n+1)th stage GOA circuit of the first GOA module, and the scanning signal may be supplied by the (n+2)th stage GOA circuit of the first GOA module. In this way, the number of GOA modules used is reduced, making it easier to achieve a narrow bezel, where n is a positive integer.

[0095] At least one embodiment of the pixel circuit shown in Figure 8A of this disclosure differs from at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure in that both the gate of M8 and the gate of M9 are electrically connected to the second reset control line RB.

[0096] The pixel circuit described in at least one embodiment of the present disclosure further includes a multiplexing control circuit, The multiplexing control circuit is electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver, and the data line, respectively, and controls the connection between the voltage output terminal and the data line to be conductive under the control of the multiplexing control signal supplied from the multiplexing control terminal.

[0097] In specific implementations, the pixel circuit may further include a multiplexing control circuit that controls the voltage output terminals of the source driver to be electrically connected to the data lines under the control of a multiplexing control signal, thereby reducing the number of voltage output terminals of the source driver.

[0098] As shown in Figure 8B, in addition to the at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit described in at least one embodiment of the present disclosure may further include a multiplexing control circuit 80. The multiplexing control circuit 80 is electrically connected to the multiplexing control terminal MX, the voltage output terminal CH of the source driver SD, and the data line DT, respectively, and controls the voltage output terminal CH and the data line DT to conduct under the control of the multiplexing control signal supplied from the multiplexing control terminal MX.

[0099] The driving method described in the embodiments of this disclosure is applied to the above-mentioned pixel circuit, and the display stage includes a first writing stage and a second writing stage, and the driving method is In the first writing stage, the first control circuit, under the control of the first reset control signal, supplies a first control voltage supplied from the data line to the second control node, and the first control circuit, under the control of the potential of the second control node, controls whether or not to supply a first light emission control signal to the first control node. The second writing stage includes the second control circuit writing the second control voltage supplied from the data line to the third control node under the control of the second reset control signal, and the second control circuit controlling whether to supply the second light emission control signal to the first control node under the control of the potential of the third control node.

[0100] The driving method described in at least one embodiment of this disclosure is When performing medium-to-high gradation display, in the first writing stage, the first control circuit controls the supply of the first light emission control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the supply of the second light emission control signal to the first control node to be stopped under the control of the potential of the third control node. When performing low-gradation display, the first writing step includes controlling the supply of the first light emission control signal to the first control node to be stopped under the control of the potential of the second control node, and the second writing step includes controlling the supply of the second light emission control signal to the first control node under the control of the potential of the third control node.

[0101] The display substrate described in the embodiment of this disclosure includes a base substrate and the above-mentioned pixel circuits arranged in multiple rows and multiple columns within a display area on the base substrate.

[0102] In at least one embodiment of the present disclosure, pixel circuits located in the same row are provided between two rows of data lines, the data lines extending along a first direction, The pixel circuit of row a is provided between the scan line of row a and the first voltage line of row a, where a is a positive integer. The scan line of row a and the first voltage line of row a extend along the second direction, The first direction intersects with the second direction.

[0103] Selectively, the first direction may be vertical, and the second direction may be horizontal, but is not limited to these two.

[0104] In related technologies, two rows of data lines are provided between two adjacent rows of pixel circuits, with one row of data lines supplying the emission time data voltage and the other row of data lines supplying the display data voltage. In contrast, in at least one embodiment of this disclosure, only one row of data lines is provided between two adjacent rows of pixel circuits.

[0105] Figure 9 is a layout diagram of at least one embodiment of the pixel circuit shown in Figure 4. Figure 10 is a layout diagram of the first gate metal layer in Figure 9, Figure 11 is a layout diagram of the semiconductor layer in Figure 9, Figure 12 is a layout diagram of the second gate metal layer in Figure 9, and Figure 13 is a layout diagram of the source-drain metal layer in Figure 9.

[0106] In at least one embodiment of the present disclosure, the first gate metal layer, the semiconductor layer, the second gate metal layer, and the source-drain metal layer may be arranged sequentially along a direction away from the base substrate.

[0107] As shown in Figure 9, code VSS is the low-voltage line, code DT is the data line, code I0 is the initial voltage line, code RA is the first reset control line, code RB is the second reset control line, code E1 is the first light emission control line, and code G1 is the scan line.

[0108] In at least one embodiment shown in Figure 9, the second light emission control line Hf may include a first light emission control line section Hf1 extending in the vertical direction and a second light emission control line section Hf2 extending in the horizontal direction, which are electrically connected to each other.

[0109] As shown in Figure 9, VSS, I0, RB, RA, E1, VDD, and G1 all extend along the horizontal direction. DT extends along the vertical direction, The first capacity C1 and the second capacity C2 are provided between VSS and I0. M3 is located between RB and I0. M1, M8, M9, M4, and M2 are all located between RA and VDD. C3, M5, M10, M6, M0, and M7 are all provided between E1 and G1.

[0110] In Figure 10, the symbol C2b1 is the first electrode plate portion of the second capacitance, the symbol C1b1 is the first electrode plate portion of the first capacitance, the symbol C3b1 is the first electrode plate portion of the third capacitance, and the symbol G0a is the bottom gate of M0.

[0111] In Figure 11, code A0 is the active pattern for M0, code A1 is the active pattern for M1, code A2 is the active pattern for M2, code A3 is the active pattern for M3, code A4 is the active pattern for M4, code A5 is the active pattern for M5, code A6 is the active pattern for M6, code A7 is the active pattern for M7, code A8 is the active pattern for M8, code A9 is the active pattern for M9, and code A10 is the active pattern for M10.

[0112] In Figure 12, the symbol G0b is the top gate of G0, the symbol C1a is the first electrode plate of the first capacitance, the symbol C2a is the first electrode plate of the second capacitance, and the symbol C3a is the first electrode plate of the third capacitance.

[0113] In Figure 13, the symbol C2b2 represents the second electrode plate portion of the second capacitance, the symbol C1b2 represents the second electrode plate portion of the first capacitance, and the symbol C3b2 represents the second electrode plate portion of the third capacitance.

[0114] In at least one embodiment shown in Figures 9 to 13, C1b1 is electrically connected to C1b2, and C1b1 and C1b2 constitute the second electrode plate of C1; C2b1 is electrically connected to C2b2, and C2b1 and C2b2 constitute the second electrode plate of C2; C3b1 is electrically connected to C3b2, and C3b1 and C3b2 constitute the second electrode plate of C3.

[0115] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit, A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided within the gap. The orthographic projection of the light-emitting element on the base substrate does not overlap with the orthographic projection of the pixel driving circuit on the base substrate.

[0116] In specific implementation, a gap is provided between at least two adjacent pixel driving circuits in the second direction, at least one light-emitting element is provided within the gap, and the light-emitting element and the pixel driving circuit do not overlap in a direction perpendicular to the base substrate.

[0117] Selectively, the second direction may be horizontal, but is not limited to this.

[0118] In at least one embodiment of the present disclosure, the light-emitting element may be provided in the gap between the pixel driving circuits, so that the light-emitting element and the pixel driving circuits do not affect each other.

[0119] A display board according to at least one embodiment of the present disclosure further includes a first signal line, the majority of which is included in the first signal line extends along a second direction. The first signal line is bent around the light-emitting element to form a first retraction space, and at least a portion of the light-emitting element is provided within the first retraction space.

[0120] In actual implementation, the display board may further include a first signal line, and the first signal line is bent around the light-emitting element to form a first retraction space, thereby enabling the light-emitting element to be provided within the first retraction space.

[0121] In at least one embodiment of the present disclosure, the majority of the signal line portion within the first signal line extends horizontally, and the first signal line is bent downward or upward around the light-emitting element to form a first retraction space, thereby facilitating the layout of the light-emitting element.

[0122] Selectively, the first signal line may include a low-voltage line, an initial voltage line, a first reset control line, a second reset control line, a first light emission control line, and a scan line.

[0123] A display substrate according to at least one embodiment of the present disclosure includes a plurality of rows of light-emitting units, the light-emitting units including at least three of the light-emitting elements, At least one of the first signal lines is bent to the first side around at least one of the light-emitting elements in an odd-numbered row of light-emitting units to form a first retractable space. At least one of the first signal lines is bent to the second side around at least one of the light-emitting elements in an even row of light-emitting units to form another first retractable space. The first side and the second side are opposing sides.

[0124] Selectively, the first side may be the lower side and the second side the upper side, or the first side may be the upper side and the second side the lower side, but is not limited to these arrangements.

[0125] As shown in Figure 14A, the display substrate according to at least one embodiment of the present disclosure may include a light-emitting unit in the first row and first column, a light-emitting unit in the first row and second column, a light-emitting unit in the first row and third column, a light-emitting unit in the first row and fourth column, a light-emitting unit in the first row and fifth column, a light-emitting unit in the first row and sixth column, a light-emitting unit in the second row and first column, a light-emitting unit in the second row and second column, a light-emitting unit in the second row and third column, a light-emitting unit in the second row and fourth column, a light-emitting unit in the second row and fifth column, a light-emitting unit in the third row and sixth column, a light-emitting unit in the third row and first column, a light-emitting unit in the third row and second column, a light-emitting unit in the third row and third column, a light-emitting unit in the third row and fourth column, a light-emitting unit in the third row and fifth column, and a light-emitting unit in the third row and sixth column. The light-emitting unit in the first row and first column includes, from top to bottom, a blue light-emitting element B11 in the first row and first column, a green light-emitting element G11 in the first row and first column, and a red light-emitting element R11 in the first row and first column. The light-emitting unit in the first row and second column includes, from top to bottom, a blue light-emitting element B12 in the first row and second column, a green light-emitting element G12 in the first row and second column, and a red light-emitting element R12 in the first row and second column. The light-emitting unit in the first row, third column includes, from top to bottom, a blue light-emitting element B13 in the first row, third column, a green light-emitting element G13 in the first row, third column, and a red light-emitting element R13 in the first row, third column. The light-emitting unit in the first row, fourth column includes, from top to bottom, a blue light-emitting element B14 in the first row, fourth column, a green light-emitting element G14 in the first row, fourth column, and a red light-emitting element R14 in the first row, fourth column. The light-emitting unit in the second row and fifth column includes, from top to bottom, a blue light-emitting element B25 in the second row and fifth column, a green light-emitting element G25 in the second row and fifth column, and a red light-emitting element R25 in the second row and fifth column. The light-emitting unit in the second row and sixth column includes, from top to bottom, a blue light-emitting element B26 in the second row and sixth column, a green light-emitting element G26 in the second row and sixth column, and a red light-emitting element R26 in the second row and sixth column. The light-emitting unit in the second row, first column includes, from top to bottom, a blue light-emitting element B21 in the second row, first column, a green light-emitting element G21 in the second row, first column, and a red light-emitting element R21 in the second row, first column. The light-emitting unit in the second row and second column includes, from top to bottom, a blue light-emitting element B22 in the second row and second column, a green light-emitting element G22 in the second row and second column, and a red light-emitting element R22 in the second row and second column. The light-emitting unit in the second row and third column includes, from top to bottom, a blue light-emitting element B23 in the second row and third column, a green light-emitting element G23 in the second row and third column, and a red light-emitting element R23 in the second row and third column. The light-emitting unit in the second row and fourth column includes, from top to bottom, a blue light-emitting element B24 in the second row and fourth column, a green light-emitting element G24 in the second row and fourth column, and a red light-emitting element R24 in the second row and fourth column. The light-emitting unit in the second row and fifth column includes, from top to bottom, a blue light-emitting element B25 in the second row and fifth column, a green light-emitting element G25 in the second row and fifth column, and a red light-emitting element R25 in the second row and fifth column. The light-emitting unit in the second row and sixth column includes, from top to bottom, a blue light-emitting element B26 in the second row and sixth column, a green light-emitting element G26 in the second row and sixth column, and a red light-emitting element R26 in the second row and sixth column. In Figure 14A, code P1 is the first pixel drive unit, code P2 is the second pixel drive unit, code P3 is the third pixel drive unit, code P4 is the fourth pixel drive unit, code P5 is the fifth pixel drive unit, code P6 is the sixth pixel drive unit, code P7 is the seventh pixel drive unit, code P8 is the eighth pixel drive unit, and code P9 is the ninth pixel drive unit. Each pixel drive unit includes at least one pixel drive circuit. Code VSS is the low-voltage line, code I0 is the initial voltage line, code RB is the second reset control line, code RA is the first reset control line, code VDD is the power supply voltage line, code E1 is the first light emission control line, code G1 is the scan line. VSS, I0, RA, E1, and G1 may be formed in the first gate metal layer. RB and VDD may be formed in the second gate metal layer. The majority of the low-voltage lines in VSS, the majority of the initial voltage lines in I0, the majority of the second reset control lines in RB, the majority of the first reset control lines in RA, the majority of the power supply voltage lines in VDD, the majority of the first light emission control lines in E1, and the majority of the scanning lines in G1 all extend horizontally. R11, G11, B11, R21, G21, and B21 are provided in the gap on the left side of the first pixel drive unit. R12, G12, B12, R22, G22, and B22 are provided in the gap between the second pixel drive unit and the third pixel drive unit. R13, G13, B13, R23, G23, and B23 are provided in the gap between the third pixel drive unit and the fourth pixel drive unit. R14, G14, B14, R24, G24, and B24 are provided in the gap between the fifth pixel drive unit and the sixth pixel drive unit. R15, G15, B15, R25, G25, and B25 are provided in the gap between the sixth pixel drive unit and the seventh pixel drive unit. R16, G16, B16, R26, G26, and B26 are provided in the gap between the eighth pixel drive unit and the ninth pixel drive unit. The orthographic projection of each light-emitting element on the base substrate does not overlap with the orthographic projection of the pixel driving circuit included in each pixel driving unit on the base substrate.

[0126] In at least one embodiment of the present disclosure, each light-emitting element may be an LED (light-emitting diode).

[0127] Figure 14B is a layout diagram of the first gate metal layer in Figure 14A, and Figure 14C is a schematic diagram of the signal lines and the positions of each light-emitting element provided on the first gate metal layer in Figure 14A.

[0128] As shown in Figure 14B, in order to position R11, the initial voltage line I0 is bent downward to form the first retraction space A11, and as shown in Figure 14C, a portion of R11 is provided within A11. As shown in Figure 14B, in order to position R12, the initial voltage line I0 is bent downward to form a second first retraction space A21, and as shown in Figure 14C, a portion of R12 is provided within A21. As shown in Figure 14B, in order to position R13, the initial voltage line I0 is bent downward to form a third first retraction space A31, and as shown in Figure 14C, a portion of R13 is provided within A31. As shown in Figure 14B, to position R14, the initial voltage line I0 is bent downwards to form a fourth first retraction space A41, and as shown in Figure 14C, a portion of R14 is provided within A41. As shown in Figure 14B, in order to position R15, the initial voltage line I0 is bent downward to form a fifth first retraction space A51, and as shown in Figure 14C, a portion of R15 is provided within A51. As shown in Figure 14B, in order to position R16, the initial voltage line I0 is bent downward to form a sixth first retraction space A61, and as shown in Figure 14C, a portion of R16 is provided within A61. As shown in Figure 14B, in order to position B21, the first light-emitting control line E1 is bent upward to form the seventh first retractable space A71, and as shown in Figure 14C, a portion of B21 is provided within A71. As shown in Figure 14B, in order to position B22, the first light-emitting control line E1 is bent upward to form the eighth first retractable space A81, and as shown in Figure 14C, a portion of B22 is provided within A81. As shown in Figure 14B, in order to position B23, the first light-emitting control line E1 is bent upward to form the ninth first retractable space A91, and as shown in Figure 14C, a portion of B23 is provided within A91. As shown in Figure 14B, in order to position B24, the first light-emitting control line E1 is bent upward to form the tenth first retractable space A101, and as shown in Figure 14C, a portion of B24 is provided within A101. As shown in Figure 14B, in order to position B25, the first light-emitting control line E1 is bent upward to form the eleventh first retractable space A111, and as shown in Figure 14C, a portion of B25 is provided within A111. As shown in Figure 14B, in order to position B26, the first light emission control line E1 is bent upward to form the twelfth first retraction space A121, and as shown in Figure 14C, a portion of B26 is provided within A121.

[0129] In at least one embodiment of the present disclosure, each light-emitting element may be provided between each pixel driving unit, and each pixel driving unit may include at least one pixel driving circuit. Selectively, the display board may include a second signal line. Most of the signal line portion included in the second signal line extends along the first direction, The second signal line is bent around the light-emitting element to form a fourth retraction space, and at least a portion of the light-emitting element is provided within the fourth retraction space.

[0130] In actual implementation, the display board may include a second signal line that extends mostly along the vertical direction, and the second signal line may be bent around the light-emitting element to form a fourth retraction space, thus facilitating the placement of the light-emitting element.

[0131] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit, The light-emitting element is provided on the side of the pixel driving circuit that is farther from the base substrate, The orthographic projection of the light-emitting element on the base substrate overlaps, at least partially, with the orthographic projection of the pixel driving circuit on the base substrate.

[0132] In specific implementations, the pixel driving circuit is provided between the light-emitting element and the base substrate, and the orthographic projection of the light-emitting element on the base substrate may at least partially overlap with the orthographic projection of the pixel driving circuit on the base substrate.

[0133] As shown in Figure 15, code P1 is the first pixel drive unit, P1 includes multiple pixel driving circuits, Code B11 is the blue light-emitting element in the first row, first column; code G11 is the green light-emitting element in the first row, first column; code R11 is the red light-emitting element in the first row, first column; Code B12 is the blue light-emitting element in the first row, second column; code G12 is the green light-emitting element in the first row, second column; code R12 is the red light-emitting element in the first row, second column; Code B13 is the blue light-emitting element in the first row, third column; code G13 is the green light-emitting element in the first row, third column; code R13 is the red light-emitting element in the first row, third column; Code B14 is the blue light-emitting element in the first row, fourth column; code G14 is the green light-emitting element in the first row, fourth column; code R14 is the red light-emitting element in the first row, fourth column; Code B21 is the blue light-emitting element in the second row, first column; code G21 is the green light-emitting element in the second row, first column; code R21 is the red light-emitting element in the second row, first column; Code B22 is the blue light-emitting element in the second row and second column, code G22 is the green light-emitting element in the second row and second column, code R22 is the red light-emitting element in the second row and second column, Code B23 is the blue light-emitting element in the second row, third column; code G23 is the green light-emitting element in the second row, third column; code R23 is the red light-emitting element in the second row, third column; Code B24 is the blue light-emitting element in the second row and fourth column, code G24 is the green light-emitting element in the second row and fourth column, and code R24 is the red light-emitting element in the second row and fourth column. The orthographic projection of R11 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G11 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B11 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate. The orthographic projection of R12 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G12 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B12 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate. The orthographic projection of R13 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G13 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B13 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate. The orthographic projection of R14 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate, the orthographic projection of G14 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate, and the orthographic projection of B14 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate. The orthographic projection of R21 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G21 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B21 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate. The orthographic projection of R22 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate, the orthographic projection of G22 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate, and the orthographic projection of B22 on the base substrate overlaps at least partially with the orthographic projection of P1 on the base substrate. The orthographic projection of R23 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G23 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B23 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate. The orthographic projection of R24 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, the orthographic projection of G24 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate, and the orthographic projection of B24 on the base substrate at least partially overlaps with the orthographic projection of P1 on the base substrate.

[0134] In at least one embodiment shown in Figure 15, a pixel drive group is formed by a first pixel drive unit, R11, G11, B11, R12, G12, B12, R13, G13, B13, R14, G14, B14, R21, G21, B21, R22, G22, B22, R23, G23, B23, R24, G24, and B14.

[0135] A display board according to at least one embodiment of the present disclosure further includes a light-emitting control signal generation module and a second signal line, the light-emitting control signal generation module includes a plurality of stages of light-emitting control signal generation circuits, the light-emitting control signal generation circuits are provided in the display area, The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. At least one stage of the light emission control signal generation circuit is located between adjacent pixel drive groups, Most of the signal line portion included in the second signal line extends along the first direction, At least one of the second signal lines is bent around the at least one stage of the light emission control signal generation circuit to form a second retractable space, and a portion of the at least one stage of the light emission control signal generation circuit is provided within the second retractable space.

[0136] In specific implementations, at least one stage of light emission control signal generation circuit included in the light emission control signal generation module is located between adjacent pixel drive groups, and at least one second signal line is bent around the at least one stage of light emission control signal generation circuit to form a second retraction space, and a part of the at least one stage of light emission control signal generation circuit may be provided within the second retraction space, thereby facilitating the arrangement of the at least one stage of light emission control signal generation circuit, and the light emission control signal generation circuit may be provided in the display area to facilitate the realization of a narrow bezel.

[0137] In one embodiment of the present disclosure, the orthographic projection of the light emission control signal generation circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

[0138] In actual implementation, the light emission control signal generation circuit and the pixel drive group do not overlap in a direction perpendicular to the base substrate, and thus the light emission control signal generation circuit and the pixel drive group do not influence each other.

[0139] Selectively, the second signal line may include, but is not limited to, a data line and a second light emission control line.

[0140] In at least one embodiment of the present disclosure, the second light emission control line may extend vertically, or the second light emission control line may include a first light emission control line portion extending vertically and a second light emission control line portion extending horizontally.

[0141] In specific implementation, the display board may further include a first signal line, and the majority of the signal line portion included in the first signal line extends along the second direction. At least one of the first signal lines is bent around the at least one stage of the light emission control signal generation circuit to form a fifth retraction space, and a portion of the at least one stage of the light emission control signal generation circuit is provided within the fifth retraction space.

[0142] In actual implementation, the display board may include a first signal line that extends mostly horizontally, and the first signal line may be bent around the light emission control signal generation circuit to form a fifth retraction space, thus facilitating the arrangement of the light emission control signal generation circuit.

[0143] A display board according to at least one embodiment of the present disclosure further includes a gate drive module, the gate drive module includes a plurality of gate drive circuits, the gate drive circuits are provided in the display area, The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. At least one stage of the gate drive circuit is located between adjacent pixel drive groups.

[0144] In actual implementation, at least one gate drive circuit included in the gate drive module is provided between adjacent pixel drive groups, and the gate drive circuit may also be provided in the display area, thus facilitating the realization of a narrow bezel.

[0145] A display board according to at least one embodiment of the present disclosure further includes a second signal line, the majority of which is included in the second signal line extends along a first direction, At least one of the second signal lines is bent around the at least one stage of the gate drive circuit to form a third retraction space, and a portion of the at least one stage of the gate drive circuit is provided within the third retraction space.

[0146] In actual implementation, at least one second signal line is bent around the at least one stage of gate drive circuit to form a third retraction space, and a portion of the at least one stage of gate drive circuit is provided within the third retraction space, thus facilitating the arrangement of the at least one stage of gate drive circuit.

[0147] In at least one embodiment of the present disclosure, the orthographic projection of the gate drive circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

[0148] In actual implementation, the gate drive circuit and the pixel drive group do not overlap in a direction perpendicular to the base substrate, and thus the gate drive circuit and the pixel drive group do not influence each other.

[0149] In at least one embodiment of the present disclosure, the display board may further include a first signal line, the majority of which is part of the first signal line extends along a second direction. At least one of the first signal lines is bent around the at least one stage of the gate drive circuit to form a sixth retraction space, and a portion of the at least one stage of the gate drive circuit is provided within the sixth retraction space.

[0150] In actual implementation, the display board may include a first signal line that extends mostly horizontally, and the first signal line may be bent around the gate drive circuit to form a sixth retraction space, thus facilitating the arrangement of the gate drive circuit.

[0151] As shown in Figure 16, code F11 represents the pixel drive group in the first row and first column, code F12 represents the pixel drive group in the first row and second column, code F13 represents the pixel drive group in the first row and third column. Code F21 represents the pixel drive group in the second row, first column; code F22 represents the pixel drive group in the second row, second column; code F23 represents the pixel drive group in the second row, third column; Code EA1 represents the first stage light emission control signal generation circuit, and code EA2 represents the second stage light emission control signal generation circuit. Code GA1 represents the first-stage gate drive circuit, code GA2 represents the second-stage gate drive circuit, and code GA3 represents the third-stage gate drive circuit. EA1 and EA2 are located between F11, F21, F21 and F22. GA1, GA2, and GA3 are located between F12, F22, F13, and F23.

[0152] In at least one embodiment of the present disclosure, the pixel drive group may include a 2x2 pixel drive circuit, a 2x3 pixel drive circuit, a 2x4 pixel drive circuit, or a 3x3 pixel drive circuit, and the specific values ​​of the number of rows and columns of the pixel drive circuits included in the pixel drive group are not limited. In Figure 16, the code HF1 is the first second light emission control line, the code DT1 is the first data line, the code HF2 is the second second light emission control line, the code DT2 is the second data line, the code HF3 is the third second light emission control line, the code DT3 is the third data line, the code HF4 is the fourth second light emission control line, the code DT4 is the fourth data line, the code HF5 is the fifth second light emission control line, the code DT5 is the fifth data line, the code HF6 is the sixth second light emission control line, the code DT6 is the sixth data line, the code HF7 is the seventh second light emission control line, the code DT7 is the seventh data line, the code HF8 is the eighth second light emission control line, the code DT8 is the eighth data line, the code HF9 is the ninth second light emission control line, the code DT9 is the ninth data line, and the code HF10 is the tenth second These are light emission control lines, where code DT10 is the tenth data line, code HF11 is the eleventh second light emission control line, code DT11 is the eleventh data line, code HF12 is the twelfth second light emission control line, code DT12 is the twelfth data line, code HF13 is the thirteenth second light emission control line, code DT13 is the thirteenth data line, code HF14 is the fourteenth second light emission control line, code DT14 is the fourteenth data line, code HF15 is the fifteenth second light emission control line, code DT15 is the fifteenth data line, code HF16 is the sixteenth second light emission control line, code DT16 is the sixteenth data line, code HF17 is the seventeenth second light emission control line, code DT17 is the seventeenth data line, code HF18 is the eighteenth second light emission control line, code DT18 is the eighteenth data line. As shown in Figure 16, the majority of the second light emission control line portion of each second light emission control line extends along the vertical direction, and the majority of the data line portion included in each data line extends along the vertical direction. EA1 and EA2 are provided between DT6 and HF7. DT6 is bent to the left to form the first second evacuation space A12. HF7 is bent to the right to form a second evacuation space A22. Part of EA1 and part of EA2 are provided within A12, and part of EA1 and part of EA2 are provided within A22. By bending HF6 to the left, bending DT5 to the left, bending HF5 to the left, bending DT4 to the left, and bending HF4 to the left, the distances between HF6 and DT6, DT5 and HF6, HF5 and DT5, DT4 and HF5, and HF4 and DT4 become approximately equal, resulting in a uniform distribution of each signal line. By bending DT7 to the right, HF8 to the right, DT8 to the right, HF9 to the right, DT9 to the right, HF10 to the right, DT10 to the right, HF11 to the right, DT11 to the right, HF12 to the right, and DT12 to the right, the distances between HF7 and DT7, DT7 and HF8, HF8 and DT8, DT8 and HF9, and HF9 and DT9 become approximately equal, resulting in a uniform distribution of each signal line.

[0153] As shown in Figure 17, code GA1 is the first-stage gate drive circuit, code GA2 is the second-stage gate drive circuit, and code GA3 is the third-stage gate drive circuit. GA1, GA2, and GA3 are located between F12, F22, F13, and F23.

[0154] DT12 is bent to the left to form the first third evacuation space A13. HF13 is bent to the right to form the second third evacuation space A23. Parts of GA1, GA2, and GA3 are provided within A13. Parts of GA1, GA2, and GA3 are provided within A23.

[0155] In at least one embodiment of the present disclosure, a third region is provided within the display region on the side closer to the fanout region, and a pixel driving circuit is provided in the third region, but a light emission control signal generation circuit and a gate driving circuit are not provided in it. Therefore, in the first region within the display region close to the third region, the number of stages of the light emission control signal generation circuit provided between adjacent pixel driving groups is greater than the number of stages of the light emission control signal generation circuit provided between adjacent pixel driving groups in the second region other than the first and third regions within the display region. In the first region included in the display area, the number of gate drive circuits provided between adjacent pixel drive groups is greater than the number of gate drive circuits provided between adjacent pixel drive groups in the second region within the display area.

[0156] For example, in the first region, a three-stage or four-stage light emission control signal generation circuit may be provided between adjacent pixel drive groups, and in the second region, a two-stage light emission control signal generation circuit may be provided between adjacent pixel drive groups. In the first region, there may be three or four gate drive circuits between adjacent pixel drive groups, and in the second region, there may be two gate circuits between adjacent pixel drive groups. This is not limited to this.

[0157] As shown in Figure 18, code A0 is the display area, code A1 is the first area, code A2 is the second area, code A3 is the third area, and code FA is the fan-out area. Display area A0 includes the first area A1, the second area A2, and the third area A3. In Figure 18, code F11 represents the pixel drive group in the first row, first column; code F12 represents the pixel drive group in the first row, second column; code F13 represents the pixel drive group in the first row, third column; code F14 represents the pixel drive group in the first row, fourth column; code F15 represents the pixel drive group in the first row, fifth column. Code F21 is the pixel drive group in the second row, first column; code F22 is the pixel drive group in the second row, second column; code F23 is the pixel drive group in the second row, third column; code F24 is the pixel drive group in the second row, fourth column; code F25 is the pixel drive group in the second row, fifth column. Code F31 is the pixel drive group in the third row, first column; code F32 is the pixel drive group in the third row, second column; code F33 is the pixel drive group in the third row, third column; code F34 is the pixel drive group in the third row, fourth column; code F35 is the pixel drive group in the third row, fifth column. Code F41 is the pixel drive group in the fourth row, first column; code F42 is the pixel drive group in the fourth row, second column; code F43 is the pixel drive group in the fourth row, third column; code F44 is the pixel drive group in the fourth row, fourth column; code F45 is the pixel drive group in the fourth row, fifth column; Code F51 is the pixel drive group in the fifth row, first column; code F52 is the pixel drive group in the fifth row, second column; code F53 is the pixel drive group in the fifth row, third column; code F54 is the pixel drive group in the fifth row, fourth column; code F55 is the pixel drive group in the fifth row, fifth column; Code F61 is the pixel drive group in the sixth row, first column; code F62 is the pixel drive group in the sixth row, second column; code F63 is the pixel drive group in the sixth row, third column; code F64 is the pixel drive group in the sixth row, fourth column; code F65 is the pixel drive group in the sixth row, fifth column. Code F71 is the pixel drive group in the seventh row, first column; code F72 is the pixel drive group in the seventh row, second column; code F73 is the pixel drive group in the seventh row, third column; code F74 is the pixel drive group in the seventh row, fourth column; code F75 is the pixel drive group in the seventh row, fifth column. F71, F72, F73, F74 and F75 are located in the third region A3. Each of the above pixel drive groups includes at least one pixel drive circuit. The first row, first column light emission control signal generation circuit EA11 and the second row, first column light emission control signal generation circuit EA21 are provided between F11, F12, F21 and F22. The light emission control signal generation circuit EA31 in the third row, first column and the light emission control signal generation circuit EA41 in the fourth row, first column are provided between F21, F22, F31 and F32. The light emission control signal generation circuit EA51 in the fifth row, first column and the light emission control signal generation circuit EA61 in the sixth row, first column are provided between F31, F32, F41 and F42. The light emission control signal generation circuit EA71 in the seventh row, first column, the light emission control signal generation circuit EA81 in the eighth row, first column, and the light emission control signal generation circuit EA91 in the ninth row, first column are provided between F41, F42, F51, and F52. The light emission control signal generation circuits EA111 in the tenth row, first column, EA111 in the eleventh row, first column, EA121 in the twelfth row, first column, and EA131 in the thirteenth row, first column are provided between F51, F52, F61, and F62. The gate drive circuit GA11 in the first row and first column and the gate drive circuit EA21 in the second row and first column are provided between F12, F13, F22 and F23. The gate drive circuit GA31 in the third row, first column and the gate drive circuit GA41 in the fourth row, first column are provided between F22, F23, F32, and F33. The gate drive circuit GA51 in the fifth row, first column and the gate circuit GA61 in the sixth row, first column are provided between F32, F33, F42, and F43. The gate drive circuit GA71 in the seventh row, first column, the gate drive circuit GA81 in the eighth row, first column, and the gate drive circuit GA91 in the ninth row, first column are provided between F42, F43, F52, and F53. The gate drive circuits GA111 in the tenth row, first column, GA111 in the eleventh row, first column, GA121 in the twelfth row, first column, and GA131 in the thirteenth row, first column are provided between F52, F53, F62, and F63. The first row, second column light emission control signal generation circuit EA12 and the second row, second column light emission control signal generation circuit EA22 are provided between F13, F14, F23 and F24. The light emission control signal generation circuit EA31 in the third row and second column and the light emission control signal generation circuit EA42 in the fourth row and second column are provided between F23, F24, F33 and F34. The light emission control signal generation circuit EA52 in the fifth row and second column and the light emission control signal generation circuit EA62 in the sixth row and second column are provided between F33, F34, F43 and F44. The light emission control signal generation circuit EA72 in the seventh row, second column, the light emission control signal generation circuit EA82 in the eighth row, second column, and the light emission control signal generation circuit EA92 in the ninth row, second column are provided between F43, F44, F53, and F54. The light emission control signal generation circuits EA112 in the 10th row and 2nd column, EA112 in the 11th row and 2nd column, EA122 in the 12th row and 2nd column, and EA132 in the 13th row and 2nd column are provided between F53, F54, F63, and F64. The gate drive circuit GA12 in the first row and second column and the gate drive circuit EA22 in the second row and second column are provided between F14, F15, F24 and F25. The gate drive circuit GA32 in the third row and second column and the gate drive circuit GA42 in the fourth row and second column are provided between F24, F25, F34 and F35. The gate drive circuit GA52 in the fifth row and second column and the gate circuit GA62 in the sixth row and second column are provided between F34, F35, F44 and F45. The gate drive circuit GA72 in the seventh row, second column, the gate drive circuit GA82 in the eighth row, second column, and the gate drive circuit GA92 in the ninth row, second column are provided between F44, F45, F54, and F55. The gate drive circuits GA112 in the 10th row and 2nd column, GA112 in the 11th row and 2nd column, GA122 in the 12th row and 2nd column, and GA132 in the 13th row and 2nd column are provided between F54, F55, F64, and F65. As shown in Figure 18, F51, F52, F53, F54, F55, F61, F62, F63, F64, F65, EA71, EA81, EA91, EA101, EA111, EA121, EA131, GA71, GA81, GA91, GA101, GA111, GA121, GA131, EA72, EA82, EA92, EA102, EA112, EA122, EA132, GA72, GA82, GA92, GA102, GA112, GA122 and GA132 are all located within the first region A1, the first region A1 is close to the third region A3, and the third region A3 is close to the fan-out region FA. In the first region A1, adjacent pixel drive groups are provided with a 3-stage or 4-stage light emission control signal generation circuit and a 3-stage or 4-stage gate drive circuit.

[0158] In Figure 18, the row and column numbers indicating the location of each pixel drive group are merely illustrative to illustrate the position of each pixel drive group and do not represent the actual row and column corresponding to the pixel drive group. The display panel described in the embodiment of this disclosure includes the above-described display substrate.

[0159] A display panel described in at least one embodiment of the present disclosure further includes a source driver, multiple rows of data lines, and a multiplexer circuit. Multiple pixel circuits located in the same row are all electrically connected to the data lines of the same row. The multiplexer circuit is electrically connected to the multiple voltage output terminals, multiple multiplexing control terminals, and multiple rows of data lines of the source driver, respectively, and is used to write voltage signals supplied from the source driver via its voltage output terminals to the data lines under the control of multiplexing control signals supplied from the multiplexing control terminals.

[0160] In specific implementations, the display panel may further include a source driver, multiple rows of data lines, and a multiplexer circuit, the multiplexer circuit writing voltage signals supplied from the source driver via its voltage output terminal to the data lines under the control of a multiplexing control signal.

[0161] As shown in Figure 19, the display panel according to at least one embodiment of the present disclosure further includes a source driver SD, a multiplexer circuit 90, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a seventh column data line DL7, an eighth column data line DL8, a ninth column data line DL9, a tenth column data line DL10, an eleventh column data line DL11, a twelfth column data line DL12, a thirteenth column data line DL13, a fourteenth column data line DL14, a fifteenth column data line DL15, a sixteenth column data line DL16, a seventeenth column data line DL17, and an eighteenth column data line DL18. The source driver SD includes a first voltage output terminal CH1, a second voltage output terminal CH2, and a third voltage output terminal CH3. The first voltage output terminal CH1, the second voltage output terminal CH2, and the third voltage output terminal CH3 are each electrically connected to the input terminal of the multiplexer circuit 90. The output terminal of the multiplexer circuit 90 is electrically connected to DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, DL12, DL13, DL14, DL15, DL16, DL17, and DL18, respectively. The multiplexer circuit 90 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5, and the sixth multiplexing control terminal MX6, respectively, and is used to control whether the connection between each voltage output terminal and each data line is open or closed under the control of the multiplexing control signals supplied from each multiplexing control terminal.

[0162] In at least one embodiment of the present disclosure, the multiplexer circuit is electrically connected to N multiplexing control terminals, and the multiplexer circuit comprises M multiplexing subcircuits, where N and M are integers greater than 1. Each of the aforementioned multiplexing subcircuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and the N rows of data lines, and is for controlling the voltage signal supplied from the voltage output terminal to be supplied to the nth data line of the N rows of data lines, under the control of the nth multiplexing control signal supplied from the Nth multiplexing control terminals. n is a positive integer less than or equal to N.

[0163] In specific implementations, if the multiplexer circuit is electrically connected to N multiplexing control terminals, the multiplexer circuit may include M multiplexing subcircuits, each of which supplies voltage signals supplied from the voltage output terminal of the source driver to the data lines under the control of the nth multiplexing control signal.

[0164] As shown in Figure 20, in addition to at least one embodiment of the display panel shown in Figure 19, the multiplexer circuit includes a first multiplexing subcircuit 101, a second multiplexing subcircuit 102, and a third multiplexing subcircuit 103. The first multiplexing subcircuit 101 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the first column data line DL1, the fourth column data line DL4, the seventh column data line DL7, the tenth column data line DL10, the thirteenth column data line DL13 and the sixteenth column data line DL16, respectively, and controls the connection between CH1 and DL1 to be open or closed under the control of the first multiplexing control signal supplied from MX1, and the second multiplexing control signal supplied from MX2. This is for controlling the following under the control of the multiplexing control signal: to ensure conduction between CH1 and DL4; to ensure conduction or interruption between CH1 and DL7 under the control of the third multiplexing control signal supplied from MX3; to ensure conduction or interruption between CH1 and DL10 under the control of the fourth multiplexing control signal supplied from MX4; to ensure conduction or interruption between CH1 and DL13 under the control of the fifth multiplexing control signal supplied from MX5; and to ensure conduction or interruption between CH1 and DL16 under the control of the sixth multiplexing control signal supplied from MX6. The second multiplexing subcircuit 102 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the second column data line DL2, the fifth column data line DL5, the eighth column data line DL8, the eleventh column data line DL11, the fourteenth column data line DL14 and the seventeenth column data line DL17, respectively, and controls the connection between CH1 and DL2 to be open or closed under the control of the first multiplexing control signal supplied from MX1, and the second multiplexing control signal supplied from MX2. This is for controlling the following under the control of the multiplexing control signal: to ensure conduction between CH1 and DL5; to ensure conduction or interruption between CH1 and DL8 under the control of the third multiplexing control signal supplied from MX3; to ensure conduction or interruption between CH1 and DL11 under the control of the fourth multiplexing control signal supplied from MX4; to ensure conduction or interruption between CH1 and DL14 under the control of the fifth multiplexing control signal supplied from MX5; and to ensure conduction or interruption between CH1 and DL17 under the control of the sixth multiplexing control signal supplied from MX6. The third multiplexing subcircuit 103 is electrically connected to the first multiplexing control terminal MX1, the second multiplexing control terminal MX2, the third multiplexing control terminal MX3, the fourth multiplexing control terminal MX4, the fifth multiplexing control terminal MX5 and the sixth multiplexing control terminal MX6, the first voltage output terminal CH1, the data line DL3 of the third column, the data line DL6 of the sixth column, the data line DL9 of the ninth column, the data line DL12 of the twelfth column, the data line DL15 of the fifteenth column and the data line DL18 of the eighteenth column, respectively, and controls the connection between CH1 and DL3 to be open or closed under the control of the first multiplexing control signal supplied from MX1, and the second multiplexing supplied from MX2 This is for controlling the following: under the control of the multiplexing control signal, the connection between CH1 and DL6 is made to conduct; under the control of the third multiplexing control signal supplied from MX3, the connection between CH1 and DL9 is made to conduct or disconnect; under the control of the fourth multiplexing control signal supplied from MX4, the connection between CH1 and DL12 is made to conduct or disconnect; under the control of the fifth multiplexing control signal supplied from MX5, the connection between CH1 and DL15 is made to conduct or disconnect; and under the control of the sixth multiplexing control signal supplied from MX6, the connection between CH1 and DL18 is made to conduct or disconnect.

[0165] As shown in Figure 21, in addition to at least one embodiment of the display panel shown in Figure 20, the first multiplexing subcircuit may also include a first multiplexing transistor T1, a second multiplexing transistor T2, a third multiplexing transistor T3, a fourth multiplexing transistor T4, a fifth multiplexing transistor T5, and a sixth multiplexing transistor T6. The gate of T1 is electrically connected to MX1, the source of T1 is electrically connected to CH1, and the drain of T1 is electrically connected to DL1. The gate of T2 is electrically connected to MX2, the source of T2 is electrically connected to CH1, and the drain of T2 is electrically connected to DL4. The gate of T3 is electrically connected to MX3, the source of T3 is electrically connected to CH1, and the drain of T3 is electrically connected to DL7. The gate of T4 is electrically connected to MX4, the source of T4 is electrically connected to CH1, and the drain of T4 is electrically connected to DL10. The gate of T5 is electrically connected to MX5, the source of T5 is electrically connected to CH1, and the drain of T5 is electrically connected to DL13. The gate of T6 is electrically connected to MX6, the source of T6 is electrically connected to CH1, and the drain of T6 is electrically connected to DL16. The second multiplexing subcircuit may include a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, a ninth multiplexing transistor T9, a tenth multiplexing transistor T10, an eleventh multiplexing transistor T11, and a twelfth multiplexing transistor T12. The gate of T7 is electrically connected to MX1, the source of T7 is electrically connected to CH2, and the drain of T7 is electrically connected to DL2. The gate of T8 is electrically connected to MX2, the source of T8 is electrically connected to CH2, and the drain of T8 is electrically connected to DL5. The gate of T9 is electrically connected to MX3, the source of T9 is electrically connected to CH2, and the drain of T9 is electrically connected to DL8. The gate of T10 is electrically connected to MX4, the source of T10 is electrically connected to CH2, and the drain of T10 is electrically connected to DL11. The gate of T11 is electrically connected to MX5, the source of T11 is electrically connected to CH2, and the drain of T11 is electrically connected to DL14. The gate of T12 is electrically connected to MX6, the source of T12 is electrically connected to CH2, and the drain of T12 is electrically connected to DL17. The third multiplexing subcircuit may include the thirteenth multiplexing transistor T13, the fourteenth multiplexing transistor T14, the fifteenth multiplexing transistor T15, the sixteenth multiplexing transistor T16, the seventeenth multiplexing transistor T17, and the eighteenth multiplexing transistor T18. The gate of T13 is electrically connected to MX1, the source of T13 is electrically connected to CH3, and the drain of T13 is electrically connected to DL3 The gate of T14 is electrically connected to MX2, the source of T14 is electrically connected to CH3, and the drain of T14 is electrically connected to DL6 The gate of T15 is electrically connected to MX3, the source of T15 is electrically connected to CH3, and the drain of T15 is electrically connected to DL9 The gate of T16 is electrically connected to MX4, the source of T16 is electrically connected to CH3, and the drain of T16 is electrically connected to DL12 The gate of T17 is electrically connected to MX5, the source of T17 is electrically connected to CH3, and the drain of T17 is electrically connected to DL15 The gate of T18 is electrically connected to MX6, the source of T18 is electrically connected to CH3, and the drain of T18 is electrically connected to DL18

[0166] In at least one embodiment of the display panel shown in FIG. 21, all the transistors are p-type transistors, but are not limited thereto

[0167] In at least one embodiment of the display panel shown in FIG. 21, DL1, DL4, DL7, DL10, DL13 and DL16 may be red data lines, DL2, DL5, DL8, DLll, DL14 and DL17 may be green data lines, and DL3, DL6, DL9, DL12, DL15 and DL18 may be blue data lines, but are not limited thereto Among them, the red data line may be a data line for supplying a data voltage to a red pixel circuit, the green data line may be a data line for supplying a data voltage to a green pixel circuit, and the blue data line may be a data line for supplying a data voltage to a blue pixel circuit

[0168] During the operation of at least one embodiment of the display panel shown in FIG. 21 of the present disclosure When MX1 supplies a low-voltage signal, MX2, MX3, MX4, MX5, and MX6 all output high-voltage signals, T1, T7, and T13 turn on, the other multiplexing transistors turn off, CH1 and DL1 conduct, CH2 and DL2 conduct, and CH3 and DL3 conduct. When MX2 supplies a low-voltage signal, MX1, MX3, MX4, MX5, and MX6 all output high-voltage signals, T2, T8, and T14 turn on, the other multiplexing transistors turn off, CH1 and DL4 conduct, CH2 and DL5 conduct, and CH3 and DL6 conduct. When MX3 supplies a low-voltage signal, MX1, MX2, MX4, MX5, and MX6 all output high-voltage signals, T3, T9, and T15 turn on, the other multiplexing transistors turn off, CH1 and DL7 conduct, CH2 and DL8 conduct, and CH3 and DL9 conduct. When MX4 supplies a low-voltage signal, MX1, MX2, MX3, MX5, and MX6 all output high-voltage signals, T4, T10, and T16 turn on, the other multiplexing transistors turn off, CH1 and DL10 conduct, CH2 and DL11 conduct, and CH3 and DL12 conduct. When MX5 supplies a low-voltage signal, MX1, MX2, MX3, MX4, and MX6 all output high-voltage signals, T5, T11, and T17 turn on, the other multiplexing transistors turn off, CH1 and DL13 conduct, CH2 and DL14 conduct, and CH3 and DL15 conduct. When MX6 supplies a low-voltage signal, MX1, MX2, MX3, MX4, and MX5 all output high-voltage signals, T6, T12, and T18 turn on, the other multiplexing transistors turn off, CH1 and DL16 conduct, CH2 and DL17 conduct, and CH3 and DL18 conduct.

[0169] As shown in Figure 22, during the operation of at least one embodiment of the display panel shown in Figure 21 of this disclosure, the display cycle includes a first write period XT1, a second write period XT2, a third write period XT3, and a light emission stage FT, which are set sequentially. The first write period XT1 includes the first data write period t11 and the second data write period t12, which are set before and after it. The aforementioned second write period XT2 includes a third data write period t21 and a fourth data write period t22, which are set before and after it. The third write period XT3 includes the fifth data write period t31 and the sixth data write period t32, which are set before and after it. During the first data writing period t11, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals. When MX1 outputs a low voltage signal, T1, T7, and T13 turn on, the other multiplexing transistors turn off, CH1 and DL1 conduct, CH2 and DL2 conduct, CH3 and DL3 conduct, CH1 supplies the first light emission time control data voltage to DL1, CH2 supplies the second light emission time control data voltage to DL2, and CH3 supplies the third light emission time control data voltage to DL3. When MX2 outputs a low voltage signal, T2, T8, and T14 turn on, the other multiplexing transistors turn off, CH1 and DL4 conduct, CH2 and DL5 conduct, CH3 and DL6 conduct, CH1 supplies the fourth light emission time control data voltage to DL4, CH2 supplies the fifth light emission time control data voltage to DL5, and CH3 supplies the ninth light emission time control data voltage to DL6. When MX3 outputs a low voltage signal, T3, T9, and T15 turn on, the other multiplexing transistors turn off, CH1 and DL7 conduct, CH2 and DL8 conduct, CH3 and DL9 conduct, CH1 supplies the fourth light emission time control data voltage to DL7, CH2 supplies the fifth light emission time control data voltage to DL8, and CH3 supplies the ninth light emission time control data voltage to DL9. When MX4 supplies a low voltage signal, T4, T10, and T16 turn on, the other multiplexing transistors turn off, CH1 and DL10 conduct, CH2 and DL11 conduct, CH3 and DL12 conduct, CH1 supplies the tenth light emission time control data voltage to DL10, CH2 supplies the eleventh light emission time control data voltage to DL11, and CH3 supplies the twelfth light emission time control data voltage to DL12. When MX5 supplies a low voltage signal, T5, T11, and T17 turn on, the other multiplexing transistors turn off, CH1 and DL13 conduct, CH2 and DL14 conduct, CH3 and DL15 conduct, CH1 supplies the thirteenth light emission time control data voltage to DL13, CH2 supplies the fourteenth light emission time control data voltage to DL14, and CH3 supplies the fifteenth light emission time control data voltage to DL15. When MX6 supplies a low voltage signal, T6, T12, and T18 turn on, the other multiplexing transistors turn off, CH1 and DL16 conduct, CH2 and DL17 conduct, CH3 and DL18 conduct, CH1 supplies the sixteenth light emission time control data voltage to DL16, CH2 supplies the seventeenth light emission time control data voltage to DL17, and CH3 supplies the eighteenth light emission time control data voltage to DL18. Because each data line has parasitic capacitance, each light emission time control data voltage charges the parasitic capacitance of each data line. During the second data writing period t12, RA supplies a low-voltage signal and RB supplies a high-voltage signal, turning on the first transistor M1 in the pixel circuit, and the light emission time control data voltage on each data line is written to the second control node N2. During the third data writing period t21, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals. When MX1 outputs a low voltage signal, T1, T7, and T13 turn on, the other multiplexing transistors turn off, CH1 and DL1 conduct, CH2 and DL2 conduct, CH3 and DL3 conduct, CH1 supplies the nineteenth light emission time control data voltage to DL1, CH2 supplies the twentieth light emission time control data voltage to DL2, and CH3 supplies the twenty-first light emission time control data voltage to DL3. When MX2 outputs a low voltage signal, T2, T8, and T14 turn on, the other multiplexing transistors turn off, CH1 and DL4 conduct, CH2 and DL5 conduct, CH3 and DL6 conduct, CH1 supplies the 22nd emission time control data voltage to DL4, CH2 supplies the 23rd emission time control data voltage to DL5, and CH3 supplies the 24th emission time control data voltage to DL6. When MX3 outputs a low voltage signal, T3, T9, and T15 turn on, the other multiplexing transistors turn off, CH1 and DL7 conduct, CH2 and DL8 conduct, CH3 and DL9 conduct, CH1 supplies the 25th emission time control data voltage to DL7, CH2 supplies the 26th emission time control data voltage to DL8, and CH3 supplies the 27th emission time control data voltage to DL9. When MX4 supplies a low voltage signal, T4, T10, and T16 turn on, the other multiplexing transistors turn off, CH1 and DL10 conduct, CH2 and DL11 conduct, CH3 and DL12 conduct, CH1 supplies the 28th emission time control data voltage to DL10, CH2 supplies the 29th emission time control data voltage to DL11, and CH3 supplies the 30th emission time control data voltage to DL12. When MX5 supplies a low voltage signal, T5, T11, and T17 turn on, the other multiplexing transistors turn off, CH1 and DL13 conduct, CH2 and DL14 conduct, CH3 and DL15 conduct, CH1 supplies the 31st emission time control data voltage to DL13, CH2 supplies the 32nd emission time control data voltage to DL14, and CH3 supplies the 33rd emission time control data voltage to DL15. When MX6 supplies a low voltage signal, T6, T12, and T18 turn on, the other multiplexing transistors turn off, CH1 and DL16 conduct, CH2 and DL17 conduct, CH3 and DL18 conduct, CH1 supplies the 34th emission time control data voltage to DL16, CH2 supplies the 35th emission time control data voltage to DL17, and CH3 supplies the 36th emission time control data voltage to DL18. Because each data line has parasitic capacitance, each light emission time control data voltage charges the parasitic capacitance of each data line. During the fourth data writing period t22, RB supplies a low-voltage signal, RA supplies a high-voltage signal, and M3 in the pixel circuit turns on, writing the emission time control data voltage on each data line to the third control node N3. During the fifth data writing period t31, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals. When MX1 outputs a low voltage signal, T1, T7, and T13 turn on, the other multiplexing transistors turn off, CH1 and DL1 conduct, CH2 and DL2 conduct, CH3 and DL3 conduct, CH1 supplies the first display data voltage to DL1, CH2 supplies the second display data voltage to DL2, and CH3 supplies the third display data voltage to DL3. When MX2 outputs a low voltage signal, T2, T8, and T14 turn on, the other multiplexing transistors turn off, CH1 and DL4 conduct, CH2 and DL5 conduct, CH3 and DL6 conduct, CH1 supplies the fourth display data voltage to DL4, CH2 supplies the fifth display data voltage to DL5, and CH3 supplies the sixth display data voltage to DL6. When MX3 outputs a low voltage signal, T3, T9, and T15 turn on, the other multiplexing transistors turn off, CH1 and DL7 conduct, CH2 and DL8 conduct, CH3 and DL9 conduct, CH1 supplies the seventh display data voltage to DL7, CH2 supplies the eighth display data voltage to DL8, and CH3 supplies the ninth display data voltage to DL9. When MX4 supplies a low voltage signal, T4, T10, and T16 turn on, the other multiplexing transistors turn off, CH1 and DL10 conduct, CH2 and DL11 conduct, CH3 and DL12 conduct, CH1 supplies the tenth display data voltage to DL10, CH2 supplies the eleventh display data voltage to DL11, and CH3 supplies the twelfth display data voltage to DL12. When MX5 supplies a low voltage signal, T5, T11, and T17 turn on, the other multiplexing transistors turn off, CH1 and DL13 conduct, CH2 and DL14 conduct, CH3 and DL15 conduct, CH1 supplies the thirteenth display data voltage to DL13, CH2 supplies the fourteenth display data voltage to DL14, and CH3 supplies the fifteenth display data voltage to DL15. When MX6 supplies a low voltage signal, T6, T12, and T18 turn on, the other multiplexing transistors turn off, CH1 and DL16 conduct, CH2 and DL17 conduct, CH3 and DL18 conduct, CH1 supplies the sixteenth display data voltage to DL16, CH2 supplies the seventeenth display data voltage to DL17, and CH3 supplies the eighteenth display data voltage to DL18. Because each data line has parasitic capacitance, each light emission time control data voltage charges the parasitic capacitance of each data line. During the sixth data writing period t32, G1 supplies a low-voltage signal, causing M6 and M7 in the pixel circuit to turn on, thereby performing charging and threshold voltage compensation, and enabling the writing of the display data voltage. In the light emission stage FT, E1 supplies a low voltage signal and M5 is turned on, controlling the connection between the power supply voltage line VDD and the source of the drive transistor M0. When performing medium-to-high gradation display, the M2 in the pixel circuit is turned on, which controls the connection between the first light emission control line E1 and the first control node N1 to conduct electricity. When low-gradation display is performed, the M4 in the pixel circuit is turned on, which controls the connection between the second light emission control line Hf and the first control node N1 to conduct electricity.

[0170] In the operation of the display panel described in at least one embodiment of the present disclosure, during the second data writing period, the system may be controlled to supply a high-voltage signal from RA and a low-voltage signal from RB, and during the fourth data writing period, the system may be controlled to supply a low-voltage signal from RA and a high-voltage signal from RB.

[0171] In at least one embodiment of the present disclosure, the on-time of each multiplexing control terminal is reduced, and the storage of the emission time control data voltage on the data line can be completed quickly, thereby increasing the on-time of RA, RB and G1, and providing more sufficient time for writing, charging and threshold voltage compensation of the data voltage inside the pixel circuit.

[0172] In at least one embodiment of this disclosure, timing control by GOA (Gate On Array) ensures that all low-level stages of the second light emission control line Hf are in the light emission stage. This avoids coupling effects on the writing of the display data voltage and disturbances in the gate voltage of the drive transistor, which would otherwise occur due to the lowering of the potential of the second light emission control signal by high frequency. As a result, one transistor is reduced compared to the associated pixel circuit to prevent coupling effects of Hf.

[0173] During actual implementation, the presence of parasitic capacitance on the data lines can cause the data lines to couple with each other, influencing each other and potentially altering the voltage.

[0174] As shown in Figure 23, when performing medium-to-high grayscale display, if it is within the second data writing period, RB supplies a low-voltage signal and RA supplies a high-voltage signal, and if it is within the fourth data writing stage, RA supplies a low-voltage signal and RB supplies a high-voltage signal. During the first data writing period t11, the data voltage Vdata applied to DL1 may be 18V. During the third data writing period t21, the data voltage Vdata applied to DL1 may be 0V. During the fifth data writing period t31, the data voltage Vdata applied to DL1 may be 13V. When MX1 is turned on, a data voltage is written to DL1, and DL1 is maintained at the potential of the time immediately before MX1 is turned off. For example, the ideal voltage of DL1 in Figure 23 is VDL10. The 18V voltage signal and the 0V voltage signal are signals that control the switching on of the first and second light emission control lines, respectively, and have little effect on grayscale display. However, when the voltage jumps from 0V to 13V, it is the time when G1 is turned on, and the voltage on DL1 jumps in accordance with the voltage on DL4, affecting the writing of the data voltage. As a result, the written voltage becomes a relatively high potential, and the display of pixels electrically connected to DL1 becomes darker than expected.

[0175] In FIG. 23, VDL40 is the ideal voltage on DL4, and VDL1 is the actual voltage on DL1.

[0176] As shown in FIG. 24, when performing medium and high tone display, if it is within the second data writing period t12, RA supplies a low voltage signal and RB supplies a high voltage signal. If it is within the fourth data writing period t22, RB supplies a low voltage signal and RA supplies a high voltage signal. In the first data writing period t11, the data voltage Vdata input to DL1 may be 0V. In the third data writing period t21, the data voltage Vdata input to DL1 may be 18V. In the fifth data writing period t31, the data voltage Vdata input to DL1 may be 13V. By setting as described above, at the on-time of G1, the data voltage on DL1 jumps from 18V to 13V, the jump width of the data voltage is reduced, and the problem of variations in pixel display is improved.

[0177] As shown in FIG. 25, during the operation of at least one embodiment of the display panel shown in FIG. 21 of the present disclosure, the display period includes a first writing period, a second writing period, a third writing period, and a light emission stage FT set successively. The first writing period includes a first data writing period t11 and a second data writing period t12. The first data writing period is included in the second data writing period t12. The second writing period includes a third data writing period t21 and a fourth data writing period t22. The third data writing period t21 is included in the fourth data writing period t22. The third writing period includes a fifth data writing period t31 and a sixth data writing period t32 set successively. [[ID="]] During the first data writing period t11, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on, thereby writing the corresponding light emission time control data voltage. During the second data writing period t12, RA supplies a low-voltage signal, RB and G1 supply high-voltage signals, and the first transistor M1 in the pixel circuit turns on, writing the light emission time control data voltage on each data line to the second control node N2. During the third data writing period t21, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on, thereby writing the corresponding light emission time control data voltage. During the fourth data writing period t22, RB supplies a low-voltage signal, RA and G1 supply high-voltage signals, and M3 in the pixel circuit turns on, writing the emission time control data voltage on each data line to the third control node N3. During the fifth data writing period t31, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on, thereby writing the corresponding display data voltage. During the sixth data writing period t32, G1 supplies a low-voltage signal, RA and RB supply high-voltage signals, and M6 and M7 in the pixel circuit are turned on, thereby performing charging and threshold voltage compensation, and enabling the writing of the display data voltage. During the light emission stage FT, the EM outputs a low-voltage signal. During a certain period included in the emission stage FT, Hf outputs a low-voltage signal. When performing medium-to-high gradation display, in the light emission stage FT, the micro light-emitting diode ML is driven to emit light by the drive transistor M0 in the pixel circuit. When performing low-gradation display, in the light emission stage FT, when Hf supplies a low-voltage signal, the drive transistor M0 in the pixel circuit drives the micro light-emitting diode ML to emit light.

[0178] In Figure 25, the symbol E1_N represents the next line of light emission control lines adjacent to E1.

[0179] In related technologies, low-gradation display is typically achieved by using current + time control to emit light for a short period of time with a constant current. However, within the display time of one frame, after emitting light for a short time, the LED (light-emitting diode) transitions to a black state, causing the human eye to clearly perceive flicker, which can be unpleasant for viewers. Based on this, at least one embodiment of this disclosure provides a pixel circuit that reduces flicker by controlling the emission time length with a high frequency, thereby distributing short emission time lengths within one frame time.

[0180] In at least one embodiment of the present disclosure, since the light emission control signal supplied from E1 remains a low-voltage signal for a relatively long time, the light emission control signal supplied from Hf becomes a high-frequency pulse signal for the entire duration that it remains a low-voltage signal from E1.

[0181] Figure 26 is an operation timing chart of a display panel described in at least one embodiment of the present disclosure.

[0182] In Figure 26, the code ESTV is the first start voltage, the code ECK is the first clock signal, the code ECB is the second clock signal, the code GSTV is the second start voltage, the code GCK is the third clock signal, the code GCB is the fourth clock signal, the code Hf is the second light emission control line, the code MX1 is the first multiplexing control terminal, the code MX2 is the second multiplexing control terminal, the code MX3 is the third multiplexing control terminal, the code MX4 is the fourth multiplexing control terminal, the code MX5 is the fifth multiplexing control terminal, the code MX6 is the sixth multiplexing control terminal, and the code Vdata is the data voltage.

[0183] The driving method described in the embodiments of this disclosure is applied to the above-mentioned display panel, wherein the display cycle includes a first write period and a second write period, the first write period includes a first data write period and a second data write period, the second write period includes a third data write period and a fourth data write period, and the driving method is During the first data writing period, the multiplexer circuit writes the first control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. During the second data writing period, the first control circuit supplies a first control voltage supplied from the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether or not to supply a first light emission control signal to the first control node under the control of the potential of the second control node. During the third data writing period, the multiplexer circuit writes the second control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. During the fourth data writing period, the second control circuit, under the control of the second reset control signal, writes the second control voltage supplied from the data line to the third control node, and the second control circuit, under the control of the potential of the third control node, controls whether or not to supply the second light emission control signal to the first control node.

[0184] In at least one embodiment of this disclosure, the first data writing period and the second data writing period are set sequentially, and the third data writing period and the fourth data writing period are set sequentially, or The first data writing period is included in the second data writing period, and the third data writing period is included in the fourth data writing period.

[0185] The display device described in the embodiments of this disclosure includes the display panel described above.

[0186] The foregoing describes preferred embodiments of the Disclosure, and it should be noted that those skilled in the art can make some further improvements and modifications without departing from the principles described in the Disclosure, and such improvements and modifications should also be considered within the scope of the Disclosure.

Claims

1. A pixel circuit comprising a light-emitting element and a pixel driving circuit, wherein the pixel driving circuit comprises a driving circuit, a first light-emitting control circuit, a first control circuit, a second control circuit, and a data writing circuit. The aforementioned drive circuit is for generating a drive current to drive the light-emitting element, The first light-emitting control circuit is electrically connected to the first control node, the first end of the drive circuit, and the light-emitting element, respectively, and controls the connection between the first end of the drive circuit and the light-emitting element under the control of the potential of the first control node. The first control circuit is electrically connected to the data line, the first reset control line, the first light emission control line, the first control node, and the second control node, respectively, and is for controlling the supply of the first control voltage supplied from the data line to the second control node under the control of the first reset control signal supplied from the first reset control line, and for controlling the supply of the first light emission control signal to the first control node by the first light emission control line under the control of the potential of the second control node. The second control circuit is electrically connected to the data line, the second reset control line, the second light emission control line, the first control node, and the third control node, respectively, and controls the second reset control signal supplied from the second reset control line to be written to the third control node, and the second light emission control signal to be supplied to the first control node by the second light emission control line, under the control of the potential of the third control node. The data writing circuit is electrically connected to the scan line, the data line, and the second end of the drive circuit, respectively, and is for writing the display data voltage supplied from the data line to the second end of the drive circuit under the control of the scan signal supplied from the scan line. The first control circuit, the second control circuit, and the data writing circuit are for receiving the corresponding voltage signal on the data line in a time-division manner. A pixel circuit in which the pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same, or at least two of the pulse widths of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are different.

2. The scan line, the first reset control line, and the second reset control line are each electrically connected to different GOA circuits within the same GOA module, and each receives a drive signal supplied from the different GOA circuits, or The scan line, the first reset control line, and the second reset control line are each electrically connected to one GOA circuit in a different GOA module, and each receives a drive signal supplied from one GOA circuit in a different GOA module, or The pixel circuit according to claim 1, wherein two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module and each receives a drive signal supplied from the different GOA circuits in the first GOA module, and the remaining one of the scan line, the first reset control line, and the second reset control line is electrically connected to one GOA circuit in the second GOA module and receives a drive signal supplied from one GOA circuit in the second GOA module.

3. The first control circuit includes a first write control circuit, a first energy storage circuit, and a second write control circuit. The first write control circuit is electrically connected to the first reset control line, the data line, and the second control node, respectively, and is for supplying the first control voltage supplied from the data line to the second control node under the control of the first reset control signal. The first energy storage circuit is electrically connected to the second control node and is for storing electrical energy. The pixel circuit according to claim 1 or 2, wherein the second writing control circuit is electrically connected to the second control node, the first light emission control line, and the first control node, respectively, and controls the supply of a first light emission control signal by the first light emission control line to the first control node under the control of the potential of the second control node.

4. The second control circuit includes a third write control circuit, a second energy storage circuit, and a fourth write control circuit. The third write control circuit is electrically connected to the second reset control line, the data line, and the third control node, respectively, and under the control of the second reset control signal, writes the second control voltage supplied from the data line to the third control node. The second energy storage circuit is electrically connected to the third control node and is for storing electrical energy. The pixel circuit according to claim 1 or 2, wherein the fourth writing control circuit is electrically connected to the third control node, the second light emission control line, and the first control node, respectively, and controls the supply of a second light emission control signal to the first control node by the second light emission control line under the control of the potential of the third control node.

5. The first write control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second write control circuit includes a second transistor. The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node. The first electrode plate of the first capacitance is electrically connected to the second control node, and the second electrode plate of the first capacitance is electrically connected to the first initial voltage line. The pixel circuit according to claim 3, wherein the gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light emission control line, and the second pole of the second transistor is electrically connected to the first control node.

6. The third write control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth write control circuit includes a fourth transistor. The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node. The first electrode plate of the second capacitance is electrically connected to the third control node, and the second electrode plate of the second capacitance is electrically connected to the second initial voltage line. The pixel circuit according to claim 4, wherein the gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

7. Further including a second light emission control circuit, The pixel circuit according to claim 1, wherein the second light emission control circuit is electrically connected to the first light emission control line, the power supply voltage line, and the second end of the drive circuit, respectively, and controls the power supply voltage line and the second end of the drive circuit to conduct electricity under the control of the first light emission control signal.

8. The system further includes a compensation control circuit and a third energy storage circuit, The compensation control circuit is electrically connected to the scan line, the control terminal of the drive circuit, and the first terminal of the drive circuit, respectively, and controls the control of the scan signal so that conductivity is maintained between the control terminal of the drive circuit and the first terminal of the drive circuit. The pixel circuit according to claim 1 or 2, wherein the third energy storage circuit is electrically connected to the control terminal of the drive circuit and is for storing electrical energy.

9. It further includes a first reset circuit, The pixel circuit according to claim 1 or 2, wherein the first reset circuit is electrically connected to a third reset control line, a third initial voltage line, and the control terminal of the drive circuit, respectively, and writes the third initial voltage supplied from the third initial voltage line to the control terminal of the drive circuit under the control of a third reset control signal supplied from the third reset control line.

10. It further includes a second reset circuit, The second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line, and the first pole of the light-emitting element, respectively, and is used to write the fourth initial voltage supplied from the fourth initial voltage line to the first pole of the light-emitting element under the control of the fourth reset control signal supplied from the fourth reset control line. The pixel circuit according to claim 9, wherein the second pole of the light-emitting element is electrically connected to the first voltage line.

11. The third reset control line is either the first reset control line or the second reset control line. The pixel circuit according to claim 10, wherein the fourth reset control line is the first reset control line or the second reset control line.

12. The second light-emitting control circuit includes a fifth transistor, The pixel circuit according to claim 7, wherein the gate of the fifth transistor is electrically connected to the first light emission control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second end of the drive circuit.

13. The data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor, and the drive circuit includes a drive transistor. The gate of the sixth transistor is electrically connected to the scan line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the drive transistor. The gate of the seventh transistor is electrically connected to the scan line, the first pole of the seventh transistor is electrically connected to the gate of the drive transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the drive transistor. The pixel circuit according to claim 8, wherein the first electrode plate of the third capacitance is electrically connected to the gate of the drive transistor, and the second electrode plate of the third capacitance is electrically connected to a power supply voltage line.

14. The first reset circuit includes an eighth transistor, The pixel circuit according to claim 9, wherein the gate of the eighth transistor is electrically connected to the third reset control line, the first pole of the eighth transistor is electrically connected to the third initial voltage line, and the second pole of the eighth transistor is electrically connected to the control terminal of the drive circuit.

15. The second reset circuit includes a ninth transistor, The pixel circuit according to claim 10, wherein the gate of the ninth transistor is electrically connected to the fourth reset control line, the first pole of the ninth transistor is electrically connected to the fourth initial voltage line, and the second pole of the ninth transistor is electrically connected to the first pole of the light-emitting element.

16. Includes a multiplexing control circuit, The pixel circuit according to claim 1 or 2, wherein the multiplexing control circuit is electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver, and the data line, respectively, and controls the connection between the voltage output terminal and the data line to be conductive under the control of a multiplexing control signal supplied from the multiplexing control terminal.

17. A driving method, applied to a pixel circuit according to any one of claims 1 to 16, wherein the display stage includes a first writing stage and a second writing stage, and the driving method is In the first writing stage, the first control circuit, under the control of the first reset control signal, supplies a first control voltage supplied from the data line to the second control node, and the first control circuit, under the control of the potential of the second control node, controls whether or not to supply a first light emission control signal to the first control node. A driving method comprising: in a second writing stage, a second control circuit writing a second control voltage supplied from the data line to a third control node under the control of a second reset control signal; and a second control circuit controlling whether to supply a second light emission control signal to the first control node under the control of the potential of the third control node.

18. When performing medium-to-high gradation display, in the first writing stage, the first control circuit controls the supply of the first light emission control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the supply of the second light emission control signal to the first control node to be stopped under the control of the potential of the third control node. The driving method according to claim 17, wherein, when performing low-gradation display, in the first writing stage, the first control circuit controls the supply of a first light emission control signal to the first control node to be stopped under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the supply of a second light emission control signal to the first control node under the control of the potential of the third control node.

19. A display board comprising a base substrate and a plurality of rows and columns of pixel circuits according to any one of claims 1 to 16 provided within a display area on the base substrate.

20. Pixel circuits located in the same row are provided between two rows of data lines, and the data lines extend along the first direction. The pixel circuit of row a is provided between the scan line of row a and the first voltage line of row a, where a is a positive integer. The scan line of row a and the first voltage line of row a extend along the second direction, The display board according to claim 19, wherein the first direction intersects with the second direction.

21. The pixel circuit includes a light-emitting element and a pixel driving circuit, A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided within the gap. The display substrate according to claim 19, wherein the orthographic projection of the light-emitting element on the base substrate does not overlap with the orthographic projection of the pixel driving circuit on the base substrate.

22. It further includes a first signal line, the majority of which is included in the first signal line extends along a second direction. The display board according to claim 21, wherein the first signal line is bent around the light-emitting element to form a first retractable space, and at least a portion of the light-emitting element is provided within the first retractable space.

23. It includes multiple rows of light-emitting units, and each light-emitting unit includes at least three of the light-emitting elements. At least one of the first signal lines is bent to the first side around at least one of the light-emitting elements in an odd-numbered row of light-emitting units to form a first retractable space. At least one of the first signal lines is bent to the second side around at least one of the light-emitting elements in an even row of light-emitting units to form another first retractable space. The display board according to claim 22, wherein the first side and the second side are opposing sides.

24. The pixel circuit includes a light-emitting element and a pixel driving circuit, The light-emitting element is provided on the side of the pixel driving circuit that is farther from the base substrate, The display substrate according to claim 19, wherein the orthographic projection of the light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

25. It further includes a light emission control signal generation module and a second signal line, the light emission control signal generation module includes a plurality of stages of light emission control signal generation circuits, and the light emission control signal generation circuits are provided in the display area. The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. At least one stage of the light emission control signal generation circuit is located between adjacent pixel drive groups, Most of the signal line portion included in the second signal line extends along the first direction, The display board according to claim 19, wherein at least one of the second signal lines is bent around the at least one stage of light emission control signal generation circuit to form a second retractable space, and a portion of the at least one stage of light emission control signal generation circuit is provided within the second retractable space.

26. The display substrate according to claim 25, wherein the orthographic projection of the light emission control signal generation circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

27. It further includes a gate drive module, the gate drive module includes a plurality of gate drive circuits, and the gate drive circuits are provided in the display area. The display board includes a pixel drive group with multiple rows and columns, and the pixel drive group includes at least one pixel drive circuit. The display board according to claim 19, wherein at least one stage of the gate drive circuit is located between adjacent pixel drive groups.

28. It further includes a second signal line, the majority of which is included in the second signal line extends along the first direction, The display board according to claim 27, wherein at least one of the second signal lines is bent around the at least one stage of gate drive circuit to form a third retractable space, and a portion of the at least one stage of gate drive circuit is provided within the third retractable space.

29. The display substrate according to claim 27 or 28, wherein the orthographic projection of the gate drive circuit on the base substrate does not overlap with the orthographic projection of the pixel drive group on the base substrate.

30. A display panel including a display board according to any one of claims 19 to 29.

31. The system further includes a source driver, multiple data lines, and a multiplexer circuit. Multiple pixel circuits located in the same row are all electrically connected to the data lines of the same row. The display panel according to claim 30, wherein the multiplexer circuit is electrically connected to a plurality of voltage output terminals, a plurality of multiplexing control terminals, and a plurality of data lines of the source driver, respectively, and writes voltage signals supplied from the source driver via its voltage output terminals to the data lines under the control of multiplexing control signals supplied from the multiplexing control terminals.

32. The multiplexer circuit is electrically connected to N multiplexing control terminals, and the multiplexer circuit includes M multiplexing subcircuits, where N and M are integers greater than 1. Each of the aforementioned multiplexing subcircuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and the N rows of data lines, and is for controlling the voltage signal supplied from the voltage output terminal to be supplied to the nth data line of the N rows of data lines, under the control of the nth multiplexing control signal supplied from the nth multiplexing control terminal. The display panel according to claim 31, wherein n is a positive integer less than or equal to N.

33. A driving method applied to the display panel described in claim 31 or 32, wherein the display cycle includes a first write period and a second write period, the first write period includes a first data write period and a second data write period, the second write period includes a third data write period and a fourth data write period, and the driving method is During the first data writing period, the multiplexer circuit writes the first control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. During the second data writing period, the first control circuit supplies a first control voltage supplied from the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether or not to supply a first light emission control signal to the first control node under the control of the potential of the second control node. During the third data writing period, the multiplexer circuit writes the second control voltage supplied from the source driver via its voltage output terminal to the data line under the control of the reset control signal. A driving method comprising: during a fourth data writing period, a second control circuit writing a second control voltage supplied from the data line to a third control node under the control of a second reset control signal, and a second control circuit controlling whether to supply a second light emission control signal to the first control node under the control of the potential of the third control node.

34. The first data writing period and the second data writing period are set one after the other, and the third data writing period and the fourth data writing period are set one after the other, or The drive method according to claim 33, wherein the first data writing period is included in the second data writing period, and the third data writing period is included in the fourth data writing period.

35. A display device comprising a display panel according to any one of claims 30 to 32.

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