Angle-averaged calibration on a bare wafer measurement tool to improve ESFQR matching.

Abstract

The present invention relates to a method and system for generating tool correction maps. One method involves measuring the surface heights of the front and rear surfaces of first and second calibration wafers at multiple wafer rotation angles. The calibration wafers are low-profile wafers having opposite shapes to each other when viewed from the measuring device, and they may be a single wafer, but are inverted in the measuring device during the second measurement. The method also comprises generating a first correction map (uninverted) and a second correction map (inverted) at multiple rotation angles from the surface heights measured on the front and rear surfaces, respectively, of the first and second calibration wafers. Furthermore, the method includes the steps of generating a tool correction map by calculating the average of the uninverted and inverted correction maps, and storing the tool correction map for use in calibrating the thickness map of the wafer being tested.

Description

Technical Field

[0001] The present invention generally relates to a method and system for angular averaging calibration for improving an edge surface flatness quotient range (ESFQR) on a bare wafer measurement tool.

Background Art

[0002] The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.

[0003] The manufacture of semiconductor devices, such as logic devices and memory devices, typically involves processing a specimen, such as a semiconductor wafer, using several semiconductor manufacturing processes to form various features and multiple levels of the semiconductor device. For example, lithography is a semiconductor manufacturing process that typically involves transferring a pattern to a resist disposed on a semiconductor wafer. Further examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing, etching, deposition, and ion implantation. Multiple semiconductor devices can be fabricated on and then separated into individual semiconductor devices on a semiconductor wafer.

[0004] The metrology process is used at various steps in the semiconductor manufacturing process to monitor and control the process. Unlike inspection processes, which detect defects on a sample, metrology processes are used to measure one or more properties of a sample that cannot be determined using currently used inspection tools. For example, metrology processes can be used to measure one or more properties of a sample, such as surface flatness in the case of a bare wafer, and the performance of the bare wafer manufacturing process can be determined from that one or more property. Furthermore, if one or more properties of a sample are unacceptable (e.g., outside a predetermined range of properties), the measured values ​​of one or more properties of the sample can be used to modify one or more parameters of the process so that additional samples manufactured by the process have acceptable properties.

[0005] The metrology process also differs from the defect review process in that, unlike the defect review process where defects detected by inspection are revisited in the defect review, the metrology process can be performed at locations where no defects have been detected. In other words, unlike the defect review, the location on the sample where the measurement process is performed is independent of the results of the inspection process performed on the sample. In particular, the location on the sample where the measurement process is performed can be selected independently of the inspection results. In addition, since the location on the sample where the measurement is performed can be selected independently of the inspection results, the location where the measurement is performed can be determined before the inspection process is performed on the sample, unlike the defect review where the location on the sample where the defect review is performed cannot be determined until the inspection results for the sample are generated and available for use.

[0006] The Edge Surface Flatness Quotient Range (ESFQR) is a metric used in wafer metrology to describe edge roll-off (deviation or tilt from the plane) at various angular sectors of a wafer. Traditionally, dual-side wafer metrology equipment generates it by measuring surface height maps of both sides of the wafer. The wafer thickness map is then calculated by adding the two wafer surface maps and removing apparent distance variations associated with the measuring equipment. Some measurement tools require the removal of the "cavity map" (i.e., the distance map between the two reference planes in a dual-side interferometer).

[0007] To calculate the ESFQR, the wafer thickness map must be processed to extract the 2D thickness profile in defined angular sectors. An angular sector is a rectangular area in polar coordinates near the wafer edge. In some bare wafer measurement tools, it is defined by a radial length of 30 mm from the wafer edge and a polar angular width of 5 degrees. In addition, edge exclusion (EE) is usually applied to remove low-quality data at the wafer edge. 1 mm edge exclusion (1EE) and 0.5 mm edge exclusion (0.5EE) are the most common choices. Finally, in each angular sector, the ESFQR is calculated as the "peak-(minus) valley" distance of the 2D thickness profile after removing the slope. Intuitively, the ESFQR describes how quickly the wafer thickness decreases near the edge.

[0008] With an angular width of 5 degrees, the wafer has 72 angular sectors, and therefore 72 ESFQR values ​​are generated by each measurement, one for each angular sector. The actual ESFQR values ​​also depend on the selection of the EE and the resolution of the thickness map. In some bare wafer measurement tools, ESFQR is typically calculated at standard resolution (StdRes) and high resolution (HiRes). Different groups of ESFQR can be generated using different combinations of EE and resolution. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] U.S. Patent Application Publication 2020 / 0033117 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] However, the bare wafer measurement methods and tools currently in use have several drawbacks. For example, ESFQR StdRes 1 EE on some bare wafer measurement tools currently exhibits relatively large systematic errors, making its matching relatively risky compared to other metrics. ESFQR matching between tools is known to often present a periodic pattern when plotted against angular sectors. The peaks and troughs of the pattern can often reach ~2 nm (0.42 nm is the matching specification relative to the mean of all angular sectors). The pattern is both tool-dependent and wafer-dependent. The error sources contributing to this matching error likely include (tool-specific) errors in the cavity map (i.e., the distance map between the two reference planes in a bifacial interferometer), phase-dependent errors due to laser output instability or vibration (which may be called "fringe print-through"), wafer retracing errors (RTE) dependent on tool aberrations and wafer geometry (more specifically, phase errors dependent on both the optical aberrations of the imaging system and the wafer surface tilt), and thickness errors at the wafer edge due to edge mismatch between the front and rear wafer maps. Without a way to address the root causes of systematic errors, ESFQR matching performance may not be able to support the needs of future generating tools.

[0011] Therefore, it would be advantageous to develop a system and method for generating a corrected thickness map that does not have one or more of the aforementioned drawbacks. [Means for solving the problem]

[0012] The following description of various embodiments should not be construed as limiting the subject matter of the appended claims.

[0013] One embodiment relates to a system configured to generate a tool correction map. The system includes a measurement subsystem configured to measure the surface heights of the front and rear surfaces of first and second calibration wafers at a plurality of wafer rotation angles. (Note that wafers compliant with SEMI standards must have notches for defining the rotation angles in the measurement device.) The first and second calibration wafers are low-profile wafers having opposite shapes to each other so that they are "seen" by the measurement subsystem (or, as herein also, the “measurement device”). In other words, the shapes of the first and second calibration wafers seen (or measured) by the measurement subsystem should be opposite to each other, regardless of how the wafers are arranged in the measurement subsystem, which wafers are used for measurement, and whether a single wafer or multiple wafers are used for measurement to achieve such shape opposition. One way to obtain such a pair of wafers is to find two wafers having similar shapes and then invert one of them in a wafer container so that its front and rear surfaces are swapped when loaded into the measurement device. Another possibility is that a single low-profile wafer can function as both the first and second calibration wafers, but when measured as the second calibration wafer, it needs to be inverted within the measuring device, such as a dual-side interferometer. Whatever method is chosen to implement the method, the key point is that the wafers seen by the measuring device during the first and second measurements should have opposite shapes.

[0014] The system also includes a computer subsystem configured to generate two ("first" and "second") correction maps from the measured surface heights (or thickness maps) of the front and rear surfaces of the first and second calibration wafers at multiple rotation angles, respectively. Since the second calibration wafer may be a flipped version of the first calibration wafer, the correction maps generated from the first and second calibration wafers are referred to as the "non-flip correction map" and the "flip correction map," respectively. In addition, the computer subsystem is configured to generate a tool correction map by averaging the first and second correction maps. The computer subsystem is further configured to store the tool correction map for use in calibrating the thickness map of a test wafer generated from the surface heights of the front and rear surfaces of a test wafer measured by the measurement subsystem. The system may be further configured as described herein.

[0015] Another embodiment relates to a computer implementation method for generating tool correction maps. This method includes the measurement steps described above, performed using a measurement subsystem configured as described above. The calibration wafer is configured as described above. This method also includes the steps of generating a first correction map, a second correction map, and a tool correction map, and the steps of storing the tool correction maps as described above, performed by the computer subsystem. Each of the steps of this method may be performed as further described herein. This method may include any other steps of any other method described herein. This method may be carried out by any of the systems described herein.

[0016] Another embodiment relates to a non-temporary computer-readable medium for storing program instructions executable on a computer system for performing a computer implementation method for generating a tool modification map. The computer implementation method includes the steps of the method described above. The computer-readable medium may be further configured as described herein. The steps of the computer implementation method may be performed as further described herein. In addition, the computer implementation method on which the program instructions are executable may include any other steps of any other method described herein.

[0017] Further advantages of the present invention will become apparent to those skilled in the art by benefiting from the following detailed description of preferred embodiments and by referring to the accompanying drawings: [Brief explanation of the drawing]

[0018] [Figure 1] This is a schematic diagram showing an aspect of one embodiment of a system configured to generate a tool correction map. [Figure 2] This flowchart shows one embodiment of a method for generating a tool correction map. [Figure 3] This is a flowchart illustrating one embodiment of a computer implementation method for using a tool correction map generated as described herein. [Figure 4] This is a schematic diagram showing an example of a valid wafer pair with a similar shape before the second wafer is flipped. [Figure 5] This flowchart shows one embodiment of a method for generating a tool correction map. [Figure 6] This is a schematic diagram showing an example of a valid calibration wafer pair. [Figure 7] This is a flowchart illustrating one embodiment of a computer implementation method for using a tool correction map generated as described herein. [Figure 8]A block diagram showing one embodiment of a non - transient computer - readable medium storing program instructions for causing a computer system to execute the computer - implemented method described herein. **DETAILED DESCRIPTION OF THE INVENTION**

[0019] The present invention is capable of various modifications and alternative forms, and specific embodiments thereof are shown by way of example in the drawings and described in detail herein. The drawings may not be to scale. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0020] Referring now to the drawings, it should be noted that the figures are not drawn to scale. In particular, the scales of some of the elements of the figures are greatly exaggerated for the purpose of emphasizing the characteristics of the elements. It should also be noted that the drawings are not drawn to the same scale. Elements shown in multiple figures that may be similarly configured are shown using the same reference numerals. Unless otherwise noted herein, any of the elements described and illustrated may include any suitable commercially available elements.

[0021] Generally, the embodiments described herein are configured for angle averaging calibration on a metrology tool for improving edge surface flatness quotient range (ESFQR) matching. During the investigation of ESFQR matching errors, a calibration method has been developed to remove the tool - specific angular - dependent systematic error in the standard resolution ( "StdRes") thickness map on the metrology tool, which is also referred to herein as "averaging" calibration. This calibration method works well for improving ESFQR StdRes, 1 - mm edge exclusion ( "IEE") matching, and there is also interest in extending this method to ESFQR high - resolution ( "HiRes") 0.5 - mm edge exclusion ( "0.5EE"). The principle of this calibration method is described below.

[0022] One embodiment of a system configured to generate a tool correction map includes a measurement subsystem configured to measure the surface heights of the front and rear surfaces of first and second calibration wafers at multiple wafer rotation angles. For example, as shown in Figure 1, system 100 includes an interferometer-based measurement system 10 configured to measure the surface heights of the front and rear surfaces of wafer 14 at multiple wafer rotation angles. The interferometer-based measurement system 10 can be configured as a Fizeau interferometer type measurement system. For example, the measurement system can be configured as described in U.S. Patent Application Publication 2020 / 0033117 (Huang et al., January 30, 2020), which is incorporated herein by reference as if fully defined herein. The measurement subsystem can be further configured as described herein. The measurement subsystem may also include a commercially available measurement subsystem, such as the WaferSight® tool, commercially available from KLA Corp., Milpitas, California.

[0023] The measurement subsystem may be warmed up in any suitable way known in the art before any of the measurements described herein, for example, before the measurement of the correction map. Multiple wafer rotation angles in degrees can be, for example, 0, 30, 60, 120, 150, 180, 210, 240, 300, and 330. Thus, a total of 10 angles may exist. However, any suitable wafer rotation angle and any suitable number of such angles may be used in the embodiments described herein. The measurement subsystem can measure the surface height at the wafer rotation angle in any suitable way known in the art.

[0024] The measurement subsystem may also include a scanning subsystem configured to change the position on the wafer where the measurement is performed and, optionally, to scan the wafer during the measurement. For example, the measurement subsystem may include a stage 22 on which the wafer 14 is positioned during the measurement. As shown in Figure 1, the stage may support the wafer near the edge of the wafer, rather than in the central portion of the wafer, so that the rear surface of the wafer can be measured by the measurement subsystem. The stage may contact the edge of the wafer either across the entire periphery of the wafer or only in specific spaced regions around the periphery of the wafer. The scanning subsystem may include any suitable mechanical and / or robotic assembly (including the stage 22) that can be configured to move the wafer so that the measurement can be performed at different locations on the wafer. In addition, or alternatively, the measurement subsystem may be configured so that one or more optical elements of the measurement subsystem perform some scanning of the wafer.

[0025] The system also includes a computer subsystem, for example, computer subsystem 36, configured to perform one or more functions described herein using the output generated by the measurement subsystem. For example, computer subsystem 36 may be coupled to the detector (not shown) of the measurement subsystem in any preferred manner (for example, via one or more transmission media, which may include "wired" and / or "wireless" transmission media) so that the computer subsystem can receive the output generated by the detector. Computer subsystem 36 may be further configured as described herein.

[0026] The computer subsystem 36 may also be referred to as a computer system in this specification. The computer subsystem may take various forms, including personal computer systems, image computers, mainframe computer systems, workstations, network appliances, internet appliances, or other devices. Generally, the term “computer subsystem” can be broadly defined to encompass any device having one or more processors that execute instructions from a memory medium. The computer subsystem may also include any suitable processor known in the art, such as a parallel processor. In addition, the computer subsystem may include a computer platform having high-speed processing and software, either as a standalone tool or a network tool.

[0027] In one embodiment, the measurement subsystem is configured to measure the surface heights of the front and rear surfaces of the first and second calibration wafers at standard resolution. For example, the experimental results used to create the embodiments described herein included only StdRes thickness maps. However, the same calibration principle should be applicable to thickness maps at other resolutions, such as HiRes. Calibration of thickness maps at different resolutions may have differences in operational details depending on the system. For example, in some wafer measurement systems, StdRes thickness maps are stored in standard wnt / pwg files and can be easily modified and replaced. However, HiRes thickness maps are not usually stored directly, but they can be calculated from the front and rear height maps as needed. Thus, while the StdRes and HiRes applications of the embodiments described herein may actually differ somewhat, the overall concept is generally independent of the resolution at which the measurement is performed. In another option, the computer subsystem may be configured to extract HiRes thickness maps. It is also possible to calculate the HiRes correction map first and then downsample it to obtain the StdRes correction map.

[0028] The first and second calibration wafers are low-shape wafers. In one embodiment, the low-shape wafer has a shape with a 6σ of less than 9500 nm, and the combined 6σ of the shape maps of the first and second calibration wafers is less than 2200 nm. For example, the calibration wafers described herein are preferably low-shape because, if the wafer is a high-shape wafer, the correction map generated as described herein can carry a significant wafer signature. Experimental results show that calibration wafers with a shape with a 6σ of less than approximately 9000 nm can function well. Thus, the term "low-shape wafer" is defined as a wafer having a shape with a 6σ of less than 9500 nm when used herein.

[0029] The first and second calibration wafers also have opposite shapes to each other, as observed by the measurement subsystem. Thus, the method includes creating first and second correction maps using two oppositely shaped calibration wafers, as observed by the measurement subsystem. The first and second calibration wafers, which have opposite shapes to each other as observed by the measurement subsystem, may be identified and selected as further described herein.

[0030] In one embodiment, the first and second calibration wafers are standard bare wafers. The standard bare wafers may include any suitable wafers known in the art. In another embodiment, the computer subsystem is configured to select the first and second calibration wafers from a single batch of wafers, and based on the shape of the wafers within that single batch. For example, in practice, it is difficult to find two wafers with exactly opposite shapes. During the initial tests carried out to create the embodiments described herein, the same wafers were flipped to generate flipped correction maps. In practical implementations, it is preferable to flip one of two wafers of similar shape to prepare a “calibration wafer pair”. Note that flipping a wafer also performs a mirror image operation with respect to the wafer shape. Therefore, it is preferable to use wafers with shapes that are approximately symmetrical with respect to the diameter through the notch. Experimental results have shown that it is not difficult to find wafers of such similar shape within the same batch of wafers from vendors such as Wafernet Inc., San Jose, California and Siltronic, Munich, Germany. Accordingly, the term “opposite shapes” as used herein is defined as two wafer shapes that are sufficiently opposite to each other to satisfy the criteria further described herein. Thus, the shapes of calibration wafers do not need to be exactly opposite to each other to be suitable for use in the embodiments described herein, as long as they satisfy the criteria described herein.

[0031] In another embodiment, the computer subsystem is configured to select the first and second calibration wafers by determining a difference shape map from different pairs of shape maps of wafers and selecting one of the different pairs having a difference shape map with a 6σ of less than 1500 nm. For example, the computer subsystem can be configured to select the first and second calibration wafers by determining a difference shape map from a pair of wafer shape maps, the pass criterion being that the 6σ of the difference shape map is less than 1500 nm. One of the wafers is then inverted upside down to become a pair of calibration wafers (also referred to herein as wafer A and wafer B).

[0032] In summary, the criteria for selecting wafer pairs (before inversion) from a batch (group) of similar wafers are as follows: 1. The 6σ of the shape map for both wafers is less than 9000 nm; 2. The 6σ of the differential shape map between the two wafers before flipping is less than 1500 nm.

[0033] Figure 4 shows an example of a valid pair of wafers with similar shapes before one of the wafers is flipped. In particular, Figure 4 shows the shape map 400 of a wafer in slot 9 of the lot having 6σ = 4378 nm. Shape map 402 relates to a wafer in slot 10 of the same lot having 6σ = 4521 nm. Subtracting the two shape maps (i.e., shape of slot 9 - shape of slot 10) yields shape map 404 having 6σ = 854. Thus, these two wafers meet the criteria identified above and can be selected for use after one of the first and second calibration wafers has been flipped.

[0034] In a further embodiment, the computer subsystem is configured to verify a pair of wafers selected as first and second calibration wafers by determining the sum of the wafer shape maps of the pair after flipping one of the shape maps of one of the wafers in the pair (for example, near the diameter through a notch), and determining whether the 6σ of the sum of the wafer shape maps of the pair is less than 2200 nm. The pass criteria for verifying the calibration wafer pair are as follows: 1. The 6σ of the shape map for both wafers is less than 9500 nm; 2. The 6σ of the horizontal flip of wafer A shape + wafer B shape is less than 2200 nm.

[0035] An example of a valid calibration wafer pair is shown in Figure 6. Shape map 600 is for the wafer in slot 9 of the lot having 6σ = 4410 nm, and shape map 602 is for the wafer in slot 10 of the lot having 6σ = 5089 nm. Adding the first shape map to the second shape map, which is horizontally inverted (i.e., the wafer shape map for slot 9 + the horizontal flip of the wafer shape map for slot 10), yields shape map 604 having 6σ = 1133 nm. Thus, these two wafers satisfy the criteria identified above and constitute a valid calibration wafer pair. Note that the second map is horizontally inverted because the wafer notch is at the bottom of the figure. The diameter passing through the notch is vertical, and this is the inversion axis.

[0036] The computer subsystem can be configured to generate and display shape maps of one or more wafer pairs to the user. For example, in some embodiments, the computer subsystem is configured to generate shape maps of first and second calibration wafers and to display to the user one or more of the shape maps of the first and second calibration wafers, a difference shape map generated from the shape maps of the first and second calibration wafers, and a sum of the shape maps of the first and second calibration wafers. The computer subsystem may also be configured to perform operations such as map flipping, map summing, and map subtraction and to display 6σ of the resulting map to the user. For example, the computer subsystem's display device and / or user interface may be configured to display such wafer shape maps and one or more results generated by adding or subtracting wafer shape maps, perhaps in a manner similar to that shown in Figures 4 and 6. This functionality is, of course, optional, but can visually provide the user with confirmation that the shape maps are sufficiently similar and / or that the addition and / or subtraction results are appropriate. This functionality may also optionally be provided with a user input mechanism so that the user can confirm or reject a pair of wafers as calibration wafers.

[0037] The computer subsystem is configured to generate a first ("non-flip") correction map from the measured surface heights of the front and rear surfaces of a first calibration wafer at a plurality of wafer rotation angles. The wafer rotation angles at which the surface height is measured can be the rotation angles described above, e.g., 0, 30, 60, 120, 150, 180, 210, 240, 300, and 330. However, this is merely an example. Any suitable wafer rotation angle and any suitable number of such angles may be used. Importantly, the average thickness map from these rotation thickness maps should be essentially radially symmetric, i.e., any angle-dependent features in individual thickness maps are preferably suppressed by averaging. The wafer rotation angle used to select the calibration wafer may be one of the wafer rotation angles used to generate the correction maps described herein, but 0 degrees is the most convenient choice. The generation of the non-flip correction map may be carried out as further described herein.

[0038] In one embodiment, the computer subsystem is configured to generate a first (non-flip) correction map by generating a first thickness map of the first calibration wafer from the surface heights of the front and rear surfaces of the first calibration wafer measured at a first wafer rotation angle among a plurality of wafer rotation angles. An angle-average thickness map of the first calibration wafer is generated from the surface heights of the front and rear surfaces of the first calibration wafer measured at a plurality of wafer rotation angles, and the angle-average thickness map is subtracted from the first thickness map. For example, as shown in Figure 2, the low-profile wafer 200 (first calibration wafer or "wafer A") may be measured by a measurement subsystem as described herein, and the computer subsystem may generate a 0-degree thickness map 202 and an angle-average thickness map 204 from the measured values. The computer subsystem can then, in step 206, subtract the angle-average thickness map from the 0-degree thickness map to generate a non-flip correction map 208.

[0039] Therefore, a 0-degree thickness map can be generated for surface heights measured at a single wafer rotation angle. Here, “0-degree thickness map” means a thickness map created at a 0-degree wafer rotation angle or the default wafer rotation angle. Thus, the term “0-degree thickness map” is used more generally to refer to any thickness map measured at the default wafer rotation angle. A 0-degree thickness map can otherwise be generated by any suitable method known in the art.

[0040] The surface height used to generate the angle-averaged thickness map may include the surface height measured at all wafer rotation angles in which the wafer measurement was performed. Thus, the surface height measured at the default wafer rotation angle may be used to generate the 0-degree thickness map, or it may be used in combination with other surface heights measured at other wafer rotation angles to generate the angle-averaged thickness map. However, the angle-averaged thickness map can be generated using the surface height measured at wafer rotation angles less than all wafer rotation angles. The angle-averaged thickness map may be generated in any preferred format otherwise known in the art. Alternatively, an averaged thickness map for all angles may be calculated using "partial averaging". For example, if some maps have void data at a certain point (such as the wafer gripper region) and other maps have non-void data, the computer subsystem can average only the non-void data as a result.

[0041] The computer subsystem is also configured to generate a second ("flipped") correction map from the measured surface heights of the front and back surfaces of a second calibration wafer at multiple wafer rotation angles. The wafer rotation angles at which the surface height is measured for the flipped calibration wafer may be the rotation angles described above. The generation of the flipped correction map may be carried out as further described herein.

[0042] In some embodiments, the computer subsystem is configured to generate a second (flipped) correction map by generating a first thickness map of the second calibration wafer from the surface heights of the front and rear surfaces of the second calibration wafer measured at a first wafer rotation angle among a plurality of wafer rotation angles. An angle-average thickness map of the second calibration wafer is generated from the surface heights of the front and rear surfaces of the second calibration wafer measured at a plurality of wafer rotation angles, and the angle-average thickness map is subtracted from the first thickness map. For example, as shown in Figure 2, a flipped wafer 210, which is the same or similar wafer as the wafer used for the low-shape wafer 200, may be measured by the measurement subsystem described herein, and the computer subsystem may generate a 0-degree thickness map 212 and an angle-average thickness map 214 from the measured values. The computer subsystem can then, in step 216, subtract the angle-average thickness map from the 0-degree thickness map, thereby generating a flip correction map 218. Each of these steps may be performed as further described above.

[0043] The computer subsystem is further configured to generate a tool correction map by averaging the first and second correction maps. For example, as shown in Figure 2, the computer subsystem may, in step 220, average the non-flip correction map 208 and the flip correction map 218 to thereby generate a tool correction map 222. Averaging can be performed in any suitable manner. The final tool correction map with a timestamp may be stored in the computer subsystem, any other computer subsystem that may have a reason to use the tool correction map, or in a default location on a storage medium configured as further described herein.

[0044] In some embodiments, the computer subsystem is configured to generate a tool correction map by determining the average of the averaging results and subtracting the average from the averaging results. For example, as shown in step 220 of Figure 2, the computer subsystem may remove the DC shift from the averaging results performed in that step. Removing the average (or DC shift) before generating the tool correction map may be done to ensure that the average thickness value in the correction map is zero, and therefore subtracting it does not affect the average thickness of the wafer thickness map. This subtraction step may be performed in any suitable method otherwise known in the art.

[0045] In one embodiment, the tool correction map includes tool-specific systematic errors. For example, the embodiments described herein can create a correction map that includes tool-specific systematic errors by using two calibration wafers of opposite shapes, selected and configured as further described herein. In another embodiment, the tool correction map includes tool-specific angle-dependent systematic errors. For example, as further described herein, each of the angle-averaged thickness maps described herein is an average map of thickness maps of the same wafer measured at different wafer rotation angles. Individual thickness maps at a particular rotation angle typically have angle-dependent systematic errors that are visible on the map, but after averaging across maps from different rotations, the result is substantially rotationally symmetric and the angle-dependent systematic errors are significantly suppressed. Thus, by subtracting the 0-degree thickness map from the angle-averaged map, the resulting correction map carries the angle-dependent systematic errors at 0 degrees.

[0046] The correction map generated by subtracting the two thickness maps described above still has a wafer dependency due to recurrent error (RTE) or other error sources, which is a phase error that depends on both the optical aberrations of the imaging system and the wafer surface tilt. However, averaging the first and second correction maps reduces the dependence of the tool correction map on the first and second calibration wafers (more specifically, their individual wafer surface tilts). For example, the tool correction map 222 shown in Figure 2 has its wafer-dependent error removed due to the steps shown in the figure. Averaging two correction maps from two wafers of opposite shapes is key to the embodiments described herein. More specifically, this step removes wafer dependency, and the resulting map is essentially independent of the wafer used to generate the map. Thus, the resulting correction map is essentially a signature (characteristic) of the tool-specific error at 0 degrees. Without this step, the calibration would not work and could result in a worse matching outcome, because the correction map would carry wafer signatures that would get mixed with other wafer signatures when the correction map is applied to data on other wafers.

[0047] The computer subsystem is configured to store tool correction maps for use in calibrating the thickness map of a test wafer generated from the front and rear surface heights of the test wafer measured by the measurement subsystem. For example, the computer subsystem may store tool correction maps in a wafer measurement recipe, or by generating a wafer measurement recipe in which a tool correction map is used. As used herein, the term “recipe” can generally be defined as a set of instructions that can be used by a tool to perform a process on a wafer. Thus, generating a recipe may include generating information about how the process should be performed, which can then be used to generate instructions for performing that process. The tool correction maps stored by the computer subsystem may also be stored with any information that can be used to identify and / or use the tool correction maps (e.g., file names and storage locations).

[0048] The computer subsystem can be configured to store the tool correction map in any suitable computer-readable storage medium. The tool correction map may be stored together with any of the results described herein, or in any format well known in the art. The storage medium may include any storage medium described herein or any other suitable storage medium known in the art. After the tool correction map is stored, it can be accessed within the storage medium and used by any of the methods or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc. For example, the embodiments described herein can generate a measurement recipe as described above. The measurement recipe may then be stored and used by the system to measure a wafer, thereby generating information for the wafer (e.g., thickness information).

[0049] Therefore, as described herein, embodiments can be used to set up a new process or recipe. Embodiments may also be used to modify an existing process or recipe.

[0050] Since calibration may be performed on-site from time to time, the computer subsystem may perform a special job of measuring a correction map using calibration wafers A and B. The operational process of this function is shown in Figure 5. As shown in this figure, in step 504, the computer subsystem can measure wafers A(500) and B(502) at the designed rotation angles. The wafer measurements may be performed as further described herein. In step 506, the computer subsystem may verify that wafers A and B are a valid pair using a 0-degree shape map. This step may be performed as described herein with respect to selecting two wafers for calibration. If the computer subsystem cannot verify in step 506 that wafers A and B are a valid pair, the computer subsystem may determine that the wafers are an invalid pair and terminate the process in step 508. In this case, the system may re-execute the calibration wafer selection as further described herein. If the computer subsystem determines that the wafers are a valid pair, the computer subsystem may, in step 504, measure wafers A and B at additional designed rotation angles, which may be done as described herein.

[0051] The computer subsystem may use the results of step 504 to generate a 0-degree thickness map 510 and an average thickness map 512 for all angles of wafer A, as further described herein. The computer subsystem may also use the results of step 504 and generate a 0-degree thickness map 518 and an average thickness map for all angles 520 for wafer B, as further described herein. In step 514, the computer subsystem may subtract the average thickness map 512 for all angles of wafer A from the 0-degree thickness map 510 for wafer A to generate an A-correction map 516, and in step 522, subtract the average thickness map 520 for all angles of wafer B from the 0-degree thickness map 518 to generate a B-correction map 524. The computer subsystem may average the two correction maps and remove the average from the result of the averaging in step 526 to generate a tool-correction map 528. Step 526 may be performed as further described herein.

[0052] In another embodiment, the computer subsystem is configured to calibrate the thickness map of a test wafer by subtracting a stored tool correction map from the thickness map, thereby generating a corrected thickness map of the test wafer. In this way, the same computer subsystem that generates the tool correction map can use the tool correction map to calibrate the thickness map of the test wafer. For example, a second part of the calibration is to calibrate the test wafer thickness map using the tool correction map, thereby creating a calibrated thickness map for recipe processing during job execution or offline analysis. One such method is shown in Figure 3. As shown in step 300, the system can generate or obtain a wnt / pwg / waf file (or any other standard file type) for all slots and all cycles. In step 306, the computer subsystem generates the original thickness map 302 for the test wafer, subtracts the tool correction map 304 from the original thickness map, thereby generating a corrected wnt / pwg / waf file 308 for the test wafer. The computer subsystem may then use the corrected thickness map to perform recipe processing 310 for the test wafer.

[0053] Another embodiment of wafer thickness map calibration is shown in Figure 7. Using a tool correction map generated as described herein, the wafer thickness map created in the job run is subtracted by the tool correction map to create a correction map before recipe processing. The computer subsystem may be configured to add this function to the current workflow of the job. As shown in Figure 7, the computer subsystem generates a conventional thickness map 702 from data acquired from job 700, which can be done in any suitable way known in the art. The computer subsystem may load a tool correction map from disk, as shown in step 704, and in step 706, subtract the tool correction map from the conventional thickness map to generate a correction thickness map 708. The computer subsystem can then perform recipe processing 710, which may include any wafer measurement processing that can be performed on the currently used thickness map. In this case, the currently generated thickness map is replaced with the correction thickness map during recipe processing. Thus, the correction thickness map can be used in the same way as any other currently generated thickness map.

[0054] The calibrations described herein can be applied to thickness maps at different resolutions, such as the StdRes (standard resolution) and HiRes (high resolution) thickness maps in the WaferSight® tool commercially available from KLA Corp., in Milpitas, California.

[0055] In one embodiment, the system is one of several systems, and calibrating the thickness map of the test wafer with the stored tool correction maps of each of the several systems improves the matching between the several systems by reducing the systematic error of each of the several systems. For example, angle-averaged calibration has been tested by the inventors, and the results show that it can significantly improve ESFQR matching between tools. ESFQR matching often exhibits an angle-dependent pattern. This pattern is reduced by approximately half after the calibration described herein, and the average ESFQR matching across all angle sectors is significantly improved. Based on statistics of test results between several tools and several wafer sets, angle-averaged calibration can reduce the angle-dependent pattern by approximately 40% on average and improve the average ESFQR matching by approximately 70% on average. Thus, the embodiments described herein provide value-added functionality for wafer measurement tools, particularly when substantially high accuracy of edge metrics such as ESFQR metrics is desired.

[0056] In another embodiment, the computer subsystem is configured to calibrate the thickness map of a test wafer using a stored tool correction map, calculate the ESFQR of the test wafer from the calibrated thickness map, and determine additional metrics of the test wafer from the thickness map. For example, the embodiments described herein provide value-added functionality for wafer measurement tools, particularly when substantially high accuracy of the ESFQR metric is desired. Furthermore, for wnt files stored on disk, both the conventional thickness map and the corrected thickness map may be stored. In some examples, the corrected thickness map is calculated and used only for ESFQR calculations during recipe processing. Other metrics may not be affected by calibration, and the currently used recipe processing may be modified to accommodate this functionality (for example, so that one metric is determined using the corrected thickness map and another metric is calculated using the uncorrected thickness map). In this way, the ESFQR recipe can be modified and isolated from other metrics.

[0057] The computer subsystem may be configured to store the corrected (calibrated) thickness map of the test wafer, and / or any results of recipe processing performed using the corrected thickness map and optionally the uncorrected thickness map. The results of recipe processing may be generated by the computer subsystem in any preferred form and may have any preferred form or format, such as a standard file type.

[0058] The results and information generated by performing measurements on a wafer can be used in various ways by the embodiments and / or other systems and methods described herein. Functions that can be performed using such information include, but are not limited to, modifying processes such as manufacturing processes or steps that have been performed or will be performed on the test wafer or other wafers in a feedback or feedforward manner. For example, a computer subsystem may be configured to determine one or more changes to a process performed on a test wafer based on a process performed on a test wafer measured as described herein and / or a corrected thickness map generated for the test wafer. Changes to a process may include any suitable changes to one or more parameters of the process. Preferably, the computer subsystem determines these changes so that wafer thickness variations can be compensated for in another process performed on the wafer, so that unacceptable thickness variations can be prevented on other wafers on which the modified process is performed, so that wafer thickness variations can be corrected or eliminated in another process performed on the wafer. The computer subsystem can determine such changes in any suitable way known in the art.

[0059] These changes can then be transmitted to a semiconductor manufacturing system (not shown) or a computer subsystem and a storage medium (not shown) accessible to the semiconductor manufacturing system. The semiconductor manufacturing system may be part of or not part of the embodiments of the system described herein. For example, the computer subsystem and / or measurement subsystem described herein may be connected to the semiconductor manufacturing system via one or more common elements such as a housing, power supply, sample handling device or mechanism. The semiconductor manufacturing system may include any semiconductor manufacturing system known in the art, such as sawing tools, edge grinding tools, lapping tools, polishing tools, etc.

[0060] Each of the above-described embodiments of the system can be combined into a single embodiment. In other words, unless otherwise noted herein, no system embodiment is mutually exclusive with any other system embodiment.

[0061] The embodiments described herein offer several advantages for bare wafer measurement over currently used systems and methods. For example, the calibration described herein can significantly improve the accuracy of ESFQR values ​​measured on wafer measurement tools or generally measurement devices using dual Fizeau interferometers. Systematic errors can be reduced by 40% to 70% compared to currently used methods and systems, which leads to much better tool matching performance.

[0062] The advantages provided by the embodiments described herein are made possible by several key differences between the embodiments and currently used methods and systems. For example, the embodiments described herein use twin wafer pairs and multi-angle measurements to generate a thickness correction map that includes tool-specific systematic errors. The embodiments described herein also favorably reduce systematic errors by calibrating the measured thickness map with a tool correction map.

[0063] Another embodiment relates to a computer implementation method for generating a tool correction map. This method includes measuring the surface heights of the front and rear surfaces of first and second calibration wafers at multiple wafer rotation angles using a measurement subsystem (e.g., step 504 in Figure 5). The first and second calibration wafers are low-profile wafers having opposite shapes to each other, as seen by the measurement system (e.g., the wafers in slots 9 and 10, whose shape maps are shown in Figures 4 and 6). The method also includes generating a first ("non-flip") correction map from the measured surface heights of the front and rear surfaces of the first calibration wafer at multiple wafer rotation angles (step 208 in Figure 2). In addition, the method includes generating a second ("flipped") correction map from the measured surface heights of the front and rear surfaces of a second calibration wafer at multiple wafer rotation angles (step 218 in Figure 2). The method further includes the steps of generating a tool correction map (222, Figure 2) by averaging the first and second correction maps (step 220 in Figure 2), and storing the tool correction map for use in calibrating the thickness map of the test wafer generated from the surface heights of the front and rear surfaces of the test wafer measured by the measurement subsystem (step 306 in Figure 3 and step 706 in Figure 7). The steps are performed by a computer subsystem (36, Figure 1), which may be configured according to any embodiment described herein.

[0064] Each step of this method may be performed as further described herein. This method may also include any other steps that can be performed by the measurement subsystem and / or computer subsystem described herein. In addition, the above-described method may be performed by any of the system embodiments described herein.

[0065] Further embodiments relate to a persistent computer-readable medium for storing program instructions executable on a computer system for performing a computer implementation method for generating tool correction maps. One such embodiment is shown in Figure 8. In particular, as shown in Figure 8, the non-temporary computer-readable medium 800 includes program instructions 802 executable on a computer system 804. The computer implementation method may include any step of any method described herein.

[0066] Program instructions 802 implementing methods such as those described herein may be stored on a computer-readable medium 800. The computer-readable medium may be a storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-temporary computer-readable medium known in the art.

[0067] Program instructions can be implemented in any of the following ways, including, among other things, procedure-based techniques, component-based techniques, and / or object-oriented techniques. For example, program instructions may be implemented using ActiveX control, C objects, JavaBeans, Microsoft Foundation Classes ("MFC"), SSE (Streaming SIMD Extension), or other techniques or methodologies, as desired.

[0068] The computer system 804 may be configured according to any of the embodiments described herein.

[0069] Further modifications and alternative embodiments of various aspects of the present invention will be apparent to those skilled in the art in consideration of this description. For example, methods and systems for generating tool correction maps are provided. This description should therefore be interpreted as merely illustrative and is intended to teach those skilled in the art general methods of carrying out the present invention. It should be understood that the forms of the present invention shown and described herein should be interpreted as currently preferred embodiments. As will be apparent to those skilled in the art after benefiting from this description of the present invention, elements and materials may be substituted with those illustrated and described herein, parts and processes may be reversed, and certain attributes of the present invention may be utilized independently. Modifications to the elements described herein may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

1. A system configured to generate tool correction maps, Measurement subsystem, Measurement subsystem and Computer subsystems and Includes, The aforementioned measurement subsystem is The system is configured to measure the surface heights of the front and rear surfaces of the first and second calibration wafers at multiple wafer rotation angles, wherein the first and second calibration wafers are low-profile wafers having opposite shapes to each other when viewed by the measurement subsystem. The aforementioned computer subsystem is A first correction map is generated from the measured surface heights of the front and rear surfaces of the first calibration wafer at multiple wafer rotation angles. A second correction map is generated from the measured surface heights of the front and rear surfaces of the second calibration wafer at multiple wafer rotation angles. A tool correction map is generated by averaging the first and second correction maps. The measurement subsystem stores a tool correction map for use when calibrating the thickness map of the test wafer, which is generated from the surface heights of the front and rear surfaces of the test wafer measured by the aforementioned measurement subsystem. It is configured in such a way. system.

2. The tool correction map includes tool-specific systematic errors. The system according to claim 1.

3. The tool correction map includes tool-specific angle-dependent systematic errors. The system according to claim 1.

4. Averaging the first and second correction maps reduces the dependence of the tool correction maps on the first and second calibration wafers. The system according to claim 1.

5. The aforementioned system is one of several systems, Calibrating the thickness map of a test wafer using the stored tool correction maps of each of the multiple systems improves the consistency between the multiple systems by reducing the systematic errors of each of the multiple systems. The system according to claim 1.

6. The low-profile wafer has a shape where 6σ is less than 9500 nm, and the sum of the shape maps of the first and second calibration wafers is less than 2200 nm. The system according to claim 1.

7. The system according to claim 1, wherein the first and second calibration wafers are standard bare wafers.

8. The system according to claim 1, wherein the computer subsystem is further configured to select the first and second calibration wafers from a single batch of wafers and based on the shape of the wafers within the single batch.

9. The computer subsystem is further configured to select the first and second calibration wafers by determining a differential shape map from different pairs of shape maps of a wafer and selecting one of the different pairs of differential shape maps having 6σ less than 1500 nm. The system according to claim 1.

10. The system according to claim 1, further configured to verify a pair of wafers selected as the first and second calibration wafers by flipping the shape map of one of the wafer pair, determining the sum of the shape maps of the wafer pair, and determining whether the 6σ of the sum of the shape maps of the wafer pair is less than 2200 nm.

11. The aforementioned computer subsystem is A first thickness map of the first calibration wafer is generated from the surface heights of the front and rear surfaces of the first calibration wafer measured at a first wafer rotation angle among multiple wafer rotation angles. An angle-average thickness map of the first calibration wafer is generated from the surface heights of the front and rear surfaces of the first calibration wafer measured at multiple wafer rotation angles. The system is further configured to generate a first correction map by subtracting an angle-average thickness map from the first thickness map. The system according to claim 1.

12. The aforementioned computer subsystem is A first thickness map of the second calibration wafer is generated from the surface heights of the front and rear surfaces of the second calibration wafer measured at a first wafer rotation angle among multiple wafer rotation angles. An angle-average thickness map of the second calibration wafer is generated from the surface heights of the front and rear surfaces of the second calibration wafer measured at multiple wafer rotation angles. The system is further configured to generate a second correction map by subtracting an angle-average thickness map from the first thickness map. The system according to claim 1.

13. The aforementioned computer subsystem further, The system is configured to generate a tool correction map by determining the mean from the averaging result and subtracting the mean from the averaging result. The system according to claim 1.

14. The aforementioned computer subsystem further, The system is configured to calibrate the thickness map of a test wafer by subtracting a stored tool correction map from the aforementioned thickness map, thereby generating a corrected thickness map for the test wafer. The system according to claim 1.

15. The aforementioned measurement subsystem further, The system is configured to measure the surface heights of the front and rear surfaces of the first and second calibration wafers with standard resolution. The system according to claim 1.

16. The aforementioned computer subsystem is The shape maps of the first and second calibration wafers are generated, The system is further configured to display to the user one or more of the shape maps of the first and second calibration wafers, the difference shape map generated from the shape maps of the first and second calibration wafers, and the sum of the shape maps of the first and second calibration wafers. The system according to claim 1.

17. The aforementioned computer subsystem is The system is further configured to calibrate the test wafer's thickness map using a stored tool correction map, calculate the edge surface flatness quotient range (ESFQR) of the test wafer from the calibrated thickness map, and determine additional metrics of the test wafer from the test wafer's thickness map. The system according to claim 1.

18. A computer-readable medium for storing program instructions executable on a computer system for performing a computer implementation method for generating a tool correction map, The aforementioned computer implementation method is A step of measuring the surface heights of the front and rear surfaces of first and second calibration wafers at multiple wafer rotation angles using a measurement subsystem, wherein the first and second calibration wafers are low-profile wafers having opposite shapes to each other when viewed by the measurement subsystem; The steps include generating a first correction map from the measured surface heights of the front and rear surfaces of the first calibration wafer at the plurality of wafer rotation angles, The steps include generating a second correction map from the measured surface heights of the front and rear surfaces of the second calibration wafer at the plurality of wafer rotation angles, A step of generating a tool correction map by averaging the first and second correction maps, The measurement subsystem stores a tool correction map for use when calibrating the thickness map of the test wafer, which is generated from the surface heights of the front and rear surfaces of the test wafer measured by the aforementioned measurement subsystem. Computer-readable media.

19. A computer implementation method for generating a tool correction map, A step of measuring the surface heights of the front and rear surfaces of first and second calibration wafers at multiple wafer rotation angles using a measurement subsystem, wherein the first and second calibration wafers are low-profile wafers having opposite shapes to each other when viewed by the measurement subsystem, A step of generating a first correction map from the measured surface heights of the front and rear surfaces of a first calibration wafer at multiple wafer rotation angles, A step of generating a second correction map from the measured surface heights of the front and rear surfaces of a second calibration wafer at multiple wafer rotation angles, A step of generating a tool correction map by averaging the first and second correction maps, A step of storing a tool correction map for use in calibrating a test wafer thickness map generated from the front and rear surface heights of the test wafer measured by a measurement subsystem, wherein the steps of generating the first correction map, the second correction map, and the tool correction map, and storing the tool correction map are performed by a computer subsystem, Computer implementation methods, including those mentioned above.

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