Shift register unit, gate drive circuit, and display device

Abstract

The shift register unit includes an input circuit that receives a first clock signal and an input signal and provides the input signal to a first node under the control of the first clock signal; a first control circuit that is electrically connected to the first and second nodes, receives the first clock signal, and controls the voltage of the second node under the control of the first clock signal and the voltage of the first node; an output circuit that is electrically connected to the first node and the output terminal, receives the second clock signal, and provides an output signal to the output terminal based on the second clock signal under the control of the voltage of the first node; an output voltage control circuit that is electrically connected to the second node and the output terminal, and controls the voltage of the output signal under the control of the voltage of the second node; and a discharge circuit that is electrically connected to the first and second nodes, receives the second clock signal, and is configured to realize discharge to the first node under the control of the second clock signal and the voltage of the second node.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and more specifically, to a shift register unit, a gate driving circuit including the shift register unit, and a display device including the gate driving circuit.

Background Art

[0002] Thin film transistors are electronic components commonly used in various display devices. The main elements of both a gate driving circuit that provides a gate scanning signal and a pixel circuit that drives each pixel in a display device to emit light include thin film transistors. Currently, commonly used types of thin film transistors include low-temperature polycrystalline thin film transistors, metal oxide thin film transistors, and amorphous silicon thin film transistors, etc. Different types of thin film transistors have their own advantages and problems. For example, compared with the manufacturing process of amorphous silicon thin film transistors, the manufacturing process of low-temperature polycrystalline thin film transistors increases the laser crystallization process and the ion implantation process, changing the amorphous silicon thin film into polycrystalline silicon, thereby significantly improving the electron mobility. By using a low-temperature polycrystalline silicon thin film transistor as a driving element, the brightness of a liquid crystal display can be increased and the power consumption can be reduced. Also, by applying a low-temperature polycrystalline silicon transistor to an organic light-emitting diode display device, high resolution can be achieved. However, the manufacturing process of a display device based on low-temperature polycrystalline silicon thin film transistors is relatively complex, limited by the laser crystallization process, and it is also difficult to realize a large-sized display device. Currently, the circuit structure of the gate driving circuit has room for simplification, and there is room for improvement in the operating performance and output signal of the gate driving circuit.

Summary of the Invention

[0003] Embodiments of the present invention propose a shift register unit comprising: an input circuit configured to receive a first clock signal and an input signal and to provide the input signal to a first node under the control of the first clock signal; a first control circuit electrically connected to the first and second nodes and configured to receive the first clock signal and to control the voltage of the second node under the control of the first clock signal and the voltage of the first node; an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal and to provide an output signal to the output terminal based on the second clock signal under the control of the voltage of the first node; an output voltage control circuit electrically connected to the second node and the output terminal and to control the voltage of the output signal under the control of the voltage of the second node; and a discharge circuit electrically connected to the first and second nodes and configured to receive the second clock signal and to realize discharge to the first node under the control of the second clock signal and the voltage of the second node.

[0004] According to some embodiments of the present application, the input circuit includes a first transistor, the control terminal of the first transistor is electrically connected to a first clock signal terminal to receive the first clock signal, the first pole of the first transistor is electrically connected to an input signal terminal to receive the input signal, and the second pole of the first transistor is electrically connected to the first node.

[0005] According to some embodiments of the present application, the first control circuit includes a second transistor and a third transistor, wherein the control terminal of the second transistor is electrically connected to a first clock signal terminal to receive the first clock signal, the first pole of the second transistor is electrically connected to a first reference voltage terminal, the second pole of the second transistor is electrically connected to the second node, the control terminal of the third transistor is electrically connected to the first node, the first pole of the third transistor is electrically connected to the first clock signal terminal, and the second pole of the third transistor is electrically connected to the second node.

[0006] According to some embodiments of the present invention, the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and the second pole of the fourth transistor is electrically connected to the output terminal.

[0007] According to some embodiments of the present invention, the output voltage control circuit includes a fifth transistor, the control terminal of the fifth transistor is electrically connected to the second node, the first pole of the fifth transistor is electrically connected to the second reference voltage terminal, and the second pole of the fifth transistor is electrically connected to the output terminal.

[0008] According to some embodiments of the present application, the discharge circuit includes a sixth transistor and a seventh transistor, the sixth transistor and the seventh transistor being connected in series with each other between the first node and the third reference voltage terminal, the control terminal of the sixth transistor being electrically connected to the second clock signal terminal to receive the second clock signal, and the control terminal of the seventh transistor being electrically connected to the second node.

[0009] According to some embodiments of the present invention, the shift register unit further includes a node voltage limiting circuit, the node voltage limiting circuit being electrically connected to the first node and the signal input terminal of the output circuit, and the node voltage limiting circuit being configured to limit the amplitude of the voltage at the first node.

[0010] According to some embodiments of the present invention, the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and the second pole of the fourth transistor is electrically connected to the output terminal; the node voltage limiting circuit includes an eighth transistor, the first and second poles of the eighth transistor are electrically connected to the control terminals of the first node and the fourth transistor, respectively, and the control terminal of the eighth transistor is configured to receive a fourth reference voltage and turn on the eighth transistor.

[0011] According to some embodiments of the present application, the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, and the second pole of the fourth transistor is electrically connected to the output terminal; the node voltage limiting circuit includes a ninth transistor, the first pole and control terminal of the ninth transistor are electrically connected to the first node, respectively, and the second pole of the ninth transistor is electrically connected to a fifth reference voltage terminal to receive the fifth reference voltage.

[0012] According to some embodiments of the present invention, the output voltage control circuit further includes a first capacitor electrically connected between the first pole of the fifth transistor and the control terminal of the fifth transistor.

[0013] According to some embodiments of the present application, the output circuit further includes a second capacitor electrically connected between the output terminal and the control terminal of the fourth transistor.

[0014] According to some embodiments of the present application, the output voltage control circuit further includes a tenth transistor, the first and second poles of the tenth transistor being connected to the control terminals of the first node and the fifth transistor, respectively, and the control terminals of the tenth transistor being configured to receive a sixth reference voltage and turn on the tenth transistor.

[0015] According to some embodiments of the present application, the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the eighth transistor.

[0016] Another embodiment of the present invention provides a gate drive circuit which includes a plurality of shift register units described in any of the above embodiments, connected in a cascade.

[0017] Another embodiment of the present application provides a display device which includes the gate drive circuit described in the above embodiment.

[0018] The embodiments described below will clarify these and other advantages of the present application, and these and other advantages of the present application will be explained with reference to the embodiments described below. [Brief explanation of the drawing]

[0019] Here, embodiments of the present application will be described in more detail with reference to the drawings.

[0020] [Figure 1] Figure 1 shows a schematic diagram of a circuit module in a shift register unit according to one embodiment of the present invention. [Figure 2] Figure 2 shows a schematic diagram of the circuit principle of a shift register unit according to one embodiment of the present invention. [Figure 3] Figure 3 shows the signal timing diagram for the shift register unit shown in Figure 2. [Figure 4] Figure 4 shows a schematic diagram of a circuit module in a shift register unit according to another embodiment of the present invention. [Figure 5]FIG. 5 shows a circuit principle schematic diagram of a shift register unit according to another embodiment of the present application. [Figure 6] FIG. 6 shows a circuit principle schematic diagram of a shift register unit according to another embodiment of the present application. [Figure 7] FIG. 7 shows a circuit principle schematic diagram of a shift register unit according to another embodiment of the present application. [Figure 8] FIG. 8 shows a circuit principle schematic diagram of a shift register unit according to another embodiment of the present application. [Figure 9] FIG. 9 shows a circuit principle schematic diagram of a shift register unit according to another embodiment of the present application. [Figure 10] FIG. 10 is used to show the elapsed time of the level change of the output signal of the shift register unit shown in FIG. 5 or FIG. 6. [Figure 11] FIG. 11 shows a circuit principle schematic diagram of a shift register unit according to yet another embodiment of the present application. [Figure 12] FIG. 12 shows the voltage waveforms of related nodes and the waveform of the output signal when the shift register unit shown in FIG. 9 operates. [Figure 13] FIG. 13 shows the voltage waveforms of related nodes and the waveform of the output signal when the shift register unit shown in FIG. 11 operates. [Figure 14] FIG. 14 shows a plurality of cascade-connected shift register units in a gate driving circuit according to another embodiment of the present application. [Figure 15] FIG. 15 shows an example of the layout of the bottom gate of each transistor in the shift register unit shown in FIG. 9. [Figure 16] FIG. 16 shows a partial plan view of the shift register unit obtained after forming a semiconductor layer, a top gate, and a signal connection layer on each bottom gate shown in FIG. 15. [Figure 17] FIG. 17 shows an example of the layout of the bottom gate of each transistor in the shift register unit shown in FIG. 11. [Figure 18]Figure 18 shows a partial plan view of the shift register unit obtained after forming a semiconductor layer, a top gate, and a signal connection layer on each bottom gate shown in Figure 17. [Modes for carrying out the invention]

[0021] The description below provides specific details of various embodiments of the present application, thereby enabling those skilled in the art to fully understand and implement these embodiments. In some cases, the present application does not illustrate or describe in detail some structures or functions that are well known in the art, thereby avoiding that such unnecessary descriptions would obscure the description of the embodiments of the present application. The technical solutions of the present application can be embodied in many different forms and purposes and should not be limited to the embodiments described herein. These embodiments are provided for clarity and completeness of the technical solutions of the present application, but such embodiments do not limit the scope of protection of this patent application.

[0022] Here, we will first explain some of the terms related to the embodiments of this application in order to facilitate understanding for those skilled in the art.

[0023] As used herein, “control terminal” refers to the gate of a transistor for receiving a scanning signal, and the transistor can be on or off under the control of the signal received by its control terminal; “first pole” refers to one of the two terminals of a transistor excluding the control terminal; and “second pole” refers to the other of the two terminals of a transistor excluding the control terminal. That is, the first pole may be either the source or the drain of the transistor, and the second pole may be the other of the source or the drain of the transistor. As used herein, “display device” may be an assembled display product with image display functionality, or a component of a complete display product, the component of which includes the gate drive circuit described in the embodiments of this application.

[0024] Figure 1 illustrates an exemplary topology of a shift register unit according to an embodiment of the present invention. As shown in Figure 1, the shift register unit includes an input circuit 101, a first control circuit 102, an output circuit 103, an output signal control circuit 104, and a discharge circuit 105. The input circuit 101 is configured to receive a first clock signal CK1 and an input signal IN and to provide the input signal IN to a first node N1 under the control of the first clock signal CK1. The first control circuit 102 is electrically connected to the first node N1 and the second node N2 and is configured to receive the first clock signal CK1 and to control the voltage of the second node N2 under the control of the first clock signal CK1 and the voltage of the first node N1. The output circuit 103 is electrically connected to the first node N1 and the output terminal of the shift register unit and is configured to receive a second clock signal CK2. The output signal control circuit 104 is configured to provide an output signal OUT to the output terminal based on the second clock signal CK2 under the control of the voltage of the first node N1, and the output signal control circuit 104 is electrically connected to the second node N2 and the output terminal and controls the voltage of the output terminal under the control of the voltage of the second node N2, and the discharge circuit 105 is electrically connected to the first node N1 and the second node N2 and is configured to receive the second clock signal CK2 and to realize discharge to the first node N1 under the control of the second clock signal CK2 and the voltage of the second node N2.

[0025] The shift register unit shown in Figure 1 receives an input signal IN, a first clock signal CK1, and a second clock signal CK2, and can output an output signal OUT with an expected pulse level to the output terminal. The input signal IN can be provided periodically, and accordingly, the output signal OUT with an expected pulse level can be output periodically from the output terminal. In each cycle, after the output signal OUT with an expected pulse level is output from the output terminal, the discharge circuit 105 can perform a discharge operation on the first node N1 before the next cycle, thereby removing the charge accumulated in the first node and improving the accuracy of control over the output circuit 103 in the next cycle. Each circuit module in the shift register unit shown in Figure 1 can be realized based on metal oxide thin-film transistors, has a simple circuit configuration, and can be applied to the gate drive circuit of an organic light-emitting diode display device, providing a scanning drive signal to the drive element in the pixel circuit of an organic light-emitting diode display device.

[0026] The embodiments of the shift register unit will be further described below with specific examples. Figure 2 shows an example of a circuit principle diagram of the shift register unit. As shown in Figure 2, the input circuit may include a first transistor T1, the control terminal of the first transistor is electrically connected to a first clock signal input terminal to receive a first clock signal CK1, the first pole of the first transistor T1 is electrically connected to an input signal terminal to receive an input signal IN, and the second pole of the first transistor T1 is electrically connected to a first node N1. As a result, the first transistor T1 can provide the input signal IN to the first node N1 under the control of the first clock signal CK1. The first control circuit may include a second transistor T2 and a third transistor T3. The control terminal of the second transistor T2 is electrically connected to a first clock signal terminal to receive the first clock signal CK1. The first pole of the second transistor T2 is electrically connected to a first reference voltage terminal to receive the first reference voltage V1. The second pole of the second transistor T2 is electrically connected to a second node N2. The control terminal of the third transistor T3 is electrically connected to a first node N1. The first pole of the third transistor T3 is electrically connected to a first clock signal terminal to receive the first clock signal CK1. The second pole of the third transistor T3 is electrically connected to a second node N2. The output circuit includes a fourth transistor T4. The control terminal of the fourth transistor T4 is electrically connected to a first node N1. The first pole of the fourth transistor T4 is electrically connected to a second clock signal terminal to receive the second clock signal CK2. The second pole of the fourth transistor T4 is electrically connected to an output terminal. As a result, the fourth transistor T4 can output an output signal OUT from its output terminal based on the change in the second clock signal CK2 under the control of the first node N1. The output voltage control circuit includes a fifth transistor T5, the control terminal of which is electrically connected to the second node N2, the first pole of which is electrically connected to the second reference voltage terminal to receive the second reference voltage V2, and the second pole of which is electrically connected to the output terminal. Thus, the output voltage control circuit can control the voltage at the output terminal via the fifth transistor and generate the expected pulse signal at the output terminal.The discharge circuit 105 includes a sixth transistor T6 and a seventh transistor T7. As shown in Figure 2, the sixth transistor T6 and the seventh transistor T7 are connected in series with each other between the first node N2 and the third reference voltage terminal. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal to receive the second clock signal CK2, and the control terminal of the seventh transistor is electrically connected to the second node N2. The first pole of the seventh transistor T7 is electrically connected to the third reference voltage terminal to receive the third reference voltage, the second pole of the seventh transistor T7 is electrically connected to the first pole of the sixth transistor T6, and the second pole of the sixth transistor T6 is electrically connected to the first node N1. As a result, the sixth transistor T6 and the seventh transistor T7 in the discharge circuit can achieve discharge to the first node N1 under the control of the second clock signal CK2 and the voltage of the second node N2.

[0027] Next, the operating principle of the shift register unit shown in Figure 2 will be explained in detail with a specific example. Figure 3 shows examples of input signals, a first clock signal and a second clock signal provided to the shift register unit shown in Figure 2, and examples of output signals at the output terminals of the shift register unit, the voltage at the first node and the voltage at the second node. To ensure that it is clear that the waveform diagrams shown in Figure 3 are merely to illustrate the operating principle of the shift register unit shown in Figure 2, and do not represent the actual waveforms during operation of the shift register unit shown in Figure 2.

[0028] As shown in Figure 3, the operating cycle of the shift register unit shown in Figure 2 may include four time zones P1 to P4. In this example, the transistors (first to seventh transistors) in each circuit module shown in Figure 2 are all N-type transistors, the first reference voltage V1 is a high-level signal, and the second reference voltage V2 and third reference voltage V3 are both low-level signals. During the first time zone P1 period, the input signal IN and the first clock signal CK1 change from low level to high level, and the second clock signal CK2 changes from high level to low level. Accordingly, the first transistor T1 and the second transistor T2 turn on, and the voltage at the first node N1 and the voltage at the second node are both high level. As a result, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 all turn on, the second clock signal CK2 and the second reference voltage V2 are both low level, and therefore the output signal OUT at the output terminal remains low level. Furthermore, because the second clock signal CK2 is at a low level, the sixth transistor T6 is in the off state, and the voltage at the first node N1 is not affected by the third reference voltage V3 at this time. During the second time period P2, the input signal IN and the first clock signal CK1 change from a high level to a low level, and the second clock signal CK2 changes from a low level to a high level. Accordingly, both the first transistor T1 and the second transistor T2 are in the off state, and because of the inter-electrode capacitance of the fourth transistor, the voltage at the first node N1 can be maintained at a high level, and therefore the third transistor T3 can be maintained at the on state, changing the voltage at the second node N2 from a high level to the level of the first clock signal CK1 (i.e., a low level), thereby keeping the fifth transistor T5 and the seventh transistor T7 in the off state, and the fourth transistor T4 can be maintained at the on state. Therefore, the output signal OUT at the output terminal of the shift register unit is determined solely by the second clock signal CK2 at this time, and as shown in Figure 3, the output signal OUT changes from a low level to a high level. Furthermore, because the seventh transistor is in the off state, the voltage at the first node N1 is not affected by the third reference voltage V3.In the third time zone P3, the input signal IN remains at a low level, the first clock signal CK1 changes from a low level to a high level, and the second clock signal CK2 changes from a high level to a low level. Accordingly, both the first transistor T1 and the second transistor T2 are ON, the voltage at the first node N1 changes to a low level, and the voltage at the second node N2 becomes high. Therefore, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are OFF, and the fifth transistor T5 is ON. The output signal OUT of the shift register unit is determined by the second reference voltage V2 at this time, and therefore the output signal OUT remains at a low level. The voltage at the first node N1 is not affected by the third reference voltage V3. In the fourth time zone P4, the input signal IN remains at a low level, the first clock signal CK1 changes from a high level to a low level, and the second clock signal CK2 changes from a low level to a high level. Accordingly, the first transistor T1 and the second transistor T2 are in the off state, the second node N2 maintains a high level due to the inter-electrode capacitance of the fifth transistor, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in the on state, the first node N1 maintains the previous low level, the fourth transistor T4 and the third transistor T3 are in the off state, the first node N1 forms a path to the third reference voltage terminal via the sixth transistor T6 and the seventh transistor T7, that is, the sixth transistor T6 and the seventh transistor T7 can form a discharge path to the first node N1, allowing sufficient discharge of charge on the first node N1, which is advantageous for achieving precise control of the on and off states of the fourth transistor T4 within the next cycle period and is advantageous for improving the accuracy of the pulse waveform of the acquired output signal. In this way, within a single cycle period including the four time zones P1 to P4 described above, the shift register unit generates a high-level pulse output signal OUT at its output terminal, as shown in Figure 3. In the embodiment shown in Figure 2, to enhance the stability of the voltage N2 at the second node, the shift register unit further includes a first capacitor C1 electrically connected between the first pole of the fifth transistor T5 and the second node N2.

[0029] Figure 4 shows a structural block diagram of a shift register unit according to another embodiment of the present invention. In addition to the circuit modules in the shift register unit shown in Figure 1, the shift register unit shown in Figure 4 further includes a node voltage limiting circuit 106, which is electrically connected to the signal input terminals of the first node N1 and the output circuit 103, and is configured to limit the amplitude of the voltage at the first node N1. In this embodiment, the node voltage limiting circuit 106 can mitigate or avoid the impact on the voltage at the first node N1 due to potential voltage fluctuations (e.g., voltage spikes) occurring in the output circuit 103, thereby promoting the stabilization of the voltage at the first node N1, which is advantageous in protecting the transistor electrically connected to the first node N1, slowing the degradation of the transistor electrically connected to the first node N1, or reducing the threshold voltage drift of the associated transistor.

[0030] Figure 5 shows a circuit diagram of a shift register unit according to another embodiment of the present invention. As shown in Figure 5, the node voltage limiting circuit 106 of the shift register unit includes an eighth transistor T8, and the output circuit includes a fourth transistor T4. The first and second poles of the eighth transistor T8 are electrically connected to the control terminals of the first node N1 and the fourth transistor T4, respectively, and the control terminals of the eighth transistor T8 are configured to receive a fourth reference voltage V4 and turn on the eighth transistor T8. The first pole of the fourth transistor T4 is electrically connected to the second clock signal terminal to receive the second clock signal CK2, and the second pole of the fourth transistor T4 is electrically connected to the output terminal of the shift register unit. In the shift register unit shown in Figure 5, when the shift register unit is in operation, the eighth transistor T8 is always in the on state, and if the eighth transistor T8 is an N-type transistor, the fourth reference voltage V4 is a constant high-level signal.

[0031] Returning to the embodiment shown in Figure 2, when a sudden surge occurs in the voltage level of the output signal OUT of the shift register unit due to the inter-electrode capacitance of the fourth transistor T4, a sudden surge also occurs in the potential of the first node N1. This may be detrimental to the third transistor T3, sixth transistor T6, and first transistor T1, which are electrically connected to the first node N1. In particular, the threshold shift of the third transistor T3 may be shifted due to the excessively high voltage at the first node N1. On the other hand, in the embodiment shown in Figure 5, the eighth transistor T8, which is in the ON state, can function as a buffer for the voltage at the first node N1. Even if the voltage amplitude of the output signal OUT of the shift register unit surges, the amplitude of the voltage at the first node N1 is also limited, thereby reducing the influence of the output signal of the output circuit on the voltage at the first node N1. Therefore, the first transistor T1, third transistor T3, and sixth transistor T6, which are electrically connected to the first node N1, can avoid the adverse effects of the sudden surge in high voltage.

[0032] Figure 6 shows a circuit diagram of a shift register unit according to another embodiment of the present invention. As shown in Figure 6, the node voltage limiting circuit 106 of the shift register unit includes a ninth transistor T9, the first pole and control terminal of the ninth transistor T9 are electrically connected to the first node N1, and the second pole of the ninth transistor T9 is electrically connected to the fifth reference voltage terminal to receive the fifth reference voltage V5. In this embodiment, when the voltage of the first node N1 increases sharply due to the influence of the output signal of the shift register unit, for example, when the voltage of the first node N1 exceeds the threshold voltage of the ninth transistor T9, the ninth transistor T9 turns on, thereby pulling down the voltage of the first node N1 to the fifth reference voltage V5. The fifth reference voltage V5 may be a voltage with a constant amplitude, and the amplitude of the fifth reference voltage V5 may be set close to the amplitude of a high-level pulse of the input signal IN. Thus, the node voltage limiting circuit 106 in the embodiment shown in Figure 6 can similarly play a role in appropriately limiting the amplitude of the voltage of the first node N1.

[0033] According to some embodiments of the present invention, the output voltage control circuit 104 of the shift register unit further includes a first capacitor C1 electrically connected between the first pole of the fifth transistor T5 and the control terminal of the fifth transistor T5. As shown in Figures 2, 5, and 6, the first capacitor C1 is connected between the control terminal and the first pole of the fifth transistor T5, thereby improving the voltage stability of the first node N2 and being advantageous for achieving rapid control of the fifth transistor T5.

[0034] As shown in Figure 7, according to another embodiment of the present invention, the output circuit of the shift register unit further includes a second capacitor C2 electrically connected between the output terminal of the shift register unit and the control terminal of the fourth transistor T4. The embodiment shown in Figure 7 is advantageous for applying the shift register unit to a high-resolution display device because the second capacitor C2 can improve the on-rate of the fourth transistor T4 in the output circuit, or reduce the switching time between the off and on states of the fourth transistor T4, thereby enabling the shift register unit to generate a larger output current.

[0035] Figure 8 shows a circuit diagram of a shift register unit according to yet another embodiment of the present invention. Similar to the embodiment shown in Figure 7, in this embodiment the output circuit of the shift register unit includes a second capacitor C2 connected between the control terminal of the fourth transistor T4 and the output terminal of the shift register unit. The shift register unit further includes a node voltage limiting circuit 106, and the fourth transistor T4, the second capacitor C2, and the eighth transistor T8 in the node voltage limiting circuit 106 are jointly electrically connected to the third node N3. This is advantageous not only for the rapid turning on of the fourth transistor T4 in the output circuit, but also for reducing the impact of potential voltage fluctuations (e.g., voltage spikes) occurring in the output circuit 103 on the voltage of the first node N1 by the node voltage limiting circuit 106, thereby promoting voltage stabilization of the first node N1 and protecting the transistor elements electrically connected to the first node N1.

[0036] In another embodiment of the present invention, the output voltage control circuit of the shift register unit further includes a tenth transistor, the first and second poles of the tenth transistor being connected to the control terminals of the second node and the fifth transistor, respectively, and the control terminal of the tenth transistor being configured to receive a sixth reference voltage and turn on the tenth transistor. Figure 9 shows a circuit diagram of the shift register unit according to this embodiment. In the embodiment of Figure 9, the tenth transistor T10 is an N-type metal oxide transistor, and the sixth reference voltage V6 may be a high-level signal with a constant voltage. The tenth transistor T10, the first capacitor C1, and the fifth transistor T5 are jointly connected to the fourth node N4. The tenth transistor T10 can function as a buffer between the second node N2 and the fourth node N4, mitigating or avoiding adverse effects on the voltage of the other node due to a sudden voltage change at one of the two nodes. Furthermore, experimental studies have shown that the installation of the tenth transistor T10 is advantageous in reducing the elapsed time during which the output signal OUT of the shift register unit changes between different levels. The waveform changes of the output signal OUT of the shift register unit are illustrated below with reference to Figure 10. Figure 10 is used to show the elapsed time of the level change of the output signal of the shift register unit shown in Figure 5 or Figure 6. As shown in Figure 10, in the actual operation of the shift register unit, the output signal OUT at its output terminal is not a regular square wave pulse as shown in Figure 3, but rather an almost trapezoidal pulse as shown in Figure 10. In other words, both the change from a low level to a high level and the change from a high level to a low level of the output signal OUT require a certain amount of time to pass. In Figure 10, Ta indicates the elapsed time for the output signal OUT to change from a low level to a high level, and Tb indicates the elapsed time for the output signal OUT to change from a high level to a low level. The smaller the times Ta and Tb, the higher the quality of the output signal OUT of the shift register unit.Compared to the shift register unit shown in Figure 2, the shift register unit shown in Figure 9 incorporates a 10th transistor T10 in the output voltage control circuit, thereby reducing the elapsed time Ta during which the output signal OUT changes from a low level to a high level and the elapsed time Tb during which the output signal OUT changes from a high level to a low level, as shown in Figure 10. In other words, it improves the quality of the output signal of the shift register unit.

[0037] Figure 11 shows a circuit diagram of a shift register unit according to yet another embodiment of the present invention. In this embodiment, the shift register unit includes a node voltage limiting circuit, which includes a ninth transistor T9, the first pole and control terminal of the ninth transistor T9 being electrically connected to the first node N1, and the second pole of the ninth transistor T9 being electrically connected to the fifth reference voltage terminal to receive the fifth reference voltage V5. The output voltage control circuit includes a fifth transistor T5, a tenth transistor T10, and a first capacitor C1, the first and second poles of the tenth transistor T10 being connected to the second node N2 and the control terminal of the fifth transistor, respectively, and the control terminal of the tenth transistor T10 receiving the sixth reference voltage V6 to turn on the tenth transistor T10. In this embodiment, when a sudden increase in voltage occurs at the first node N1, the ninth transistor T9 can play a role in appropriately limiting the voltage amplitude at the first node N1. For example, when the voltage at the first node N1 exceeds the threshold voltage of the ninth transistor T9, the ninth transistor T9 turns on, thereby pulling down the voltage at the first node N1 to the fifth reference voltage V5. The fifth reference voltage V5 may be a voltage with a constant amplitude, and the amplitude of the fifth reference voltage V5 may be set close to the amplitude of the high-level pulse of the input signal IN. Furthermore, by installing a tenth transistor T10 in the output voltage control circuit, the quality of the output signal of the shift register unit can be improved.

[0038] Next, Figures 12 and 13 illustrate the differences in the associated nodes and output signals in the shift register unit described in the above different embodiments. Figure 12 shows the voltage waveforms of the associated nodes and output signals when the shift register unit of the embodiment shown in Figure 9 is operating. Figure 13 shows the voltage waveforms of the associated nodes and output signals when the shift register unit of the embodiment shown in Figure 11 is operating. As shown in Figure 12, the input signal, first clock signal, and second clock signal provided to the shift register unit are identified as IN, CK1, and CK2, respectively. The waveforms corresponding to SN1 and SN2 in Figure 12 show the voltage waveforms of the first node N1 and the second node N2 in Figure 9, respectively. As can be seen from Figure 12, there is one obvious spike in the voltage SN1 of the first node N1 during the time period corresponding to the high-level pulse of the output signal OUT, which may be affecting the voltage of the first node N1 due to the output signal OUT changing from a low level to a high level. A sharp increase in the voltage SN1 at the first node N1 could be detrimental to the operating life of the third transistor T3, the sixth transistor T6, and the first transistor T1, and could consequently cause a shift in the threshold voltage of the third transistor T3. As shown in Figure 13, for the shift register unit shown in Figure 11, the presence of a node voltage limiting circuit (ninth transistor T9) means that the voltage SN1 at the first node N1 remains fundamentally stable even during periods of high pulse levels in the output signal OUT, and the voltage surge phenomenon shown in Figure 12 does not occur. Furthermore, as can be seen from Figures 12 and 13, the time elapsed when the output signal OUT switches between high and low levels is relatively short; that is, the rising and falling edges of the high-level pulses of the output signal OUT both show a tendency to change at near right angles, and the output signal OUT has a high-quality pulse waveform, which is mainly due to the tenth transistor T10 in the output voltage control circuit of the shift register unit.

[0039] The shift register units described in each of the above embodiments can be applied to a display device, and the output signals generated by the shift register units can be used as scanning signals for pixel circuits used in the display device. Accordingly, another embodiment of the present application provides a gate drive circuit which includes a plurality of shift register units described in any of the above embodiments, cascaded together. Cascading, as referred to herein, means that a plurality of shift register units are connected in a series, and the output signal of an earlier shift register unit becomes the input signal of a later shift register unit. Figure 14 illustrates four cascaded shift register units. Each shift register unit includes an input signal terminal for receiving an input signal IN, an output signal terminal for providing an output signal OUT, a first clock signal input terminal for receiving a first clock signal CK1, and a second clock signal input terminal for receiving a second clock signal CK2. For simplicity, the reference voltage terminals of each shift register unit for receiving each reference voltage are not shown in Figure 14. The first clock signal input terminal and the second clock signal input terminal of each shift register unit can be electrically connected to the first clock signal line CL1 and the second clock signal line CL2, respectively. Figure 14 shows four cascaded shift register units, but the gate drive circuit used in the display device may include any number of shift register units, and the embodiments of this application are not limited thereto. Furthermore, although each circuit module in the example circuit diagram for the shift register unit of this application is implemented using N-type transistors, this does not limit the scope of protection of this application, and according to the embodiments disclosed hereof, a circuit module implemented using P-type transistors is an obvious variation of the embodiments disclosed hereof and falls within the scope of protection of this patent application.

[0040] Further embodiments of the present application provide a display device which may include the gate drive circuit described in the above embodiments. As previously discussed herein, the “display device” referred to herein may be an assembled display product having an image display function, or it may be a component of a complete display product. For example, an example of a display device may include an array board of gate drive circuits, a display panel, and a finished display device shipped for sale.

[0041] In some embodiments, each transistor (e.g., the first to tenth transistors) in the shift register unit described with reference to each drawing may include a dual-gate transistor, that is, each transistor may include a bottom gate, a top gate, and a semiconductor or active layer located between the bottom gate and the top gate. Thus, the performance of the transistor can be adjusted by controlling the voltage applied to the bottom gate, and the transistor is on or off in response to its top gate receiving different signals. Figure 15 shows an example of the layout of the bottom gates of each transistor in the shift register unit shown in Figure 9. Referring to Figures 9 and 15, the fourth transistor T4 and the fifth transistor T5 include bottom gates GB4 and GB5, respectively, and the bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 are connected to each other. As can be seen from Figure 15, the bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 both include a plurality of elongated electrodes connected to each other, which is advantageous in realizing that the channels of the fourth transistor T4 and the fifth transistor T5 have a large aspect ratio. The bottom gates GB1 of the first transistor T1, GB2 of the second transistor T2, and GB3 of the third transistor T3 are connected to each other, and the bottom gates GB6 of the sixth transistor T6, GB7 of the seventh transistor T7, and GB10 of the tenth transistor T10 are connected to each other. The lengths of the bottom gates of the first transistor T1, second transistor T2, third transistor T3, sixth transistor T6, seventh transistor T7, and tenth transistor T10 are clearly shorter than the bottom gates of the fourth transistor T4 and fifth transistor T5. The bottom gates of each of the above transistors can be formed on a base substrate, which can support the structures necessary for each element of the shift register unit to operate correctly.In some embodiments, after forming the bottom gate of each transistor on a base substrate, a semiconductor layer (active layer) used for each transistor, a top gate used for each transistor located on the semiconductor layer, and a signal connection layer on the top gate can be formed on the bottom gate.

[0042] Figure 16 shows a partial plan view of a shift register unit obtained after forming semiconductor layers, top gates, and signal connection layers on each bottom gate shown in Figure 15. Referring to Figures 9 and 16, the top gates of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and tenth transistor T10 are identified as GT1, GT2, GT3, GT4, GT5, GT6, GT7, and GT10, respectively. Figure 16 further shows clock signal lines CKA and CKB for transmitting the first and second clock signals, a reference signal line VGH for receiving a constant high level, and a reference signal line VGL for receiving a constant low level. In some embodiments, the reference signal line VGH can transmit the first reference voltage V1 and sixth reference voltage V6 shown in Figure 9, and the reference signal line VGL can transmit the second reference voltage V2 and third reference voltage V3 shown in Figure 9. Other metal electrodes can be formed on the base substrate, and these other metal electrodes can be paired with the top gates of the fourth transistor T4 and the fifth transistor T5, respectively, to form the first capacitor C1 and the second capacitor C2 shown in Figure 9. As can be seen from Figures 15 and 16, for each transistor in the shift register unit, the aspect ratio of the channel of either the fourth transistor or the fifth transistor is greater than the aspect ratio of the channels of the other transistors in the shift register unit, thereby allowing the fourth and fifth transistors to have higher switching speeds, which is advantageous in improving the quality of the output signal of the shift register unit.

[0043] Figure 17 shows an example of the bottom gate layout of each transistor in the shift register unit shown in Figure 11. Referring to Figures 11 and 17, the fourth transistor T4 and the fifth transistor T5 include bottom gates GB4 and GB5, respectively, with the bottom gate GB4 of the fourth transistor T4 and the bottom gate GB5 of the fifth transistor T5 connected to each other. The bottom gates GB1 of the first transistor T1, GB2 of the second transistor T2, GB3 of the third transistor T3, and GB9 of the ninth transistor are connected to each other, and the bottom gates GB6 of the sixth transistor T6, GB7 of the seventh transistor T7, and GB10 of the tenth transistor T10 are connected to each other. The lengths of the bottom gates of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are clearly shorter than the bottom gates of the fourth transistor T4 and the fifth transistor T5.

[0044] Figure 18 shows a partial plan view of a shift register unit obtained after forming semiconductor layers, top gates, and signal connection layers on each bottom gate shown in Figure 17. Referring to Figures 11 and 18, the top gates of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, ninth transistor T9, and tenth transistor T10 are identified as GT1, GT2, GT3, GT4, GT5, GT6, GT7, GT9, and GT10, respectively. Figure 18 shows clock signal lines CKA and CKB for transmitting the first and second clock signals, a reference signal line VGH for receiving a constant high level, and a reference signal line VGL for receiving a constant low level. In some embodiments, the reference signal line VGH can transmit the first reference voltage V1, fifth reference voltage V5, and sixth reference voltage V6 shown in Figure 11, and the reference signal line VGL can transmit the second reference voltage V2 and third reference voltage V3 shown in Figure 11. As can be seen from Figures 17 and 18, for each transistor in the shift register unit, the aspect ratio of either the fourth or fifth transistor's channel is greater than the aspect ratio of the other transistors' channels in the shift register unit. This allows the fourth and fifth transistors to have higher switching speeds, which is advantageous in improving the quality of the output signal of the shift register unit.

[0045] To ensure understanding, terms such as the first, second, third, etc., may describe various devices, elements, components, or parts in this specification, but should not be limited to these devices, elements, components, or parts; they are merely for distinguishing names. For example, the first to seventh subpackage structures are used solely to distinguish the names of subpackage structures in different embodiments of the power amplifier. Also, "electrical connection" as used herein includes "direct connection" or "indirect connection." Although several embodiments have been combined to illustrate the technical solutions of this application, the scope of protection of this application is not limited to the specific forms described herein, and the scope of this application is defined by the appended claims. [Explanation of Symbols]

[0046] 101 Input Circuit 102 First Control Circuit 103 Output Circuit 104 Output signal control circuit 105 Discharge circuit 106-node voltage limiting circuit C1 First capacitor C2 Second capacitor CK1 First clock signal CK2 Second clock signal CKA Clock Signal Line CKB Clock signal line CL1 First Clock Signal Line CL2 Second Clock Signal Line GB1~10 Bottom Gate N1~4 Nodes 1~4 T1-10 Transistors 1-10 V1-6 1st-6th Reference Voltages

Claims

1. It is a shift register unit, An input circuit configured to receive a first clock signal and an input signal, and to provide the input signal to a first node under the control of the first clock signal, A first control circuit is electrically connected to the first node and the second node and is configured to receive the first clock signal and control the voltage of the second node under the control of the first clock signal and the voltage of the first node. An output circuit is electrically connected to the first node and the output terminal, and is configured to receive a second clock signal and provide an output signal to the output terminal based on the second clock signal under the control of the voltage of the first node. An output voltage control circuit is electrically connected to the second node and the output terminal and controls the voltage of the output signal under the control of the voltage of the second node, A shift register unit characterized by including a discharge circuit that is electrically connected to the first node and the second node, and is configured to receive the second clock signal and to perform a discharge to the first node under the control of the second clock signal and the voltage of the second node.

2. The shift register unit according to claim 1, wherein the input circuit includes a first transistor, the control terminal of the first transistor is electrically connected to a first clock signal terminal to receive the first clock signal, the first pole of the first transistor is electrically connected to an input signal terminal to receive the input signal, and the second pole of the first transistor is electrically connected to the first node.

3. The shift register unit according to claim 1, wherein the first control circuit includes a second transistor and a third transistor, the control terminal of the second transistor is electrically connected to a first clock signal terminal to receive the first clock signal, the first pole of the second transistor is electrically connected to a first reference voltage terminal, the second pole of the second transistor is electrically connected to the second node, the control terminal of the third transistor is electrically connected to the first node, the first pole of the third transistor is electrically connected to the first clock signal terminal, and the second pole of the third transistor is electrically connected to the second node.

4. The shift register unit according to claim 1, wherein the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, and the second pole of the fourth transistor is electrically connected to the output terminal.

5. The shift register unit according to claim 1, wherein the output voltage control circuit includes a fifth transistor, the control terminal of the fifth transistor is electrically connected to the second node, the first pole of the fifth transistor is electrically connected to the second reference voltage terminal, and the second pole of the fifth transistor is electrically connected to the output terminal.

6. The shift register unit according to claim 1, wherein the discharge circuit includes a sixth transistor and a seventh transistor, the sixth transistor and the seventh transistor are connected in series with each other between the first node and the third reference voltage terminal, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal to receive the second clock signal, and the control terminal of the seventh transistor is electrically connected to the second node.

7. The shift register unit according to claim 1, further comprising a node voltage limiting circuit, wherein the node voltage limiting circuit is electrically connected to the signal input terminals of the first node and the output circuit, and the node voltage limiting circuit is configured to limit the amplitude of the voltage of the first node.

8. The shift register unit according to claim 7, wherein the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, the second pole of the fourth transistor is electrically connected to the output terminal, and the node voltage limiting circuit includes an eighth transistor, the first and second poles of the eighth transistor are electrically connected to the control terminals of the first node and the fourth transistor, respectively, and the control terminal of the eighth transistor is configured to receive a fourth reference voltage and turn on the eighth transistor.

9. The shift register unit according to claim 7, characterized in that the output circuit includes a fourth transistor, the control terminal of the fourth transistor is electrically connected to the first node, the first pole of the fourth transistor is electrically connected to a second clock signal terminal to receive the second clock signal, the second pole of the fourth transistor is electrically connected to the output terminal, the node voltage limiting circuit includes a ninth transistor, the first pole and control terminal of the ninth transistor are electrically connected to the first node, and the second pole of the ninth transistor is electrically connected to a fifth reference voltage terminal to receive the fifth reference voltage.

10. The shift register unit according to claim 5, characterized in that the output voltage control circuit further includes a first capacitor electrically connected between the first pole of the fifth transistor and the control terminal of the fifth transistor.

11. The shift register unit according to any one of claims 4, 8, or 9, further characterized in that the output circuit includes a second capacitor electrically connected between the output terminal and the control terminal of the fourth transistor.

12. The shift register unit according to claim 5 or 10, wherein the output voltage control circuit further includes a tenth transistor, the first and second poles of the tenth transistor being connected to the control terminals of the first node and the fifth transistor, respectively, and the control terminal of the tenth transistor being configured to receive a sixth reference voltage and turn on the tenth transistor.

13. The shift register unit according to claim 8, wherein the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the eighth transistor.

14. A gate drive circuit characterized by including a plurality of shift register units according to any one of claims 1 to 13, which are connected in a plurality of cascades.

15. A display device including the gate drive circuit described in claim 14.

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