Battery management systems, batteries, vehicles, and battery management methods

Abstract

A battery management system, battery, vehicle, and battery management method are provided. The battery management system includes an analog front-end chip, a high-voltage management chip, a dedicated integrated chip, and a processor chip. The analog front-end chip is connected to a battery group and configured to detect status parameter information for at least one battery cell in the battery group. The high-voltage management chip is connected to the power cord of a battery pack and configured to detect status parameter information for the battery pack. The battery pack includes multiple battery groups. The processor chip is electrically connected to the analog front-end chip via a dedicated integrated chip. The high-voltage management chip is electrically connected to the processor chip via a dedicated integrated chip. The processor chip is configured to manage the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack.

Description

Technical Field

[0001] Cross - reference to Related Applications This application was filed with the China National Intellectual Property Administration on April 28, 2023, and claims the priority of Chinese Patent Application No. 202310489819.8, entitled "BATTERY MANAGEMENT SYSTEM, BATTERY, VEHICLE, AND BATTERY MANAGEMENT METHOD", the entire content of which is incorporated herein by reference.

[0002] This application relates to the field of battery technology, and particularly to battery management systems, batteries, vehicles, and battery management methods.

Background Art

[0003] Currently, battery management systems have low performance and cannot accurately and timely estimate and manage battery status. As a result, the operating efficiency of battery management systems is affected. In some application scenarios, conventional battery management systems are not applicable at all, further affecting the use and popularization of batteries.

Summary of the Invention

[0004] This application is intended to solve at least one of the existing technical problems in the prior art. Thus, according to a first aspect, embodiments of this application provide a battery management system. The battery management system can improve the operating efficiency, safety, and reliability of the battery management system and is applicable to more application scenarios.

[0005] According to a second aspect, embodiments of this application provide a battery.

[0006] According to a third aspect, embodiments of this application provide a vehicle.

[0007] According to a fourth aspect, an embodiment of the present application provides a battery management method.

[0008] To solve the aforementioned problems, an embodiment of the present application according to a first aspect provides a battery management system comprising: an analog front-end chip connected to a group of batteries and configured to detect status parameter information of battery cells in the group of batteries; a battery group comprising an analog front-end chip including at least one battery cell; a high-voltage management chip connected to the power cord of a battery pack and configured to detect status parameter information of a battery pack; a battery pack comprising a high-voltage management chip including a group of batteries; a dedicated integrated chip; and a processor chip electrically connected to the analog front-end chip via the dedicated integrated chip; the high-voltage management chip electrically connected to the processor chip via the dedicated integrated chip; and a processor chip configured to manage the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack.

[0009] According to the battery management system of this embodiment of the present application, battery management is performed based on a configuration of an analog front-end chip, a high-voltage management chip, a dedicated integrated chip, and a processor chip. The processor chip acquires data more quickly and efficiently, improving the operational efficiency of the system, and the data transmission path is more unified, improving data stability. In addition, the battery management system based on this configuration is applicable to a wider range of application scenarios.

[0010] In some embodiments, the dedicated integrated chip includes a power supply circuit configured to connect to an external power supply and provide operating power to at least one chip in the battery management system.

[0011] In some embodiments, the dedicated integrated chip further includes power input ports and power output ports, wherein a power supply circuit is connected to an external power supply via the power input ports, and the power supply circuit is connected to a processor chip via the power output ports to supply operating power for the processor chip.

[0012] In some embodiments, the power supply circuit is connected to a high-voltage management chip via a power output port to supply operating power for the high-voltage management chip.

[0013] In some embodiments, the power supply circuit includes a voltage conversion subcircuit for applying different operating voltages to the processor chip and the high-voltage management chip.

[0014] In some embodiments, the processor chip is further configured to generate power setting information according to the power requirements of the internal electrical chip of the battery management system, and to send the power setting information to a dedicated integrated chip to manage the battery management system when supplying operating power for the internal electrical chip, and the dedicated integrated chip further includes a first digital logic circuit that is electrically connected separately to the processor chip and the power circuit and is configured to control the power circuit according to the power setting information to supply operating power for the internal electrical chip of the battery management system.

[0015] In some embodiments, the dedicated integrated chip further includes a power switching circuit, the first end of which is connected to a power supply circuit, and the second end of which is suitable for connecting to an external electrical unit, and the power switching circuit is configured to control the power status of the external electrical unit to connect or disconnect it.

[0016] The power switching circuit includes a high-side drive subcircuit, the first end of which is connected to the output terminal of the power supply circuit, the second end of which is suitable for connecting to the power supply side of the power loop of an external electrical unit, and the third end of which is suitable for connecting to the positive terminal of an external electrical unit, and the high-side drive subcircuit is configured to control the connection / disconnection between the external electrical unit and the power supply side.

[0017] In some embodiments, the power switching circuit includes a low-side drive subcircuit, the first end of which is connected to the output terminal of the power supply circuit, the second end of which is suitable for connecting to the power ground side of the power loop of an external electrical unit, and the third end of which is suitable for connecting to the negative terminal of the external electrical unit, and the low-side drive subcircuit is configured to control the connection / disconnection between the external electrical unit and the power ground side.

[0018] In some embodiments, the power switching circuit further includes an activation switching subcircuit, one end of which is connected to a high-side drive subcircuit and a low-side drive subcircuit, respectively, and the other end of which is connected to a power supply circuit and configured to control the connection / disconnection of the high-side drive subcircuit and the low-side drive subcircuit.

[0019] In some embodiments, the processor chip is further configured to generate power switching channel selection control signals for high-side and low-side drive subcircuits according to the power demand of an external electrical unit, and to send the power switching channel selection control signals to a dedicated integrated chip to manage a battery management system when connecting or disconnecting power for the external electrical unit, and a first digital logic circuit is electrically connected to the enable switching subcircuit and configured to control the enable switching subcircuit according to the power switching channel selection control signals.

[0020] In some embodiments, the dedicated integrated chip further includes an input source detection subcircuit, one end of which is connected to an external power supply via a power input port, and the other end of which is connected to a first digital logic circuit, and which is configured to detect the external power supply and transmit power detection information of the external power supply to the first digital logic circuit.

[0021] In some embodiments, the dedicated integrated chip includes an input source isolation circuit connected to an external power supply and a power supply circuit, wherein the power supply circuit is connected to the external power supply via the input source isolation circuit.

[0022] In some embodiments, the dedicated integrated chip includes a first daisy-chain serial peripheral interface circuit, the dedicated integrated chip being electrically connected to an analog front-end chip via the first daisy-chain serial peripheral interface circuit.

[0023] In some embodiments, the dedicated integrated chip is A first standard serial peripheral interface circuit, wherein one end of the first standard serial peripheral interface circuit is electrically connected to a first daisy-chain serial peripheral interface circuit, and the other end of the first standard serial peripheral interface circuit is electrically connected to a processor chip. Includes.

[0024] In some embodiments, the first standard serial peripheral interface circuit is configured to send standard serial data to or receive data from a processor chip, and to send the data received from the processor chip as standard serial data to a first daisy-chain serial peripheral interface circuit, and the first daisy-chain serial peripheral interface circuit is configured to convert the standard serial data into corresponding differential data and send the corresponding differential data to an analog front-end chip. The first daisy-chain serial peripheral interface circuit is further configured to receive differential data from the analog front-end chip and send the differential data received from the analog front-end chip to the first standard serial peripheral interface circuit, and the first standard serial peripheral interface circuit is configured to convert the differential data into corresponding standard serial data and send the corresponding standard serial data to the processor chip.

[0025] In some embodiments, the application specific integrated circuit includes a second daisy-chain serial peripheral interface circuit through which the application specific integrated circuit is connected to a high voltage management chip.

[0026] In some embodiments, the application specific integrated circuit includes a second standard serial peripheral interface circuit, one end of which is electrically connected to the second daisy-chain serial peripheral interface circuit and the other end of which is electrically connected to the processor chip.

[0027] ​​In some embodiments, the second standard serial peripheral interface circuit is configured to receive data from the processor chip and transmit the data received from the processor chip as standard serial data to a second daisy chain serial peripheral interface circuit, and the second daisy chain serial peripheral interface circuit is configured to convert the standard serial data into corresponding differential data and send the corresponding differential data to a high voltage management chip. The second daisy chain serial peripheral interface circuit is further configured to receive differential data from the high voltage management chip and send the differential data received from the high voltage management chip to the second standard serial peripheral interface circuit, and the second standard serial peripheral interface circuit is configured to convert the differential data into corresponding standard serial data and send the corresponding standard serial data to the processor chip.

[0028] In some embodiments, the application specific integrated chip further includes at least one of a first I2C bus interface circuit, a first general purpose asynchronous receiver / transmitter interface circuit, and a first controller area network bus interface circuit, and the at least one interface circuit is configured for an electrical connection between the daisy chain serial peripheral interface circuit of the application specific integrated chip and the processor chip, or the at least one interface circuit is configured for communication between the application specific integrated chip and an external control system.

[0029] In some embodiments, the application specific integrated chip further includes a first analog input interface circuit, one end of the first analog input interface circuit is electrically connected to an external sensor, the other end of the first analog input interface circuit is electrically connected to a first digital logic circuit, and the first analog input interface circuit is configured to collect sensor information of the external sensor.

[0030] In some embodiments, the dedicated integrated chip is A first general-purpose input / output interface circuit, further comprising a first general-purpose input / output interface circuit, one end of which is electrically connected to a peripheral circuit, and the other end of which is connected to a first digital logic circuit, and configured to output control information of the first digital logic circuit for the peripheral circuit, or to collect status information of the peripheral circuit.

[0031] In some embodiments, the processor chip is further configured to send configuration information of a dedicated integrated chip to the dedicated integrated chip and to obtain at least one of the following from the dedicated integrated chip: interface circuit transmission information, safety monitoring information, safety alarm information, and operational status information.

[0032] In some embodiments, the high-voltage management chip is A signal input port configured to receive status parameter information for the battery pack, and It includes a first detection circuit connected to the battery pack's power cord via a signal input port and configured to detect status parameter information of the battery pack.

[0033] In some embodiments, the high-voltage management chip is A peripheral differential detection circuit further includes a peripheral differential detection circuit, one end of which is connected to the power cord of a battery pack, and the other end of which is connected to the signal input port of a high-voltage management chip, wherein a first detection circuit detects status parameter information of the battery pack via the peripheral differential detection circuit.

[0034] In some embodiments, the first detection circuit includes a first voltage detection circuit connected to a signal input port and configured to detect voltage information of the battery pack.

[0035] In some embodiments, the first detection circuit includes a first current detection circuit connected to a signal input port and configured to detect current information of the battery pack.

[0036] In some embodiments, the processor chip is configured to manage a battery management system according to battery cell status parameter information and / or battery pack status parameter information, which includes the processor chip being configured to estimate the charge state value and / or health state value of the battery pack according to the battery pack voltage information and current information.

[0037] In some embodiments, the high-voltage management chip further includes a data processing circuit that is individually connected to a first voltage detection circuit and a first current detection circuit and configured to estimate the charge state value and / or health state value of the battery pack according to the voltage information and current information of the battery pack.

[0038] In some embodiments, the first detection circuit includes an insulation resistance detection circuit configured to detect the resistance between the battery pack's power cord and the vehicle body's insulating ground. The data processing circuit is further configured to determine the leakage status of the battery pack according to its resistance.

[0039] In some embodiments, the high-voltage management chip is The system further includes a first safety diagnostic circuit connected to a first detection circuit, which is configured to identify whether the status parameter information of the battery pack is abnormal and to perform safety protection if the status parameter information of the battery pack is abnormal.

[0040] In some embodiments, the first safety diagnostic circuit is: The system includes a first current diagnostic circuit connected to a first current detection circuit, which is configured to identify whether there is an overcurrent in the battery pack according to the current information of the battery pack, and to perform overcurrent protection if there is an overcurrent in the battery pack.

[0041] In some embodiments, the first safety diagnostic circuit is: The system includes a first voltage diagnostic circuit connected to a first voltage detection circuit, which is configured to identify whether the battery pack has an overvoltage or undervoltage according to the voltage information of the battery pack, and to perform overvoltage or undervoltage protection if the battery pack has an overvoltage or undervoltage.

[0042] In some embodiments, the high-voltage management chip is Includes a second general-purpose input / output interface circuit that is connected to an external sensor or external load and configured to collect information from the external sensor or output control signals to the external load.

[0043] In some embodiments, the high-voltage management chip is A first temperature detection circuit, which is connected to an external temperature sensor via a second general-purpose input / output interface circuit and detects temperature information from a high-voltage management chip, and The system further includes a first temperature diagnostic circuit connected to a first temperature detection circuit, which is configured to identify whether the high voltage management chip is overheating according to the temperature information of the high voltage management chip, and to perform overheating protection if the high voltage management chip is overheating.

[0044] In some embodiments, the processor chip is further configured to send configuration information for the high voltage management chip to the high voltage management chip via a dedicated integrated chip, and to acquire at least one of the detection information, calculation result information, safety diagnostic information, and safety alarm information for the high voltage management chip via the dedicated integrated chip.

[0045] In some embodiments, the high-voltage management chip is A third daisy-chain serial peripheral interface circuit, comprising a high-voltage management chip connected to a second daisy-chain serial peripheral interface circuit of a dedicated integrated chip via the third daisy-chain serial peripheral interface circuit.

[0046] In some embodiments, the high-voltage management chip includes at least one of a second standard serial peripheral interface circuit and a second I2C bus interface circuit, the at least one of the second standard serial peripheral interface circuit and the second I2C bus interface circuit being a standby interface circuit.

[0047] In some embodiments, the high-voltage management chip includes a second controller area network bus interface circuit configured to connect to an external communication bus and acquire external bus information.

[0048] In some embodiments, the analog front-end chip includes a second detection circuit connected to a battery group and configured to detect status parameter information of battery cells in the battery group.

[0049] In some embodiments, the analog front-end chip further includes a second analog input interface circuit, the second of which a second detection circuit is connected to an external detection circuit via the second analog input interface circuit to detect status parameter information of battery cells in a battery group.

[0050] In some embodiments, the analog front-end chip further includes a third general-purpose input / output interface circuit connected to an external sensor, wherein a second detection circuit is connected to the external sensor via the third general-purpose input / output interface circuit to detect status parameter information of battery cells in a battery group.

[0051] In some embodiments, the second detection circuit includes a second voltage detection circuit configured to collect voltage information of battery cells in a group of batteries.

[0052] In some embodiments, the second detection circuit further includes a second current detection circuit configured to collect current information of battery cells in a group of batteries.

[0053] In some embodiments, the second detection circuit further includes a stress detection circuit configured to detect stress information of battery cells in a group of batteries.

[0054] In some embodiments, the second detection circuit further includes a second temperature detection circuit configured to detect temperature information of battery cells in a group of batteries.

[0055] In some embodiments, the front-end analog chip further includes a second safety diagnostic circuit connected to a second detection circuit, which is configured to identify whether the status parameter information of the battery cell is abnormal and to perform safety protection if the status parameter information of the battery cell is abnormal.

[0056] In some embodiments, the second safety diagnostic circuit includes a second voltage diagnostic circuit that is connected to a second voltage detection circuit and configured to identify whether there is an overvoltage or undervoltage in the battery cell voltages in the battery group, and to perform overvoltage or undervoltage protection if there is an overvoltage or undervoltage in the battery cell voltages.

[0057] In some embodiments, a second voltage detection circuit is further configured to detect the voltage of the battery group and the voltage of the internal components of the analog front-end chip, and a second voltage diagnostic circuit is further configured to identify whether the voltage of the battery group is abnormal, identify whether the voltage of the internal components of the analog front-end chip is abnormal, and to perform voltage safety protection if an exception occurs.

[0058] In some embodiments, the second safety diagnostic circuit includes a second current diagnostic circuit that is connected to a second current detection circuit and configured to identify whether there is an overcurrent in the battery cell current and to perform overcurrent protection if there is an overcurrent in the battery cell current.

[0059] In some embodiments, a second current detection circuit is further configured to detect the current of the battery group and the current of the internal components of the analog front-end chip, and a second current diagnostic circuit is further configured to diagnose whether the current of the battery group is abnormal, identify whether the current of the internal components of the analog front-end chip is abnormal, and perform current abnormality safety protection if there is an abnormal current.

[0060] In some embodiments, the second safety diagnostic circuit includes a stress diagnostic circuit configured to identify whether the stress on battery cells in a battery group is abnormal and, if the stress is abnormal, to perform stress abnormality safety protection.

[0061] In some embodiments, the second safety diagnostic circuit includes a second temperature diagnostic circuit that is connected to a second temperature detection circuit and configured to identify whether there is an overtemperature for the battery cells in the battery group and to perform overtemperature safety protection if there is an overtemperature for the battery cells.

[0062] In some embodiments, the analog front-end chip further includes a second digital logic circuit connected to a second safety diagnostic circuit, which is configured to generate exception information and provide an alarm prompt if the status parameter information of the battery cells in the battery group is abnormal.

[0063] In some embodiments, the processor chip is further configured to send configuration information for the analog front-end chip to the analog front-end chip via a dedicated integrated chip, and to acquire at least one of the following from the analog front-end chip via the dedicated integrated chip: detection information, safety diagnostic information, safety alarm information, and calculation result information.

[0064] In some embodiments, the processor chip is configured to manage a battery management system according to status parameter information of battery cells and status parameter information of battery packs, which includes the processor chip being configured to generate power equalization information when it is determined that the power of the battery cells in the battery group is unbalanced according to the status parameter information of the battery cells in the battery group, and to transfer the power equalization information to a corresponding front-end analog chip via a dedicated integrated chip, the analog front-end chip including an equalization circuit configured to perform a power equalization process on the battery cells in the battery group according to the power equalization information.

[0065] In some embodiments, the processor chip is configured to manage a battery management system according to status parameter information of battery cells and status parameter information of a battery pack, which includes the processor chip being configured to determine the battery state according to the status parameter information of battery cells and status parameter information of a battery pack, and to determine whether to charge or discharge the battery pack and to stop charging or discharging the battery pack according to the battery state.

[0066] In some embodiments, the processor chip is configured to manage a battery management system according to battery cell status parameter information and battery pack status parameter information, which includes the processor chip being configured to estimate the battery pack charge state value according to the battery cell status parameter information and / or battery pack status parameter information, to obtain the battery pack charge state value estimated by the high voltage management chip, and to perform battery state verification according to the battery pack charge state value estimated by the processor chip and the battery pack charge state value estimated by the high voltage management chip.

[0067] In some embodiments, there are multiple analog front-end chips, which are connected in series.

[0068] In some embodiments, there are two first daisy-chain serial peripheral interface circuits, and each analog front-end chip includes a fourth daisy-chain serial peripheral interface circuit and a fifth daisy-chain serial peripheral interface circuit. In a series-connected set of multiple analog front-end chips, the leading analog front-end chip is connected via the fourth daisy-chain serial peripheral interface circuit to one of the first daisy-chain serial peripheral interface circuits of the dedicated integrated chip, and the trailing analog front-end chip is connected via the fifth daisy-chain serial peripheral interface circuit to the other first daisy-chain serial peripheral interface circuit of the dedicated integrated chip.

[0069] In some embodiments, in a plurality of analog front-end chips connected in series, the nth analog front-end chip is connected to the fourth daisy-chain serial peripheral interface circuit of the (n + 1)th analog front-end chip via the fifth daisy-chain serial peripheral interface circuit, where 1 ≦ n < n + 1 ≦ N, and N is the total number of the plurality of analog front-end chips connected in series.

[0070] In some embodiments, the analog front-end chip includes at least one of a third standard serial peripheral interface circuit and a third I2C bus interface circuit, and at least one of the third standard serial peripheral interface circuit and the third I2C bus interface circuit is a standby interface circuit.

[0071] To achieve the foregoing object, an embodiment of the present application according to a second aspect includes a battery pack including a battery, the battery pack including a plurality of battery groups, each battery group including at least one battery cell, the battery pack being connected to a battery management system, and each battery group being connected to the battery management system.

[0072] Therefore, the battery according to the present embodiment of the present application is connected to the battery management system provided in the foregoing embodiment. The battery management system operates efficiently and has high data stability and reliability, thereby improving the use safety of the battery.

[0073] To achieve the foregoing object, an embodiment of the present application according to a third aspect provides a vehicle including a battery pack including a plurality of battery groups, each battery group including at least one battery cell, and a battery management system connected to the battery pack.

[0074] Therefore, the vehicle according to the embodiments of this application uses the battery management system described in the embodiments above. The battery management system has high operational efficiency, safety, and reliability, and is applicable to many application scenarios, thereby improving the battery management efficiency and safety of the vehicle.

[0075] To achieve the aforementioned objectives, an embodiment of the present application according to a fourth aspect provides a battery management method applicable to a battery management system. The battery management method includes detecting status parameter information of a battery pack by a high-voltage management chip, detecting status parameter information of battery cells in a battery group by an analog front-end chip, wherein the battery pack includes a plurality of battery groups, and each battery group includes at least one battery cell, transferring the status parameter information of the battery pack and the status parameter information of the battery cells in the battery group to a processor chip by a dedicated integrated chip, and managing the battery management system by the processor chip according to the status parameter information of the battery cells and the status parameter information of the battery pack.

[0076] In the battery management method according to this embodiment of the present application, data exchange between the analog front-end chip and the processor chip, and data exchange between the high-voltage management chip and the processor chip are performed via a dedicated integrated chip. As a result, data is transmitted effectively and quickly, improving the operational efficiency of the system, and the data transmission path is more unified, thereby improving the safety and reliability of the system and making it suitable for a wider range of application scenarios.

[0077] In some embodiments, managing a battery management system by a processor chip according to battery cell status parameter information and battery pack status parameter information includes estimating the charge state value and / or health state value of the battery pack by the processor chip according to the battery pack voltage information and current information.

[0078] In some embodiments, the processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack, which further includes the processor chip determining whether to charge or discharge the battery pack, and whether to stop charging or discharging the battery pack, according to the charge state of the battery pack.

[0079] In some embodiments, the processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack, which includes the processor chip determining, according to the status parameter information of the battery cells in the battery group, that the power of the battery cells in the battery group is unbalanced, generating power equalization information, and transferring the power equalization information to the front-end analog chip via a dedicated integrated chip.

[0080] In some embodiments, the battery management method further includes a processor chip generating power setting information according to the power requirements of the internal electrical chip of the battery management system, and sending the power setting information to a dedicated integrated chip to manage the battery management system when supplying operating power for the internal electrical chip.

[0081] In some embodiments, the battery management method further includes a processor chip generating a power switching channel selection control signal according to the power demand of an external electrical unit, sending the power switching channel selection control signal to a dedicated integrated chip to manage the battery management system when connecting or disconnecting power for the external electrical unit, and the dedicated integrated chip controlling the connection / disconnection between the external electrical unit connected to the power supply circuit and the power supply side, or the connection / disconnection between the external electrical unit and the power supply ground side, according to the power switching channel selection control signal.

[0082] In some embodiments, the battery management method further includes sending configuration information of a dedicated integrated chip to the dedicated integrated chip via a processor chip, obtaining interface circuit transmission information of the dedicated integrated chip, and obtaining at least one of the dedicated integrated chip's safety monitoring information, safety alarm information, and operational status information via a processor chip.

[0083] In some embodiments, the battery management method further includes sending configuration information for the high voltage management chip to the high voltage management chip via a dedicated integrated chip, obtaining detection information for the high voltage management chip via the dedicated integrated chip, and obtaining at least one of the calculation result information, safety diagnostic information, and safety alarm information of the high voltage management chip via the dedicated integrated chip, by the processor chip.

[0084] In some embodiments, the battery management method further includes, by a processor chip, sending configuration information for the analog front-end chip to the analog front-end chip via a dedicated integrated chip, obtaining detection information for the analog front-end chip via the dedicated integrated chip, and by a processor chip obtaining at least one of safety diagnostic information, safety alarm information, and calculation result information for the analog front-end chip via the dedicated integrated chip.

[0085] In some embodiments, the battery management method further includes, by a dedicated integrated chip, controlling the power supply circuit of the dedicated integrated chip according to power setting information to supply operating power for at least one of the internal electrical chips of the battery management system.

[0086] In some embodiments, the status parameter information of the battery pack includes voltage information and current information of the battery pack, and the battery management method further includes estimating the charge state value and / or health state value of the battery pack according to the voltage information and current information of the battery pack by a high-voltage management chip.

[0087] In some embodiments, the processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack, and further includes the processor chip obtaining the battery pack charge state value estimated by the high voltage management chip via a dedicated integrated chip, and verifying the status of the battery pack according to the battery pack charge state value estimated by the processor chip and the battery pack charge state value estimated by the high voltage management chip.

[0088] In some embodiments, the status parameter information of the battery pack includes the resistance between the battery pack's power cord and the vehicle's insulating ground, and the battery management method further includes a high-voltage management chip determining the battery pack's leakage status according to the resistance.

[0089] In some embodiments, the battery management method further includes using a high-voltage management chip to identify whether the status parameter information of the battery pack is abnormal, and if the status parameter information of the battery pack is abnormal, to perform safety protection.

[0090] In some embodiments, the high-voltage management chip identifies whether the status parameter information of the battery pack is abnormal and, if so, performs safety protection, which includes at least one of the following: the high-voltage management chip identifies whether there is an overcurrent in the battery pack according to the current information of the battery pack and, if so, performs overcurrent protection; and the high-voltage management chip identifies whether there is an overvoltage or undervoltage in the battery pack according to the voltage information of the battery pack and, if so, performs overvoltage or undervoltage protection.

[0091] In some embodiments, the battery management method further includes obtaining temperature information of the high voltage management chip, and, according to the temperature information of the high voltage management chip, identifying whether the high voltage management chip is overheating, and, if the high voltage management chip is overheating, performing overheating protection.

[0092] In some embodiments, the battery management method further includes using an analog front-end chip to identify whether the status parameter information of a battery cell is abnormal, and if the status parameter information of a battery cell is abnormal, to perform safety protection.

[0093] In some embodiments, the analog front-end chip identifies whether the status parameter information of a battery cell is abnormal and, if so, performs safety protection, which includes at least one of the following: the analog front-end chip identifies whether there is an overvoltage or undervoltage in the voltage of a battery cell in a battery group and, if so, performs overvoltage or undervoltage protection; the analog front-end chip identifies whether there is an overcurrent in the current of a battery cell and, if so, performs overcurrent protection; the analog front-end chip identifies whether the stress on a battery cell in a battery group is abnormal and, if so, performs safety protection; and the analog front-end chip identifies whether there is an overtemperature in the temperature of a battery cell in a battery group and, if so, performs overtemperature safety protection.

[0094] In some embodiments, the battery management method further includes at least one of the following: using an analog front-end chip to identify whether the voltage of a group of batteries is abnormal, identifying whether the voltage of the internal components of the analog front-end chip is abnormal, and performing voltage safety protection if an exception occurs; and using an analog front-end chip to diagnose whether the current of a group of batteries is abnormal, identifying whether the current of the internal components of the analog front-end chip is abnormal, and performing current protection if there is an abnormal current.

[0095] Additional aspects and advantages of this application are partially shown in the following description, partially apparent from the following description, or can be learned from the practice of this application.

[0096] The aforementioned and / or additional aspects and advantages of this application will become apparent and readily apparent from the description of the embodiments with reference to the following appended drawings. [Brief explanation of the drawing]

[0097] [Figure 1] This is a structural diagram of a battery management system according to an embodiment of the present application. [Figure 2] This is a block diagram of a dedicated integrated chip according to an embodiment of the present application. [Figure 3] This is a flowchart illustrating the high-side and low-side drive settings according to the embodiments of this application. [Figure 4] This figure illustrates an embodiment of the present application that implements a communication connection between a processor chip and an analog front-end chip via an interface circuit of a dedicated integrated chip. [Figure 5] This is a block diagram of a high-voltage management chip according to an embodiment of the present application. [Figure 6] This is a block diagram of an analog front-end chip according to an embodiment of the present application. [Figure 7] This is a flowchart of data exchange according to the embodiment of this application. [Figure 8] This is a block diagram of a vehicle according to an embodiment of the present application. [Figure 9] This is a flowchart of a battery management method according to an embodiment of this application. [Figure 10] This is a block diagram of a battery according to an embodiment of the present application. [Modes for carrying out the invention]

[0098] Embodiments of this application are described in detail below. Embodiments described with reference to the accompanying drawings are illustrative.

[0099] A battery management system provided in an embodiment of the present application according to a first aspect is described below with reference to Figures 1 to 7.

[0100] Figure 1 is a block diagram of a battery management system according to an embodiment of the present application. As shown in Figure 1, the battery management system 100 according to this embodiment of the present application includes an analog front-end chip 10, a high-voltage management chip 20, a dedicated integrated chip 30, and a processor chip 40.

[0101] The analog front-end chip 10 is connected to the battery group and configured to detect status parameter information of the battery cells in the battery group. For example, the battery group includes at least one battery cell. The analog front-end chip 10 monitors status parameter information of the battery group, including, but not limited to, the battery current, voltage, internal and external stress, or external temperature. The battery cell may be a lithium battery, a rechargeable battery, a secondary lithium battery, or a secondary rechargeable battery.

[0102] The high-voltage management chip 20 is connected to the power cord of the battery pack and is configured to detect status parameter information of the battery pack, such as current and voltage. The battery pack includes multiple battery groups.

[0103] As shown in Figure 1, the battery pack includes multiple battery groups, each battery group connected to an analog front-end chip 10, which is configured to detect status parameter information for each battery cell in the corresponding battery group. The high-voltage management chip 20 is configured to detect status parameter information for the multiple battery groups as a whole, i.e., the battery pack.

[0104] The dedicated integrated chip 30 acts as a bridge chip. The processor chip 40 is connected to the analog front-end chip 10 via the dedicated integrated chip 30, and the processor chip 40 is connected to the high-voltage management chip 20 via the dedicated integrated chip 30. The dedicated integrated chip 30 is configured to transfer detection data or generated data from the analog front-end chip 10 to the processor chip 40, and the dedicated integrated chip 30 is configured to transfer detection data and generated data from the high-voltage management chip 20 to the processor chip 40. In addition, the processor chip 40 can send monitoring parameters to the analog front-end chip 10 and the high-voltage management chip 20 via the dedicated integrated chip 30.

[0105] The processor chip 40 may also be a processing unit having control, management, and computational capabilities, and is responsible for jobs such as monitoring the operational status of the entire battery management system 100 and modules connected to the battery management system 100, data scheduling, and data calculations.

[0106] In this embodiment of the present application, the processor chip 40 is configured to exchange data with the analog front-end chip 10 and the high-voltage management chip 20 via a bridge connection with the dedicated integrated chip 30, and to perform data processing and task scheduling according to the feedback information, for example, to manage the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack. The management may include charging and discharging the battery pack, equalizing and power estimation of the battery cells, and functional safety monitoring.

[0107] The dedicated integrated chip 30 acts as an extension interface for the processor chip 40, acting as a bridge chip between the processor chip 40 and the front-end analog chip 10, and as a bridge chip between the processor chip 40 and the high-voltage management chip 20. In addition, the dedicated integrated chip 30 can perform data transmission between the high-voltage management chip 20 and the processor chip 40, and between the analog front-end chip 10 and the processor chip 40. In this mode, data is transmitted efficiently, the operating efficiency of the processor chip 40 is improved, the data transmission path is more unified, thereby improving the safety and reliability of the system and making it suitable for a wider range of application scenarios.

[0108] In some embodiments, the processor chip 40 can monitor the operating status of other systems and devices connected to the interface of the dedicated integrated chip 30, such as the operating status and set operating parameters of the analog front-end chip 10 and the high-voltage management chip 20, and perform data transmission. The processor chip 40 can perform status setting on the front-end analog chip 10 and the high-voltage management chip 20 via the dedicated integrated chip 30, acquire corresponding data such as collected data, or acquire processing data directly, thereby reducing the workload of the processor chip 40.

[0109] The processor chip 40 sends configuration information and transmission information to the dedicated integrated chip 30, and can acquire collected data, stored data, calculation result data, etc., which are fed back by the dedicated integrated chip 30, and can receive at least one of the following from the dedicated integrated chip 30: interface circuit transmission information, safety monitoring information, safety alarm information, and operation status information. Furthermore, based on such information, the processor chip 40 can perform task scheduling or monitor the operation of the dedicated integrated chip 30.

[0110] The processor chip 40 can transmit configuration information of the analog front-end chip 10, such as system operating time parameters, collection parameters, and data communication parameters of the analog front-end chip 10, to the analog front-end chip 10 via the dedicated integrated chip 30. As a result, the analog front-end chip 10 performs parameter sampling of the connected battery group, performs safety monitoring of the analog front-end chip 10, and returns feedback to the processor chip 40 according to the settings. The collected battery parameters include, but are not limited to, signals such as battery cell voltage, current, temperature, and stress. The processor chip 40 acquires at least one of the detection information, safety diagnostic information, safety alarm information, and calculation result information of the analog front-end chip 10 via the dedicated integrated chip 30, receives the collected data transmitted from the analog front-end chip 10, and can estimate the status of each battery cell, including, but not limited to, the calculation of the SOC value.

[0111] The processor chip 40 sends configuration information of the high voltage management chip 20, such as system operating time parameters, collection parameters, data communication parameters, and calculation operations of the high voltage management chip 20, to the high voltage management chip 20 via the dedicated integrated chip 30. As a result, the high voltage management chip 20 performs differential sampling on the total voltage and total current of all battery cells connected to the high voltage management chip 20, estimates the operating status of all battery cells in the high voltage management chip 20, including but not limited to SOC calculations, performs safety monitoring internally, and transmits relevant data to the processor chip 40 according to the settings. For example, the processor chip 40 can acquire at least one of the following from the high voltage management chip 20 via the dedicated integrated chip 30: detection information, calculation result information, safety diagnostic information, and safety alarm information.

[0112] The internal structure of each chip in the battery management system 100 according to this embodiment of the present application is described below.

[0113] Figure 2 is a functional block diagram of a dedicated integrated chip 30 according to an embodiment of this application. As shown in Figure 2, the dedicated integrated chip 30 includes a power supply circuit 31.

[0114] The power supply circuit 31 is connected to an external power supply and configured to supply operating power for at least one chip in the battery management system 100. As shown in Figure 1, the analog front-end chip 10 is connected to a battery group, which can directly supply power. In this embodiment of the application, the dedicated integrated chip 30 is provided with the power supply circuit 31, and the external power supply can be allocated to the chip in the system via the power supply circuit 31 to supply power to the internal electrical chip. Therefore, the battery management system 100 does not need to supply independent power for each module, thereby improving power consistency, reducing the complexity of the overall system design, and lowering costs.

[0115] As shown in Figure 2, the dedicated integrated chip 30 further includes a power input port 32 and a power output port 33. The power supply circuit 31 is connected to an external power supply via the power input port 32, and the power supply circuit 31 is connected to the processor chip 40 via the power output port 33 to supply operating power for the processor chip 40.

[0116] As shown in Figure 1, the dedicated integrated chip 30 can obtain operating power from the vehicle's battery via the power input port 32, convert this operating power into a stable power supply, for example, by performing voltage stabilization processing via a voltage regulator circuit, and supply operating power for the processor chip 40. Therefore, the processor chip 40 does not need to be provided with an independent power supply.

[0117] For example, the power supply circuit 31 can convert the input power supply voltage to the operating voltage of the chip's internal modules and the drive voltage of external units connected to the power output port 33 via a low-dropout linear regulator (LDO) module. In other words, the cascaded input power supply is converted to a stable voltage via the power input port 32, the power supply circuit 31 (low-dropout linear regulator), and the power output port 33 to supply power to the internal electrical chips in the system.

[0118] The power supply circuit 31 is also connected to the high-voltage management chip 20 via the power output port 33, and can supply operating power for the high-voltage management chip 20. Therefore, the high-voltage management chip 20 does not need to be provided with an independent power supply.

[0119] It can be understood that the operating voltages of the electrical chips in the battery management system 100 may differ. Therefore, as shown in Figure 2, the power supply circuit 31 includes a voltage conversion subcircuit 311, one end of which is connected to an external power supply via a power input port 32, and the other end of which is connected to the processor chip 40 and the high voltage management chip 20, so that the voltage conversion subcircuit 311 can apply different operating voltages for the processor chip 40 and the high voltage management chip 20 to meet the operating voltage requirements of different electrical chips.

[0120] In some embodiments, the processor chip 40 can generate power setting information according to the power requirements of the internal electrical chip of the battery management system 100, and send the power setting information to a dedicated integrated chip 30 to manage the battery management system 100 when supplying operating power for the internal electrical chip.

[0121] As shown in Figure 2, the dedicated integrated chip 30 further includes a first digital logic circuit 34. The first digital logic circuit 34 is electrically connected separately to the processor chip 40 and the power supply circuit 31 and is configured to control the power supply circuit 31 according to power setting information to supply operating power for the internal electrical chip of the battery management system 100.

[0122] For example, after powering up from the dedicated integrated chip 30, the processor chip 40 checks the connection status between the dedicated integrated chip 30 and the processor chip 40, and the status of the devices mounted on the dedicated integrated chip 30. If the processor chip 40 detects that the dedicated integrated chip 30 is connected to the analog front-end chip 10 and the high-voltage management chip 20, it configures and monitors the two chips.

[0123] In this way, the power supply circuit 31 of the dedicated integrated chip 30 allocates the external power supply to the system's internal electrical chips. As a result, the internal electrical chips do not all need to have independent power supplies, thereby reducing circuit complexity and improving power supply consistency. In addition, the high-voltage management chip 20 has data processing capabilities, and the processor chip 40 directly acquires the calculation results, thereby reducing the computational workload of the processor chip 40 and improving data processing efficiency.

[0124] In this embodiment of the present application, the dedicated integrated chip 30 can further perform power monitoring for external electrical units of the battery management system 100. As shown in Figure 2, the dedicated integrated chip 30 includes a power switching circuit 35, the first end of which is connected to a power supply circuit 31, and the second end of which is suitable for connecting to an external electrical unit. For example, as shown in Figure 1, the external electrical device may be an expansion device connected to the dedicated integrated chip 30, or an external high-voltage device connected via a contactor. The power switching circuit 35 is configured to control the power supply status of the external electrical unit, either connected or disconnected. In other words, the dedicated integrated chip 30 in this embodiment of the present application can have functions such as voltage stabilization, voltage conversion, and switching, can implement a power supply for internal electrical chips in the system, and can control the connection / disconnection of power for external electrical units.

[0125] Furthermore, as shown in Figure 2, the power switching circuit 35 includes a high-side drive subcircuit 351. The first end of the high-side drive subcircuit 351 is connected to the output terminal of the power supply circuit 31. The second end of the high-side drive subcircuit 351 is suitable for connecting to the power supply side of the power loop of the external electrical unit, and the third end of the high-side drive subcircuit 351 is suitable for connecting to the positive terminal of the external electrical unit. The high-side drive subcircuit 351 is configured to control the connection / disconnection between the external electrical unit and the power supply side of the external electrical unit. The high-side drive subcircuit 351 can control the input on the power supply side of the external electrical unit to perform power control to the external electrical unit.

[0126] As shown in Figure 2, the power switching circuit 35 further includes a low-side drive subcircuit 352. The first end of the low-side drive subcircuit 352 is connected to the output terminal of the power supply circuit 31, the second end of the low-side drive subcircuit 352 is suitable for connecting to the power ground side of the power loop of the external electrical unit, and the third end of the low-side drive subcircuit 352 is suitable for connecting to the negative terminal of the external electrical unit. The low-side drive subcircuit 352 is configured to control the connection / disconnection between the external electrical unit and the power ground side of the external electrical unit. In other words, the low-side drive subcircuit 352 can control the connection to the power ground side of the external electrical unit to perform power control to the external electrical unit.

[0127] Specifically, in this embodiment, each of the high-side drive subcircuit 351 and the low-side drive subcircuit 352 can be a triode vacuum tube, a MOS transistor, or another switching transistor. The high-side drive subcircuit 351 and / or the low-side drive subcircuit 352 are connected to an external electrical unit via contactors, and the power supply or grounding of the external electrical unit can be controlled to be connected or disconnected according to the power supply requirements of the external electrical unit.

[0128] As shown in Figure 2, the power switching circuit 35 further includes an activation switching subcircuit 353. One end of the activation switching subcircuit 353 is connected to the high-side drive subcircuit 351 and the low-side drive subcircuit 352. The other end of the activation switching subcircuit 353 is connected to the power supply circuit 31 and is configured to control the connection / disconnection of the high-side drive subcircuit 351 and the low-side drive subcircuit 352. In other words, the high-side drive subcircuit 351 or the low-side drive subcircuit 352 is selectively connected via the activation switching subcircuit 353 to perform power control to external electrical units.

[0129] In this embodiment, the processor chip 40 is further configured to generate power switching channel selection control signals for the high-side drive subcircuit 351 and the low-side drive subcircuit 352 according to the power demand of the external electrical unit, and to send the power switching channel selection control signals to a dedicated integrated chip 30 to manage the battery management system 100 when connecting or disconnecting power for the external electrical unit. The first digital logic circuit 34 is electrically connected to the enable switching subcircuit 353 and is configured to control the enable switching subcircuit 353 according to the power switching channel selection control signals, so that the enable switching subcircuit 353 selects to connect the low-side drive subcircuit 352 or selects to connect the high-side drive subcircuit 351 according to the power switching channel selection control signals, thereby performing power control to the external electrical unit.

[0130] As described above, the dedicated integrated chip 30 in this embodiment of the present application can perform not only power control for the internal electrical units of the battery management system 100, but also power control for external electrical units.

[0131] Specifically, the dedicated integrated chip 30 applies a power supply voltage to the processor chip 40. In this embodiment, the processor chip 40 can select the interface type, activate the interface, and select the transmission channel according to the current interface requirements and idle state of the dedicated integrated chip 30. The processor chip 40 can set the operating parameters of the dedicated integrated chip 30 via the interface to the dedicated integrated chip 30, for example, enabling and selecting high-side or low-side drive subcircuits, enabling drive power supply and channel selection, interface parameters (such as transmission rate and transmission cycle), time-related parameters (such as WDT and internal clock check), as well as operating modes (to set operating modes that change according to the system status), and safety monitoring parameters (such as detection time and the type of parameter to be detected). The first digital logic circuit 34 can control the power switching circuit 35 and the power supply circuit 31 according to the task scheduling information and setting information of the processor chip 40 to meet the power requirements of different modules.

[0132] Figure 3 is a flowchart illustrating the configuration of the high-side drive subcircuit 351 and the low-side drive subcircuit 352 according to an embodiment of the present application. As shown in Figure 3, the flowchart includes the following steps.

[0133] S1: A dedicated integrated chip is connected to the vehicle's battery to obtain startup power and start up, generating a stable power supply from an external source.

[0134] S2: The processor chip starts up by obtaining power from a dedicated integrated chip.

[0135] S3: The processor chip scans the systems and devices mounted on contactors connected to the dedicated integrated chip via a dedicated integrated chip.

[0136] S4: The processor chip sets the operating status of the high-side and low-side drive subcircuits in the relevant contactor channels according to the characteristics of the system and the devices connected to the contactors.

[0137] In some embodiments, as shown in Figure 2, the dedicated integrated chip 30 further includes an input source detection subcircuit 36.

[0138] One end of the input source detection subcircuit 36 ​​is connected to an external power supply via a power input port 32, and the other end of the input source detection subcircuit 36 ​​is connected to a first digital logic circuit 34, which is configured to detect the external power supply and transmit power detection information of the external power supply to the first digital logic circuit 34. The first digital logic circuit 34 adjusts the power signals input to the high-side drive subcircuit 351 and the low-side drive subcircuit 352 according to the power detection information of the external power supply, and can perform fault diagnosis at the input source based on the power detection information of the input external power supply (e.g., the detected voltage), for example, to determine whether there is an overvoltage or undervoltage, or whether there is a difference.

[0139] In other words, the dedicated integrated chip 30 of this embodiment in the present application can form a controllable contactor loop based on a power input port 32, an input external power supply, a low-side drive subcircuit 352, a high-side drive subcircuit 351, and an input source detection subcircuit 36. As shown in Figure 1, the loop incorporates the input power supply into the low-side drive subcircuit 352 and the high-side drive subcircuit 351 and extends to multiple contactor output ports, thereby allowing the contactor connection status to be controlled in a programmable manner, and the contactor drive status to be quickly set to effectively protect connected devices and change the operating status of the devices. In addition, the dedicated integrated chip 30 adds safety protection means for the power output, thereby ensuring the normal operation of the loop.

[0140] As shown in Figure 2, the dedicated integrated chip 30 in this embodiment of the present application is further provided with an input source isolation circuit 37. The input source isolation circuit 37 is connected to an external power supply and a power supply circuit 31. The power supply circuit 31 is connected to the external power supply via the input source isolation circuit 37. Since the internal power of the chip is at a lower voltage compared to the external power supply, the input source isolation circuit 37 can isolate communication signals or separate high-voltage power supplies from low-voltage power supplies to avoid crosstalk of communication signals and interference between high-voltage and low-voltage power supplies, thereby improving the stability of the power supply provided by the dedicated integrated chip 30.

[0141] As shown in Figure 2, the dedicated integrated chip 30 includes a first daisy-chain serial peripheral interface circuit 301, and the dedicated integrated chip 30 is electrically connected to the analog front-end chip 10 via the first daisy-chain serial peripheral interface circuit 301. Communication between the dedicated integrated chip 30 and the analog front-end chip 10 is carried out via the first daisy-chain serial peripheral interface circuit 301. The daisy-chain serial peripheral interface circuit 301 performs a communication isolation function, can reduce signal crosstalk, and improve communication stability.

[0142] As shown in Figure 2, the dedicated integrated chip 30 further includes a first standard serial peripheral interface circuit 302. One end of the first standard serial peripheral interface circuit 302 is electrically connected to a first daisy-chain serial peripheral interface circuit 301, and the other end of the first standard serial peripheral interface circuit 302 is electrically connected to a processor chip 40.

[0143] In other words, isolated data communication between the processor chip 40 and the analog front-end chip 10 is performed via the first daisy-chain serial peripheral interface circuit 301 and the first standard serial peripheral interface circuit 302 of the dedicated integrated chip 30.

[0144] Figure 4 shows the communication connection between the processor chip 40 and the analog front-end chip 10 via the first daisy-chain serial peripheral interface circuit 301 and the first standard serial peripheral interface circuit 302. As shown in Figure 4, the dedicated integrated chip 30 performs the conversion between the standard serial signals of the processor chip 40 and the differential signals of the analog front-end chip 10, and the transmission of these signals.

[0145] Specifically, the first standard serial peripheral interface circuit 302 is configured to send standard serial data such as "0" and "1" to the processor chip 40, or to receive data from the processor chip 40 and to send the data received from the processor chip 40 as standard serial data to the first daisy-chain serial peripheral interface circuit 301. The first daisy-chain serial peripheral interface circuit 301 is configured to convert the standard serial data into corresponding differential data and to send the corresponding differential data to the analog front-end chip 10. The first daisy-chain serial peripheral interface circuit 301 is further configured to receive data from the analog front-end chip 10 and to send the data received from the analog front-end chip 10 as corresponding differential data to the first standard serial peripheral interface circuit 302. The first standard serial peripheral interface circuit 302 converts the differential data into corresponding standard serial data and to send the corresponding standard serial data to the processor chip 40. Therefore, isolated communication between the analog front-end chip 10 and the processor chip 40 is performed via the dedicated integrated chip 30.

[0146] Similarly, in this embodiment, as shown in Figure 2, the dedicated integrated chip 30 includes a second daisy-chain serial peripheral interface circuit 303, and the dedicated integrated chip 30 is connected to the high-voltage management chip 20 via the second daisy-chain serial peripheral interface circuit 303. In other words, communication between the dedicated integrated chip 30 and the high-voltage management chip 20 is carried out via the second daisy-chain serial peripheral interface circuit 303. The daisy-chain serial peripheral interface circuit performs a communication isolation function, can reduce signal crosstalk, and can improve communication stability.

[0147] As shown in Figure 2, the dedicated integrated chip 30 further includes a second standard serial peripheral interface circuit 304. One end of the second standard serial peripheral interface circuit 304 is electrically connected to a second daisy-chain serial peripheral interface circuit 303, and the other end of the second standard serial peripheral interface circuit 304 is electrically connected to the processor chip 40.

[0148] In other words, isolated data communication between the processor chip 40 and the high-voltage management chip 20 is performed via the second daisy-chain serial peripheral interface circuit 303 and the second standard serial peripheral interface circuit 304 of the dedicated integrated chip 30.

[0149] Specifically, the second standard serial peripheral interface circuit 304 is configured to receive data from the processor chip 40 and transmit the data received from the processor chip 40 as standard serial data such as "1" and "0" to the second daisy-chain serial peripheral interface circuit 303. The second daisy-chain serial peripheral interface circuit 303 is configured to convert the standard serial data into corresponding differential data and send the corresponding differential data to the high-voltage management chip 20. The second daisy-chain serial peripheral interface circuit 303 is further configured to receive data from the high-voltage management chip 20 and transmit the data received from the high-voltage management chip 20 as corresponding differential data to the second standard serial peripheral interface circuit 304. The second standard serial peripheral interface circuit 304 converts the differential data into corresponding standard serial data and sends the corresponding standard serial data to the processor chip 40. Thus, isolated communication between the high-voltage management chip 20 and the processor chip 40 is carried out via the dedicated integrated chip 30.

[0150] In addition, as shown in Figure 2, the dedicated integrated chip 30 further includes a first analog input interface circuit 305. One end of the first analog input interface circuit 305 is electrically connected to an external sensor, and the other end of the first analog input interface circuit 305 is electrically connected to a first digital logic circuit 34, configured to collect sensor information from the external sensor. For example, the external sensor may include a voltage sensor, a current sensor, etc. Analog detection signals, such as circuit signals or voltage signals, can be received via the first analog input interface circuit 305.

[0151] The dedicated integrated chip 30 further includes a first general-purpose input / output interface circuit 306. One end of the first general-purpose input / output interface circuit 306 is connected to a peripheral circuit such as an LED loop. The other end of the first general-purpose input / output interface circuit 306 is connected to a first digital logic circuit 34 and is configured to output control information for the first digital logic circuit 34 for the peripheral circuit, or to collect status information for the peripheral circuit.

[0152] The dedicated integrated chip 30 further includes at least one of a first I2C bus interface circuit, a first general-purpose asynchronous receiver / transmitter interface circuit, and a first controller area network bus interface circuit. At least one interface circuit is configured for electrical connection between the daisy-chain serial peripheral interface circuit of the dedicated integrated chip 30 and the processor chip 40, or at least one interface circuit is configured for communication between the dedicated integrated chip 30 and an external control system, thereby facilitating system expansion.

[0153] In conclusion, the dedicated integrated chip 30 in this embodiment of the application not only integrates the functions of a wide range of voltage inputs, multiple ports, and multiple output power supplies, but also provides a stable power supply required by the peripheral system. In addition, the dedicated integrated chip 30 integrates multiple interface circuits to exchange data with the control system of another system, convert interface data to different interface data formats, thereby providing interface data required for systems with lower information processing capabilities, and supporting the functional expansion of the dedicated integrated chip 30. Furthermore, the dedicated integrated chip 30 can be organized, for example, into a specific power network for a power system including internal and external electrical units of the battery management system 100 to perform multi-party monitoring and improve the overall consistency and reliability of the battery management system 100. A linear and stable power supply can be supplied via a power output port 33 connected to a power supply circuit 31 for systems not directly connected to a battery. In addition, controllable contactor outputs can be implemented through high-side and low-side drives to control the power supply for external electrical units.

[0154] The internal structure of the high-voltage management chip 20 in this embodiment of the present application is described below.

[0155] Figure 5 is a diagram of the internal structure of a high-voltage management chip 20 according to an embodiment of the present application. As shown in Figure 5, the high-voltage management chip 20 includes a signal input port 21 and a first detection circuit 22.

[0156] The signal input port 21 is configured to receive status parameter information of the battery pack. The first detection circuit 22 is connected to the power cord of the battery pack via the signal input port 21 and is configured to detect status parameter information of the battery pack, such as voltage signals and current signals, in order to perform detection of the battery pack's status parameter information. In this way, the high-voltage management chip 20 can perform battery status estimation and other operations based on the detected information, and can also send the information to the processor chip 40 via the dedicated integrated chip 30, which in turn allows the processor chip 40 to perform management, task scheduling, and other operations based on such information.

[0157] The high-voltage management chip 20 includes a peripheral differential detection circuit 23, one end of which is connected to the power cord of the battery pack, and the other end of which is connected to the signal input port 21 of the high-voltage management chip 20. The first detection circuit 22 detects the status parameter information of the battery pack via the peripheral differential detection circuit 23.

[0158] Specifically, the peripheral differential detection circuit 23 detects status parameter information of the battery pack, such as voltage differential signals and current differential signals, and can send the detected status parameter information of the battery pack to the first detection circuit 22 of the high-voltage management chip 20 via the signal input port 21. As a result, the first detection circuit 22 detects the status parameter information of the battery pack.

[0159] As shown in Figure 5, the first detection circuit 22 includes a first voltage detection circuit 221. The first voltage detection circuit 221 is connected to a signal input port 21 and is configured to detect voltage information of the battery pack.

[0160] In this embodiment, the first voltage detection circuit 221 can be an AD circuit. The peripheral differential detection circuit 23 detects the voltage information of the battery pack and sends the voltage information to the first voltage detection circuit 221 of the high voltage management chip 20 via the signal input port 21. The first voltage detection circuit 221 acquires and converts the voltage information.

[0161] As shown in Figure 5, the first detection circuit 22 includes a first current detection circuit 222. The first current detection circuit 222 is connected to a signal input port 21 and is configured to detect current information of the battery pack.

[0162] Specifically, the first current detection circuit 222 can be an AD circuit. The peripheral differential detection circuit 23 detects the current signal of the battery pack and sends the current information to the first current detection circuit 222 of the high-voltage management chip 20 via the signal input port 21. The first current detection circuit 222 acquires the current information and converts it.

[0163] In this embodiment, the processor chip 40 managing the battery management system according to the status parameter information of the battery cells and / or the status parameter information of the battery pack includes the processor chip 40 estimating the charge state value and / or health state value of the battery pack according to the voltage information and current information of the battery pack.

[0164] Specifically, the first voltage detection circuit 221 and the first current detection circuit 222 of the high-voltage management chip 20 acquire voltage and current information from the battery pack separately and send the voltage and current information to the processor chip 40 via the dedicated integrated chip 30. The processor chip 40 estimates the charge status value and / or health status value based on the SOC algorithm according to the voltage and current information of the battery pack. Furthermore, the processor chip 40 can perform tasks such as scheduling power information and adjusting the operating status of each electrical unit based on the charge status of the battery pack.

[0165] In this embodiment of the present application, the high-voltage management chip 20 can have data processing capabilities, for example, it can perform corresponding estimations based on the status parameter information of the battery pack, share data processing tasks with the processor chip 40, thereby reducing the data processing workload of the processor chip 40 and improving the data processing efficiency of the processor chip 40.

[0166] As shown in Figure 5, the high-voltage management chip 20 includes a data processing circuit 24. The data processing circuit 24 is individually connected to a first voltage detection circuit 221 and a first current detection circuit 222, and is configured to estimate the charge state value and / or health state value of the battery pack according to the voltage and current information of the battery pack.

[0167] In this embodiment, the data processing circuit 24 can be a digital logic circuit, which has data processing capability, i.e., a more powerful data processing capability compared to a simple digital logic circuit. For example, the data processing circuit 24 can estimate the charge state and / or health state of a battery pack, etc., share the computational tasks of the processor chip 40, and improve data processing efficiency. Furthermore, it can perform corresponding function protection, fault handling, etc., based on the data processing results.

[0168] In this embodiment, the processor chip 40 can estimate the charge state value of the battery pack based on the status parameter information of the battery cells and / or the status parameter information of the battery pack. Specifically, based on different charge state value estimation algorithms, for example, a method for estimating the charge state value based on the status parameters of the battery cells and a method for estimating the charge state value based on the status parameters of the battery pack, the processor chip 40 can estimate the charge state value of the battery pack according to the status parameter information of the battery cells, or the processor chip 40 can estimate the charge state value of the battery pack according to the status parameter information of the battery pack, or the processor chip 40 can estimate the charge state value of the battery pack by combining the status parameter information of the battery cells and the status parameter information of the battery pack.

[0169] Furthermore, the processor chip 40 can obtain the battery pack's charge status value estimated by the high-voltage management chip 20 via the dedicated integrated chip 30, and verify the battery status according to the battery pack's charge status value estimated by the processor chip 40 and the battery pack's charge status value estimated by the high-voltage management chip 20. For example, if the two values ​​match, the battery status is considered normal; otherwise, if there is a difference between the two values ​​that exceeds the acceptable range, the battery pack is considered abnormal. In this way, mutual verification can be performed.

[0170] In some embodiments, as shown in Figure 5, the first detection circuit 22 includes an insulation resistance detection circuit 223. The insulation resistance detection circuit 223 is connected to a signal input port 21 and is configured to detect the resistance between the battery pack's power cord and the vehicle body's insulating ground. The data processing circuit 24 is further configured to determine the battery pack's leakage status according to the resistance, and to issue an alarm and take timely action if a leakage is detected.

[0171] Specifically, the insulation resistance detection circuit 223 may be an AD circuit, or it may detect the insulation resistance via an adjacent insulation resistance detection bridge. The insulation resistance detection circuit 223 acquires the resistance via the signal input port 21 and sends the resistance to the data processing circuit 24. The data processing circuit 24 calculates and stores the current insulation resistance of the battery pack, thereby improving safety.

[0172] In this embodiment, the high-voltage management chip 20 further includes a first safety diagnostic circuit 25. The first safety diagnostic circuit 25 is connected to a first detection circuit 22 and is configured to identify whether the status parameter information of the battery pack is abnormal and to perform safety protection if the status parameter information of the battery pack is abnormal, for example, by disconnecting the power supply circuit of the battery pack.

[0173] Specifically, the first safety diagnostic circuit 25 includes a first current diagnostic circuit 251. The first current diagnostic circuit 251 is connected to a first current detection circuit 222 and is configured to identify whether there is an overcurrent in the battery pack according to the current information of the battery pack, and to perform overcurrent protection if there is an overcurrent in the battery pack.

[0174] Specifically, the first current detection circuit 222 receives current information from the battery pack via the signal input port 21 and sends the current information to the first current diagnostic circuit 251. The first current diagnostic circuit 251 identifies whether the current value in the current information exceeds the overcurrent threshold, and if it does, it determines that there is an overcurrent in the battery pack. In this case, disconnection protection and the like can be performed through the monitoring loop, and the overcurrent protection trigger signal is fed back to the processor chip 40 to further perform overcurrent protection processing.

[0175] Specifically, the signal input port 21, the first current detection circuit 222, the first current diagnostic circuit 251, and the processor chip 40 form a current detection and protection loop. The loop detects the differential current between the two ends of the battery group, converts the differential current value into a numerical value, stores the numerical value, and performs related calculations. During detection, overcurrent protection is continuously performed for the input current signal, and related protection measures such as open-circuit protection and short-circuit protection are implemented for the current monitoring loop.

[0176] The first safety diagnostic circuit 25 includes a first voltage diagnostic circuit 252. The first voltage diagnostic circuit 252 is connected to a first voltage detection circuit 221 and is configured to identify whether the battery pack has an overvoltage or undervoltage according to the voltage information of the battery pack, and to perform overvoltage or undervoltage protection if the battery pack has an overvoltage or undervoltage.

[0177] Specifically, the first voltage detection circuit 221 receives voltage information from the battery pack via the signal input port 21 and sends the voltage information to the first voltage diagnostic circuit 252. The first voltage diagnostic circuit 252 identifies whether the voltage value in the voltage information exceeds the overvoltage threshold or falls below the undervoltage threshold. If the overvoltage threshold is exceeded, it is determined that there is overvoltage in the battery pack, and if the voltage value falls below the undervoltage threshold, it is determined that there is undervoltage in the battery pack. In this case, disconnection protection, etc., can be performed in the monitoring loop, and the overvoltage or undervoltage protection trigger signal is fed back to the processor chip 40 to further perform overvoltage or undervoltage protection processing.

[0178] Specifically, the signal input port 21, the first voltage detection circuit 221, the first voltage diagnostic circuit 252, and the processor chip 40 form a high-voltage detection and protection loop. The loop detects the differential voltage between the two ends of the battery group, converts the differential voltage value into a numerical value, and stores the value. During detection, overvoltage / undervoltage protection is continuously performed for the input signal, and related protection measures such as open-circuit protection and short-circuit protection can be implemented for the monitoring loop.

[0179] As shown in Figure 5, the high-voltage management chip 20 includes a second general-purpose input / output interface circuit 26. The second general-purpose input / output interface circuit 26 is connected to an external sensor and an external load and is configured to collect information from the external sensor or output control signals to the external load. For example, the external sensor may include a temperature sensor configured to detect temperature information from the high-voltage management chip 20. In addition, the high-voltage management chip 20 can be connected to an external load via the second general-purpose input / output interface circuit 26 to perform control on the external load, etc.

[0180] In this embodiment, the high-voltage management chip 20 further includes a first temperature detection circuit 27 and a first temperature diagnostic circuit 28.

[0181] The first temperature detection circuit 27 is connected to an external temperature sensor via a second general-purpose input / output interface circuit 26 to detect temperature information of the high-voltage management chip 20. The first temperature diagnostic circuit 28 is connected to the first temperature detection circuit 27 and is configured to identify whether the high-voltage management chip 20 is overheating according to the temperature information of the high-voltage management chip 20, and to perform over-temperature protection if the high-voltage management chip 20 is overheating.

[0182] Specifically, the first temperature detection circuit 27 can receive a temperature detection signal via the second general-purpose input / output interface 26. In other words, the second general-purpose input / output interface 26, the first temperature detection circuit 27, the first temperature diagnostic circuit 28, and the processor chip 40 form a temperature detection and protection loop. The loop performs temperature detection in the current detection loop of the high-voltage management chip 20, converts the temperature-sensitive voltage value into a numerical value, stores the numerical value, performs specific correction and protection measures such as continuous thermal switch protection for the current collection loop through the temperature-sensitive parameters, and performs related protection measures such as open-circuit protection and short-circuit protection for the temperature-sensitive monitoring loop.

[0183] In this embodiment, the processor chip 40 is further configured to acquire at least one of the detection information, calculation result information, safety diagnostic information, and safety alarm information from the high-voltage management chip 20 via the dedicated integrated chip 30. For example, the processor chip 40 can acquire voltage information, current information, etc. of the battery pack detected by the high-voltage management chip 20, acquire the SOC value of the battery pack estimated by the high-voltage management chip 20 and perform mutual verification, and can acquire safety diagnostic information of the high-voltage management chip 20, such as overvoltage, overcurrent, undervoltage, and overtemperature, and can feed back safety alarm information to the processor chip 40 if the high-voltage management chip 20 determines through diagnosis that a safety exception has occurred in the battery pack. The processor chip 40 can determine protective measures based on the diagnostic results. For example, protective measures may include stopping the relevant detection step, stopping the relevant calculation step to perform further detection and diagnosis such as open circuit detection or short circuit detection, and issuing an alarm to a higher-level control system.

[0184] In summary, the high-voltage management chip 20 of this embodiment of the present application can detect differential voltage and differential current between two ends of a battery group, detect insulation resistance and ambient temperature sensitive values ​​of the battery group, and provide calculations, functional safety protection, safety measures, and the like.

[0185] As shown in Figure 5, the high-voltage management chip 20 further includes a third daisy-chain serial peripheral interface circuit 201. As shown in Figures 1 and 2, the high-voltage management chip 20 is connected to the second daisy-chain serial peripheral interface circuit 303 of the dedicated integrated chip 30 via the third daisy-chain serial peripheral interface circuit 201, and as a result, communication between the dedicated integrated chip 30 and the high-voltage management chip 20 is carried out via the third daisy-chain serial peripheral interface circuit 201 and the second daisy-chain serial peripheral interface circuit 303. The daisy-chain serial peripheral interface circuits perform a function of communication isolation, can reduce signal crosstalk and improve communication stability.

[0186] The high-voltage management chip 20 includes at least one of a second standard serial peripheral interface circuit and a second I2C bus interface circuit, and at least one of the second standard serial peripheral interface circuit and the second I2C bus interface circuit can be configured for connection between the high-voltage management chip 20 and the processor chip 40. In this application, the high-voltage management chip 20 is connected to the processor chip 40 via a dedicated integrated chip 30. Thus, the second standard serial peripheral interface circuit and the second I2C bus interface circuit can still be kept as standby interface circuits.

[0187] The high-voltage management chip 20 includes a second controller area network bus interface circuit 202. The second controller area network bus interface circuit 202 is configured to connect to an external communication bus to acquire external bus information and to perform data exchange between the high-voltage management chip 20 and the external communication bus.

[0188] Specifically, the processor chip 40 is bridged to the dedicated integrated chip 30 and connected to the high-voltage management chip 20 via a daisy-chain serial peripheral interface circuit. Through this connection, the processor chip 40 can participate in the management tasks of the high-voltage management chip 20. The processor chip 40 can analyze the status of high-voltage signals by setting relevant parameters (operating behavior, operating mode, interface parameters, and time parameters) and reading differential and computational data collected by the high-voltage management chip 20. It can also analyze the operating status of the high-voltage management chip 20 by reading relevant registration data and functional safety detection data. In addition, the processor chip 40 can further set relevant parameters via the analysis interface to manage the monitoring chip system with higher information processing capabilities.

[0189] The internal structure of the analog front-end chip 10 in this embodiment of the present application is described below.

[0190] Figure 6 is a diagram of the internal structure of the analog front-end chip 10 according to an embodiment of the present application. As shown in Figure 6, the analog front-end chip 10 includes a second detection circuit 11. The second detection circuit 11 is connected to a battery group and is configured to detect status parameter information of battery cells in the battery group, such as current value, voltage value, stress, and temperature, for use in safety diagnostics and monitoring of the analog front-end chip 10. The status parameter information can also be sent to the processor chip 40 via a dedicated integrated chip 30 so that the processor chip 40 can properly manage the battery management system 100.

[0191] As shown in Figure 6, the analog front-end chip 10 further includes an analog input interface circuit 12. The second detection circuit 11 is connected to an external detection circuit via the analog input interface circuit 12 to detect status parameter information of battery cells in the battery group.

[0192] Specifically, the second detection circuit 11 may be an A / D circuit that detects status parameter information of battery cells in a battery group, such as voltage, current, and stress, via an external detection circuit, and sends the analog values ​​of the detected status parameter information to the second detection circuit 11 via the analog input interface circuit 12. The second detection circuit 11 converts and stores the analog values ​​of the status parameter information of the battery cells.

[0193] The analog front-end chip 10 further includes a third general-purpose input / output interface circuit 13. The third general-purpose input / output interface circuit 13 is connected to an external sensor, and the second detection circuit 11 is connected to the external sensor via the third general-purpose input / output interface circuit 13 to detect status parameter information of battery cells in a battery group, such as temperature information.

[0194] As shown in Figure 6, the second detection circuit 11 includes a second voltage detection circuit 111, which is configured to collect voltage information of battery cells in a battery group. For example, the second voltage detection circuit 111 can be an A / D circuit. The external voltage detection circuit detects the voltage value of the battery cells and transmits the voltage value to the second voltage detection circuit 111 via the analog input interface circuit 12. The second voltage detection circuit 111 converts the analog voltage value and performs voltage detection.

[0195] The second detection circuit 11 further includes a second current detection circuit 112, which is configured to collect current information of battery cells in a battery group. For example, the second current detection circuit 112 can be an A / D circuit. The external current detection circuit detects the current value of the battery cells and transmits the current value to the second current detection circuit 112 via the analog input interface circuit 12. The second current detection circuit 112 converts the analog current value and performs current detection.

[0196] The second detection circuit 11 further includes a stress detection circuit 113. The stress detection circuit 113 is configured to detect stress information of battery cells in a battery group. For example, the stress detection circuit 113 can be an A / D circuit. The external stress detection circuit detects the stress value of the battery cells and transmits the stress value to the stress detection circuit 113 via the analog input interface circuit 12. The stress detection circuit 113 converts the analog stress value and performs stress detection.

[0197] The second detection circuit 11 may further include a second temperature detection circuit 114. The second temperature detection circuit 114 is configured to detect temperature information of battery cells in a battery group. For example, the second temperature detection circuit 114 may be an AD circuit. An external sensor detects temperature information and transmits the temperature information to the second temperature detection circuit 114 via a third general-purpose input / output interface circuit 13.

[0198] As shown in Figure 6, the analog front-end chip 10 further includes a second safety diagnostic circuit 14. The second safety diagnostic circuit 14 is connected to the second detection circuit 11 and is configured to identify whether the status parameter information of the battery cells in the battery group is abnormal, and to perform safety protection if the status parameter information of the battery cells is abnormal.

[0199] The analog front-end chip 10 further includes a second digital logic circuit 15. The second digital logic circuit 15 is connected to a second safety diagnostic circuit 14 and is configured to generate exception information and provide an alarm prompt when the status parameter information of the battery cells in the battery group is abnormal.

[0200] The second safety diagnostic circuit 14 includes a second voltage diagnostic circuit 141. The second voltage diagnostic circuit 141 is connected to the second voltage detection circuit 111 and is configured to identify whether there is an overvoltage or undervoltage in the battery cells of the battery group, and to perform overvoltage or undervoltage protection if there is an overvoltage or undervoltage in the battery cells.

[0201] In some embodiments, the second voltage diagnostic circuit 141 is further configured to identify whether the voltage of the battery group is abnormal, whether the voltage of the internal components of the analog front-end chip 10 is abnormal, and to perform voltage safety protection if an exception occurs.

[0202] Specifically, the analog input interface circuit 12, the second voltage detection circuit 111, the second voltage diagnostic circuit 141, and the second digital logic circuit 15 form a voltage detection and protection loop. The loop detects the operating voltage between the two ends of a connected battery group or battery cell, converts the voltage value between the two ends of the battery cell, i.e., between the positive and negative terminals of the battery cell, into a numerical value, and stores the numerical value. During detection, overvoltage / undervoltage protection is continuously performed for the input signal, open-circuit protection and short-circuit protection can be implemented for the monitoring loop, and relevant monitoring and protection measures can be implemented for the components of the loop and the parameters of the components.

[0203] The second safety diagnostic circuit 14 further includes a second current diagnostic circuit 142. The second current diagnostic circuit 142 is connected to the second current detection circuit 112 and is configured to identify whether there is an overcurrent in the battery cells of the battery group and to perform overcurrent protection if there is an overcurrent in the battery cells.

[0204] In this embodiment, the second current detection circuit 112 is further configured to detect the current of the battery group and the current of the internal components of the analog front-end chip 10, and the second current diagnostic circuit 142 is further configured to diagnose whether the current of the battery group is abnormal, identify whether the current of the internal components of the analog front-end chip 10 is abnormal, and perform current abnormality safety protection if there is an abnormal current.

[0205] Specifically, the analog input interface circuit 12, the second current detection circuit 112, the second current diagnostic circuit 142, and the second digital logic circuit 15 form a current detection and protection loop. The loop detects the current between the two ends of the battery group, converts the current value into a numerical value, and stores the numerical value. During detection, overcurrent protection is continuously performed for the input current signal, protection measures such as open-circuit protection, short-circuit protection, and over-temperature protection are implemented for the current monitoring loop, and relevant monitoring and protection measures are implemented for the components of the loop and the parameters of the components.

[0206] The second safety diagnostic circuit 14 further includes a stress diagnostic circuit 143. The stress diagnostic circuit 143 is configured to identify whether the stress on the battery cells in the battery group is abnormal and to perform stress abnormality safety protection if the stress is abnormal.

[0207] Specifically, the analog input interface circuit 12, stress detection circuit 113, stress diagnostic circuit 143, and second digital logic circuit 15 form a current detection and protection loop. The loop detects internal and external stress on the battery cell, converts the stress value into a numerical value, and stores the value. During detection, the input stress signal is continuously threshold-limited, and protective measures such as open-circuit protection, short-circuit protection, and over-temperature protection are implemented for the stress monitoring loop, and relevant monitoring and protection measures are implemented for the loop components and component parameters.

[0208] The second safety diagnostic circuit 14 further includes a second temperature diagnostic circuit 144. The second temperature diagnostic circuit 144 is connected to the second temperature detection circuit 114 and is configured to identify whether there is an overtemperature in the battery cells of the battery group and to perform overtemperature safety protection if there is an overtemperature in the battery cells.

[0209] Specifically, the third general-purpose input / output interface circuit 13, the second temperature detection circuit 114, the second temperature diagnostic circuit 144, and the second digital logic circuit 15 form a temperature detection and protection loop. The loop detects temperature changes outside the battery connected to the current analog front-end chip, converts the aforementioned temperature-sensitive voltage values ​​into numerical values, and stores these values. During detection, protection such as over-temperature protection, under-temperature protection, and thermal switch protection is continuously performed for the detected temperature-sensitive signals, open-circuit protection and short-circuit protection are implemented for the temperature-sensitive monitoring loop, and relevant monitoring and protection measures are implemented for the components of the loop and the parameters of the components.

[0210] In summary, the analog front-end chip 10 of this embodiment of the present application is provided with a number of safety protection functions, including, but not limited to, overvoltage / undervoltage protection, overtemperature protection, undertemperature protection, stress protection, and open-circuit / short-circuit protection.

[0211] In this embodiment, the processor chip 40 can further acquire at least one of the detection information, safety diagnostic information, safety alarm information, and calculation result information of the analog front-end chip 10 via the dedicated integrated chip 30, and perform task scheduling and management based on the acquired information of the analog front-end chip 10. The processor chip 40 can further control the status transitions of the analog front-end chip 10 and determine the information acquisition method, communication mode, etc.

[0212] In this embodiment, when managing the battery management system 100, the processor chip 40 can be configured to determine the battery state according to the status parameter information of the battery cells and the status parameter information of the battery pack, and to determine whether to continue charging or discharging the battery pack or to stop charging or discharging the battery pack according to the battery state, for example, to determine whether to perform charging or discharging or stop charging according to the charge state value of the battery pack.

[0213] In some embodiments, as shown in Figure 6, the high-voltage management system 20 further includes an equalization circuit 16.

[0214] The processor chip 40 is configured to manage the battery management system 100 according to the status parameter information of the battery cells and the status parameter information of the battery pack. This configuration includes the processor chip 40 generating power equalization information when it determines that the power of the battery cells in the battery group is unbalanced according to the status parameter information of the battery cells in the battery group, and transferring the power equalization information to the front-end analog chip 10 via a dedicated integrated chip 30. The equalization circuit 16 of the analog front-end chip 10 is configured to perform power equalization processing on the battery cells in the battery group according to the power equalization information, thereby improving the power equalization of the battery cells, improving the usability of the battery cells, and extending the service life of the battery pack.

[0215] Specifically, in order to prevent capacity mismatches between battery cells in a group of batteries connected to the analog front-end chip 10, or capacity mismatches between battery cells in one battery group and battery cells in another battery group, the analog front-end chip 10 initiates an equalization function and can discharge the electrical charge of battery cells with slightly larger capacities in a battery group.

[0216] Furthermore, in this embodiment, the battery pack may include multiple battery groups, each of which is connected to an analog front-end chip 10. As shown in Figure 1, there are multiple analog front-end chips 10, which are connected in series. Each analog front-end chip 10 is configured to detect status parameter information of the battery cells in the battery group to which it is connected.

[0217] In some embodiments, the plurality of analog front - end chips 10 can be connected in a daisy - chain manner. As shown in FIG. 1, there are two first daisy - chain serial peripheral interface circuits 301, through which the dedicated integrated chip 30 is connected to the analog front - end chip 10.

[0218] In addition, each analog front - end chip 10 includes at least two daisy - chain serial peripheral interface circuits. For example, each analog front - end chip 10 includes a fourth daisy - chain serial peripheral interface circuit 101 and a fifth daisy - chain serial peripheral interface circuit 102. In a plurality of analog front - end chips 10 connected in series, the first analog front - end chip 10 is connected to one of the first daisy - chain serial peripheral interface circuits 301 of the dedicated integrated chip 30 through the fourth daisy - chain serial peripheral interface circuit 101, and the last analog front - end chip 10 is connected to the other first daisy - chain serial peripheral interface circuit 301 of the dedicated integrated chip 30 through the fifth daisy - chain serial peripheral interface circuit 102 to implement communication between each analog front - end chip 10 and the dedicated integrated chip 30.

[0219] Furthermore, as shown in FIG. 1, in a plurality of analog front - end chips 10 connected in series, the nth analog front - end chip 10 is connected to the fourth daisy - chain serial peripheral interface circuit 101 of the (n + 1)th analog front - end chip 10 through the fifth daisy - chain serial peripheral interface circuit 102, where 1≦n<n + 1≦N, and N is the total number of a plurality of analog front - end chips 10 connected in series.

[0220] In some embodiments, as shown in Figure 6, the analog front-end chip 10 includes at least one of a third standard serial peripheral interface circuit and a third I2C bus interface circuit, the at least one of which is a standby interface circuit. When the analog front-end chip 10 is not connected to the processor chip 40 via the dedicated integrated chip 30, communication between the analog front-end chip 10 and the processor chip 40 can be performed via the standby interface circuit, or the analog front-end chip 10 can be connected to another control or monitoring system via the standby interface circuit. This is not specifically limited herein.

[0221] In summary, the analog front-end chip 10 in this embodiment of the application can be connected to a single battery cell or to a battery group in which multiple battery cells are cascaded. The analog front-end chip 10 can collect battery parameters such as current, voltage, stress, and temperature, and provide relevant functional safety protection. In addition, the analog front-end chip 10 can perform calculations such as SOC and SOH calculations according to these parameters.

[0222] Specifically, the processor chip 40 can be bridged to a dedicated integrated chip 30 and connected to the analog front-end chip 10 via a daisy-chain serial peripheral interface circuit. Through this connection, the processor chip 40 can perform management tasks on the analog front-end chip 10. The processor chip 40 can analyze the collected battery-related operating status by setting relevant parameters (operating behavior, operating mode, interface parameters, and time parameters) and reading data and computation data collected by the analog front-end chip 10. The processor chip 40 further performs equalization operations on the relevant chips and batteries according to the analysis results and helps to further set relevant parameters by analyzing the operating status of the analog front-end chip 10 and reading relevant registration data and functional safety detection data.

[0223] Based on the description of the embodiments above, Figure 7 is a flowchart of signal exchange between various chips in the battery management system 100 according to an embodiment of the present application. As shown in Figure 7, the flowchart includes the following steps.

[0224] S10: A dedicated integrated chip is connected to the battery to obtain startup power, and after startup, it generates a stable power supply from an external source.

[0225] S11: The processor chip starts up by obtaining power from a dedicated integrated chip.

[0226] S12: The processor chip scans the devices mounted on the protocol interface of the dedicated integrated chip via a bridge connection with the dedicated integrated chip.

[0227] S13: The processor chip detects the analog front-end chip and high-voltage management chip via the daisy-chain serial peripheral interface, and the processor chip sends instructions to set the relevant parameters of the chips according to the requirements, and instructions to perform battery parameter collection.

[0228] S14: After receiving an instruction, the analog front-end chip and high-voltage management chip first verify the data of the received instruction. If the instruction data is valid, they correct the internal parameters and begin data acquisition, or if an exception occurs, they report the error to the processor chip.

[0229] S15: After data acquisition is complete, the dedicated integrated chip sends the acquired data, computation data, operating environment status data, and safety data requested by the processor chip to the corresponding interface via the daisy-chain serial peripheral interface circuit.

[0230] S16: After receiving the data, the dedicated integrated chip first verifies the data, and if the data is correct, converts the data into the data format of the bridge interface protocol for the processor chip and sends the data to the processor chip, or if the data is abnormal, requests the relevant chip to send the data again.

[0231] S17: After receiving battery-related parameters from the analog front-end chip and high-voltage management chip, the processor chip performs relevant calculations such as SOC, SOH, or SOP calculations to obtain highly accurate values, check the operating environment of the dedicated integrated chip, determine if an exception has occurred, check the functional safety status of the dedicated integrated chip, and diagnose any malfunctions.

[0232] S18: The processor chip generates relevant adjustment requirements such as equalization according to the calculation results, and generates relevant further diagnostic and safety measure execution requirements according to the detection results, and sends the requirements to the analog front-end chip and high-voltage management chip via a dedicated integrated chip, in which case the processor chip can further update the battery operation status to a higher-level processing system.

[0233] Overall, the battery management system 100 in this embodiment of the present application is based on the configuration of an analog front-end chip 10, a high-voltage management chip 20, a dedicated integrated chip 30, and a processor chip 40, thereby reducing the number, cost, wiring, and complexity of independent components. In addition, the high-voltage management chip 20 can perform calculations related to the signals collected by the high-voltage management chip 20, and the processor chip 40 only needs to schedule the results of the calculations performed by the high-voltage management chip 20, and then perform further improvements according to the system data. Thus, the processor chip 40 has higher data acquisition efficiency and data processing efficiency, and as a result, the battery management system 100 is more stable and reliable. In addition, the dedicated integrated chip 30 supplies power to meet the different requirements of the processor chip 40, the high-voltage management chip 20, and expansion devices, thereby improving the system's power control to expansion devices, reducing the complexity of the system's circuitry and improving the consistency of the drive power supply, unlike conventional systems where power is supplied individually by separate devices. In addition, in this embodiment of the present application, each chip has complete functional safety means. Each chip is capable of detecting and diagnosing faults around the chip and is subject to systematic safety monitoring performed by the processor chip 40, thereby ensuring the complete state of high-level vehicle safety of the system in this application and reducing the system failure rate.

[0234] Based on the battery management system 100 in the above-described embodiment, a second embodiment of the present application provides a battery 2 as shown in Figure 10.

[0235] Battery 2 includes a battery pack 200. The battery pack 200 includes a plurality of battery groups, each battery group including at least one battery cell. The battery pack 200 is connected to the battery management system 100 in the embodiment described above, and each battery group is also connected to the battery management system 100.

[0236] Therefore, the battery 2 in this embodiment of the present application is connected to the battery management system 100 in the previously described embodiment. The battery management system 100 has a compact structure, a simple design, and high system safety and reliability, thereby improving the safety of battery use.

[0237] Based on the battery management system 100 in the above-described embodiment, a third embodiment of the present application further provides a vehicle 1.

[0238] Figure 8 is a block diagram of vehicle 1 according to an embodiment of the present application. As shown in Figure 8, vehicle 1 according to this embodiment of the present application includes the battery pack 200 and battery management system 100 in the previously described embodiment, the battery management system 100 being connected to the battery pack 200.

[0239] In some embodiments, the battery pack 200 may include a plurality of battery groups, each of which includes at least one battery cell.

[0240] Therefore, the vehicle 1 in this embodiment of the present application uses the battery management system 100 in the aforementioned embodiment, and has high operational efficiency, safety and reliability, as well as numerous application scenarios, thereby improving the efficiency and safety of vehicle battery management.

[0241] Based on the battery management system 100 in the above-described embodiment, a fourth embodiment of the present application further provides a battery management method.

[0242] Figure 9 is a flowchart of a battery management method according to an embodiment of this application. As shown in Figure 9, the method includes the following steps.

[0243] S100: The high-voltage management chip detects the status parameter information of the battery pack, and the analog front-end chip detects the status parameter information of the battery cells in the battery group, in which case the battery pack includes multiple battery groups, and each battery group includes at least one battery cell.

[0244] S200: A dedicated integrated chip transfers status parameter information of the battery pack and status parameter information of the battery cells in the battery group to the processor chip.

[0245] S300: The processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack.

[0246] According to the battery management method of this embodiment, data exchange between the analog front-end chip and the processor chip, and data exchange between the high-voltage management chip and the processor chip are performed via a dedicated integrated chip, thereby saving the interface resources of the processor chip, reducing the interface load on the processor chip, improving the data processing efficiency of the processor chip, and thereby improving the safety and reliability of the system.

[0247] In this embodiment, managing the battery management system by the processor chip includes, but is not limited to, acquiring the battery status through monitoring data, and determining whether to perform charging or discharging, and when to stop charging or discharging. The processor chip can estimate the charge status value of the battery pack according to the status parameter information of the battery pack and / or the status parameter information of the battery cells, and can further perform cross-validation with another estimation module. Furthermore, the processor chip can further perform monitoring, management, and control associated with functional safety. In addition, the processor chip can further perform parameter setting on each chip, and can perform task scheduling, adjustment of the operating status of each chip, etc., based on monitoring data.

[0248] In some embodiments, managing the battery management system by a processor chip according to battery cell status parameter information and battery pack status parameter information includes managing the status of the battery pack by the processor chip estimating the battery pack's charge state value and / or health state value according to the battery pack's voltage information and current information. For information regarding the estimation algorithm, please refer to the relevant technical description.

[0249] Furthermore, the processor chip can determine whether to charge or discharge the battery pack, and whether to stop charging or discharging the battery pack, according to the battery pack's charge state.

[0250] In some embodiments, the processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack, which includes the processor chip determining, according to the status parameter information of the battery cells in the battery group, that the power of the battery cells in the battery group is unbalanced, generating power equalization information, and transferring the power equalization information to the front-end analog chip via a dedicated integrated chip, thereby enabling the equalization circuit of the analog front-end chip to perform power equalization processing on the battery cells in the battery group.

[0251] In some embodiments, the processor chip can further manage and control the connection / disconnection of power and external electrical units for the internal electrical chip of the battery management system based on monitoring data.

[0252] For example, the processor chip generates power setting information according to the power requirements of the internal electrical chip of the battery management system, sends the power setting information to a dedicated integrated chip, and manages the battery management system when supplying operating power for the internal electrical chip.

[0253] The dedicated integrated chip can manage and control the internal power supply by controlling the power supply circuit of the dedicated integrated chip according to power setting information, thereby supplying operating power for at least one of the internal electrical chips of the battery management system.

[0254] In another embodiment, the processor chip generates a power switching channel selection control signal according to the power demand of an external electrical unit, and sends the power switching channel selection control signal to a dedicated integrated chip to manage the battery management system when connecting or disconnecting power for the external electrical unit.

[0255] The dedicated integrated chip controls the connection / disconnection between the external electrical unit connected to the power supply circuit and the power supply side, or the connection / disconnection between the external electrical unit and the power supply ground side, according to the power switching channel selection control signal, thereby managing the power supply for the external electrical unit.

[0256] In some embodiments of this application, the processor chip sends configuration information of a dedicated integrated chip to the dedicated integrated chip, obtains interface circuit transmission information of the dedicated integrated chip, and obtains at least one of the dedicated integrated chip's safety monitoring information, safety alarm information, and operating status information.

[0257] In this way, the processor chip can participate in the management tasks of the dedicated integrated chip. The processor chip can set relevant parameters (operating behavior, operating mode, interface parameters, and time parameters), exchange data with other chips via the dedicated integrated chip, thereby saving the processor chip's interface resources and improving the processor chip's data processing efficiency.

[0258] In some embodiments, the processor chip sends configuration information for the high voltage management chip to the high voltage management chip via a dedicated integrated chip and obtains detection information for the high voltage management chip via the dedicated integrated chip. In addition, the processor chip obtains at least one of the calculation result information, safety diagnostic information, and safety alarm information of the high voltage management chip via the dedicated integrated chip.

[0259] For example, the processor chip can acquire voltage and current information of the battery pack detected by the high-voltage management chip, acquire the battery pack's SOC value estimated by the high-voltage management chip and perform mutual verification, and acquire safety diagnostic information from the high-voltage management chip, such as overvoltage, overcurrent, undervoltage, and overtemperature. If the high-voltage management chip determines through diagnosis that a safety exception has occurred in the battery pack, it can feed back safety alarm information to the processor chip. The processor chip can determine protective measures based on the diagnostic results. For example, protective measures include stopping the relevant detection step, stopping the relevant calculation step, performing further detection and diagnosis such as open circuit detection or short circuit detection, and issuing an alarm to a higher-level control system.

[0260] In this way, the processor chip can participate in the management of the high-voltage management chip via a dedicated integrated chip. The processor chip can analyze the status of the high-voltage signal by setting relevant parameters (operating behavior, operating mode, interface parameters, and time parameters) and reading differential and computational data collected by the high-voltage management chip, and further analyze the operating status of the high-voltage management chip by reading relevant registration data and functional safety detection data. In addition, the processor chip can further set relevant parameters via an analysis interface to manage the monitoring chip system with higher information processing capabilities.

[0261] In some embodiments, the processor chip sends configuration information for the analog front-end chip to the analog front-end chip via a dedicated integrated chip and obtains detection information for the analog front-end chip via the dedicated integrated chip. In addition, the processor chip obtains at least one of the following from the analog front-end chip via the dedicated integrated chip: safety diagnostic information, safety alarm information, and calculation result information.

[0262] In this way, the processor chip can participate in the management of the analog front-end chip via a dedicated integrated chip. The processor chip can analyze the collected battery-related operating status by setting relevant parameters (operating behavior, operating mode, interface parameters, and time parameters) and reading data and computational data collected by the analog front-end chip. The processor chip further performs equalization operations on the relevant chip and battery according to the analysis results and helps to further set relevant parameters by analyzing the operating status of the analog front-end chip and reading relevant registration data and functional safety detection data.

[0263] In some embodiments of this application, the high-voltage management chip may have data processing capabilities. For example, the high-voltage management chip may estimate the charge state and / or health state values ​​of the battery pack according to the voltage and current information of the battery pack, thereby sharing data processing tasks with the processor chip and improving the data processing efficiency of the processor chip.

[0264] Furthermore, the processor chip obtains the battery pack's charge status value estimated by the high-voltage management chip via a dedicated integrated chip, and verifies the battery pack's status according to the battery pack's charge status value estimated by the processor chip and the battery pack's charge status value estimated by the high-voltage management chip, thereby performing mutual verification and improving the accuracy of the estimation.

[0265] In some embodiments, the status parameter information of the battery pack includes the resistance between the battery pack's power cord and the vehicle's insulating ground, and the battery management method further includes a high-voltage management chip determining the battery pack's leakage status according to the resistance, and if there is a leakage, generating leakage alarm information and transferring the information to a processor chip via a dedicated integrated chip, thereby enabling a leakage alarm to be issued and associated protective measures to be implemented.

[0266] In some embodiments, the high-voltage management chip identifies whether the battery pack's status parameter information is abnormal and, if so, performs safety protection. For example, this could be as follows: The high-voltage management chip identifies whether there is an overcurrent in the battery pack according to the battery pack's current information, and if there is an overcurrent in the battery pack, it performs overcurrent protection, and The high-voltage management chip identifies whether the battery pack has overvoltage or undervoltage based on the battery pack's voltage information, and performs overvoltage or undervoltage protection if the battery pack has overvoltage or undervoltage. It includes at least one of the following.

[0267] In some embodiments, the high-voltage management chip acquires temperature information of the high-voltage management chip, identifies whether the high-voltage management chip is overheated according to the temperature information of the high-voltage management chip, and performs overheat protection if the high-voltage management chip is overheated.

[0268] Similarly, in some embodiments, the analog front-end chip identifies whether the status parameter information of a battery cell is abnormal and performs safety protection if the status parameter information of a battery cell is abnormal. For example, this includes at least one of the following: the analog front-end chip identifies whether there is an overvoltage or undervoltage in the voltage of a battery cell in a battery group and performs overvoltage or undervoltage protection if there is an overvoltage or undervoltage in the voltage of a battery cell; the analog front-end chip identifies whether there is an overcurrent in the current of a battery cell and performs overcurrent protection if there is an overcurrent in the current of a battery cell; the analog front-end chip identifies whether the stress of a battery cell in a battery group is abnormal and performs safety protection if the stress is abnormal; and the analog front-end chip identifies whether there is an overtemperature in the temperature of a battery cell in a battery group and performs overtemperature safety protection if there is an overtemperature in the temperature of a battery cell.

[0269] In some other embodiments, the battery management method further includes at least one of the following: an analog front-end chip identifies whether the voltage of a group of batteries is abnormal, whether the voltage of the internal components of the analog front-end chip is abnormal, and if an exception occurs, performing voltage safety protection; and an analog front-end chip diagnoses whether the current of a group of batteries is abnormal, whether the current of the internal components of the analog front-end chip is abnormal, and if there is an abnormal current, performing current protection.

[0270] In conclusion, the battery management method in this embodiment of the application, based on the configuration of an analog front-end chip, a high-voltage management chip, a dedicated integrated chip, and a processor chip, reduces the complexity of the system design, improves data transmission efficiency, enhances the consistency of the data transmission path, and thereby improves the stability and reliability of the system. In addition, the high-voltage management chip can perform calculations related to the signals collected by the high-voltage management chip, and the processor chip only needs to schedule the results of the calculations performed by the high-voltage management chip, and then further perform improvements according to the system data, thereby improving data processing efficiency. Furthermore, each chip has complete functional safety measures. Each chip can detect and diagnose faults around the chip and is subject to systematic safety monitoring performed by the processor chip, thereby improving battery management and achieving more comprehensive safety protection. Thus, the battery management system is applicable to a wider range of application scenarios. In particular, the battery management system in this embodiment of the application is also applicable to scenarios requiring high efficiency, stability, and safety.

[0271] In this specification, reference terms such as “embodiment,” “some embodiments,” “exemplary embodiment,” “example,” “specific example,” and “some examples” are intended to indicate that certain features, structures, materials, or properties associated with an embodiment or example are included in at least one embodiment or example of this application. In this specification, the illustrative use of the aforementioned terms does not necessarily mean the same embodiment or example.

[0272] While embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and objectives of this application, and that the scope of this application is equivalent to the claims of this application and the art therein.

Claims

1. Battery management system (100), An analog front-end chip (10) connected to a battery group and configured to detect status parameter information of battery cells in the battery group, wherein the battery group comprises at least one battery cell. A high-voltage management chip (20) connected to the power cord of a battery pack (200) and configured to detect status parameter information of the battery pack (200), wherein the battery pack (200) comprises a group of batteries, A dedicated integrated chip (30), and A processor chip (40) electrically connected to the analog front-end chip (10) via the dedicated integrated chip (30), wherein the high-voltage management chip (20) is electrically connected to the processor chip (40) via the dedicated integrated chip (30), and the processor chip (40) is configured to manage the battery management system (100) according to the status parameter information of the battery cell and the status parameter information of the battery pack (200). A battery management system (100) is provided.

2. The dedicated integrated chip (30) is A power supply circuit (31) is connected to an external power supply and configured to supply operating power to at least one chip in the battery management system (100). A battery management system (100) according to claim 1, comprising:

3. The dedicated integrated chip (30) is A power input port (32) and a power output port (33), wherein the power supply circuit (31) is connected to the external power supply via the power input port (32), and the power supply circuit (31) is connected to the processor chip (40) via the power output port (33) to supply operating power for the processor chip (40). The battery management system (100) according to claim 2, further comprising the above.

4. The battery management system (100) according to claim 2 or 3, wherein the power supply circuit (31) is connected to the high voltage management chip (20) via the power output port (33) to supply operating power for the high voltage management chip (20).

5. The battery management system (100) according to claim 4, wherein the power supply circuit (31) comprises a voltage conversion subcircuit (311), one end of the voltage conversion subcircuit (311) is connected to the external power supply via the power input port (32), and the other end of the voltage conversion subcircuit (311) is connected to the processor chip (40) and the high voltage management chip (20), and is configured to apply different operating voltages for the processor chip (40) and the high voltage management chip (20).

6. The processor chip (40) is further configured to generate power setting information according to the power requirements of the internal electrical chip of the battery management system (100), send the power setting information to the dedicated integrated chip (30), and manage the battery management system (100) when supplying operating power for the internal electrical chip. The dedicated integrated chip (30) is A first digital logic circuit (34) is electrically connected separately to the processor chip (40) and the power supply circuit (31), and is configured to control the power supply circuit (31) according to the power setting information to supply the operating power for the internal electrical chip of the battery management system (100). Furthermore, A battery management system (100) according to any one of claims 2 to 5.

7. The dedicated integrated chip (30) is A power switching circuit (35), wherein a first end of the power switching circuit (35) is connected to the power supply circuit (31), a second end of the power switching circuit (35) is suitable for connecting to an external electrical unit, and the power switching circuit (35) is configured to control the power status of the external electrical unit to connect or disconnect it. The battery management system (100) according to claim 6, further comprising the above.

8. The aforementioned power switching circuit (35) A high-side drive subcircuit (351), wherein a first end of the high-side drive subcircuit (351) is connected to the output terminal of the power supply circuit (31), a second end of the high-side drive subcircuit (351) is suitable for connecting to the power supply side of the power loop of the external electrical unit, a third end of the high-side drive subcircuit (351) is suitable for connecting to the positive terminal of the external electrical unit, and the high-side drive subcircuit (351) is configured to control the connection / disconnection between the external electrical unit and the power supply side. A battery management system (100) according to claim 7, comprising:

9. The aforementioned power switching circuit (35) Low-side drive subcircuit (352), wherein a first end of the low-side drive subcircuit (352) is connected to the output terminal of the power supply circuit (31), a second end of the low-side drive subcircuit (352) is suitable for connecting to the power supply ground side of the power supply loop of the external electrical unit, a third end of the low-side drive subcircuit (352) is suitable for connecting to the negative terminal of the external electrical unit, and the low-side drive subcircuit (352) is configured to control the connection / disconnection between the external electrical unit and the power supply ground side. A battery management system (100) according to claim 8, comprising:

10. The aforementioned power switching circuit (35) An activation switching subcircuit (353) wherein one end of the activation switching subcircuit (353) is individually connected to the high-side drive subcircuit (351) and the low-side drive subcircuit (352), and the other end of the activation switching subcircuit (353) is connected to the power supply circuit (31), and is configured to control the connection / disconnection of the high-side drive subcircuit (351) and the low-side drive subcircuit (352). The battery management system (100) according to claim 9, further comprising the above.

11. The processor chip (40) is further configured to generate power switching channel selection control signals for the high-side drive subcircuit (351) and the low-side drive subcircuit (352) according to the power demand of the external electrical unit, send the power switching channel selection control signals to the dedicated integrated chip (30), and manage the battery management system (100) when connecting or disconnecting the power supply for the external electrical unit. The first digital logic circuit (34) is electrically connected to the activation switching subcircuit (353) and is configured to control the activation switching subcircuit (353) according to the power switching channel selection control signal. Battery management system (100) according to claim 10.

12. The dedicated integrated chip (30) is An input source detection subcircuit (36) is configured such that one end of the input source detection subcircuit (36) is connected to the external power supply via the power input port (32), and the other end of the input source detection subcircuit (36) is connected to the first digital logic circuit (34), and the subcircuit (36) detects the external power supply and transmits power supply detection information of the external power supply to the first digital logic circuit (34). The battery management system (100) according to claim 3, further comprising the above.

13. The dedicated integrated chip (30) is An input source isolation circuit (37) connected to the external power supply and the power supply circuit (31), wherein the power supply circuit (31) is connected to the external power supply via the input source isolation circuit (37). A battery management system (100) according to any one of claims 2 to 12, comprising:

14. The dedicated integrated chip (30) is A first daisy-chain serial peripheral interface circuit (301), wherein the dedicated integrated chip (30) is electrically connected to the analog front-end chip (10) via the first daisy-chain serial peripheral interface circuit (301). A battery management system (100) according to any one of claims 1 to 13, comprising:

15. The dedicated integrated chip (30) is A first standard serial peripheral interface circuit (302), wherein one end of the first standard serial peripheral interface circuit (302) is electrically connected to the first daisy-chain serial peripheral interface circuit (301), and the other end of the first standard serial peripheral interface circuit (302) is electrically connected to the processor chip (40). A battery management system (100) according to claim 14, comprising:

16. The first standard serial peripheral interface circuit (302) is configured to send standard serial data to the processor chip (40) or to receive data from the processor chip (40), and to transmit the data received from the processor chip (40) as standard serial data to the first daisy-chain serial peripheral interface circuit (301), and the first daisy-chain serial peripheral interface circuit (301) is configured to convert the standard serial data into corresponding differential data and to send the corresponding differential data to the analog front-end chip (10), The first daisy-chain serial peripheral interface circuit (301) is further configured to receive differential data from the analog front-end chip (10) and send the differential data received from the analog front-end chip (10) to the first standard serial peripheral interface circuit (302), the first standard serial peripheral interface circuit (302) converts the differential data into corresponding standard serial data and sends the corresponding standard serial data to the processor chip (40). Battery management system (100) according to claim 15.

17. The dedicated integrated chip (30) is A second daisy-chain serial peripheral interface circuit (303), wherein the dedicated integrated chip (30) is connected to the high-voltage management chip (20) via the second daisy-chain serial peripheral interface circuit (303). A battery management system (100) according to any one of claims 1 to 16, comprising:

18. The dedicated integrated chip (30) is A second standard serial peripheral interface circuit (304), wherein one end of the second standard serial peripheral interface circuit (304) is electrically connected to the second daisy-chain serial peripheral interface circuit (303), and the other end of the second standard serial peripheral interface circuit (304) is electrically connected to the processor chip (40). A battery management system (100) according to claim 17, comprising:

19. The second standard serial peripheral interface circuit (304) is configured to receive data from the processor chip (40) and transmit the data received from the processor chip (40) as standard serial data to the second daisy-chain serial peripheral interface circuit (303), and the second daisy-chain serial peripheral interface circuit (303) is configured to convert the standard serial data into corresponding differential data and send the corresponding differential data to the high-voltage management chip (20). The second daisy-chain serial peripheral interface circuit (303) is further configured to receive differential data from the high-voltage management chip (20) and send the differential data received from the high-voltage management chip (20) to the second standard serial peripheral interface circuit (304), the second standard serial peripheral interface circuit (304) converts the differential data into corresponding standard serial data and sends the corresponding standard serial data to the processor chip (40). Battery management system (100) according to claim 18.

20. The battery management system (100) according to claim 14 or 17, wherein the dedicated integrated chip (30) further comprises at least one of a first I2C bus interface circuit, a first general-purpose asynchronous receiver / transmitter interface circuit, and a first controller area network bus interface circuit, wherein the at least one interface circuit is configured for electrical connection between the daisy-chain serial peripheral interface circuit of the dedicated integrated chip (30) and the processor chip (40), or the at least one interface circuit is configured for communication between the dedicated integrated chip (30) and an external control system.

21. The dedicated integrated chip (30) is A first analog input interface circuit (305), wherein one end of the first analog input interface circuit (305) is electrically connected to an external sensor, and the other end of the first analog input interface circuit (305) is electrically connected to the first digital logic circuit (34) and configured to collect sensor information from the external sensor. A battery management system (100) according to any one of claims 6 to 11, further comprising the above.

22. The dedicated integrated chip (30) is A first general-purpose input / output interface circuit (306), wherein one end of the first general-purpose input / output interface circuit (306) is electrically connected to a peripheral circuit, and the other end of the first general-purpose input / output interface circuit (306) is connected to a first digital logic circuit (34), and is configured to output control information for the first digital logic circuit (34) for the peripheral circuit, or to collect status information for the peripheral circuit. A battery management system (100) according to any one of claims 6 to 11, further comprising the above.

23. The battery management system (100) according to any one of claims 2 to 22, wherein the processor chip (40) is further configured to send setting information of the dedicated integrated chip (30) to the dedicated integrated chip (30) and to acquire at least one of the interface circuit transmission information, safety monitoring information, safety alarm information and operation status information of the dedicated integrated chip (30).

24. The aforementioned high-voltage management chip (20) A signal input port (21) configured to input the status parameter information of the battery pack (200), and A first detection circuit (22) is connected to the power cord of the battery pack (200) via the signal input port (21) and is configured to detect the status parameter information of the battery pack (200). A battery management system (100) according to any one of claims 1 to 23, comprising:

25. The aforementioned high-voltage management chip (20) A peripheral differential detection circuit (23) wherein one end of the peripheral differential detection circuit (23) is connected to the power cord of the battery pack (200), and the other end of the peripheral differential detection circuit (23) is connected to the signal input port (21) of the high voltage management chip (20), and the first detection circuit (22) detects the status parameter information of the battery pack (200) via the peripheral differential detection circuit (23). The battery management system (100) according to claim 24, further comprising the above.

26. The first detection circuit (22) A first voltage detection circuit (221) is connected to the signal input port (21) and configured to detect voltage information of the battery pack (200). A battery management system (100) according to claim 24 or 25, comprising the above.

27. The first detection circuit (22) A first current detection circuit (222) is connected to the signal input port (21) and configured to detect current information of the battery pack (200). A battery management system (100) according to claim 26, comprising:

28. The processor chip (40) is configured to manage the battery management system (100) according to the status parameter information of the battery cell and / or the status parameter information of the battery pack (200). The processor chip (40) is configured to estimate the charge state value and / or health state value of the battery pack (200) according to the voltage information and current information of the battery pack (200). A battery management system (100) according to claim 27, comprising:

29. The aforementioned high-voltage management chip (20) A data processing circuit (24) is individually connected to the first voltage detection circuit (221) and the first current detection circuit (222), and is configured to estimate the charge state value and / or health state value of the battery pack (200) according to the voltage information and current information of the battery pack (200). A battery management system (100) according to claim 27 or 28, further comprising the above.

30. The first detection circuit (22) An insulation resistance detection circuit is connected to the signal input port (21) and configured to detect the resistance between the power cord of the battery pack (200) and the insulating ground of the vehicle body. Equipped with, The data processing circuit is connected to the insulation resistance detection circuit and is configured to determine the leakage current status of the battery pack (200) according to the resistance. Battery management system (100) according to claim 29.

31. The aforementioned high-voltage management chip (20) A first safety diagnostic circuit (25) is connected to the first detection circuit (22) and is configured to identify whether the status parameter information of the battery pack (200) is abnormal, and to perform safety protection if the status parameter information of the battery pack (200) is abnormal. A battery management system (100) according to any one of claims 26 to 30, further comprising:

32. The first safety diagnostic circuit (25) A first current diagnostic circuit (251) is connected to the first current detection circuit (222) and is configured to identify whether there is an overcurrent in the battery pack (200) according to the current information of the battery pack (200), and to perform overcurrent protection if there is an overcurrent in the battery pack (200). A battery management system (100) according to claim 31, comprising the above.

33. The first safety diagnostic circuit (25) A first voltage diagnostic circuit (252) is connected to the first voltage detection circuit (221) and is configured to identify whether the battery pack (200) has an overvoltage or undervoltage according to the voltage information of the battery pack (200), and to perform overvoltage or undervoltage protection if the battery pack (200) has an overvoltage or undervoltage. A battery management system (100) according to any one of claims 26 to 32, comprising:

34. The aforementioned high-voltage management chip (20) A second general-purpose input / output interface circuit (26) is connected to an external sensor or external load and configured to collect information from the external sensor or to output a control signal to the external load. A battery management system (100) according to any one of claims 1 to 33, comprising:

35. The aforementioned high-voltage management chip (20) A first temperature detection circuit (27) is connected to an external temperature sensor via the second general-purpose input / output interface circuit (26) to detect temperature information of the high-voltage management chip (20), and A first temperature diagnostic circuit (28) is connected to the first temperature detection circuit (27) and is configured to identify whether the high voltage management chip (20) is overheated according to the temperature information of the high voltage management chip (20), and to perform overheat protection if the high voltage management chip (20) is overheated. The battery management system (100) according to claim 34, further comprising the above.

36. The battery management system (100) according to any one of claims 1 to 35, wherein the processor chip (40) is further configured to send setting information of the high voltage management chip (20) to the high voltage management chip (20) via the dedicated integrated chip (30), and to acquire at least one of the detection information, calculation result information, safety diagnostic information and safety alarm information of the high voltage management chip (20) via the dedicated integrated chip (30).

37. The aforementioned high-voltage management chip (20) A third daisy-chain serial peripheral interface circuit (201), wherein the high-voltage management chip (20) is connected to the second daisy-chain serial peripheral interface circuit (303) of the dedicated integrated chip (30) via the third daisy-chain serial peripheral interface circuit (201). A battery management system (100) according to claim 17, comprising:

38. The battery management system (100) according to any one of claims 1 to 37, wherein the high-voltage management chip (20) comprises at least one of the second standard serial peripheral interface circuit (304) and the second I2C bus interface circuit, and at least one of the second standard serial peripheral interface circuit (304) and the second I2C bus interface circuit is a standby interface circuit.

39. The aforementioned high-voltage management chip (20) A second controller area network bus interface circuit (202) configured to connect to an external communication bus and acquire external bus information. A battery management system (100) according to any one of claims 1 to 38, comprising:

40. The aforementioned analog front-end chip (10) A second detection circuit (11) is connected to the battery group and configured to detect the status parameter information of the battery cells in the battery group. A battery management system (100) according to any one of claims 1 to 39, comprising:

41. The aforementioned analog front-end chip (10) A second analog input interface circuit (12), wherein the second detection circuit (11) is connected to an external detection circuit via the second analog input interface circuit (12) to detect the status parameter information of the battery cells in the battery group. The battery management system (100) according to claim 40, further comprising the above.

42. The aforementioned analog front-end chip (10) A third general-purpose input / output interface circuit (13) connected to an external sensor, wherein the second detection circuit (11) is connected to the external sensor via the third general-purpose input / output interface circuit (13) to detect the status parameter information of the battery cells in the battery group. A battery management system (100) according to claim 40 or 41, further comprising the above.

43. The second detection circuit (11) A second voltage detection circuit (111) configured to collect voltage information of the battery cells in the battery group. A battery management system (100) according to claim 40, comprising:

44. The second detection circuit (11) A second current detection circuit (112) configured to collect current information of the battery cells in the battery group. The battery management system (100) according to claim 43, further comprising the above.

45. The second detection circuit (11) A stress detection circuit (113) configured to detect stress information of the battery cells in the battery group. A battery management system (100) according to claim 44, further comprising the above.

46. The second detection circuit (11) A second temperature detection circuit (114) configured to detect temperature information of the battery cells in the battery group. The battery management system (100) according to claim 45, further comprising the above.

47. The front-end analog chip (10) A second safety diagnostic circuit (14) is connected to the second detection circuit (11) and is configured to identify whether the status parameter information of the battery cell is abnormal, and to perform safety protection if the status parameter information of the battery cell is abnormal. A battery management system (100) according to claim 46, further comprising the above.

48. The second safety diagnostic circuit (14) A second voltage diagnostic circuit (141) is connected to the second voltage detection circuit (111) and is configured to identify whether there is an overvoltage or undervoltage in the voltage of the battery cells in the battery group, and to perform overvoltage or undervoltage protection if there is an overvoltage or undervoltage in the voltage of the battery cells. A battery management system (100) according to claim 47, comprising:

49. The second voltage detection circuit (111) is further configured to detect the voltage of the battery group and the voltage of the internal components of the analog front-end chip (10), The second voltage diagnostic circuit (141) is further configured to identify whether the voltage of the battery group is abnormal, whether the voltage of the internal components of the analog front-end chip (10) is abnormal, and to perform voltage safety protection if an exception occurs. Battery management system (100) according to claim 48.

50. The second safety diagnostic circuit (14) A second current diagnostic circuit (142) is connected to the second current detection circuit (112) and is configured to identify whether there is an overcurrent in the current of the battery cell and to perform overcurrent protection if there is an overcurrent in the current of the battery cell. A battery management system (100) according to any one of claims 47 to 49, comprising:

51. The second current detection circuit (112) is further configured to detect the current of the battery group and the current of the internal components of the analog front-end chip (10), The second current diagnostic circuit (142) is further configured to diagnose whether the current of the battery group is abnormal, identify whether the current of the internal components of the analog front-end chip (10) is abnormal, and perform current abnormality safety protection if an abnormal current is present. Battery management system (100) according to claim 50.

52. The second safety diagnostic circuit (14) A stress diagnostic circuit (143) is configured to identify whether the stress on the battery cells in the battery group is abnormal, and to perform stress abnormality safety protection if the stress is abnormal. A battery management system (100) according to any one of claims 47 to 51, comprising:

53. The second safety diagnostic circuit (14) A second temperature diagnostic circuit (144) is connected to the second temperature detection circuit (114) and is configured to identify whether there is an overtemperature in the battery cells of the battery group, and to perform overtemperature safety protection if there is an overtemperature in the battery cells. A battery management system (100) according to any one of claims 47 to 52, comprising:

54. The aforementioned analog front-end chip (10) A second digital logic circuit (15) is connected to the second safety diagnostic circuit (14) and is configured to generate exception information and provide an alarm prompt when the status parameter information of the battery cells in the battery group is abnormal. A battery management system (100) according to any one of claims 47 to 53, further comprising:

55. The battery management system (100) according to claim 54, further configured such that the processor chip (40) sends setting information of the analog front-end chip (10) to the analog front-end chip (10) via the dedicated integrated chip (30), and acquires at least one of the detection information, safety diagnostic information, safety alarm information, and calculation result information of the analog front-end chip (10) via the dedicated integrated chip (30).

56. The processor chip (40) is configured to manage the battery management system (100) according to the status parameter information of the battery cells and the status parameter information of the battery pack (200), and the processor chip (40) is configured to generate power equalization information when it is determined that the power of the battery cells in the battery group is unbalanced according to the status parameter information of the battery cells in the battery group, and to transfer the power equalization information to the corresponding front-end analog chip via the dedicated integrated chip (30), The analog front-end chip (10) includes an equalization circuit (16) configured to perform power equalization processing on the battery cells in the battery group according to the power equalization information. A battery management system (100) according to any one of claims 1 to 55.

57. The processor chip (40) is configured to manage the battery management system (100) according to the status parameter information of the battery cells and the status parameter information of the battery pack (200), and the processor chip (40) is configured to determine the battery state according to the status parameter information of the battery cells and the status parameter information of the battery pack (200), and to determine whether to charge or discharge the battery pack (200) and whether to stop charging or discharging the battery pack (200) according to the battery state. A battery management system (100) according to any one of claims 1 to 56.

58. The battery management system (100) according to any one of claims 1 to 57, wherein the processor chip (40) is configured to manage the battery management system (100) according to the status parameter information of the battery cells and the status parameter information of the battery pack (200), the processor chip (40) is configured to estimate the charge state value of the battery pack (200) according to the status parameter information of the battery cells and / or the status parameter information of the battery pack (200), obtain the charge state value of the battery pack (200) estimated by the high voltage management chip (20), and perform battery state verification according to the charge state value of the battery pack (200) estimated by the processor chip (40) and the charge state value of the battery pack (200) estimated by the high voltage management chip (20).

59. The battery management system (100) according to claim 14, wherein there are multiple analog front-end chips (10), and the multiple analog front-end chips (10) are connected in series.

60. There are two first daisy-chain serial peripheral interface circuits (301), Each analog front-end chip (10) includes a fourth daisy-chain serial peripheral interface circuit and a fifth daisy-chain serial peripheral interface circuit. In the plurality of analog front-end chips (10) connected in series, the leading analog front-end chip (10) is connected to one of the first daisy-chain serial peripheral interface circuits (301) of the dedicated integrated chip (30) via the fourth daisy-chain serial peripheral interface circuit, and the last analog front-end chip (10) is connected to the other first daisy-chain serial peripheral interface circuit (301) of the dedicated integrated chip (30) via the fifth daisy-chain serial peripheral interface circuit. Battery management system (100) according to claim 59.

61. The battery management system (100) according to claim 60, wherein, in the plurality of analog front-end chips (10) connected in series, the nth analog front-end chip (10) is connected to the fourth daisy-chain serial peripheral interface circuit of the (n+1)th analog front-end chip (10) via the fifth daisy-chain serial peripheral interface circuit, such that 1 ≤ n < n+1 ≤ N, where N is the total number of the plurality of analog front-end chips (10) connected in series.

62. The battery management system (100) according to any one of claims 1 to 61, wherein the analog front-end chip (10) comprises at least one of a third standard serial peripheral interface circuit and a third I2C bus interface circuit, and at least one of the third standard serial peripheral interface circuit and the third I2C bus interface circuit is a standby interface circuit.

63. Battery (2), A battery pack (200) comprising multiple battery groups, wherein each battery group comprises at least one battery cell. Equipped with, The battery pack (200) is connected to the battery management system (100) described in any one of claims 1 to 62, and each battery group is connected to the battery management system (100). Battery (2).

64. A battery pack (200) comprising multiple battery groups, wherein each battery group comprises at least one battery cell, and A battery management system (100) according to any one of claims 1 to 62, which is connected to the aforementioned battery pack (200). A vehicle (1) equipped with the following:

65. A battery management method applicable to the battery management system (100) according to any one of claims 1 to 62, A high-voltage management chip detects the status parameter information of the battery pack, and an analog front-end chip detects the status parameter information of the battery cells in the battery group, wherein the battery pack comprises multiple battery groups, and each battery group comprises at least one battery cell. A dedicated integrated chip transfers the status parameter information of the battery pack and the status parameter information of the battery cells in the battery group to the processor chip, and The processor chip manages the battery management system according to the status parameter information of the battery cells and the status parameter information of the battery pack. A battery management method that includes the following features.

66. The processor chip manages the battery management system according to the status parameter information of the battery cell and the status parameter information of the battery pack. The processor chip estimates the charge state value and / or health state value of the battery pack according to the voltage information and current information of the battery cells, and / or the voltage information and current information of the battery pack. The battery management method according to claim 65, comprising:

67. The processor chip manages the battery management system according to the status parameter information of the battery cell and the status parameter information of the battery pack. The processor chip determines, according to the charge state of the battery pack, whether to charge or discharge the battery pack, and whether to stop charging or discharging the battery pack. The battery management method according to claim 66, further comprising:

68. The processor chip manages the battery management system according to the status parameter information of the battery cell and the status parameter information of the battery pack. The processor chip determines, based on the status parameter information of the battery cells in the battery group, that the power of the battery cells in the battery group is unbalanced, generates power equalization information, and transfers the power equalization information to the front-end analog chip via the dedicated integrated chip. A battery management method according to any one of claims 65 to 67, comprising:

69. The processor chip generates power setting information according to the power requirements of the internal electrical chip of the battery management system, sends the power setting information to the dedicated integrated chip, and manages the battery management system when supplying operating power for the internal electrical chip. A battery management method according to any one of claims 65 to 68, further comprising the above.

70. The processor chip generates a power switching channel selection control signal according to the power demand of the external electrical unit, sends the power switching channel selection control signal to the dedicated integrated chip to manage the battery management system when connecting or disconnecting the power supply for the external electrical unit, and The dedicated integrated chip controls the connection / disconnection between the external electrical unit connected to the power supply circuit and the power supply side, or controls the connection / disconnection between the external electrical unit and the power supply ground side, according to the power switching channel selection control signal. A battery management method according to any one of claims 65 to 69, further comprising the above.

71. The processor chip sends the configuration information of the dedicated integrated chip to the dedicated integrated chip and obtains the interface circuit transmission information of the dedicated integrated chip, and The processor chip acquires at least one of the following from the dedicated integrated chip: safety monitoring information, safety alarm information, and operational status information. A battery management method according to any one of claims 65 to 70, further comprising the above.

72. The processor chip sends the setting information of the high voltage management chip to the high voltage management chip via the dedicated integrated chip, and obtains detection information of the high voltage management chip via the dedicated integrated chip, and The processor chip acquires at least one of the calculation result information, safety diagnostic information, and safety alarm information of the high-voltage management chip via the dedicated integrated chip. A battery management method according to any one of claims 65 to 71, further comprising the above.

73. The processor chip sends the setting information of the analog front-end chip to the analog front-end chip via the dedicated integrated chip, and obtains the detection information of the analog front-end chip via the dedicated integrated chip, and The processor chip acquires at least one of the following from the analog front-end chip via the dedicated integrated chip: safety diagnostic information, safety alarm information, and calculation result information. A battery management method according to any one of claims 65 to 72, further comprising the above.

74. The dedicated integrated chip controls the power supply circuit of the dedicated integrated chip according to the power setting information, and supplies operating power for at least one of the internal electrical chips of the battery management system. The battery management method according to claim 69, further comprising:

75. The status parameter information of the battery pack includes the voltage information and current information of the battery pack, and the battery management method is The high-voltage management chip estimates the charge state value and / or health state value of the battery pack according to the voltage information and current information of the battery pack. The battery management method according to claim 66, further comprising:

76. The processor chip manages the battery management system according to the status parameter information of the battery cell and the status parameter information of the battery pack. The processor chip obtains the charge status value of the battery pack estimated by the high voltage management chip via the dedicated integrated chip, and verifies the status of the battery pack according to the charge status value of the battery pack estimated by the processor chip and the charge status value of the battery pack estimated by the high voltage management chip. The battery management method according to claim 75, further comprising:

77. The status parameter information of the battery pack includes the resistance between the power cord of the battery pack and the insulating ground of the vehicle body, and the battery management method is The high-voltage management chip determines the leakage current status of the battery pack according to the resistance. A battery management method according to any one of claims 65 to 76, further comprising the above.

78. The high-voltage management chip identifies whether the status parameter information of the battery pack is abnormal, and if the status parameter information of the battery pack is abnormal, safety protection is performed. The battery management method according to claim 72, further comprising:

79. The high-voltage management chip identifies whether the status parameter information of the battery pack is abnormal, and if the status parameter information of the battery pack is abnormal, safety protection is performed as follows: The high-voltage management chip identifies whether there is an overcurrent in the battery pack according to the current information of the battery pack, and if there is an overcurrent in the battery pack, it performs overcurrent protection, and The high-voltage management chip identifies whether the battery pack has an overvoltage or undervoltage according to the voltage information of the battery pack, and performs overvoltage or undervoltage protection if the battery pack has an overvoltage or undervoltage. The battery management method according to claim 78, comprising at least one of the following.

80. The high voltage management chip acquires temperature information of the high voltage management chip, and The high-voltage management chip identifies whether the high-voltage management chip is overheating according to the temperature information of the high-voltage management chip, and if the high-voltage management chip is overheating, it performs overheating protection. The battery management method according to claim 79, further comprising:

81. The analog front-end chip identifies whether the status parameter information of the battery cell is abnormal, and if the status parameter information of the battery cell is abnormal, safety protection is performed. A battery management method according to any one of claims 73 to 76, further comprising the above.

82. The analog front-end chip identifies whether the status parameter information of the battery cell is abnormal, and if the status parameter information of the battery cell is abnormal, safety protection is performed as follows: The analog front-end chip identifies whether there is an overvoltage or undervoltage in the voltage of the battery cells in the battery group, and if there is an overvoltage or undervoltage in the voltage of the battery cells, it performs overvoltage or undervoltage protection. The analog front-end chip identifies whether there is an overcurrent in the battery cell, and if there is an overcurrent in the battery cell, it performs overcurrent protection. The analog front-end chip identifies whether the stress on the battery cells in the battery group is abnormal, and if the stress is abnormal, it performs safety protection, and The analog front-end chip identifies whether the temperature of the battery cells in the battery group is excessive, and if the temperature of the battery cells is excessive, it performs over-temperature safety protection. The battery management method according to claim 81, comprising at least one of the following.

83. below, The analog front-end chip identifies whether the voltage of the battery group is abnormal, identifies whether the voltage of the internal components of the analog front-end chip is abnormal, and performs voltage safety protection if an exception occurs, and The analog front-end chip diagnoses whether the current of the battery group is abnormal, identifies whether the current of the internal components of the analog front-end chip is abnormal, and performs current protection if there is an abnormal current. The battery management method according to claim 82, further comprising at least one of the following.

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