Relay control device and method

Abstract

A relay control device according to one aspect of the present invention includes: a processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having a signal level such as a difference depending on its recovery state; a monitoring unit configured to monitor the operating state of the processor and output a decision control signal having a signal level such as a difference depending on the operating state of the processor, and a retain signal for maintaining the operating state of the relay; and a relay state determination unit configured to output either the basic control signal or the retain signal as a relay control signal for controlling the on / off state of the relay, based on the signal level of the decision control signal or the recovery signal.

Description

Technical Field

[0001] This application claims priority based on Korean Patent Application No. 10-2023-0077694 filed on June 16, 2023, and all the contents disclosed in the specification and drawings of that application are incorporated into this application.

[0002] The present invention relates to a relay control device and method, and more particularly, to a relay control device and method capable of maintaining the operating state of a relay even when a processor is reset due to a system error or the like.

Background Art

[0003] The demand for portable electronic products such as notebook PCs, video cameras, mobile phones, etc. that use electricity as a power source has increased rapidly, and as mobile robots, electric bicycles, electric carts, electric vehicles, etc. are commercialized, research on high-performance secondary batteries capable of repeated charging and discharging has been actively conducted.

[0004] Examples of commercialized secondary batteries include nickel-cadmium batteries, nickel-metal hydride batteries, nickel-zinc batteries, lithium secondary batteries, etc. Among these, lithium secondary batteries have almost no memory effect compared to nickel-based secondary batteries, so they can be freely charged and discharged, and have the advantages of a very low self-discharge rate. In addition, due to their high energy density and high operating voltage characteristics, they are being more intensively studied compared to other types of secondary batteries and are being increasingly applied to actual products.

[0005] Recently, secondary batteries are widely applied not only to small devices such as portable electronic devices but also to medium- and large-sized devices such as electric vehicles and energy storage systems (ESS).

[0006] In this case, a battery module in which multiple electrically connected secondary batteries are housed together inside a module case is primarily applied, and furthermore, when high power or large capacity is required, a battery pack in which multiple such battery modules are electrically connected may be applied.

[0007] Secondary battery cells, cell assemblies, battery modules, or battery packs (hereinafter collectively referred to as "batteries") have power efficiency and safety as important factors. Therefore, research is actively being conducted not only on BMS (Battery Management Systems) that monitor the electrical characteristics of the battery and perform feedback control such as charging and discharging based on the monitoring results, but also on battery peripheral devices such as relays that interrupt the electrical connection between the battery and loads (motors, electric heaters, in-vehicle electrical components, etc.).

[0008] The power supply system, specifically the processor located within the power supply system, controls the on / off switching of relays between the battery and the load to ensure that optimized power is supplied to the load, addressing issues such as energy efficiency, stable battery operation, and safety concerns like overcharging and over-discharging.

[0009] Electric vehicles (EVs) or hybrid electric vehicles (HEVs) equipped with such power systems are inherently exposed to external environments with strong vibrations and diverse temperature / humidity fluctuations. Furthermore, in recent electric vehicles, various devices such as air conditioning systems (air conditioners, heaters, etc.), cameras, navigation systems, braking systems, and suspension systems are composed of electrical and electronic components.

[0010] Therefore, power supply systems installed in electric vehicles and other devices, which are composed of electrical and electronic components, are constantly exposed to these physical and electromagnetic influences, which can cause errors in the power supply system's processor.

[0011] In the event of a processor malfunction, the system may be designed to restore the processor to a normal state via a reset state driven by built-in algorithms, but this process can lead to a problem where the processor is unable to properly control relays.

[0012] In particular, if the processor fails to properly control the relays while the vehicle is in motion, a fatal safety accident could occur. Therefore, it is crucial that the system is designed to remain on even if system errors occur, without being turned off. [Overview of the project] [Problems that the invention aims to solve]

[0013] The present invention was devised to solve the above-mentioned problems, and aims to provide a relay control device and method that can maintain the relay connection state even when the processor is reset due to a system error or the like, by applying an improved configuration that is relatively simple and clearly operable.

[0014] However, the technical problems that this invention aims to solve are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description of the invention. [Means for solving the problem]

[0015] A relay control device according to one aspect of the present invention may include: a processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having a signal level such as a difference depending on its recovery state; a monitoring unit configured to monitor the operating state of the processor and output a decision control signal having a signal level such as a difference, and a retain signal for maintaining the operating state of the relay, depending on the operating state of the processor; and a relay state determination unit configured to output either the basic control signal or the retain signal as a relay control signal for controlling the on / off state of the relay, based on the signal level of the decision control signal or the recovery signal.

[0016] Furthermore, the monitoring unit of the present invention may be configured to output a switching control signal to the relay state determination unit, which is a determination control signal having a different signal level from the determination control signal output when the operating state of the processor is in a reset state and when the processor is in a steady state.

[0017] Furthermore, the processor of the present invention may be configured to output a switching recovery signal, which is a recovery signal having a different signal level from the recovery signal output in states other than the recovery state, to the relay state determination unit when its operating state is in a recovery state in which it is switched from a reset state to a steady state.

[0018] Preferably, the processor of the present invention may be configured to output the recovery signal, with its signal level transitioned, to the relay state determination unit after a first reference time has elapsed following the output of the switching recovery signal.

[0019] Furthermore, the monitoring unit of the present invention may be configured to output the switching control signal only when both software monitoring using feedback information for a request and hardware monitoring using whether or not a trigger signal has been received have failed.

[0020] Furthermore, the relay state determination unit of the present invention may be configured to output the basic control signal as the relay control signal when the switching recovery signal is received.

[0021] Preferably, the relay state determination unit of the present invention may be configured to output the basic control signal as the relay control signal when the switching control signal is not received, and to output the retain signal as the relay control signal when the switching control signal is received.

[0022] Furthermore, the monitoring unit of the present invention may be configured to output a retain signal having a signal level corresponding to the basic control signal output by the processor in the steady state immediately before the reset state, when the operating state of the processor is in a reset state.

[0023] In some embodiments, the monitoring unit of the present invention may be configured to output the retain signal at a second signal level if the reset state of the processor persists during a second reference time, and to output the retain signal at a first signal level after the second reference time.

[0024] Furthermore, a battery pack according to another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0025] An automobile according to yet another aspect of the present invention may include a relay control device according to one aspect of the present invention.

[0026] According to another aspect of the present invention, a relay control method may include a basic signal receiving step of receiving a basic control signal for controlling the operation of a relay and a recovery signal having a signal level such as a difference according to the recovery state of a processor, a control signal receiving step of receiving a determination control signal having a signal level such as a difference according to the operation state of the processor and a retain signal for maintaining the operation state of the relay, and a control signal output step of outputting either one of the basic control signal and the retain signal as a relay control signal for controlling the on / off of the relay based on the signal level of the determination control signal or the recovery signal.

Advantages of the Invention

[0027] According to one aspect of the present invention, not only can the steady state and the reset state of a processor be accurately discriminated, but also the clarity and efficiency of relay control can be further optimized by organically combining the discriminated results in relay control.

[0028] Also, according to one aspect of the present invention, even if the processor is reset, the operation states of one or more relays can be effectively maintained, so that operation interruptions or safety accidents caused by the reset of the processor and relay opening or the like can be fundamentally prevented.

[0029] Furthermore, according to one aspect of the present invention, a retain signal is generated so as to correspond to a control signal output by the processor in the steady state immediately before the reset state, and the relay is configured to be controlled using the retain signal, whereby the relay state before the reset state can be more effectively maintained.

[0030] Also, according to one aspect of the present invention, when the operation state of the processor is recovered, by implementing an architecture in which the processor itself outputs a recovery signal, the operation states of one or more relays can be more accurately controlled by the processor.

[0031] In addition, the present invention provides a variety of other effects, which will be explained in each embodiment, or effects that can be easily inferred by a person skilled in the art will not be explained.

[0032] The following drawings accompanying this specification illustrate preferred embodiments of the invention and, together with the detailed description of the invention, serve to further illustrate the technical idea of ​​the invention. Therefore, the invention should not be construed as being limited solely to what is shown in the drawings. [Brief explanation of the drawing]

[0033] [Figure 1] This is a block diagram showing the detailed configuration of a relay control device according to one embodiment of the present invention. [Figure 2] Figure 1 is a block diagram showing the detailed configuration of the relay state determination unit. [Figure 3] This is a block diagram showing a detailed configuration of another embodiment of the relay state determination unit shown in Figure 1. [Figure 4] This is a flowchart illustrating the processing process according to one embodiment of the present invention. [Figure 5] This is a flowchart illustrating the processing process according to another embodiment of the present invention. [Figure 6] This is a flowchart illustrating the processing steps according to yet another embodiment of the present invention. [Figure 7] This is a flowchart illustrating the processing steps taken when the processor enters a recovery state. [Figure 8] This diagram illustrates the signaling system according to one embodiment of the present invention in both the steady state and the reset state. [Figure 9] This diagram illustrates the signal system according to another embodiment of the present invention, for both the steady state and the reset state. [Figure 10] This figure illustrates a signal system according to yet another embodiment of the present invention. [Figure 11] This diagram illustrates a signaling system according to one embodiment of the present invention, which controls multiple relays. [Figure 12] This diagram illustrates the signaling scheme according to one embodiment of the present invention, based on the processor's recovery state. [Modes for carrying out the invention]

[0034] Preferred embodiments of the present invention will now be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and in the claims should not be interpreted in a manner limited to their ordinary or dictionary meanings, but rather in a manner and concept appropriate to the technical idea of ​​the present invention, in accordance with the principle that the inventor himself may appropriately define the concept of a term in order to best describe the invention.

[0035] Therefore, the embodiments described herein and the configurations shown in the drawings represent only one of the most preferred embodiments of the present invention and do not represent the entire technical concept of the present invention. It should be understood that there are various equivalents and modifications that can be substituted for these at the time of filing this application.

[0036] In addition, when describing the present invention, if it is determined that a specific description of a related known configuration or function would unnecessarily obscure the gist of the present invention, such description will be omitted.

[0037] When a part of the specification is described as "including" a certain component, unless otherwise specified, it means that it may include other components, rather than excluding them.

[0038] Furthermore, terms such as "processor" as used in the specification refer to a unit that processes at least one function or operation, which can be embodied by hardware, software, or a combination of hardware and software.

[0039] Furthermore, when a part of the specification is described as being "connected" to another part, this includes not only cases where the parts are "directly connected," but also cases where they are "indirectly connected" through other elements in between.

[0040] Figure 1 is a block diagram showing the detailed configuration of a relay control device 100 according to one embodiment of the present invention, and Figures 2 and 3 are block diagrams showing the detailed configuration of the relay state determination unit 130 shown in Figure 1.

[0041] First, the detailed configuration of the relay control device 100 according to the present invention and the processing performed by these configurations will be explained in detail with reference to Figure 1 and related drawings, and the detailed contents of the relay state determination unit 130 will be described later.

[0042] The relay control device 100 of the present invention shown in Figure 1 may be configured to include a processor 110, a monitoring unit 120, and a relay state determination unit 130.

[0043] Specifically, the relay state determination unit 130 may be configured to include a flip-flop 131, a buffer unit 132, a gate unit 133, and a second buffer unit 134, as shown in Figures 2 and 3 according to the embodiment.

[0044] The relay control device 100 of the present invention is a device that controls the on / off state of a relay 200 by organically combining the signal system based on the monitoring results of the processor 110 and the signals that the processor 110 originally outputs for operation control of the relay 200 (hereinafter referred to as "basic control signals") to output a signal that ultimately controls the relay 200 (hereinafter referred to as "relay control signals").

[0045] The drawing shows a first relay 210, which is a high-side relay and a second relay 220, which is a low-side relay. However, this is just an example, and a different number and type of relays 200 may be used.

[0046] The processor 110 provided in the relay control device 100 is configured for executing various control logics as described in the present invention and may selectively include known ASICs (application-specific integrated circuits), chipsets, logic circuits, registers, communication modems, data processing devices, etc., in the art.

[0047] Furthermore, if the control logic is implemented as software, it can be implemented by the processor 110 executing a collection of program modules stored in memory or the like. The memory may be located inside or outside the processor 110 and may be connected to the processor 110 in a communicative manner by various known means.

[0048] Prior to a detailed description of the present invention, it is obvious that the relay control device 100 and relay state determination unit 130 according to the present invention can be realized by applying various combinations of electronic elements and components such as storage means, calculation processing means, and input / output means. Therefore, the components of the relay control device 100 shown in Figure 1 and the relay state determination unit 130 shown in Figure 2 and so on should be understood not as physically separated components, but rather as functionally or logically separated components.

[0049] In other words, each component shown in the drawings is a logical configuration for effectively explaining the technical concept of the present invention. Therefore, even if each component is integrated or separated, as long as the function performed by the logical configuration of the present invention can be realized, it should be interpreted as being within the scope of the present invention. Furthermore, if the components perform the same or similar functions, they should be interpreted as being within the scope of the present invention, regardless of whether their names are identical.

[0050] The relay control device 100 according to the present invention is configured such that, when the operating state of the processor 110 is in a steady state, the on / off state of the relay 200 is controlled by outputting a relay control signal RCS, which is a signal that ultimately controls the relay 200, to the relay 200 based on the basic control signal CS output by the processor 110.

[0051] Specifically, when the processor 110 outputs a first basic control signal CS1 for controlling the first relay 210 and a second basic control signal CS2 for controlling the second relay 220 (S400, see Figure 4), a first relay control signal RCS1 and a second relay control signal RCS2 based on these signals are output to the first relay 210 and the second relay 220, respectively (S440), thereby controlling the on / off state of the first relay 210 and the second relay 220 (S450).

[0052] Since the relay 200 is controlled in an on / off manner rather than in a stepwise or linear manner, the basic control signal CS and / or the relay control signal RCS may be configured to have a signal level higher (high level or second signal level) or lower (low level or first signal level) than a preset reference.

[0053] Depending on the embodiment, the basic control signal CS and / or the relay control signal RCS may have a digital signal system through processing such as sampling and quantization.

[0054] Furthermore, because the input signal can be inverted and output using a simple circuit configuration or gate, a high-level (low-level) signal can always be converted to a low-level (high-level) signal.

[0055] Therefore, even if a specific level of signal is mapped to a specific operation, it should be understood that it is self-evident to an average engineer that the same specific operation can be controlled using a signal at the opposite level.

[0056] It goes without saying that these interpretation criteria are also applicable to a variety of signals used in the present invention, including the signals described later, specifically the retain signal RS output from the monitoring unit 120 of the present invention to maintain the operating state of the relay 200, the decision-control signal DS having a signal level such as a difference depending on the operating state of the processor 110, and the recovery signal R output by the processor 110.

[0057] The monitoring unit 120 of the present invention is configured to monitor the operating state of the processor 110 (such as a steady state or a reset state), and it is desirable that it be designed to be independent of the processor 110 in order to fundamentally eliminate dependence on the processor 110.

[0058] The monitoring unit 120 of the present invention monitors the operating status of the processor 110 (S420) and outputs a decision control signal DS having a signal level such as a difference depending on the operating status of the processor 110 (S430, S435).

[0059] Figures 4 and 8 show an example where, when the processor 110 is in a steady state, it outputs a high-level (second signal level) decision control signal DS, and when the processor 110 is in a reset state, it outputs a low-level (first signal level) decision control signal DS.

[0060] Furthermore, the monitoring unit 120 of the present invention is configured to output a retain signal RS for maintaining the operating state of the relay 200 independently of the decision control signal DS (S410). The signal level of the retain signal RS may be configured differently depending on the embodiment or the main purpose of the control.

[0061] Specifically, in an embodiment in which the relay 200 is turned ON when the processor 110 is in a reset state, regardless of the relay 200's previous state, and this state is maintained, the retain signal RS may be configured to maintain a high level (second signal level) (see Figure 8).

[0062] Furthermore, depending on the embodiment, the retain signal RS may be configured to have a low level when the processor 110 is in a steady state and a high level when the processor 110 is in a reset state (see Figure 9).

[0063] In an embodiment aimed at improving energy efficiency and suppressing overcharging, the signal level of the retain signal RS is set to a high level (second signal level) during the second reference time Δt (see Figures 10 and 11), during which the reset state of the processor 110 is maintained in order to turn off the relay 200 after the reference time (second reference time). However, the signal level of the retain signal RS may be set to a low level (first signal level) from the second reference time t3 onward.

[0064] In an embodiment in which the state of relay 200 when processor 110 is in a steady state (immediately before the reset state) is maintained even in the reset state, that is, in an embodiment in which relay 200 is maintained in the ON state when it is ON, and in the OFF state when it is OFF, the monitoring unit 120 of the present invention may be configured to output a retain signal RS having a signal level corresponding to the basic control signal CS output by processor 110 when it is in a steady state immediately before the reset state.

[0065] On the other hand, the determination control signal DS, which is output by the monitoring unit 120 of the present invention and input to the relay state determination unit 130 of the present invention, functions as a signal that determines which signal to output from the relay state determination unit 130.

[0066] The relay state determination unit 130 of the present invention receives a basic control signal CS from the processor 110 and the determination control signal DS and retain signal RS from the monitoring unit 120. Depending on the embodiment, the relay state determination unit 130 of the present invention may be configured to receive a recovery signal R from the processor 110. Details of this will be described later.

[0067] In this manner, when three types of signals (basic control signal CS, retain signal RS, and decision control signal DS) are input to the relay state determination unit 130 of the present invention, the relay state determination unit 130 outputs either the basic control signal CS or the retain signal RS as the relay control signal RCS, depending on whether the signal level of the decision control signal DS is high or low.

[0068] As mentioned above, the decision control signal DS has signal levels such as differences depending on the operating state of the processor 110 (steady state or reset state), and therefore the decision control signal DS indicates the current operating state of the processor 110.

[0069] In other words, when the operating state of the processor 110 is in a reset state, the monitoring unit 120 of the present invention outputs a decision control signal DS having a different signal level from the decision control signal DS that is output when the processor 110 is in a steady state.

[0070] In the following explanation, to clarify the relative distinction, the decision control signal DS output when the operating state of the processor 110 is in the reset state will be referred to as the "switching control signal".

[0071] If the determination control signal DS input from the monitoring unit 120 is a switching control signal DS, that is, a signal indicating that the operating state of the processor 110 is in a reset state (for example, a low-level (first signal level) signal) (S435), the relay state determination unit 130 of the present invention outputs the retain signal RS from the basic control signal CS as the relay control signal RCS (S445).

[0072] In contrast, the relay state determination unit 130 of the present invention outputs the basic control signal CS as the relay control signal RCS (S440) when it does not receive a switching control signal DS from the monitoring unit 120, that is, when the determination control signal DS input from the monitoring unit 120 is a signal indicating that the operating state of the processor 110 is in a steady state (for example, a high-level (second signal level) signal) (S430).

[0073] When the relay control signal RCS, which is generated by accurately reflecting the operating state of the processor 110, is output to the relay 200, the relay 200 of the present invention is controlled by the input relay control signal RCS (S450).

[0074] The processing of the present invention described above can be applied cyclically unless a pre-set termination condition is met, such as forced termination, a complete system shutdown, or the occurrence of an emergency event (S460).

[0075] When relay 200 is composed of a first relay 210 and a second relay 220, the relay state determination unit 130 of the present invention outputs a first relay control signal RCS1 to the first relay 210, which is determined to be either a first basic control signal CS1 or a retain signal RS based on the signal level of the determination control signal DS, and outputs a second relay control signal RCS2 to the second relay 220, which is determined to be either a second basic control signal CS2 or a retain signal RS based on the signal level of the determination control signal DS in a corresponding manner.

[0076] The embodiments of the present invention described above will be further explained below with reference to Figure 8. Figure 8 is a diagram illustrating the signal system according to one embodiment of the present invention in both the steady state and the reset state.

[0077] In Figure 8, t1 indicates the point in time when the reset state of the processor 110 (MCU, etc.) begins due to a system error or the like, and t2 indicates the point in time when the processor 110 is restored to a steady state after the reset state.

[0078] As shown in Figure 8, when the processor 110 is in an initial steady state (Normal State) (S420), the decision control signal DS output from the monitoring unit 120 of the present invention (S430) is at a high level (second signal level). Therefore, the relay state determination unit 130 of the present invention outputs the basic control signal CS as the relay control signal RCS from the basic control signal CS input from the processor 110 (S400) and the retain signal RS input from the monitoring unit 120 (S410) based on this decision control signal DS (S440).

[0079] Therefore, the relay control signal RCS that the processor 110 ultimately uses to control the relay 200 until it reaches the initial steady state t1 is based on the basic control signal CS.

[0080] If the processor 110 enters a reset state at time t1 (S420), the monitoring unit 120 outputs a decision control signal DS, i.e., a switching control signal DS, which has a signal level such as the difference from the decision control signal DS when in a steady state (for example, a low level (first signal level)) (S435).

[0081] When a switching control signal DS, which is a decision control signal DS having a level such as a difference from the decision control signal DS output when the processor 110 is in a steady state, is input to the relay state determination unit 130 (S435), the relay state determination unit 130 of the present invention outputs the retain signal RS input from the monitoring unit 120 as a relay control signal RCS (S445).

[0082] Therefore, the relay control signal RCS output from the relay state determination unit 130 in the t1 and t2 intervals is based on the retain signal RS.

[0083] When the processor 110 is restored to a steady state at time t2, the monitoring unit 120 of the present invention outputs a decision control signal DS (for example, a high level) indicating this, and when this signal is received, the relay state determination unit 130 of the present invention outputs the basic control signal CS as the relay control signal RCS, out of the basic control signal CS and the retain signal RS.

[0084] Therefore, after time point t2, when the steady state is restored, the relay control signal RCS of the present invention becomes even more based on the basic control signal CS.

[0085] The embodiment shown in Figure 8 is an embodiment in which the monitoring unit 120 of the present invention is configured to output a retain signal RS having a high level, regardless of the operating state of the processor 110.

[0086] As mentioned above, the relay control signal RCS is selectively determined to be either the basic control signal CS or the retain signal RS based on the decision control signal DS. Therefore, even if the retain signal RS is set to remain at a high level regardless of the operating state of the processor 110, the retain signal RS is reflected as the relay control signal RCS only when the processor 110 is switched to a reset state, making it possible to keep the relay 200 in the ON state.

[0087] According to this embodiment of the present invention, it is sufficient to maintain a constant signal level without linking the signal level of the retain signal RS to the operating state of the processor 110, which has the advantage of making circuit design easy to implement.

[0088] Figure 5 is a flowchart illustrating a processing process according to another embodiment of the present invention, and Figure 9 is a diagram illustrating an example of a signal system according to such an embodiment.

[0089] The embodiment of the present invention shown in Figure 5 differs from the embodiments described above with reference to Figure 4, etc., in that the monitoring unit 120 is configured to output a high-level retain signal RS only when it is monitored that the processor 110 is in a reset state.

[0090] When the processor 110 is in a steady state (S510), as described above, the monitoring unit 120 of the present invention outputs a high-level decision control signal DS (S530), and the relay state determination unit 130 of the present invention outputs the basic control signal CS input from the processor 110 (S500) as a relay control signal RCS (S540). The relay 200 is controlled to be on or off by the relay control signal RCS output in this manner (S550).

[0091] On the other hand, if the processor 110 is in a reset state, in S510, the monitoring unit 120 of the present invention outputs a high-level (second signal level) retain signal RS (S520), and independently of this, the monitoring unit 120 of the present invention outputs a low-level (first signal level) decision control signal DS (S520).

[0092] When a low-level determination control signal DS is input to the relay state determination unit 130 in this manner, the relay state determination unit 130 outputs the retain signal RS from the basic control signal CS and retain signal RS as a relay control signal RCS (S545), and the relay 200 is controlled by the relay control signal RCS (S550).

[0093] In this embodiment as well, as shown in the lower part of Figure 9, in the initial steady state (~t1), the relay control signal RCS is output based on the basic control signal CS, and in the t1~t2 interval, the relay control signal RCS is output based on the retain signal RS.

[0094] When the processor 110 is restored to a steady state at time t2, the monitoring unit 120 of the present invention outputs a decision control signal DS (for example, a high level) indicating this, and when this signal is received, the relay state determination unit 130 of the present invention outputs the basic control signal CS as the relay control signal RCS, out of the basic control signal CS and the retain signal RS.

[0095] Therefore, after time t2, when the system is restored to a steady state, the relay control signal RCS of the present invention becomes even more based on the basic control signal CS. As shown in Figure 9, in this embodiment, when the processor 110 is restored to a steady state (t2), the retain signal RS may be switched to a low level.

[0096] On the other hand, as described above, the retain signal RS of the present invention may be set to have a signal level corresponding to the basic control signal CS output by the processor 110 in the steady state immediately before the reset state, when the operating state of the processor 110 is in a reset state.

[0097] With this implementation configuration, if relay 200 is open (OFF) immediately before the reset state (steady state), it can be controlled to remain open even in the reset state. If relay 200 is closed (ON) immediately before the reset state (steady state), it can be controlled to maintain the closed state even in the reset state. Since the state of relay 200 can be maintained identical to the steady state immediately before the reset state, it has the advantage of maintaining consistency in operation.

[0098] Figure 6 is a flowchart illustrating the processing process according to yet another embodiment of the present invention. Figures 10 and 11 further illustrate the signal system according to the embodiment shown in Figure 6.

[0099] The processing shown in Figure 6 assumes that the processor 110 is in a reset state and the monitoring unit 120 outputs a switching control signal DS, i.e., a decision control signal DS indicating that the processor 110 is in a reset state.

[0100] When the monitoring unit 120 generates a high-level retain signal RS (S600), the retain signal RS is output to the relay state determination unit 130 (S610). The relay state determination unit 130 outputs the relay control signal RCS, which has been determined as the retain signal RS based on the switching control signal DS (S620), to the relay 200 (S630).

[0101] Through this processing, the relay 200 of the present invention is controlled to be in the ON state (S640).

[0102] If the processor 110 is not restored to a steady state after time t1, the decision control signal DS will continue to maintain a low level (first signal level), and the relay control signal RCS will not be switched. In other words, after time t1, the relay control signal RCS will be output based on the retain signal RS which has a high level, and as a result the relay 200 will remain in the ON state.

[0103] As shown in Figure 10, the monitoring unit 120 of the present invention, with reference to the time t1 when the processor 110 enters a reset state, outputs a retain signal RS at a second signal level (high level) during the second reference time Δt if the reset state persists during the second reference time Δt (S650, S600), but after the second reference time (from t3 onwards), the signal level of the retain signal RS becomes the first signal level (low level) (S660).

[0104] After the second reference time Δt has elapsed with respect to t1, the retain signal RS, which has been switched to a low level, is output to the relay state determination unit 130 (S670). The relay state determination unit 130 then outputs this retain signal RS as a relay control signal RCS (S680, S685).

[0105] In this way, the relay control signal RCS based on a low level is output to the relay 200, which controls the relay 200 to be turned off (S690).

[0106] According to this embodiment of the present invention, if the processor 110 does not return to a steady state after a reference time has elapsed, the relay 200 can be turned off, preventing unnecessary energy waste. Furthermore, the fact that the processor 110 does not return to a steady state for a medium to long period of time suggests the possibility that a fatal error or defect has actually occurred, and therefore, the embodiment of the present invention can prevent safety accidents and the like.

[0107] Figure 11 shows an example of a signal system that is generated or output when the relays 200 to be controlled are the first relay 210 and the second relay 220, and is substantially the same as the signal system shown in Figure 10.

[0108] The portion D shown in Figure 11 represents the signal delay that occurs during the process of the processor 110 being converted from a steady state to a reset state. This portion is omitted in Figures 8 to 10.

[0109] The first output signal Q1 and the second output signal Q2 shown in Figure 11 are signal values ​​that are output in conjunction with the signal switching of the aforementioned decision control signal DS. When the relay state determination unit 130 of the present invention is configured to include a flip-flop 131 as shown in Figures 2 and 3, these are signals output from the flip-flop 131. This will be explained later.

[0110] On the other hand, the monitoring unit 120 of the present invention may be configured to output the switching control signal using one or more of the results of software monitoring, which determines the current state of the processor 110 using feedback information for the request, and hardware monitoring, which uses whether or not a trigger signal has been received.

[0111] As described above, the monitoring unit 120 of the present invention is configured to output a switching control signal DS, which is a decision control signal DS, when the operating state of the processor 110 is not a steady state, that is, when it is in a reset state.

[0112] As mentioned above, this switching control signal DS is an important parameter signal that determines the signal that will be determined as the relay control signal RCS by the relay state determination unit 130.

[0113] Therefore, in order to more accurately implement monitoring of the operating state of the processor 110, it is desirable that the monitoring unit 120 of the present invention be configured to output the switching control signal DS only when both the software monitoring S / W, which determines the current operating state of the processor 110, and the hardware monitoring HW, which uses whether or not a trigger signal has been received, are failures.

[0114] Software monitoring can involve methods such as transmitting requests (e.g., questions) over a set period of time via a WDT (Window Watchdog) and verifying whether corresponding feedback (e.g., answers) is received. Hardware monitoring can involve methods such as assigning one or more lines or channels and verifying whether they successfully trigger a specific signal.

[0115] In the following, an embodiment of the present invention in which the relay 200 is controlled by a recovery signal R output by the processor 110 will be described with reference to Figures 7 and 12, etc.

[0116] When the processor 110 is in a reset state, the operating state of the relay 200 is maintained by a unique processing method of the present invention that uses a signal system such as the retain signal RS and the decision control signal DS, as described above (S700).

[0117] The processor 110 of the present invention may be configured to output a recovery signal R independently of outputting a basic control signal CS for controlling the operation of the relay 200.

[0118] The recovery signal R refers to a signal that indicates the processor 110 is in a recovery state, and means a signal or signal system that indicates the state of the processor 110 has moved out of a reset state (such as a reboot state) and entered a steady state (hereinafter referred to as the "recovery state").

[0119] As shown in Figure 12, the recovery signal R may be configured to have a second signal level (high level) when the processor 110 is in a state other than the recovery state, and to have a first signal level (low level) when the processor 110 is in the recovery state.

[0120] Hereinafter, the recovery signal R output when the processor 110 is in a recovery state will be referred to as the "switching recovery signal," and the recovery signal R output when the processor 110 is in a state other than the recovery state will be referred to as the "non-switching recovery signal."

[0121] The embodiment shown in Figure 12 is one in which the first signal level (low level) is set in the case of a switching recovery signal R, and the second signal level (high level) is set in the case of a non-switching recovery signal R.

[0122] The processor 110 of the present invention can output a recovery signal R (switching recovery signal R) to the relay state determination unit 130 immediately when its operating state changes from a reset state to a recovery state.

[0123] In this case, the decision control signal DS output by the monitoring unit 120 may be set differently depending on the embodiment. For example, when the processor 110 enters a recovery state, that is, when a switching recovery signal R is output, the signal level of the decision control signal DS output by the monitoring unit 120 may be configured to transition from a low level to a high level.

[0124] In another example, even if the processor 110 outputs a switching recovery signal R (t2), the signal level of the decision control signal DS may not transition immediately. After a first reference time Δt' has elapsed, if the signal level of the recovery signal R transitions further (from the first signal level to the second signal level) (t2'=t2+Δt'), the signal level of the decision control signal DS may be configured to transition accordingly. Figure 12 shows the signal system for the latter embodiment.

[0125] In other words, the processor 110 of the present invention may be configured to output a recovery signal with a transitioned signal level to the relay state determination unit 130 after a first reference time Δt' has elapsed following the output of a switching recovery signal R, so that switching or transitions of other related signal systems can occur.

[0126] Based on the latter embodiment, when a low-level (first signal level) recovery signal R (switching recovery signal) is input to the relay state determination unit 130 of the present invention, and then a high-level (second signal level) recovery signal R is input (S710), the relay state determination unit 130 of the present invention is configured to output the basic control signal CS as the relay control signal RCS among the basic control signal CS and the retain signal RS (S740).

[0127] When the relay control signal RCS is output in this manner, the relay 200 of the present invention is controlled to be on or off by the relay control signal RCS (S750).

[0128] Subsequently, if the processor 110 does not enter a reset state (S770), the on / off state of the relay 200 is controlled in a cyclical manner using steps 740 and 750 of Figure 7. When the processor 110 enters a reset state again (S770), control processing based on the reset state of the processor 110 is performed through the configuration and method described above (S700).

[0129] On the other hand, if a low-level (first signal level) recovery signal R, i.e., a switching recovery signal R, is not input, or if a recovery signal R whose signal level has transitioned after a switching recovery signal R is input, i.e., a non-switching recovery signal R, is not input (S710), it is considered that the restoration to a complete steady state has not yet been completed, and the relay state determination unit 130 of the present invention outputs the retain signal RS from the basic control signal CS and retain signal RS as a relay control signal RCS (S720), and the relay 200 can be configured to be controlled by the relay control signal RCS (S730).

[0130] Therefore, as shown in the lower part of Figure 12, the relay control signal RCS that ultimately controls the relay 200 is generated based on the basic control signal CS in the initial steady state (~t1), based on the retain signal RS in the reset and recovery states (t1~t2'), and finally generated based on the basic control signal CS from the point t2' when it is restored to the steady state.

[0131] When the processor 110 is configured to output a recovery signal R, the relay state determination unit 130 of the present invention may be configured to output either the basic control signal CS or the retain signal RS as a relay control signal RCS that controls the on / off state of the relay 200, based on the signal level of the determination control signal DS or the recovery signal R.

[0132] In one embodiment of the present invention, the relay control device 100 can control the operating state of the relay 200 based on the decision control signal DS output from the monitoring unit 120 when the processor 110 is reset once or more times.

[0133] Subsequently, when the operating state of the processor 110 is switched to the recovery state, the signal levels of the basic control signal CS, the first output signal Q1, the second output signal Q2, etc. are restored to their original signal levels based on the recovery signal R output by the processor 110, thereby enabling the operating state of the relay 200 to be controlled by the processor 110.

[0134] In the following, a specific embodiment of the relay state determination unit 130, which is one component of the relay control device 100 according to the present invention, will be described with reference to Figures 2 and 3.

[0135] As shown in Figures 2 and 3, the relay state determination unit 130 of the present invention may be configured to include a flip-flop 131, a buffer unit 132, a gate unit 133, and a second buffer unit 134.

[0136] The flip-flop 131 is a logic circuit capable of holding one bit of information, and depending on the embodiment, the flip-flop 131 shown in Figure 3 may be implemented as a D flip-flop, RS flip-flop, JK flip-flop, or T flip-flop.

[0137] The flip-flop 131 may have a clock terminal C to which the output signal of the second buffer unit 134, into which the decision control signal DS and the recovery signal R are signal-processed, and a data terminal D to which the second basic control signal CS2 is input, and may include a first output terminal Q and a second output terminal Q'.

[0138] The first output signal Q1 output from the first output terminal Q is determined by the signal levels of the second basic control signal CS2 and the decision control signal DS or recovery signal R, which are signals input to the flip-flop 131, and the second output signal Q2 output from the second output terminal Q' may be designed to have the opposite signal level to the first output signal Q1 (first signal level vs second signal level).

[0139] As a specific example, if the decision control signal DS is converted from a high level to a low level through the internal design of the flip-flop 131, or if the recovery signal R is converted from a low level to a high level, the first output signal Q1 may be configured to be converted from a low level to a high level in conjunction with this. In this case, the second output signal Q2 is designed to have the opposite level of the first output signal Q1, so the second output signal Q2 becomes a low-level signal.

[0140] The buffer unit 132 receives the first basic control signal CS1 and the second basic control signal CS2 from the processor 110, the first output signal Q1 and the second output signal Q2 from the flip-flop 131, and the retain signal RS from the monitoring unit 120.

[0141] The buffer unit 132 is configured to output a first relay control signal RCS1 and a second relay control signal RCS2 to the first relay 210 and the second relay 220, respectively, which are signals that ultimately control the on / off state of the first relay 210 and the second relay 220 through a circuit architecture that embodies the technical concept of the present invention described above.

[0142] More specifically, the buffer unit 132 may include a plurality of buffers. One of these, the first buffer, may be configured to receive the retain signal RS and the first output signal Q1, and to determine whether or not to output the retain signal RS based on the signal level of the first output signal Q1.

[0143] For example, the system can be designed so that when the signal level of the first output signal Q1 is at the second signal level (high level), a retain signal RS is output from the first buffer, and when the signal level of the first output signal Q1 is at the first signal level (low level), the retain signal RS is not output.

[0144] The second buffer among the multiple buffers may be designed to receive the first basic control signal CS1 and the second output signal Q2, and the presence or absence of the output of the first basic control signal CS1 may be determined by the signal level of the second output signal Q2.

[0145] For example, the system can be designed so that when the signal level of the second output signal Q2 is at the second signal level (high level), the first basic control signal CS1 is output from the second buffer, and when the signal level of the second output signal Q2 is at the first signal level (low level), the first basic control signal CS1 is not output.

[0146] Furthermore, the output channels (lines) of the first buffer and the output channels (lines) of the second buffer can be configured to integrate with each other. In this case, since the first buffer and the second buffer each receive the first output signal Q1 and the second output signal Q2, which have opposite signal levels as described above, it is possible to prevent the first basic control signal CS1 from being output from the second buffer when the retain signal RS is output from the first buffer.

[0147] As mentioned above, the fact that the retain signal RS is output from the first buffer means that the signal level of the first output signal Q1 input to the first buffer is the second signal level (high level), and the second output signal Q2 input to the second buffer is a low-level signal, which is the opposite level of the first output signal Q1. In this way, the second buffer is configured so that the first basic control signal CS1 is not output from the second buffer when the low-level second output signal Q2 is input to it.

[0148] Therefore, depending on the signal levels of the first output signal Q1 and the second output signal Q2, either the first basic control signal CS1 or the retain signal RS can be output from the buffer unit 132 as the first relay control signal RCS1. As mentioned above, the first output signal Q1 and the second output signal Q2 are determined based on the presence or absence of signal transitions of the decision control signal DS or recovery signal R output by the monitoring unit 120, and the decision control signal DS and recovery signal R are determined based on the operating state of the processor 110.

[0149] Therefore, the relay control device 100 according to the present invention ultimately controls the on / off state of the first relay 210 through processing that includes "monitoring the operating state of the processor 110, outputting a decision control signal DS based on the monitoring results, outputting a first output signal Q1 and / or a second output signal Q2, determining one of the first basic control signal CS1 and the retain signal RS, and outputting the determined signal as the first relay control signal RCS1."

[0150] Furthermore, in an embodiment using a recovery signal R related to the recovery state of the processor 110, the on / off state of the first relay 210 is ultimately controlled through processing that includes the recovery state of the processor 110, the output and signal level transition of the switching recovery signal R, the output of the first output signal Q1 and / or the second output signal Q2, the determination of one of the first basic control signal CS1 and the retain signal RS, and the output of the determined signal as the first relay control signal RCS1.

[0151] Thus, the relay control device 100 according to the present invention can output a first relay control signal RCS1 for controlling the first relay 210 in a binary signal system that accurately reflects the operating state of the processor 110 and differs depending on the operating state.

[0152] The second relay control signal RCS2, which ultimately controls the second relay 220, can also be output in a manner in which either the second basic control signal CS2 or the retain signal RS is selected by multiple buffers (e.g., a third buffer, a fourth buffer, etc.) that embody the aforementioned technical configuration. The details of the third and fourth buffers correspond to those of the first and second buffers described above, so a detailed explanation is omitted.

[0153] The second buffer unit 134 of the present invention is configured to process a recovery signal R output from the processor 110 and a decision control signal DS output from the monitoring unit 120, and can be implemented by a combination of one or more lower-level buffers and / or inverters (inverters, NOT gates) that implement signal delay, signal pass-through, signal suppression, signal inversion, etc.

[0154] As described above, the second buffer unit 134 is configured to output a decision control signal DS or a recovery signal R to the clock terminal C of the flip-flop 131 when such a signal is input, and can perform functions such as outputting a specific signal based on the signal levels of the decision control signal DS and the recovery signal R (switching recovery signal) shown in Figure 12.

[0155] With this configuration of the invention, when the operating state of the processor 110 is switched to the recovery state, the signal levels of the basic control signal CS, the first output signal Q1, the second output signal Q2, etc. are restored to their original signal levels based on the recovery signal R output by the processor 110, thereby enabling the operating state of the relay 200 to be controlled by the processor 110.

[0156] Depending on the embodiment, the relay state determination unit 130 of the present invention may further include a gate unit 133 interposed between at least one of the first relay 210 and the second relay 220 and the buffer unit 132, as shown in Figure 3. Figure 3 is an example of this, showing an example in which the gate unit 133 is provided between the buffer unit 132 and the second relay 220.

[0157] The gate unit 133 may be designed to receive a third relay control signal RCS3 from the buffer unit 132, receive a retain signal RS from the monitoring unit 120, and output a second relay control signal RCS2 to the second relay 300 based on the signal levels of the third relay control signal RCS3 and the retain signal RS.

[0158] As described in the embodiment above, when the operating state of the processor 110 is in a reset state, a retain signal RS can be output from the fourth buffer of the buffer unit 132. Therefore, the third relay control signal RCS3 can be the retain signal RS output from the fourth buffer.

[0159] Therefore, since the gate unit 133 receives the retain signal RS output from the buffer unit 132 and the monitoring unit 120 respectively, when the gate unit 133 is implemented as an AND gate, it is configured to output a high-level signal only when both received signals are at a high level, thereby further improving the accuracy of the signal system.

[0160] The relay control device 100 according to the present invention can be applied to a Battery Management System (BMS). That is, the BMS according to the present invention may include the relay control device 100 described above. In such a configuration, at least some of the components of the relay control device 100 can be realized by complementing or adding functions of components included in a conventional BMS. For example, the processor 110, monitoring unit 120, and relay state determination unit 130 of the relay control device 100 can be realized as components of the BMS.

[0161] Furthermore, the relay control device 100 according to the present invention may be provided in a battery pack. That is, the battery pack according to the present invention may include the relay control device 100 described above and one or more battery cells. The battery pack may further include electrical components (relays, fuses, etc.) and a case, etc.

[0162] Furthermore, the relay control device 100 according to the present invention may be installed in an automobile. Therefore, the relay control device 100 can control the relays so that even if the processor 110 is reset due to a system error while the automobile is running, the relays connecting the battery and the automobile remain closed without being opened.

[0163] Although the present invention has been described above with reference to limited embodiments and drawings, the present invention is not limited thereto, and it goes without saying that a wide range of modifications and variations are possible within the equivalent scope of the technical concept of the present invention and the following claims by persons with ordinary skill in the art to which the present invention pertains.

[0164] The description of the present invention and the accompanying drawings illustrating the embodiments thereof may be presented in a somewhat exaggerated form to emphasize the technical content of the present invention. However, considering the above-mentioned content and the matters shown in the drawings, it is obvious that various modifications are possible at the level of an ordinary person skilled in the art.

[0165] Furthermore, in describing the present invention, it is self-evident that expressions such as first, second, upper, lower, top and bottom, etc., are merely instrumental conceptual terms used to relatively distinguish each component (element) from one another, and are not terms used to indicate specific procedures, priorities, etc., nor are they terms used to physically distinguish each component (element) by an absolute standard. [Explanation of Symbols]

[0166] 100 Relay Control Device 110 processors 120 Monitoring Department 130 Relay status determination unit 131 Flip-flops 132 Buffer section 133 Gate section 134 Second Buffer Section 200 relays 210 1st Relay 220 2nd Relay CS Basic Control Signal CS1 First Basic Control Signal CS2 Second Basic Control Signal DS decision control signal RS Retained Signal RCS relay control signal RCS1 1st Relay Control Signal RCS2 2nd Relay Control Signal R recovery signal Q1 First output signal Q2 Second output signal

Claims

1. A processor configured to output a basic control signal for controlling the operation of a relay and a recovery signal having a signal level such as a difference depending on its own recovery state, A monitoring unit is configured to monitor the operating state of the processor and output a determination control signal having a signal level such as a difference based on the operating state of the processor, and a retain signal for maintaining the operating state of the relay. A relay control device comprising: a relay state determination unit configured to output either the basic control signal or the retain signal as a relay control signal for controlling the on / off state of the relay, based on the signal level of the determination control signal or the recovery signal.

2. The monitoring unit, The relay control device according to claim 1, wherein when the operating state of the processor is in a reset state, a switching control signal is output to the relay state determination unit, which is a determination control signal having a different signal level from the determination control signal output when the processor is in a steady state.

3. The aforementioned processor, The relay control device according to claim 1, wherein, when its operating state is in a recovery state in which it can be switched from a reset state to a steady state, it is configured to output a switching recovery signal, which is the recovery signal having a different signal level from the recovery signal output in states other than the recovery state, to the relay state determination unit.

4. The aforementioned processor, The relay control device according to claim 3, wherein after the switching recovery signal is output and a first reference time has elapsed, the recovery signal with the transitioned signal level is output to the relay state determination unit.

5. The monitoring unit, The relay control device according to claim 2, configured to output the switching control signal only when both software monitoring using feedback information for a request and hardware monitoring using whether or not a trigger signal has been received have failed.

6. The relay state determination unit, The relay control device according to claim 3, wherein when the switching recovery signal is received, the basic control signal is output as the relay control signal.

7. The relay state determination unit, The relay control device according to claim 2, configured to output the basic control signal as the relay control signal when the switching control signal is not received, and to output the retain signal as the relay control signal when the switching control signal is received.

8. The monitoring unit, The relay control device according to claim 1, wherein, when the operating state of the processor is in a reset state, it is configured to output the retain signal having a signal level corresponding to the basic control signal output by the processor in the steady state immediately before the reset state.

9. The monitoring unit, The relay control device according to claim 1, configured to output the retain signal at a second signal level if the reset state of the processor persists during a second reference time, and to output the retain signal at a first signal level after the second reference time.

10. A battery pack comprising a relay control device according to any one of claims 1 to 9.

11. An automobile comprising a relay control device according to any one of claims 1 to 9.

12. A basic signal reception stage that receives a basic control signal for controlling the operation of a relay and a recovery signal having a signal level such as a difference depending on the recovery state of the processor, A control signal reception stage that receives a determination control signal having a signal level such as a difference depending on the operating state of the processor, and a retain signal for maintaining the operating state of the relay, A relay control method comprising: a control signal output step of outputting either the basic control signal or the retain signal as a relay control signal for controlling the on / off state of the relay, based on the signal level of the decision control signal or the recovery signal.

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