Scalable architecture for controlling quantum devices in low-temperature environments

Abstract

This disclosure relates to a quantum processor system. The system includes a qubit structure, control lines, and a cavity filter. The control lines are configured to transmit control signals to and from the qubit structure. The cavity filter is configured to filter the control signals transmitted by the control lines. The cavity filter includes a waveguide comprising a cavity and a material placed within the cavity. The material has a refractive index greater than 1.0. The material may be a dielectric material (e.g., a dielectric), a metallic material (e.g., a conductive or magnetic material), or a combination thereof. The cavity filter includes a resonator structure enclosed within the material and has a floating ground connection. The cavity filter includes a central conductor that transmits low-frequency signals, and the waveguide transmits high-frequency signals.

Description

Technical Field

[0001] Priority Claim This application claims the benefit of priority of U.S. Application No. 17 / 950,807, filed on September 22, 2022, entitled "SCALABLE ARCHITECTURES FOR CONTROL OF QUANTUM DEVICES WITHIN COLD ENVIRONMENTS", which is incorporated herein by reference.

[0002] The present disclosure generally relates to quantum computing and information processing systems, and more particularly to scalable architectures for quantum devices within cold environments.

Background Art

[0003] Quantum computing is a computational method that utilizes quantum effects such as superposition and entanglement of ground states in order to perform certain calculations more efficiently than classical digital computers. In contrast to digital computers that store and manipulate information in the form of bits, for example, "1" or "0", quantum computing systems can manipulate information using quantum bits ("qubits"). A qubit may refer to a quantum device that enables superposition of data in multiple states, for example, both "0" and "1" states, and / or the superposition of data in multiple states itself. According to conventional terminology, the superposition of the "0" state and the "1" state in a quantum system can be expressed, for example,

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[0004] Aspects and advantages of the embodiments of this disclosure are partially shown in the following description, or can be learned from the description, or can be learned through the implementation of the embodiments.

[0005] One exemplary aspect of the present disclosure relates to a quantum computing system (QCS). The QCS may include a first cryogenic chamber, a first quantum device, a second quantum device, and a first control logic device. Each of the first quantum device, the second quantum device, and the first control logic device may be arranged together with the first cryogenic chamber. In response to receiving one or more programming signals, the first control logic device may be configured to provide a first control signal to the first quantum device and a second control signal to the second quantum device. In some embodiments, the QCS may also include a first control line. The first control line may begin outside the first cryogenic chamber and terminate at the first control logic device. The first control line is configured to transmit one or more programming signals from outside the first cryogenic chamber.

[0006] In various embodiments, the QCS may further include a third quantum device, a fourth quantum device, and a second control logic device. Each of the second quantum device, the third quantum device, and the second control logic device may be arranged together with the first cryogenic chamber. In response to receiving one or more additional programming signals, the second control logic device may be configured to provide a third control signal to the third quantum device and a fourth control signal to the fourth quantum device. In some embodiments, the QCS may also include a second control line. The second control line may start outside the first cryogenic chamber and terminate at the second control logic device. The second control line is configured to transmit one or more additional programming signals from outside the first cryogenic chamber.

[0007] Other aspects of this disclosure cover a variety of systems, methods, apparatus, non-temporary computer-readable media, computer-readable instructions, and computing devices.

[0008] These and other features, aspects and advantages of the various embodiments of this disclosure will be better understood by referring to the modes for carrying out the invention and the appended claims below. The appended drawings incorporated herein and forming part of this specification illustrate exemplary embodiments of this disclosure and, together with the modes for carrying out the invention, describe the relevant basic methods.

[0009] A detailed description of embodiments for those skilled in the art is given herein with reference to the following accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] An exemplary quantum computing system is shown according to an exemplary embodiment of the present disclosure. [Figure 2] This shows exemplary environments in which various embodiments may be implemented. [Figure 3A] This shows an exemplary DC control logic device consistent with various embodiments. [Figure 3B] This shows an exemplary digital-analog device array consistent with various embodiments. [Modes for carrying out the invention]

[0011] Embodiments relate to a scalable architecture for controlling a device located in an isolated environment (e.g., a first environment isolated from a second environment by a chamber or another sealed container located within the second environment) via a control signal. While the device may be located in an isolated environment, the generation of such control signals may be controlled and / or operated from outside the isolated environment. Such devices include, but are not limited to, quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.). The isolated environment may be, but is not limited to, an adiabatic environment. For example, the isolated environment may be a cryogenic environment. The chamber and / or container that isolates (and insulates) the cryogenic environment may be a cryogenic chamber and / or cryogenic container. Thus, the device may be a quantum device located within a cryogenic system. The generation of control signals may be controlled from outside the cryogenic system (e.g., a room temperature (RT) environment). The cryogenic environment may be an ultra-low temperature (e.g., on the order of millikelvin (mK)). Therefore, the embodiments may be used in quantum computing and information processing systems, in which the quantum device is located in an extremely cold environment (e.g., a cryogenic environment). In the embodiments, a significant reduction in the number of signal transmission lines (e.g., control lines) required to wire from the RT environment to the cryogenic cryogenic environment is achieved.

[0012] The reduction in the number of control lines required is achieved by placing one or more multiplexed logic devices in the cryogenic environment. Such multiplexed logic devices can receive input signals originating from the RT environment. Based on the input signals, a single multiplexed logic device can provide control signals to multiple quantum devices in the cryogenic environment via the logic device's output lines. The multiplexed logic device may receive its input signals via K input lines, where K is a positive integer. Based on the signals encoded from the K input signals, the multiplexed logic device may provide control signals to L quantum devices via its output lines, where L is a positive integer. To control the L quantum devices, K control lines are wired from the RT environment to the cryogenic environment. The K control lines transmit input signals from the RT environment to the multiplexed logic device.

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[0013] In a conventional quantum computing system (QCS), one or more control lines may be dedicated to each quantum device within a cryogenic chamber. As used herein, a dedicated control line may be a path that enables transmission of a control signal from outside the cryogenic environment to a single (and corresponding) quantum device within the cryogenic environment. Each of the dedicated control lines has conventionally been routed from outside the cryogenic environment, through one or more cryogenic chambers, and terminated at the corresponding quantum device within the cryogenic environment. Conventionally, a control signal may be generated outside the cryogenic chamber and transmitted through the chamber to the quantum device via one or more control lines dedicated to the device. Thus, in a conventional QCS, there may be a one-to-one correspondence between the signal transmission path outside the cryogenic environment and the signal transmission path within the cryogenic environment.

[0014] As the number of quantum devices within the cryogenic chamber increases (e.g., as the number of qubits and quantum gates within the QCS increases), the difficulty of passing dedicated control lines from outside the cryogenic environment to inside the environment for each quantum device increases significantly. This increase in difficulty is at least a result of the physical space and heat transfer constraints required to pass power from outside the chamber to inside the chamber. The increase in difficulty is further exacerbated at cryogenic temperatures (which a quantum device may require) because a single conventional dedicated control line may be required to pass through a series of nested cryogenic chambers and terminate at the “innermost” cryogenic chamber. Instead of having one or more dedicated control lines passing through one or more cryogenic chambers for each quantum device, as a conventional QCS may do, embodiments use one or more multiplexed logic devices disposed within the innermost cryogenic chamber as described above. The multiplexed logic device may be

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[0015] More specifically, a quantum processor device in an ultra-low temperature environment may include a set of quantum devices. The set of quantum devices may include a set of qubits, a set of qubit couplers, and / or a set of quantum logic gates (e.g., a set of Z gates). Each qubit in the set of qubits can be controlled via one or more control signals (e.g., microwave control signals) within a microwave frequency band and one or more DC control signals. That is, the control and / or operation of a qubit requires at least one DC control signal and at least one microwave control signal. In contrast, the control and / or operation of a quantum coupler may require one or more DC control signals, but may not require a microwave control signal.

[0016] Conventional QCS may include both microwave control logic (e.g., generation and shaping of microwave control signals for qubits) and DC control logic (e.g., generation and shaping of DC control signals for qubit couplers and qubits). In such a conventional approach, for each qubit coupler and each qubit, it is necessary to wire at least one dedicated DC control line from an RT environment to an ultra-low temperature environment. In contrast, by positioning a multiplexed control logic device within the ultra-low temperature environment, various embodiments place at least a portion of the DC control logic (e.g., for the control of qubits and quantum couplers) within the ultra-low temperature environment. That is, at least a portion of the DC control logic for qubit couplers and qubits is positioned in the same location as the quantum processor device within the ultra-low temperature environment. Positioning a portion of the DC control logic in the same location as the quantum processor device (e.g., within the ultra-low temperature environment) provides a significant reduction in the number of DC control lines required to wire from an RT environment to an ultra-low temperature environment.

[0017] The DC control logic portion of a quantum coupler can be implemented by a multiplexed control logic device located in a cryogenic environment, as described above. Therefore, the multiplexed control logic device may be a DC control logic device, or simply a DC logic device. A DC logic device may include one or more multiplexed logic devices and / or one or more demultiplexed logic devices. As used herein, the term “multiplexed” logic device (e.g., multiplexer) may refer to a logic device that is a “many-to-one” device and / or a “fan-in” device. A multiplexer logic device allows multiple input signals to be input to a single other device and / or signal line. For example, a multiplexed logic device may be a “data selector” device capable of transmitting a single output signal based on a selection of at least one of multiple input signals or lines. The term “demultiplexed” logic device may be a “one-to-many” device and / or a “fan-out” logic device that inverts the multiplexing logic of a multiplexer logic device. A demultiplexing logic device (e.g., a demultiplexer) is a device that takes a single input signal and provides an output signal to at least one of multiple output lines based on the input signal and a selection of at least one of multiple output lines. The "many-to-one" selection of a multiplexer logic device and / or the "one-to-many" selection of a demultiplexer logic device may be based on a separate input signal (e.g., a selection signal) received via a separate input line (e.g., a selection line). In the terms "many-to-one" and "one-to-many," "many" may refer to a positive integer greater than 1, i.e., K=2. n >1, where n is a positive integer. Thus, the selection input line can be made capable of transmitting a selection of an input signal that encodes n classical bits of information.

[0018] In the embodiment, the control line may start outside the cryogenic environment and terminate in a demultiplexer device within the cryogenic environment. The demultiplexer device may have N output lines. The control line may pass through one or more chamber walls separating the outside of the cryogenic environment from the inside. The control line may provide distinct control signals to up to K quantum devices via the demultiplexer device, as discussed below. Thus, a single control line passing through one or more chamber walls may provide control signals to at least K distinct quantum devices. The demultiplexer device may receive control signals as input. Each output line of the demultiplexer device may function as an input line to a distinct quantum device within the cryogenic environment. Therefore, the number of control lines that need to pass through one or more nested cryogenic chambers is...

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[0019] In at least one embodiment, bidirectional communication between a quantum device inside and outside a cryogenic environment can be achieved by a combination of demultiplexing and multiplexing devices. For example, each of several qubit devices can provide one or more input signals to a multiplexing device inside the cryogenic environment. One or more input signals can be communicated to the outside of the cryogenic environment via a single output of the multiplexing device passing through a cryogenic chamber.

[0020] DC logic devices can be enabled to receive signals (e.g., digital signals) originating from outside a cryogenic environment and transmitted via control lines. In response to receiving an input signal, a control logic device can generate and / or route one or more DC control signals. DC control signals can be provided to one or more quantum devices in the cryogenic environment, either directly from the DC logic device or via one or more multiplexing or demultiplexing devices included in the DC logic device.

[0021] In some embodiments, a DC logic device located within a cryogenic chamber may be a programmable DC logic device. The programmable DC logic device may receive one or more “programming” signals through a transmission line passing through one or more chamber walls (e.g., the control lines described above). The programmable DC logic device may be programmed to generate and provide various DC control signals to be supplied to quantum devices (e.g., via a programming signal provided by a single control line). The outputs of the programmable DC logic device, which generate and output various “programmed” DC control signals, may function as inputs to a demultiplexing device incorporated into the DC logic device. In at least one embodiment, the programmable DC logic device may be programmed to generate separate selection input signals for the demultiplexing device. Separate outputs of the programmable DC logic device may provide the generated selection input signals to the demultiplexing device. In at least one embodiment, the programmable DC logic device and the demultiplexing device may be integrated into a single programmable multiplexed control logic device. In at least one embodiment, the programmable control logic device may be programmed to read multiple quantum devices via the multiplexing device and communicate one or more quantum device signals outside the cryogenic environment. Multiplexing devices, demultiplexing devices, and programmable DC control logic devices can be integrated into a single programmable multiplexed control logic device. In at least one embodiment, the control logic device may be a digital-to-analog converter (DAC) device implemented as multiple loops paired with Josephson junctions for large inductance.

[0022] Aspects of this disclosure offer several technical effects and advantages. For example, the architecture significantly reduces the number of control lines that need to be routed from the RT environment to the cryogenic environment. DC-controlled logic devices located in the cryogenic environment are enabled to deliver DC pulses of sufficient fidelity to control qubits and quantum logic gates. Furthermore, the cryogenic DC-controlled logic devices are enabled to power and control qubits and quantum logic gates with sufficiently low power dissipation. The DC-controlled logic devices are further enabled to address each of their qubits and quantum gates individually.

[0023] Figure 1 shows an exemplary quantum computing system 100. Quantum computing system 100 is an example of a system of one or more classical computers and / or quantum computing devices in one or more locations, in which the systems, components, and techniques described below may be implemented. Those skilled in the art will understand that other quantum computing devices or systems can be used with the disclosures provided herein without departing from the scope of this disclosure.

[0024] The quantum computing system 100 includes quantum hardware 102 that communicates data with one or more classical processors 104. The classical processors 104 may be configured to execute computer-readable instructions stored in one or more memory devices in order to perform operations such as any of the operations described herein. The quantum hardware 102 includes components for performing quantum computation. For example, the quantum hardware 102 includes a quantum system 110, control devices 112(or more), and read devices 114(or more) (e.g., read resonators(or more)). The quantum system 110 may include one or more multi-level quantum subsystems, such as qubit registers (e.g., qubit 120). In some embodiments, the multi-level quantum subsystems may include superconducting qubits such as flux qubits, charge qubits, transmon qubits, Simon qubits, and spin-based qubits.

[0025] The type of multi-level quantum subsystem utilized by the quantum computing system 100 may vary. For example, it may be advantageous in some cases to include one or more superconducting qubits, e.g., transmon, flux, zimon, exmon, or one or more readout devices 114 attached to other qubits. In other cases, ion traps, photonic devices, or superconducting cavities (which can prepare states without requiring qubits) may be used. Further realizations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots, or phosphorus impurity qubits.

[0026] A quantum circuit can be constructed and applied to the registers of qubits contained within a quantum system 110 via a plurality of control lines coupled to one or more control devices 112. An exemplary control device 112 operating over the registers of qubits may be used to implement a quantum gate or quantum circuit having a plurality of quantum gates, such as Pauli gates, Hadamard gates, controlled NOT (CNOT) gates, controlled phase gates, T gates, multi-qubit quantum gates, coupler quantum gates, etc. One or more control devices 112 may be configured to operate on the quantum system 110 through one or more respective control parameters (e.g., one or more physical control parameters). For example, in some embodiments, the multi-level quantum subsystem may be a superconducting qubit, and the control device 112 may be configured to provide control pulses to the control lines to generate a magnetic field and adjust the frequency of the qubit.

[0027] The quantum hardware 102 may further include a readout device 114 (e.g., a readout resonator). Measurement results 108 obtained via the measurement device may be provided to a classical processor 104 for processing and analysis. In some embodiments, the quantum hardware 102 may also include quantum circuits, and the control device 112(or more) and readout device 114(or more) may implement one or more quantum logic gates operating on the quantum computing system 100 via physical control parameters (e.g., microwave pulses) transmitted through wires included in the quantum hardware 102. Further examples of control devices include arbitrary waveform generators from which a DAC (digital-to-analog converter) produces a signal.

[0028] The readout device 114(or more) may be configured to perform quantum measurements on the quantum system 110 and transmit the measurement results 108 to the classical processor 104. Furthermore, the quantum hardware 102 may be configured to receive data from the classical processor 104 specifying physical control qubit parameter values ​​106. The quantum hardware 102 may use the received physical control qubit parameter values ​​106 to update the actions of the control device 112(or more) and readout device 114(or more) on the quantum system 110. For example, the quantum hardware 102 may receive data specifying a new value representing the voltage intensity of one or more DACs contained within the control device 112, and accordingly update the action of the DACs on the quantum system 110. The classical processor 104 may be configured to initialize the quantum system 110 to an initial quantum state, for example, by transmitting data to the quantum hardware 102 specifying an initial set of physical control qubit parameters 106.

[0029] In some embodiments, the readout device 114(or more) reads elements of a quantum system such as qubits.

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[0030] In some embodiments, the quantum system 110 may include a plurality of qubits 120 arranged in, for example, a two-dimensional grid 122. For clarity, the two-dimensional grid 122 shown in Figure 1A contains 4 × 4 qubits, but in some embodiments, the quantum system 110 may contain fewer or more qubits. In some embodiments, the plurality of qubits 120 may interact with each other through a plurality of qubit couplers, for example, a qubit coupler 124. The qubit coupler may define the nearest neighbor interaction between the plurality of qubits 120. In some embodiments, the strength of the plurality of qubit couplers is an adjustable parameter. In some cases, the plurality of qubit couplers included in the quantum computing system 100 may be couplers with a fixed coupling strength.

[0031] In some embodiments, the qubits 120 may include data qubits such as qubit 126 and measurement qubits such as qubit 128. The data qubits are qubits involved in the computation being performed by the quantum computing system 100. The measurement qubits are qubits that can be used to determine the output results of the computation performed by the data qubits. That is, during the computation, the unknown state of the data qubits is communicated to the measurement qubits using appropriate physical operations and measured through appropriate measurement operations performed by the measurement qubits.

[0032] In some embodiments, each of the multiple qubits 120 may operate using its respective operating frequency, such as an idling frequency and / or interaction frequency and / or read frequency and / or reset frequency. The operating frequency may vary from qubit to qubit. For example, each qubit may idle at a different operating frequency. The operating frequency of qubit 120 may be selected before the calculation is performed.

[0033] Figure 1 shows one exemplary quantum computing system that may be used to implement the methods and operations according to exemplary embodiments of this disclosure. Other quantum computing systems may be used without departing from the scope of this disclosure.

[0034] Figure 2 shows an exemplary environment 200 in which various embodiments may be implemented. Environment 200 may be a room temperature (RT) environment 200. The RT environment 200 may house or include a quantum computing and / or quantum information processing system (e.g., QCS). The QCS may include a cryogenic system. The cryogenic system may include a cryogenic chamber 210 that achieves a temperature of about 4 Kelvin (K). A cryogenic chamber 220 may be nested within the cryogenic chamber. The cryogenic chamber 220 may achieve a temperature on the order of millikelvin (mK). The cryogenic chamber 220 may house a quantum processor device 240. The quantum processor device 240 may include a set of quantum devices 250. The set of quantum devices 250 may include a set of quantum logic gates 260 and a set of qubits 290. The set of quantum logic gates 260 may include a set of qubit couplers 270 and a set of Z gates 280. In addition to the quantum processor device 240, the cryogenic chamber 220 may accommodate one or more DC-controlled logic devices (e.g., DC-controlled logic device 230).

[0035] In quantum computing and quantum information processing systems (e.g., QCS housed by RT environment 200), qubits (e.g., qubits included in set 290) are fundamental information encoding mechanisms. Quantum logic gates (e.g., quantum logic gates included in set 260) are fundamental logic mechanisms used to manipulate and / or process the information encoded by qubits. Qubits encode quantum information through amplitude and relative phase that characterize the quantum states of the qubits (e.g., superposition states and / or entangled states). Quantum logic gates process quantum information by performing unitary operations (e.g., transformations) on the quantum states of the qubits. Such unitary operations process quantum information by deterministically transforming the corresponding quantum states of the qubits (e.g., transforming amplitude and relative phase). Thus, operations and / or transformations deterministically manipulate the information encoded by the qubits. Quantum logic operations performed by at least some quantum logic gates can be to some extent analogous to classical logic operations (e.g., XOR, AND, NOT, etc.). For example, the X gate is a single-qubit quantum logic gate that is somewhat similar to the classical NOT operation. Other quantum logic gates do not have classical logic analogues. For example, the Z gate (e.g., the Z gate included in set 280 of Z gates) is a single-qubit quantum logic gate that rotates the quantum state of a qubit by π radians around the z-axis of a Bloch sphere representation. Another quantum logic gate that does not have a classical logic analogue is the Hadamard gate, which transforms a "pure" quantum state into a "superposition" quantum state. Some quantum logic gates are physically implemented by one or more qubit couplers (e.g., the qubit couplers included in set 270 of qubit couplers). Such coupler-based quantum logic gates can be used to generate "entanglement" of two or more qubits.

[0036] The unitary constraints on transformations performed by quantum logic gates ensure that the transformations are reversible and therefore preserve quantum information during computation, at least until the corresponding qubit is "read out" or decohered. Even though quantum information is preserved via unitary transformations, the amplitude and relative phase may not be readily observable when the qubit is in a superposition state of its eigenstates. However, the application of certain configurations of quantum logic gates may enable the extraction of information correlated with the quantum state of the operated qubit. Both qubits and quantum logic gates (including couplers) can be viewed as variations of quantum devices, e.g., those included in the quantum device set 250.

[0037] For quantum devices to be successfully controlled and operated, each quantum device requires at least one control line configured to transmit electrical signals. Through the control line, the quantum device is communicatively coupled to other components of the quantum computing system. Depending on the nature of the quantum device, some quantum devices may require multiple control lines. A quantum computing system can operate and / or control a quantum device by transmitting one or more control signals to the quantum device along one or more control lines of the device.

[0038] If the environment of a qubit is not precisely controlled, the qubit tends to become decoherent. A decoherent qubit may not be able to maintain superposition and / or entanglement states. A decoherent qubit cannot encode quantum information and cannot quantum mechanically "interact" with other qubits. At most, a decoherent qubit can act as a classical bit. Thus, once decoherent, a qubit loses its "quantum supremacy" over classical computation bits. Fluctuations due to thermal energy are one mechanism that can lead to the decoherence of a qubit. Thus, many quantum computing systems isolate their qubit devices from the external environment through one or more cryogenic systems. Temperatures on the order of millikelvin (mK) may be required to allow for a coherence time equivalent to a sufficient time for nontrivial quantum computation. Thus, the cryogenic system can be a multi-stage system, for example, a system that achieves multiple (thermally isolated) environments in which the temperature decreases. A multi-stage cryogenic system may include at least two stages. The first stage can achieve a temperature on the order of approximately 4 Kelvin (K), while the second stage can achieve a temperature in the mK range. In the embodiment, the first stage (e.g., the 4K stage) corresponds to a low-temperature (LT) environment, and the second stage (e.g., the mK stage) corresponds to an ultra-low temperature (uLT) environment. The low-temperature chamber 210 can enable the 4K stage, while the ultra-low-temperature chamber 220 can enable the mK stage.

[0039] To operate each quantum device in the set of quantum devices 250, at least one DC control signal may be required to be delivered to the quantum device. In addition to the DC control signal, the operation of each qubit in the set of qubits 290 may require a microwave control signal. A microwave signal generator 204, located in a room temperature environment 200, can generate microwave control signals. A set of microwave control lines 214 may be routed from the room temperature environment 200 through the cryogenic chamber 210 and the cryogenic chamber 220 to the set of quantum devices 250. The set of microwave control lines 214 may be configured to transmit microwave control signals from the microwave signal generator 204 to at least some of the set of quantum devices 250. In at least one embodiment, the set of microwave control lines 214 may be configured to transmit microwave control signals from the microwave signal generator 204 to each qubit in the set of qubits 290. In at least some embodiments, the set of microwave control lines 214 may be configured to transmit microwave control signals from the microwave signal generator 204 to additional and / or alternative quantum devices of the set of quantum devices 250. For example, a set of microwave control lines 214 may be configured to transmit microwave control signals from a microwave signal generator 204 to at least one subset of a set of qubit couplers 270 and / or at least one subset of a set of Z gates 280.

[0040] To provide this DC control signal in a conventional QCS, for each individual quantum device in the set of quantum devices 250, at least one control line may start in a room temperature (RT) environment 200, cross the cooler chambers 210 and the cryogenic chamber 229, and terminate at the corresponding quantum device in the cryogenic chamber 220. In contrast to the conventional approach, in various embodiments, a multiplexed control logic device (e.g., a DC control logic device 230) is located in the cryogenic chamber 220. As shown in Figure 2, the output of the DC control logic device 230 "fans out" to multiple quantum devices. Thus, the DC control logic device 230 can be a multiplexed DC control logic device. The fan-out (or multiplexing) of the DC control logic device 230 makes it possible to provide a set of DC control signals 222 to at least one subset of the set of quantum devices 260.

[0041] One or more DC control lines (e.g., DC control line 212) may provide one or more “programming” signals to the DC control logic device 230. In the embodiment shown in Figure 2, a single DC control line (e.g., DC control line 212) provides a programming signal to the DC control logic device 230. The programming signal generator is located in a room temperature environment 200. The DC control line 212 begins in the room temperature environment 200, traverses the cryogenic chamber 210 and the cryogenic chamber 220, and terminates at the DC control logic device 230. The programming signal generator 202 may generate a programming signal, and the DC control line 212 may provide the programming signal to the DC control logic device 230. In response to receiving the programming signal, the DC control logic device 230 may provide a set of DC control signals 222 to a subset of the set 250 of quantum devices.

[0042] In other embodiments, multiple DC control lines may provide programming signals to the DC control logic device 230. The DC control logic device 230 may receive input signals via K input lines, where K is a positive integer. Based on the encoded signals from the K input signals, the DC control logic device 230 may provide control signals to L quantum devices (of the set of quantum devices 250), where L is a positive integer. K DC control lines are wired from the RT environment 200 to the cryogenic chamber 220 to control the L quantum devices. The K control lines transmit programming signals from the RT environment 200 to the DC control logic device 230.

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[0043] Although not explicitly shown in Figure 2, the cryogenic chamber 220 may include multiple DC control logic devices. Multiple DC control lines may transmit multiple programming signals to multiple DC control logic devices. Each of the multiple DC control logic devices may provide DC control signals to a distinct subset of the set of quantum devices 250. Each distinct subset of the set of quantum devices 250 may be prime to all other subsets of the set of quantum devices 250.

[0044] Figure 3A shows an exemplary DC-controlled logic device 300 consistent with various embodiments. The DC-controlled logic device 300 may be similar to the DC-controlled logic device 230 in Figure 2. Thus, the DC-controlled logic device 300 may be located in the same place as a quantum processor (e.g., the quantum processor device 240 in Figure 2) within a cryogenic chamber (e.g., the cryogenic chamber 210 and / or ultra-cryogenic chamber 220 in Figure 2). The DC-controlled logic device 300 may be a digital-to-analog converter (DAC) device. The DC-controlled logic device 300 may be implemented as a set of loops (e.g., a first loop 302 and a second loop 304) pairing a large inductance (e.g., inductor 306) with one or more Josephson junctions (e.g., a first Josephson junction 320, a second Josephson junction 322, and a third Josephson junction 324). It should be noted that the different physical sizes of "X" used to indicate distinct Josephson junctions indicate that the IC of the junction may vary among the first, second, and third Josephson junctions 320 / 322 / 324. In other embodiments, the IC may be similar across all Josephson junctions.

[0045] In this non-limiting example, the DC-controlled logic device 300 comprises a set of stages (e.g., a first stage 308). In the exemplary embodiment shown in Figure 3A, only a single stage is included. However, embodiments are not limited thereto, and additional stages may be added to the DC-controlled logic device 300. For each stage, a flux quantum is added to a loop (e.g., a first loop 302 or a second loop 304), increasing the current flowing through the loop. Each loop is then inductively coupled to a separate quantum device via a transformer (e.g., a first transformer 330 for the first loop 302, a second transformer 332 for the second loop 304) to effectively apply a bias magnetic field. Additional loops may be added to restore fine control of the output magnetic field. Each flux quantum can be added to the loop at very high speeds. The superconducting circuit can operate at rates of 100+ GHz. In addition, power dissipation is roughly about 0.22 aJ per flux quantum moving in and out of the loop.

[0046] In the non-limiting embodiment shown in Figure 3A, a “programming” input signal 310 may be provided to the DC control logic device 300. The input signal 310 is

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[0047] Figure 3B shows an exemplary digital-to-analog (DAC) device array 350 consistent with various embodiments. The DAC device array 350 may be a 2D array of DAC devices. In this non-limiting example, the DAC device array 350 includes four DAC devices, namely a first DAC device 352, a second DAC device 354, a third DAC device 356, and a fourth DAC device 358. The four DAC devices are arranged in a 2D 2x2 planar array. Other embodiments, not limited thereto, may include additional DACs. For example, a larger 2D array is possible. Furthermore, in at least one embodiment, the DAC device array 350 may be a 3D array of DAC devices. Each DAC device in the DAC device array 350 (e.g., the first DAC device 352, the second DAC device 354, the third DAC device 356, and the fourth DAC device 358) may be a DC-controlled logic device. That is, each of the DAC devices in the DAC device array 350 may be similar to the DC-controlled logic device 300 in Figure 3A. Therefore, each DAC device can provide a DC control signal to one or more quantum devices. Furthermore, the DAC device array 350 can be located in a cryogenic environment (for example, the cryogenic chamber 220 in Figure 2).

[0048] A common bias current can be shared across multiple DAC devices and therefore multiple quantum devices via one or more bias current lines (e.g., a first bias current line 362 and a second bias current line 364). For example, the first bias current line 362 may provide a common bias current to both the first DAC device 352 and the third DAC device 356. Similarly, the second bias current line 364 may provide another common bias current to the second DAC device 354 and the fourth DAC device 358. In this way, a single bias current line can provide a common bias current to multiple quantum devices; that is, the bias current can be shared across multiple quantum devices. Note that in some embodiments, the first bias current line 362 and the second bias current line 364 may be coupled to each other, and the common bias current may be shared by each of the four DAC devices 352 / 354 / 356 / 358.

[0049] The DAC device array 350 may also include multiple address lines, thereby allowing each DAC device (and therefore each quantum device) to be selectively addressed, accessed, controlled, operated, and / or read. As shown in a non-limiting embodiment, the DAC device array 350 includes four address lines arranged in a 2D array (e.g., a first address line 372, a second address line 374, a third address line 376, and a fourth address line 378). The 2D array of address lines may be configured in a “column and row” arrangement, so that each pair of column address lines and row address lines selects a specific DAC device (and / or a specific quantum device). In the non-limiting example of Figure 3B, the first address line 372 and the second address line 374 are column address lines. The third address line 376 and the fourth address line 378 are row address lines. The first DAC device 352 is selected by a combination of the first address line 372 (e.g., a column address line) and the third address line (e.g., a row address line). Note that in 3D embodiments, the array of address lines may be a 3D array.

[0050] Additional Embodiments One non-limiting embodiment includes a quantum computing system (QCS). The QCS may include a first cryogenic chamber, a first quantum device, a second quantum device, and a first control logic device. Each of the first quantum device, the second quantum device, and the first control logic device may be arranged together with the first cryogenic chamber. In response to receiving one or more programming signals, the first control logic device may be configured to provide a first control signal to the first quantum device and a second control signal to the second quantum device. In some embodiments, the QCS may also include a first control line. The first control line may begin outside the first cryogenic chamber and terminate at the first control logic device. The first control line is configured to transmit one or more programming signals from outside the first cryogenic chamber.

[0051] In various embodiments, the QCS may further include a third quantum device, a fourth quantum device, and a second control logic device. Each of the second quantum device, the third quantum device, and the second control logic device may be arranged together with the first cryogenic chamber. In response to receiving one or more additional programming signals, the second control logic device may be configured to provide a third control signal to the third quantum device and a fourth control signal to the fourth quantum device. In some embodiments, the QCS may also include a second control line. The second control line may start outside the first cryogenic chamber and terminate at the second control logic device. The second control line is configured to transmit one or more additional programming signals from outside the first cryogenic chamber.

[0052] In at least one embodiment, the first control signal is a first DC control signal, the second control signal is a second DC control signal, the third control signal is a third DC control signal, and the fourth control signal is a fourth DC control signal. Each of the first, second, third, and fourth quantum devices may be a qubit or a quantum logic gate. The quantum logic gate may be a Z gate. In some embodiments, the quantum logic gate may be implemented by a qubit coupler.

[0053] In at least one embodiment, the QCS may include a second cryogenic chamber. The first cryogenic chamber may be nested inside the second cryogenic chamber. The first cryogenic chamber may be configured to maintain a first temperature in the millikelvin (mK) range. The second cryogenic chamber may be configured to maintain a second temperature of about 4 Kelvin.

[0054] In some embodiments, the first control logic device is a DC control logic device. The DC control logic device may be a digital-to-analog (DAC) device. The DAC device can convert one or more programming signals into a first control signal and a second control signal. The first control signal may be a first analog signal, and the second control signal may be a second analog signal. The first analog signal and the second analog signal may be sinusoidal signals offset by relative phase. Furthermore, one or more programming signals may be sinusoidal signals.

[0055] The DAC device may include a first current loop and a second current loop. The first current loop may pair a first Josephson junction with a first inductance of the DAC device. The second current loop may pair a second Josephson junction with the first inductance of the DAC device. The first current loop may provide a first analog signal to a first quantum device. The second current loop may provide a second analog signal to a second quantum device. The DAC device may further include a first transformer and a second transformer. The first transformer may electrically couple the first loop to the first quantum device. The second transformer may electrically couple the second loop to the second quantum device. The DAC device may further include a set of stages. Each stage in the set of stages adds an additional flux quantum to the first inductance.

[0056] Another embodiment includes a method for operating a quantum computing system. The method may include providing one or more programming signals to a control logic device. The control logic device may be located in the same location as a first quantum device and a second quantum device within a cryogenic chamber. One or more programming signals may originate from outside the cryogenic chamber. In response to receiving one or more programming signals, the control logic device may be configured to provide a first control signal to the first quantum device within the cryogenic chamber and a second control signal to the second quantum device within the cryogenic chamber.

[0057] Another embodiment includes a cryogenic chamber comprising a first device, a second device, and a DC control logic device. Each of the first device, the second device, and the DC control logic device may be located inside the cryogenic chamber. The first device is operable via a first DC control signal. The second device may be operable via a second DC control signal. In response to receiving one or more programming signals originating from outside the cryogenic chamber, the DC control logic device may be configured to provide a first DC control signal to the first device and a second DC control signal to the second device.

[0058] The digital, classical, and / or quantum subjects, as well as embodiments of digital functional and quantum computing, described herein may be implemented in digital electronic circuits, appropriate quantum circuits, or more generally, quantum computing systems, tangibly implemented digital and / or quantum computer software or firmware, digital and / or quantum computer hardware, including structures disclosed herein and their structural equivalents, or one or more combinations thereof. The term “quantum computing system” may include, but is not limited to, quantum computers / computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0059] Embodiments of the digital and / or quantum subject described herein may be implemented as one or more digital and / or quantum computer programs, i.e., as one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-temporary storage medium to be executed by a data processing device or to control the operation of a data processing device. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit / qubit structures, or one or more combinations thereof. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagating signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, generated for encoding the digital and / or quantum information for transmission to a suitable receiver device, for execution by a data processing device.

[0060] The terms quantum information and quantum data refer to information or data transmitted, held, or stored within a quantum system, the smallest non-trivial system being a qubit, i.e., a system that defines the unit of quantum information. The term “qubit” is understood to encompass all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems may include, for example, multi-level systems having two or more levels. Examples of such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many embodiments, the computational ground state is identified by the ground state and a first excited state, but it is understood that other setups are possible in which the computational state is identified by a higher level of excited state (e.g., a qubit).

[0061] The term “data processing device” refers to digital and / or quantum data processing hardware and encompasses all types of devices, machines, and equipment for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, or multiple digital and quantum processors or computers, and combinations thereof. A device may also be, or further include, special-purpose logic circuits, such as FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), or quantum simulators—that is, quantum data processing devices designed to simulate or generate information about a particular quantum system. In particular, a quantum simulator is a special-purpose quantum computer that does not have the ability to perform universal quantum computation. In addition to hardware, a device may also optionally include codes that constitute the execution environment for digital and / or quantum computer programs, such as processor firmware, protocol stacks, database management systems, operating systems, or codes constituting one or more combinations thereof.

[0062] Digital or classical computer programs may also be referred to or described as programs, software, software applications, modules, software modules, scripts, or codes, and can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and can be deployed in any form, including as standalone programs, or as modules, components, subroutines, or other units suitable for use in a digital computing environment. Quantum computer programs may also be referred to or described as programs, software, software applications, modules, software modules, scripts, or codes, and can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and can be converted into a suitable quantum programming language, or can be written in a quantum programming language, such as QCL, Quipper, Cirq, etc.

[0063] Digital and / or quantum computer programs may, but do not necessarily, correspond to files in a file system. A program may be stored in a single file dedicated to the program in question, as part of a file holding one or more scripts stored in other programs or data, such as a document in a markup language; or in multiple collaborative files, such as files storing one or more modules, subprograms, or parts of a code. Digital and / or quantum computer programs may be deployed to run on one digital or quantum computer, on multiple digital and / or quantum computers located in one place, or on multiple computers distributed across multiple locations and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network capable of transmitting quantum data using quantum systems, such as qubits. Generally, digital data communication networks cannot transmit quantum data, but quantum data communication networks can transmit both quantum and digital data.

[0064] The processes and logic flows described herein may be implemented by one or more programmable digital and / or quantum computers equipped with one or more digital and / or quantum processors, which may, as necessary, execute one or more digital and / or quantum computer programs that perform functions by performing operations on input digital and quantum data to generate outputs. The processes and logic flows may also be implemented by special-purpose logic circuits, e.g., FPGAs or ASICs, or quantum simulators, or by a combination of special-purpose logic circuits or quantum simulators with one or more programmed digital and / or quantum computers, and the apparatus may be implemented as special-purpose logic circuits, e.g., FPGAs or ASICs, or quantum simulators, or as a combination of special-purpose logic circuits or quantum simulators with one or more programmed digital and / or quantum computers.

[0065] When one or more digital and / or quantum computer or processor systems are “configured” or “operable” to perform a particular operation or action, it means that the system has software, firmware, hardware, or a combination thereof installed on it that causes the system to perform the operation or action while in operation. When one or more digital and / or quantum computer programs are configured to perform a particular operation or action, it means that one or more programs, when executed by a digital and / or quantum data processing device, contain instructions that cause the device to perform the operation or action. A quantum computer, when executed by a quantum computing device, may receive instructions from a digital computer that cause the device to perform the operation or action.

[0066] A digital and / or quantum computer suitable for executing digital and / or quantum computer programs may be based on a general-purpose or dedicated digital and / or quantum microprocessor, or both, or any other type of central digital and / or quantum processing unit. Generally, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from read-only memory or random-access memory, or from a quantum system suitable for transmitting quantum data, such as photons, or a combination thereof.

[0067] Some exemplary elements of a digital and / or quantum computer are a central processing unit for executing or running instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and memory may be supplemented by or incorporated into special-purpose logic circuits or quantum simulators. Generally, a digital and / or quantum computer includes one or more mass storage devices for storing digital and / or quantum data, such as magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information, or is operablely coupled to receive digital and / or quantum data from them, transfer digital and / or quantum data to them, or do both. However, a digital and / or quantum computer does not necessarily need to have such devices.

[0068] Suitable digital and / or quantum computer-readable media for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, CD-ROM and DVD-ROM disks, and quantum systems (e.g., trapped atoms or electrons). Quantum memory is understood to be a device capable of storing quantum data for long periods with high fidelity and efficiency, such as an optical-matter interface where light is used for transmission and matter is used for storing and preserving the quantum properties of the quantum data, such as superposition or quantum coherence.

[0069] The control of various systems, or parts thereof, described herein can be implemented by digital and / or quantum computer program products, which include instructions that are stored on one or more tangible, non-temporary, machine-readable storage media and are executable on one or more digital and / or quantum processing devices. Each of the systems, or parts thereof, described herein can be implemented as an apparatus, method, or electronic system that includes one or more digital and / or quantum processing devices and memory for storing executable instructions for performing the operations described herein.

[0070] While this specification includes details of many specific embodiments, these should not be interpreted as limiting the scope of the claims, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment may be implemented separately or in any preferred partial combination in multiple embodiments. Furthermore, features may be described above as operating in a particular combination, and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from that combination, and the claimed combination may be directed towards a partial combination or a variation of a partial combination.

[0071] Similarly, while operations are shown in a specific order in the drawings, this should not be understood as requiring that such operations be performed in a specific illustrated order or sequence, or that all illustrated operations be performed, in order to achieve the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and the program components and systems described above should generally be understood as being able to be integrated together in a single software product or packaged in multiple software products.

[0072] Specific embodiments of the present invention have been described. Other embodiments are also within the scope of the following claims. For example, the actions described in the claims may be performed in a different order, and this may still yield desirable results. As an example, the process shown in the accompanying figures does not necessarily require to be performed in the specific order or sequence shown to obtain the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A quantum computing system, The first cryogenic chamber and A first quantum device disposed within the first cryogenic chamber, A second quantum device disposed within the first cryogenic chamber, A quantum computing system comprising: a first control logic device disposed within the first cryogenic chamber, the first control logic device configured to provide a first control signal to the first quantum device and a second control signal to the second quantum device in response to receiving one or more programming signals.

2. The quantum computing system according to claim 1, further comprising a first control line that begins outside the first cryogenic chamber and terminates at the first control logic device, wherein the first control line is configured to transmit the one or more programming signals from outside the first cryogenic chamber.

3. A third quantum device disposed within the first cryogenic chamber, A fourth quantum device disposed within the first cryogenic chamber, The quantum computing system according to claim 1, further comprising: a second control logic device disposed within the first cryogenic chamber, the second control logic device configured to provide a third control signal to the third quantum device and a fourth control signal to the fourth quantum device in response to receiving one or more additional programming signals.

4. A first control line that begins outside the first cryogenic chamber and ends at the first control logic device, wherein the first control line is configured to transmit one or more programming signals from outside the first cryogenic chamber, The quantum computing system according to claim 3, further comprising: a second control line beginning outside the first cryogenic chamber and ending at the second control logic device, wherein the second control line is configured to transmit the one or more additional programming signals from outside the first cryogenic chamber.

5. The quantum computing system according to claim 1, wherein the first control signal is a first DC control signal, and the second control signal is a second DC control signal.

6. A first control line that begins outside the first cryogenic chamber and ends at the first control logic device, wherein the first control line is configured to transmit one or more programming signals from outside the first cryogenic chamber, The quantum computing system according to claim 5, further comprising: a second control line beginning outside the first cryogenic chamber and ending at the first quantum device, wherein the second control line is configured to transmit microwave control signals to the first quantum device.

7. The quantum computing system according to claim 6, wherein the first quantum device is a qubit and the second quantum device is a quantum logic gate.

8. The quantum computing system according to claim 7, wherein the quantum logic gate is a Z gate.

9. The quantum computing system according to claim 7, wherein the quantum logic gate is implemented by a qubit coupler.

10. The quantum computing system according to claim 1, further comprising a second cryogenic chamber, the second cryogenic chamber having the first cryogenic chamber nested within the second cryogenic chamber.

11. The quantum computing system according to claim 10, wherein the first cryogenic chamber is configured to maintain a first temperature in the millikelvin (mK) range, and the second cryogenic chamber is configured to maintain a second temperature of about 4 Kelvin.

12. The quantum computing system according to claim 1, wherein the first control logic device is a DC control logic device.

13. The quantum computing system according to claim 1, wherein the first control logic device is a digital-to-analog converter (DAC) device that converts one or more programming signals into a first control signal and a second control signal, the first control signal being a first analog signal and the second control signal being a second analog signal.

14. The quantum computing system according to claim 13, wherein the first analog signal and the second analog signal are sinusoidal signals offset by relative phase.

15. The quantum computing system according to claim 13, wherein one or more programming signals are sinusoidal signals.

16. The DAC device, A first loop pairing a first Josephson junction with a first inductance, wherein the first loop provides the first analog signal to the first quantum device, The quantum computing system according to claim 13, comprising: a second loop pairing a second Josephson junction with the first inductance, wherein the second loop provides the second analog signal to the second quantum device.

17. The DAC device, A first transformer electrically coupling the first loop to the first quantum device, The quantum computing system according to claim 16, further comprising a second transformer that electrically couples the second loop to the second quantum device.

18. The DAC device, The quantum computing system according to claim 17, comprising a set of steps, each step of the set of steps being an additional flux quantum added to the first inductance.

19. A method for operating a quantum computing system, wherein the method is A method comprising providing one or more programming signals to a control logic device located in the same location as a first quantum device and a second quantum device within a cryogenic chamber, wherein the one or more programming signals originate from outside the cryogenic chamber, and in response to receiving the one or more programming signals, the control logic device provides a first control signal to the first quantum device within the cryogenic chamber and a second control signal to the second quantum device within the cryogenic chamber.

20. A cryogenic chamber, A first device contained inside the cryogenic chamber, wherein the first device is operable via a first DC control signal, A second device contained within the cryogenic chamber, wherein the second device is operable via a second DC control signal, A cryogenic chamber comprising: a DC control logic device contained inside the cryogenic chamber, wherein the DC control logic device is configured to provide a first DC control signal to a first device and a second DC control signal to a second device in response to receiving one or more programming signals transmitted from outside the cryogenic chamber.

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