Autonomous image processing system on chip

Abstract

An on-chip ultrasonic imaging system for autonomous scanning includes an on-chip input memory configured to store scan sequence instructions and parameters, an on-chip processor configured to read scan sequence instructions and parameters from the input memory, and an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters. In some examples, the scan sequence instructions and parameters are stored in factory-programmed non-volatile input memory. In other examples, the scan sequence instructions and parameters are received from an external user device. Scan parameters are optimized or minimized to fit the limited input memory capacity. In some examples, the scan sequence instructions and parameters include programmable nested loops, each of which corresponds to transmit and / or receive events in the scan sequence.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 459,905, filed on 17 April 2023, titled "AUTONOMOUS IMAGING SYSTEM ON CHIP," which relates to U.S. Patent Application No. 17 / 569,805, filed on 6 January 2022, titled "FULL-ARRAY DIGITAL 3D ULTRASOUND IMAGING SYSTEM INTEGRATED WITH A MATRIX ARRAY TRANSDUCER." Each application is incorporated herein by reference in its entirety.

[0002]

[0002] The present invention relates to a system, device, and method for ultrasonic imaging, more specifically, to a system, device, and method for an imaging system on a chip (iSoC) that autonomously performs scanning and imaging without requiring real-time control by an external processor. [Background technology]

[0003]

[0003] Ultrasound imaging is an imaging method that uses sound waves to generate images of structures within a patient's body. Because ultrasound images are captured in real time, they can display not only blood flowing through blood vessels but also the movement of internal organs. These images can provide valuable information for diagnosing various diseases and symptoms and for directing treatment.

[0004]

[0004] Wide-field-of-view 3D image processing with large steering angles generally requires a two-dimensional (2D) (matrix) array transducer with high element density in both azimuth and elevation. On the other hand, a wide aperture is generally required to achieve high resolution and high sensitivity. Therefore, a good 3D transducer generally requires a very large number of transducer elements (transducers), on the order of thousands to tens of thousands. A large number of elements presents a significant challenge in implementing the image processing system, particularly for receiving beamforming, which requires keeping the number of elements low and / or limiting receiving beamforming to multi-step beamforming, where only a first-step microbeamformer is located very close to or integrated with the array, and a second-step macrobeamformer is located on a remote processor. Microbeamformers generally perform beamformation within a subarray and are typically single-beam analog beamformers without dynamic focusing capability. Macrobeamformers perform beamformation between subarrays and are typically digital beamformers with dynamic focusing and multi-beam (parallel beam) capabilities. The splitting process can lead to connectivity issues via flex / cables and limit the bandwidth of signal and control data.

[0005]

[0005] General-purpose processors and field-programmable gate arrays (FPGAs) consume far more power than wearable products can provide. [Overview of the project] [Problems that the invention aims to solve]

[0006]

[0006] In order to operate autonomously, the image processing system on chip requires a low-power yet fully functional central controller integrated into an application-specific integrated circuit (ASIC). This requires the central controller to have a streamlined ultrasound-specific architecture and a streamlined set of input parameters to reduce the need for on-chip storage.

[0007]

[0007] In some approaches, matrix array transducers are integrated with transmit and receive beamformers packaged in an application-specific integrated circuit (image processing system on chip, iSoC) having a digital acquisition channel for each transducer element. This helps reduce the cost, size, weight, and power of ultrasonic imaging systems, while adding functionality (e.g., real-time 3D) and improving performance. A delay and weight (apodization) computer on the ASIC is also provided to generate transmit and receive beamforming delays and apodization on-chip using several parameters per beam. This eliminates the need to pre-calculate and store delay and apodization profiles, which can require large memory, especially for matrix array transducers used for 3D imaging.

[0008]

[0008] To support a wide range of clinical applications, ultrasound imaging systems can perform image processing in various modes (e.g., B-mode, color Doppler, spectral Doppler, M-mode, elastography, etc.) using various functions (e.g., pulse inversion, frequency synthesis, spatial synthesis, etc.) in various scan geometries (sector, vector, trapezoid, linear, steered linear, cone, rectangular prism, etc.) in various dimensional numbers (1D, 2D, 3D, 4D), and various functions (e.g., pulse inversion, frequency synthesis, spatial synthesis, etc.). To support this rich set of functions, imaging systems employ software-controlled general-purpose processors (central processing units (CPU), graphics processing units (GPU)) or field-programmable gate arrays (FPGAs) that execute complex mode and function-specific scan sequence algorithms and state machines to acquire data and update the parameters of transmit and receive beamformers and other signal processing blocks for each pulse echo event. Integrating an on-chip central controller for imaging devices has been a challenging task. In addition, the complexity introduced by the numerous parameters required for each image processing mode remained unresolved for on-chip controllers.

[0009]

[0009] This disclosure describes a method and system for an image processing system on a chip (iSoC) that can autonomously scan and process images without requiring real-time control by an external processor. This enables the development of low-cost, low-power, small and lightweight image processing products that can be worn by patients for diagnosis, monitoring, or treatment. [Means for solving the problem]

[0010]

[0010] In some examples, methods and systems are disclosed herein that enable an image processing system on a chip to autonomously scan and process images in any mode having any functionality, at any scan geometry, and at any number of dimensions, without real-time control by an external processor.

[0011]

[0011] In a preferred embodiment, the image processing system on chip has an input memory on the ASIC that stores an instruction set for a scan sequence and timing parameters and image processing parameters for each event in the scan sequence. The scan instructions and parameters that together define the scan sequence are called the scan design. In this preferred embodiment, the image processing system on chip also has a central controller dedicated to ultrasound that can generate a scan sequence based on the instructions in the input memory and execute each transmit and receive event in the scan sequence using the desired timing parameters and image processing parameters captured in the input memory. In a preferred embodiment, the scan design consists of programmable nested loops in the spatial and temporal dimensions of transmit and receive events, and before each event or event loop, the image processing parameters and timing parameters are updated at that point in the scan sequence. In a preferred embodiment, the image processing parameters are streamlined to minimize the storage requirements on the ASIC for the scan design.

[0012]

[0012] In some embodiments, an on-chip ultrasound imaging system integrated for autonomous scanning includes an on-chip processor configured to read scan sequence instructions and parameters. In some examples, the ultrasound imaging system also includes on-chip input memory for storing scan sequence instructions and parameters. In some examples, the ultrasound imaging system includes an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters. In some examples, the scan sequence instructions and parameters are received from an external user device. The scan parameters are optimized or minimized to fit a limited input memory capacity. In some examples, the scan sequence instructions and parameters include programmable nested loops, each of which corresponds to a transmit and / or receive event in the scan sequence.

[0013]

[0013] The scan, which is performed autonomously by the on-chip central controller, includes a sequence of events that repeat periodically. In some examples, the scan sequence includes individual events, a temporal loop of events, and a spatial loop of events in x and y, with each event and the loop of events from the innermost event loop, x loop, and y loop to the outermost scan loop being timed.

[0014]

[0014] For example, if a user sends a command to the on-chip central controller, for example from an external processor, to start the scan process, the on-chip central controller autonomously executes scan sequence commands and parameters, collectively called scan designs, which are already stored in the internal input memory, without further intervention from the user. The user can pause, resume, or stop the scan. The scan design includes scan sequence commands, parameters for each transmit and / or receive event, and a loop of events comprising the scan sequence. The scan design also defines the timing, inter-event, and / or inter-loop period for full frame / planar in the case of 2D image processing, two-plane in the case of bi-plane image processing, and full volume in the case of 3D image processing. The scan design can function as a framework for an autonomous scan process. The central controller drives the execution of the scan design. Multiple scan designs customized for different image processing modes, functions, or clinical applications are stored in the input memory and can be selected by the user as needed.

[0015]

[0015] In contrast to several other approaches to scanning processes, such as software running on a power-consuming CPU, GPU, FPGA, or a combination of mode-specific and scan geometry-specific programs, the subject art disclosed herein provides a mode / function and scan geometry-independent (agnostic) scan design / framework, allowing all possible scan requirements to be flexibly adapted to the autonomous scan performed by the ASIC.

[0016]

[0016] Additional features and advantages of the subject art are described below and may be partially evident from the description or acquired through the implementation of the subject art. The advantages of the subject art are realized and achieved by the description and embodiments herein, as well as by the structures particularly pointed out in the accompanying drawings.

[0017]

[0017] Each of the systems, methods, and devices of this disclosure has several innovative aspects, but none of them alone are solely involved in the desirable attributes disclosed herein.

[0018]

[0018] It should be understood that the above general description and the following detailed description are both illustrative and descriptive, and are intended to provide further explanation of the subject art.

[0019] It should be noted that the various embodiments described above can be combined with any other embodiments described herein. The features and advantages described herein are not exhaustive, and many additional features and advantages will become apparent to those skilled in the art, particularly in consideration of the drawings, specification, and claims. Furthermore, it should be noted that the terminology used herein has been selected primarily for readability and guidance purposes, and not to delineate or limit the subject matter of the invention.

[0019]

[0020] Various features of exemplary embodiments of the present invention are described below with reference to the drawings. The exemplary embodiments are intended to be illustrative, not limiting, the present invention. The drawings include the following figures. [Brief explanation of the drawing]

[0020] [Figure 1]

[0021] This figure illustrates exemplary architectures of components for an autonomous image processing system-on-chip (AiSoC) according to several embodiments. [Figure 2]

[0022] This is an exemplary schematic diagram of an ultrasonic system using a transducer assembly comprising a 2D array of transducers, an ASIC mounted on a PCB with additional circuitry, and a remote processor with a user interface and display, according to several embodiments. [Figure 3-1]

[0023] This is a schematic diagram of a digital 3D single-stage full array beamformer having an ASIC, according to several embodiments. [Figure 3-2] Same as above. [Figure 4-1]

[0024] This is a schematic diagram of a digital 3D two-stage full array beamformer with an ASIC, according to several embodiments. [Figure 4-2] Same as above. [Figure 5]

[0025] This is a graph of the geometry of ultrasonic beams generated by ultrasonic transducer arrays in several embodiments. [Figure 6]

[0026] This is a flowchart of a 3D dynamic delay and weighting computer according to several embodiments. [Figure 7]

[0027] This is a graph of the geometry of ultrasonic beams generated by ultrasonic transducer arrays in several embodiments. [Figure 8A]

[0028] This figure shows an exemplary rectangular beam grid for sampling a truncated pyramid, according to several embodiments. [Figure 8B] This figure shows an exemplary rectangular beam grid for sampling a truncated pyramid, according to several embodiments. [Figure 9]

[0029] This figure shows an exemplary scan design according to several embodiments. [Modes for carrying out the invention]

[0021]

[0030] Herein, examples of implementations are given, which are shown in the accompanying drawings. The following description includes numerous specific details to provide a complete understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be implemented without requiring some of these specific details.

[0022]

[0031] Various configurations of the subject art will be readily apparent to those skilled in the art from this disclosure, and it will be understood that various configurations of the subject art are shown and described as examples. As will be understood, other different configurations of the subject art are possible without departing from the scope of the subject art, and some of its details are modifiable in various other respects. Accordingly, the summary, drawings, and detailed description shall be considered as illustrative and not limiting in nature.

[0023]

[0032] The detailed descriptions provided below are intended to describe various configurations of the subject art and are not intended to represent only the configurations in which the subject art can be implemented. The accompanying drawings are incorporated herein and constitute part of the detailed descriptions. The detailed descriptions include specific details for the purpose of providing a complete understanding of the subject art. However, it will be apparent to those skilled in the art that the subject art can be implemented without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid ambiguity of the concepts of the subject art. For ease of understanding, the same components are labeled with the same element number.

[0024]

[0033] Figure 1 shows exemplary architectures of components of an autonomous image processing system-on-chip (AiSoC) 1022 in several embodiments. This disclosure focuses on the central controller and input memory shown in Figure 1.

[0025]

[0034] As shown with reference to Figure 1, the input memory 1002 may store multiple scan designs selectable by the user. This memory 1002 can be a read-only memory (ROM or EEPROM) that is programmable only at the factory by a pre-designed scan sequence. Alternatively, memory 1002 can be a random-access memory (RAM, SRAM, DDRSRAM) for storing a field-upgradable scan sequence.

[0026]

[0035] Autonomous scanning is performed by the ASIC's central controller 1004. The central controller 1004 reads the scan design from the input memory 1002, executes scan sequence commands, and simultaneously dispatches image processing parameters synchronously to each component based on the timing parameters in the scan design. The central controller 1004 is independent of the scan geometry, mode, and function. The central controller 1004 faithfully executes the scan design without any knowledge of the use case.

[0027]

[0036] The components of the AiSoC controlled by the central controller 1004 may include a beamformer 1006, a detector 1008, an output memory 1010, and a transceiver 1012. The beamformer 1006 may have an on-chip delay and weighting (apodization) computer 1014, a transmitting beamformer 1016, and a receiving beamformer 1018. The transmitting beamformer 1016 drives an array of transducer elements 1020, and the receiving beamformer 1018 receives from the array of transducer elements 1020. The AiSoC 1022 is preferably integrated with the transducer array for efficient and low-cost coupling to the transducer elements 1020. The transducer 1020 can be a 1-D, 1.25-D, 1.5-D, or 2-D array. The transducer 1020 can be a micromachine electromechanical sensor (MEMS), such as a piezoelectric or capacitive micromachine ultrasonic transducer (pMUT or cMUT).

[0028]

[0037] The detector 1008 may include a complex demodulator down to the baseband, followed by a decimator, an envelope detector, a log compressor for B-mode detection, a clutter filter, an autocorrelator, and a flow parameter detector for color Doppler mode. The output memory 1010 provides a buffer for sending the processed output of the beamformer to an external processor 1024 for further processing (e.g., volume rendering) and display. The transceiver 1012 can be wired, such as USB, or wireless, such as Bluetooth or Wi-Fi. Ultrasonic imaging system

[0038] Figure 2 shows exemplary embodiments of the ultrasonic imaging systems disclosed herein, according to several embodiments. The imaging system may preferably include an application-specific integrated circuit (ASIC) (100) integrated with transducers 200. The transducer may be a pMUT (piezoelectric micromachine ultrasonic transducer), a cMUT (capacitive micromachine ultrasonic transducer), or a one-dimensional or two-dimensional array of bulk PZT elements. The ASIC and transducer array are typically mounted on a printed circuit board (PCB) (300). The PCB may have additional circuit configurations such as (optional) a microprocessor, power supply (battery, regulator), clock, memory, and input / output devices.

[0029]

[0039] The ASIC, transducer array, and PCB form a transducer assembly (400). To maintain a small footprint, the area of ​​the transducer assembly may be equal to the area of ​​the transducer array. The transducer assembly can be packaged in a patch, wearable, or retainable housing.

[0030]

[0040] The transducer assembly may communicate with a remote processor (500) via input / output devices, which may include a user interface, display, and memory. The processor may be a mobile device such as a smartphone, smartwatch, pad, or laptop, or it may be a desktop computer. The processor may perform image processing, perform planar and volumetric rendering, and connect to networks and databases such as electronic health records. Communication between the transducer assembly and the remote processor may be wired or wireless using standard communication protocols.

[0031]

[0041] In one example, a microprocessor on a transducer assembly may initialize the ASIC with a small set of parameters, including image processing frequency and transmit and receive f-numbers, and then provide transmit and receive beam parameters (beam origin, angle, focus depth) for each pulse echo (transmit-receive) event in the scan sequence. A delay and weighting computer on the ASIC may calculate transmit beamforming parameters and receive beamforming parameters (delay and weighting) for each beam defined by the transmit and receive beam parameters. The ASIC may send out steered and focused transmit pulses, receive echoes from tissue at each transducer element, and form a receive beam using the delay and weighting calculated by the ASIC. The output of the ASIC is typically a well-formed beam using full aperture.

[0032]

[0042] In an alternative example, the microprocessor on the transducer assembly is optional and may help the ASIC communicate with a remote processor to perform field upgrades of the ASIC input memory or transfer the formed beam and collected information to the remote processor for further processing, analysis, or display. A central controller on the ASIC (e.g., 1004) executes a scan design defined by the scan sequence instruction set and image processing system parameters stored in the input memory on the ASIC, periodically forming frames or volumes of images without real-time control from an external processor. A delay and weighting computer on the ASIC may calculate static transmit beamforming parameters and dynamic receive beamforming parameters (delay and weight) for each beam defined by the transmit beam parameters and receive beam parameters in the scan design. The ASIC may send out steered and focused transmit pulses, receive echoes from tissue at each transducer element, and form a receive beam using the delay and weighting calculated by the ASIC. The output of the ASIC is typically a well-formed beam using a full aperture.

[0033]

[0043] The following sections describe the transducer assembly, the transmitter and receiver, the geometry used for the derivation of the 3D delay equation, and the methods and devices for calculating delay and weighting using the 3D delay equation. Transducer Assembly

[0044] Figure 3 shows details of a transducer assembly (400) and an ASIC (100) within the transducer assembly according to several embodiments.

[0034]

[0045] In one example, the ASIC receives an input (101) from a microprocessor on PCB(300). The input may include initialization parameters such as transmit center frequency and bandwidth, transmit and receive f-values, and receive center frequency and bandwidth. The ASIC may also receive transmit beam parameters and receive beam parameters, and triggers for each pulse echo event. The transmitter may generate a transmit pulse (110), apply element coordinate-dependent delays (111a) and weights (111b) to the pulse, and use the delayed and weighted pulse to drive the pulsers (112) of each acoustic element based on the transmit pulse and transmit beam parameters.

[0035]

[0046] In an alternative example, the microprocessor on PCB(300) is optional, and the optional microprocessor on PCB(300) may help the ASIC communicate with a remote processor to perform field upgrades of the ASIC input memory or transfer the formed beam and collected information to the remote processor for further processing, analysis, or display. A central controller on the ASIC (e.g., 1004) executes a scan design defined by the scan sequence instruction set and image processing system parameters stored in the input memory on the ASIC, periodically forming frames or volumes of images without real-time control from an external processor. A delay and weighting computer on the ASIC may calculate static transmit beamforming parameters and dynamic receive beamforming parameters (delay and weighting) for each beam defined by the transmit beam parameters and receive beam parameters in the scan design. The ASIC may send out steered and focused transmit pulses, receive echoes from tissue at each transducer element, and form a receive beam using the delay and weighting calculated by the ASIC. The output of the ASIC is typically a well-formed beam using a full aperture.

[0036]

[0047] The receiving path for each acoustic element may include a transmit / receive switch (121), an analog front-end (122) for low-noise preamplification, time-gain compensation and anti-aliasing, an analog-to-digital converter (ADC) (123), element memory (124), and a beamformer (125) capable of applying time-variable (dynamic) delay and weighting to the stored element data. The transmit beamformer (delay and weighting), pulser, receive switch, analog front-end, ADC, memory, and receive beamformer (delay and weighting) circuit configuration may form an electronic element (120). An electronic element may exist for each acoustic element.

[0037]

[0048] The outputs of the electronic elements can be summed across the entire array (140) to complete full array beamforming. The beam thus formed can then be filtered by a data compression receiver filter (150), which may include a complex time-variable multiplier followed by demodulation to the baseband by a low-pass baseband filter (BBF). The delay, weighting, array sum, and receiver filter circuit configuration can be replicated using the same element data stored in memory to form multiple parallel beams (160) with distinct delay and / or weighting parameters. The delays and weightings for transmit beamforming and receive beamforming (for all parallel beams) can be generated by a 3D dynamic delay and weighting computer (170) on the ASIC. The output (102) of the ASIC may be a complex (in-phase and quadrature-phase) sample of the parallel beams. The transducer assembly stores the output beam and sends it to a remote processor (500) for further processing, rendering, and display.

[0038]

[0049] The receiving beamforming in Figure 3 can also be performed in multiple stages. Figure 4 shows a schematic diagram of a digital 3D two-stage full array beamformer with an ASIC according to several embodiments. Multi-stage implementation allows for flexible reduction of both the size of the element memory and the parallel beam circuit configuration. Instead of summing the outputs of all electronic elements, the outputs of a subset of electronic elements (subarray) (130) can be summed (131) and stored in a second set of subarray memory (132). Beamforming in the first stage within each subarray is also known as microbeamforming. The second stage applies delay and weighting (133) to the output of the subarray beamformer, and the array sum (140) can complete full array beamforming. For parallel beam operation, only the circuit configuration of the second stage (macrobeamformer) can be replicated. The subarray size is S x ×S y It can be an element, where S x and S y These can be electronic elements such as 2, 3, 4, 5, etc. Transmitter

[0050] A single K-bit depth, L-bit length shift register with a programmable clock can function as an arbitrarily programmable pulse generator (110).

[0039]

[0051] The depth of a shift register K can be determined by the number of pulser states. Generally, a shift register with a K-bit depth can have up to 2 K The pulser can support up to three states. Therefore, K is 1 for a 2-state (unipolar) pulser, and 2 for 3-state (bipolar) and 4-state pulsers.

[0040]

[0052] The shift register length L can be determined by the maximum pulse length specification and the transmitter clock frequency. In a preferred embodiment, the shift register length L is set to 256 bits. This supports pulses up to 16 cycles long with a transmit clock cycle of 16 times the transmit center frequency. Pulses longer than 16 cycles can also be supported by lowering the transmitter clock frequency (sacrificing a delayed quantization step).

[0041]

[0053] The simplest type of pulse may be a unipolar pulse in which the active node of a transducer element is switched between ground and a positive (or negative) voltage rail by two complementary switches. These switches can be controlled by a single 1-bit stream consisting of a set of 1s for the +V segment followed by a set of 0s for GND, and this 1 and 0 pattern is repeated as many times as needed. Each bit may represent the duration of the transmitter clock cycle. Thus, if the transmitter clock cycle is 16F0, the bit stream for a 2-cycle pulse at F0 would be 11111111000000001111111100000000. The durations of the individual +V and GND segments can be fixed for linear (or nonlinear) frequency modulation, or for some other coded excitation, or they can be programmed independently. Such bit patterns can be pre-generated and loaded into the pulse generator's shift register in the ASIC during initialization, and then streamed out when an impulse indicating the start of transmission is received. In some embodiments, the start and / or end of a pulse is a very short code such as 010, for example 111111111000000001111111100000000 010This is marked and can trigger the on / off of other transmit and / or receive circuit configurations. The use of such embedded code may require a decoder (matched filter) of the same length. In some embodiments, the transmit / receive switch of each element may be switched to receive mode as soon as the element completes its own pulse transmission, without waiting for all elements to finish pulse transmission. This helps to clean up some of the near-field artifacts by temporarily distributing leaked transmit and receive enable / disable signals and eliminate dead zones due to missing receive samples.

[0042]

[0054] The next complexity involves a three-state bipolar pulse where the active node of the transducer element is changed between positive, ground, and negative voltage rails by three complementary switches. This type of pulse can be implemented using a 2-bit depth pulse stream, for example, where 00 represents ground, 10 represents +V, and 01 represents -V. 11 states can be used to mark the start and / or end of the pulse.

[0043]

[0055] In the special case of a three-state bipolar pulse, the transducer is grounded only before the pulse begins and after the pulse ends, and switches between the +V and -V states during the pulse. This type of pulse may offer the best second harmonic suppression compared to all two-state pulses or these three-state pulses that have a ground segment within the pulse. It may also be the simplest (lowest cost) architecture in terms of power supply. The special case of the bipolar pulse can be implemented using the single bitstream described above, where 1 maps to +V, for example, and 0 maps to -V. The built-in code snippet described above can be used to indicate the start of the ground state at the end of the pulse. Upon receiving this code, the transducer element is grounded until the start of the next pulse, indicated by the stream of "1". A pulse inversion function can be added using an additional programmable bit common to all elements that inverts the mapping of 1 and 0 values ​​in the pulser to -V and +V.

[0044]

[0056] A pulse common to all elements can be generated by an impulse that marks the start of a pulse echo event, which is typically repeated at a constant pulse repetition interval (PRI). The pulse can then be delayed by element-specific delays for the elements of the array (and in some embodiments, all elements) (111a). The delayed pulse can then be weighted by element-specific weights for apodization. Here, a simple binary on / off weighting is shown. In a preferred embodiment, both the delay and weighting of the transmit beamformer are generated by a delay and weighting computer (170) on the ASIC before the start of the transmit event.

[0045]

[0057] The apodization output can drive the transmit pulser (112) after being converted from digital to analog.

[0058] In some embodiments, for architecture simplification, the pulse generator and the delay operations share the same transmitter clock. Further, for efficiency purposes, the transmitter clock frequency F s can vary as a function of the transmit center frequency F0 and can be set equal to 16F0 when T0 = 1 / F0, achieving a desired delay quantization step of T0 / 16.

[0046]

[0059] In some embodiments, the order of the pulse generator, the delay, and the binary weighting can be changed. For example, for various architectural trade-offs, the binary weighting can be moved before the delay operation, or the delay operation can be moved before the pulse generator, etc. Receiver

[0060] A conventional receiver applies dynamic variable gain, delay, and weighting (apodization) to the echoes from the individual elements S ij (t), where (i,j) are the column and row indices of the elements of the matrix array. Next, the beamformer sums the amplified, delayed, and weighted element signals to generate a beam b(r,θ,x0), where x0 are the (x0,y0,z0) coordinates of the beam origin (in the case of a planar array, z0 is zero), r is the depth, and θ are the beam angles in the z-x and z-y planes. In the case of a digital beamformer, the analog signals can be digitized by an ADC after an LPF before the delay stage.

[0047]

Number

[0048]

[0061] The gain G(t) can have multiple programmable components including a static low-noise amplifier gain G LNA and a dynamic time-variable gain G TGC (t) (also called time gain compensation) to compensate for tissue attenuation. The final gain stage can be an optional programmable gain amplifier.

[0049]

[0062] A low-pass filter (LPF), preferably with a programmable cutoff frequency, provides anti-aliasing and improves the signal-to-noise ratio (SNR). Multiple poles of the LPF can be distributed across various gain stages.

[0050]

[0063] Dynamic delay τ(r,θ,x0,x ij The input to the delay stage can change over time to track the depth from which the echo is coming as the transmitted beam propagates deeper into the tissue. The input to the delay stage is a function of time, and its output is a function of depth (range). Depth is time distorted by the time-variable delay.

[0051]

[0064] Dynamic apodization or weighting α(r,θ,x0,x ij To maintain resolution, the active aperture size can be grown with depth, tapering the contribution of edge elements, i.e., apodizing them, to reduce beam side lobes. In the case of matrix arrays, the shape of the active aperture can also have an apodization effect. In some embodiments, the apodization weighting is depth-dependent but binary, 0 when off and 1 when on, eliminating the need for element-wise and depth-wise multiplication. Semicircular apodization is achieved by turning on elements around the beam origin in a continuously growing circle or ellipsoid. The growth rate of the circle and ellipsoid can be controlled by a programmable f-value. TGC Since this is applied before the delayed action, the gain can be distributed over time as a function of the element-dependent delay. This creates an additional apodization effect for depths where the gain changes abruptly.

[0052]

[0065] Beam parameters θ and x0, element coordinate x ij , ADC sampling rate F sGiven the speed of sound c0 and the f-value, dynamic delay and weighting calculations can be performed by a computer. In many conventional systems, these calculations are performed entirely or partially on a remote processor.

[0053]

[0066] The element summing stage can sum time-aligned (and therefore coherent) and weighted element signals.

[0067] Using delays, weightings, and duplicate sets of element summation stages, multiple beams with independent origins and angles can be generated in parallel. Alternatively, if element data is stored across the entire depth of interest, multiple beams can be formed sequentially using a single beamformer circuit configuration, at the expense of frame rate, by using the time between transmission events. Array and beam geometry

[0068] Figure 5 shows graphs of the ultrasonic beam geometry generated by ultrasonic transducer arrays in several embodiments.

[0054]

[0069] Figure 5 shows the N coordinate system on the xy-plane centered at (0,0,0) in Cartesian coordinates (or on a non-planar curved surface xyz not shown in Figure 5). x ×N y Shows a 2D array of elements (201). x ij This is the x,y,z coordinates of the (i,j)th element (x i ,y j ,z ij The elements of a 2D array can be on a grid of squares or rectangles, rotated squares, rhombuses (parallelograms), hexagons, rings, or any grid. Physical openings can be squares, rectangles, circles or ellipses, or any shape.

[0055]

[0070] The beam has a set of focusing depths: r for the static transmit focus or the dynamic receive focus; a (nominal) beam origin x0, which is a vector with x,y,z coordinates x0=(x0,y0,z0); and an angle θ=(θ) between the zx plane and the zy plane. zx ,θ zy It can be defined in 3D by three parameters, including the angle θ, which is also a vector. Note that bold is used here to represent vectors such as x0 and θ. The coordinates of the sample at depth (or range) r along the receiving beam (θ, x0) are (r, θ, x0). By convention, θ is θ zx and θ zy These are positive values ​​from the +z axis to the +x and +y axes, respectively. The beam origin x0 is also the zero depth (r=0). This is also the nominal center of the active aperture of the beam (θ,x0) excluding the platform due to the physical aperture. All samples of the received beam are projected at angles θ on the zx and zy planes, respectively. zx and θ zy It lies on a line.

[0056]

[0071] 2D image processing in the azimuth (i.e., xz) plane is performed for all beams θ zy and the special case where y0 is zero. 2D image processing in the orthogonal altitude (yz) plane is performed by θ zx And it corresponds to the case when x0 is zero. In the special case of 2D image processing, the array is a 1-D array (for example, N y This is the case when = 1).

[0057]

[0072] The geometry defined here can support independent combinations of azimuth and altitude scan geometry. For example, to define sector geometry for both azimuth and altitude, x0 and y0 are both set to 0 for all beams. In the case of a linear scan, for example for altitude, while y0 is varied from the first row to the last row, θ zyThis is set to zero for all beams. In the case of vector forms such as altitude, while y0 is varied from the first row to the last row, θ zy It changes from a negative angle to a positive angle.

[0058]

[0073] Here, the geometry is N x =S x M x and N y =S y M y In this case, the subarray beamformer (microbeam former) of the first stage is S x ×S y Beamforming is performed on the group of elements, and the second stage M x ×M y This can also be applied to multi-stage beamforming, where a beamformer (macrobeamformer) completes beamforming relative to the output of a subarray beamformer.

[0059]

[0074] In some examples, alternative coordinate systems exist for defining beams in 3D, such as spherical coordinates. The angle of the spherical coordinates is centered on the beam origin x0.

[0060]

number

[0061] And the beam angle (θ) of the framework applied here zx ,θ zy The relationship with ) is,

[0062]

number

[0063] That is the case.

[0075] The analysis and derivation presented here can be applied to any alternative beam definition with minor modifications. 3D delay equation

[0076] The distance d(r,θ,x0,x) along the beam (θ,x0) of a specific element (i,j) ij We were able to derive ).

[0064]

[0077] Cartesian coordinates (b) of beam sample (r,θ,x0) x ,b y ,b z )teeth, (b x ,b y ,b z )=r(v x ,v y ,v z )+(x0,y0,z0) That is the case.

[0065]

[0078] Here, the unit vector along the beam is v = (v x ,v y ,v z )teeth

[0066]

number

[0067] That is the case.

[0079] And the x, y, z coordinates of the beam are, b x =rv x +x0,b y =rv y +y0,b z =rv z That is the case.

[0068]

[0080] Next, x ij =(x i ,y j ) and (r,θ,x0)=(b x ,b y ,b z The distance between ) and is

[0069]

number

[0070] It is given by.

[0081] The square root of the sum of the squares of three terms can be written as the square root of the sum of the squares of two terms, as follows:

[0071]

number

[0072]

[0082] Delay in microseconds τ(r,θ,x0,x ij ) is the distance d(r,θ,x0,x) in millimeters, determined by the round-trip (bidirectional) sound velocity c0 in millimeters / microseconds. ij This is the result of dividing by ).

[0073] τ(r,θ,x0,x ij )=d(r,θ,x0,x ij ) / (c0 / 2)

[0083] Alternatively, the sampling rate F of the ADC in MHz units. s This is the result of dividing the sample size by its unit.

[0074] τ(r,θ,x0,x ij )=F s d(r,θ,x0,x ij ) / (c0 / 2) 3D Dynamic Latency and Weighted Computing

[0084] The above delay formulation can be efficiently implemented using CORDIC (Coordinate Rotation Digital Computer), an efficient method for calculating the square root of the square of two numbers. Figure 6 shows a block diagram and steps of a dynamic 3D delay and weighting computer (170) using two cascaded CORDIC operations (176) according to several embodiments.

[0075]

[0085] Inputs to the delay and weighting computer may include the beam origin, unit vector and depth of focus, element coordinates, ADC sampling rate, speed of sound, and f-number.

[0086] The beam sample Cartesian coordinates (174) at a specific depth r can be generated by multiplying the beam unit vector Cartesian coordinates (171) by the depth (172) and adding it to the beam origin coordinates (173). The x,y,z coordinates of the element can be subtracted from the respective x,y,z coordinates of the beam sample (175) to generate an input to a CORDIC operation. The output of the first CORDIC and the x component of the beam sample can form the input to a second CORDIC. The output of the second CORDIC can provide the distance between the element (i,j) and the beam sample (r,θ,x0), scaled by the gains of two CORDIC stages (CORDIC is not a unit-gain operation). In a preferred implementation, CORDIC gain compensation can be performed by the distance to a delay transform multiplier at the output of a delay computer (178).

[0076]

[0087] In some embodiments, the cascaded CORDIC stages each undergo 8 angular rotations. This number of rotations may be sufficient to keep the maximum distance error within ±T0 / 16, where T0 is the period at the image processing center frequency F0. Each angular rotation can perform a 2-bit shift and two additions. With 8 angular rotations, each CORDIC stage has a gain equal to approximately 1.65, and the combined gain of two CORDIC stages is approximately 2.71.

[0077]

[0088] In some examples, CORDIC-based high-precision distance (delay) calculation may only be required for coarse sets of depth, elements, and beams. Linear interpolation between distance values ​​(177) calculated by CORDIC may be sufficient to keep delay errors within specifications. In some embodiments, the spacing of the coarse range grid is

[0078]

number

[0079] Here, λ0 is the wavelength at the image processing center frequency F0. A linear distance interpolator can provide the midpoint distance value between coarse range grid points. In some embodiments, CORDIC-based delay calculations are performed on a subset of beams, e.g., edge beams of a multi-beam group, and the linear distance interpolator can provide the distance values ​​for the intermediate beams. In some embodiments, the coarse element grid is spaced four elements apart in both azimuthal and altitude. Again, the linear distance interpolator can interpolate the distance values ​​for the intermediate elements. Linear interpolation of powers of two upsampling is very efficient because it requires only addition and bit shifting.

[0080]

[0089] The final stage (178) of the delay engine can compensate for the non-unity gain of the CORDIC stage, using the ADC sampling rate and the speed of sound as inputs to calculate the distance d(r,θ,x0,x) in millimeters. ij ) is a delay τ(r,θ,x0,x) in units of the ADC sampling rate. ij This converts the signal to a delay conversion at the output stage. This allows for a simple method of optimizing the bulk velocity of sound according to clinical applications and the ADC sample rate according to the image processing center frequency. Alternatively, in some embodiments, the CORDIC input parameters can be pre-compensated (pre-scaled) by a central controller for CORDIC gain and distance to delay conversion coefficients, eliminating delay and weighting multiplication within the computer.

[0081]

[0090] The order of linear operations is interchangeable. For example, the conversion from distance to delay can be performed at any point in the delay computer signal path, or the order of interpolation can be changed depending on the implementation-specific problem.

[0082]

[0091] In some embodiments, the weighting is binary, meaning that at any given time / depth, the element is either on or off. A delay computer can provide input to the weighting computer. In some examples, by setting r to zero, the distance between any element and the beam origin can be calculated by the delay computer (|x ij -x0|=d(r=0,θ,x0,x ij This distance, scaled by a scalar function of the f-value (aperture growth rate), is compared to the distance output of a delayed computer during the received event, allowing each element to be turned on at the appropriate time (depth) (179). In this way, the aperture can be grown in a circular shape around the beam origin. Alternatively, rectangular or elliptical aperture growth can be programmed by programming both the growth rate and aperture limits independently for x and y. Data acquisition

[0092] Data acquisition for all image processing modes and functions can be generalized by a unified concept of sampling in the spatial, temporal, and parameter domains. This concept allows for the definition of scan designs for any image processing mode or function (B-mode, color Doppler, spectral Doppler, M-mode, elastography, pulse inversion, synthesis, etc.) as nested scan loops of events in the spatial and temporal domains, while varying a small set of parameters between events, for any scan geometry (sector, trapezoidal or linear, cone, cuboid, etc.) and any number of dimensions (1D, 2D, 3D, 4D). Events can be pulsed echoes (transmit and receive), pulses only, or echoes only.

[0083]

[0093] For example, a planar, or 2D, image is formed by sequentially scanning the transmitted beam electronically along the x or y axis and sampling the xz or yz plane. On the other hand, a volumetric, or 3D, image is formed by raster scanning the transmitted beam along both the x and y axes and sampling the entire xyz space. Typically, the x-axis, or azimuth, is the high-speed scanning axis, while the y-axis, or altitude, is the low-speed scanning axis. In some use cases, the high-speed and low-speed axes can be rotated relative to the x and y axes.

[0084]

[0094] The receiving beamformer uses the echoes received in response to each transmission event to form multiple parallel received beams. These parallel received beams can typically be dispersed in the x and / or y directions around the transmission beam axis (line of sight).

[0085]

[0095] The transmit and receive sampling grids in x and y can be spaced uniformly along the beam angle, uniformly along the sine of the beam angle (higher density closer to the z axis), or uniformly at the beam origin. Spatial sampling can also be performed using nonlinear grids, such as hexagons or spirals, as an alternative.

[0086]

[0096] Real-time 2D images, or real-time 3D (e.g., 4D) images, are formed by repeating the volumetric or planar scans described above at regular time intervals.

[0087]

[0097] Modes that detect motion or flow, such as color Doppler, spectral Doppler, and M-mode, require time-domain sampling, where objects are sampled at regular time intervals for each line of sight (spatial position).

[0088]

[0098] Modes that improve detail resolution, contrast resolution, or transmittance, such as synthetic aperture, pulse inversion second harmonic, frequency synthesis, spatial synthesis, and sequential transmit focus, require parameter-domain sampling, where the object is sampled multiple times because parameters such as aperture, phase, frequency, insonification angle, or focus change. Parameter changes can be interleaved across events, frames, or volume.

[0089]

[0099] In a preferred embodiment, the concepts of sampling in the spatial, temporal, and parameter domains give rise to a mode- and function-independent architecture and language for a central controller. Array and beam geometry

[0100] Figure 7 shows graphs of the ultrasonic beam geometry generated by ultrasonic transducer arrays in several embodiments.

[0090]

[0101] Figure 7 shows a 2D array, with Cartesian coordinates centered on the array, the x-axis being the major axis (or azimuth) of the array, and the y-axis being the minor axis (or altitude) of the array. The object / organization is assumed to have z≧0. For both the transmit and receive beams, the beam axis is defined by a pair of vectors representing the angle and the origin (α,o). The beam angle vector α can be defined by the angle between the z-axis and the projection of the beam onto the xz and yz planes, where α=(α x ,α y The beam origin vector o of the beam can be defined by the x and y coordinates of the point where the beam crosses the 2D array surface, o = (o x ,o y In the case of a planar transducer array, the z-coordinate of the beam origin is zero.

[0091]

[0102] The 3D space is sampled at constant depth intervals along a set of receiving beams (grid), each having its own unique angle and / or origin. The depth r of the spatial sampling point (α,o,r) on the receiving beam (α,o) is defined as the distance between the beam origin and the spatial sampling point (α,o,r) (see thick arrow). Scan Geometry

[0103] Image processing systems can be programmed to scan a single line, a plane (e.g., the xz plane), two planes (e.g., the xz and yz planes), multiple faces, or a volume. Based on the beam grid used for spatial sampling, 2D scan geometry can be sectors, vectors, trapezoids, linear, steered linear, etc., and 3D scan geometry can be pyramidal, cones, truncated pyramidal, truncated cone, rectangular prisms, oblique rectangular prisms, etc. For example, if all beams originate from the center of the array, the scan geometry is sectors, pyramidal, or cones. If the beam origins are distributed across at least a portion of the aperture and all beam angles are zero, the scan geometry is linear scan geometry, i.e., rectangular prisms. If the beam origins are distributed across the entire aperture and all beam angles are the same but not zero, the scan geometry is steered linear or oblique rectangular prisms. When beam origins are distributed across the entire aperture and the beam angle changes monotonically with respect to x and y, the scan geometry is trapezoidal, frustum, or frustum of a cone. Hybrid scan geometries also exist; for example, a 3D scan geometry can be trapezoidal along one of the horizontal axes and linear along the orthogonal axes.

[0092]

[0104] Figures 8A and 8B show exemplary rectangular beam grids for sampling a truncated pyramid according to several embodiments. Here, a 33 × 19 beam grid (N x,tx =33,N y,tx=19) The total of 627 transmission beams above are uniformly distributed in terms of angle and origin over an independently programmable angular and origin region that is offset from the center to indicate the programmability of any volume.

[0093]

[0105] In this example, the transmission beam angles α x,tx and α y,tx start at one of the corners of a rectangular grid (start α x,tx , start α y,tx ) and increase uniformly with beam spacing dα x,tx and dα y,tx . Together with the number of transmission beams in x and y, which are 33 and 19 in this example, these parameters define the angular range of the 3D FOV. The large square frame indicates the limits of the array's steerability (maximum angular region), which is a function of the image processing center frequency, the element spacing of the array, and the effective element width.

[0094]

[0106] FIG. 8A also shows a small rectangular grid 802 of the angles of a parallel reception beam group of reception beams formed in parallel by a reception beam former according to each transmission beam. Here, a total of 21 parallel reception beams on a 7×3 beam grid (N x,rx = 7, N y,rx = 3) are centered on the angle of each transmission beam. For simplicity, only the parallel reception beam angle grid for one of the transmission beams is shown. In this example, the parallel reception beam angles α x,rx and α y,rx start at (each) transmission beam angle (start α x,rx , start α y,rx ) and increase uniformly with beam spacing dα x,rx and dα y,rx .

[0095]

[0107] FIG. 8B also shows an example of a beam origin grid of the same 33×19 transmission beams and 7×3 parallel reception beams. The origins of the transmission and parallel reception beams are uniformly arranged in x and y, and the spacing between the beams is do x,tx , do y,tx , dox,rx ,do y,rx The region of the transmission beam origin is one of the corners of the rectangular grid (start o x,tx ,start o y,tx ) is defined by the number of transmit beams in x and y, which in this example are 33 and 19. The region of the parallel receive beam for each transmit beam is (start o x,rx ,start o y,rx ) is defined by the number of parallel received beams in x and y, which in this example are 7 and 3. The larger rectangle 804 represents the maximum area of ​​the beam origin. Its size is the same as that of the acoustic array.

[0096]

[0108] In some examples, the angle / origin of the receiving beam may or may not coincide with either the angle / origin of the transmitting beam. The angle / origin grid may also be unevenly distributed. The grid angle and origin of the receiving beam can be defined not only relative to the angle / origin of the transmitting beam, but also in absolute terms. All angle parameters here are in degrees, and all origin parameters are in millimeters.

[0097]

[0109] In some examples, the aforementioned wide-ranging scan geometries can be defined by reducing the 2D angles and / or origin grid to a 1D grid or a single point, and / or by moving the angles or origin region. For example, for sector, pyramidal, or conical scan geometries, all beam origins are reduced to a single point (x,y)=(0,0) at the center of the array. For linear or rectangular prism scan geometries, all beam angles are reduced to a single point (α x ,α y It is reduced to (0,0). Scan design

[0110] Figure 9 shows exemplary scan designs in several embodiments. As shown with reference to Figure 9, the scan design 900 is a serialized set of scan sequence instructions interspersed with timing and image processing parameters that are updated between instructions that can be read and interpreted by a central controller. The scan sequence instructions are parameter update, scan loop, y loop, x loop, event loop, and event. Of these, only the parameter update and event are fundamental because all scan designs can be constructed using only sequences of these two instructions. However, such a flattened scan design consumes a lot of memory and is difficult to read, understand, and debug. The four loop instructions simplify and shorten the scan design while also providing complete flexibility.

[0098]

[0111] In some embodiments, each scan design instruction can correspond to a given central controller state.

[0112] A scan design can be initiated with a parameter update instruction that initializes some or all registers before the outermost loop, the scan loop, begins. The scan design may use additional parameter update instructions before other instructions such as the y-loop, x-loop, event loop, or event. Upon reading this instruction, the central controller enters a parameter update state. In this state, the central controller retrieves the parameters listed between the parameter update instruction and the next instruction in the scan design and updates the values ​​of the respective registers within the ASIC. The scan design may update a single parameter, multiple parameters, or all parameters in this state. Once the register updates are complete, the central controller reads the next instruction in the scan design.

[0099]

[0113] The scan loop is the outermost loop of the scan sequence. For 2D and 3D image processing, the scan is a 2D frame or a 3D volume, respectively. The scan can be single-mode or a mixed mode, such as B-mode and color Doppler. When the central controller reads a scan loop command, it enters the scan loop state and either starts the scan or waits until it receives an external scan start signal before starting the scan. The central controller repeats the scan (frames, volumes) indefinitely at a rate determined by the scan loop repetition interval (the reciprocal of the frame rate or volume rate), or for a finite number of times determined by the scan count, or until an external scan end signal is received. The scan loop repetition interval and scan count are input parameters that must be updated before the scan loop command is issued. The scan start and scan end signals are initiated by an external processor upon user request. The external processor can also pause and resume the scan loop using scan pause and scan resume signals.

[0100]

[0114] The y-loop and x-loop are typically the slow (outer) and fast (inner) loops that control the raster scan of the lateral field of view. The parameters for these loops include the parameters of the transmit scan geometry and the loop repetition interval. Specifically, the y-loop parameters are N y,tx ,start α y,tx ,dα y,tx ,start o y,tx ,do y,tx , and y is the loop iteration interval, and x is the loop parameter, N x,tx ,start α x,tx ,dα x,tx ,start o x,tx ,do x,tx , and x-loop repetition interval. In some examples, for a 2D image of the azimuthal plane (xz plane), the y-loop parameters set the angle, origin and repetition interval of a single y-plane, and the x-loop sets the transmit beam, given the inter-beam spacing N. x,txSweep several times from the starting angle and origin. The order of the x-loop and y-loop can be swapped to make the y-loop a fast (inner) loop.

[0101]

[0115] Before the inner loop, the parallel beam grid parameters also need to be updated. These are N x,rx ,N y,rx ,start α x,rx , start α y,rx ,dα x,rx ,dα y,rx ,start o x,rx ,start o y,rx , do x,rx and do y,rx Includes.

[0102]

[0116] The event loop is reserved for the temporal sampling of objects for motion / flow detection. Between events, the event loop initiates a repeating set of events without updating any parameters. Before the event loop, two event loop parameters, namely the event count and the event loop repeat interval, must be updated. In some cases, the event loop can interleave with the spatial loop (x-loop or y-loop) to which it belongs, for example, for block interleaved color Doppler with long event repeat intervals.

[0103]

[0117] The central controller enters event execution mode upon reading an event command in the scan design. Before the event, the event parameters, transmit beamformer parameters, and receive beamformer parameters must be set using parameter update commands and parameter values. Event parameters may include the event type (e.g., pulsed echo, pulse only, echo only) and event duration. Transmit beamformer parameters may include the transmit f-number, depth of focus, and transmit pulse parameters. Receive beamformer parameters may include the receive analog front-end parameters, receive f-number, demodulation frequency, baseband filter parameters, etc.

[0104]

[0118] In some scan designs, certain states may be repeated multiple times. For example, within an x-loop, there may be two events, one for a shallow transmit focus and another for a deep transmit focus. Within a y-loop, there may be two consecutive x-loops, one for B-mode and another for a frame-interleaved mixed-mode flow mode (see example below). In some other scan designs, certain states may not be used. For example, in a B-mode-only scan design, there may be no event loop.

[0105]

[0119] In typical mixed-mode scan designs, completely reprogramming the beamformer parameters before all common x and y events may require less than 1k bits.

[0106]

[0120] An example of a mixed-mode scan design is shown below. The central controller instruction (text with a colored background) defines the scan sequence based on nested loops of events in space (x and y) and time, with scattered parameters that are updated before each loop or event.

[0107]

[0121] In this example, there are two common y-scans, one for B-mode and one for flow. For the first common scan (B-mode), there are two common x-events, one for shallow focus and one for deep focus. In this example, after initializing all parameters, all x-loop parameters and parallel beam grid parameters are updated before each common y-event, and all Tx and Rx beamformer parameters are updated before each common x-event. However, it should be noted that in many situations, only a subset of these parameters will need to be updated between common y-events and common x-events. Therefore, the scan design can be shorter than the example shown here. Examples of subjective technologies as terms

[0122] Various examples of aspects of this disclosure are described for convenience as numbered sections (1, 2, 3, etc.). These are provided as examples and do not limit the subject art. The following figures and reference number identifications are provided for illustrative purposes only and the sections are not limited by these identifications.

[0108]

[0123] Article 1. An image processing system integrated on a chip for autonomous scanning, comprising: an on-chip input memory configured to store scan sequence instructions and parameters; an on-chip processor configured to read scan sequence instructions and parameters from the input memory; and an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters.

[0109]

[0124] Paragraph 2. The image processing system of Paragraph 1, wherein the image processing system is coupled to an ultrasonic transducer.

[0125] Article 3. An image processing system of any of the preceding articles, wherein the chip is an application-specific integrated circuit (ASIC).

[0110]

[0126] Section 4. An image processing system of any of the preceding sections, wherein the processor is configured to perform a scan autonomously, and the scan includes a sequence of events that are repeated periodically.

[0111]

[0127] Section 5. The image processing system of Section 4, wherein the sequence of events includes individual events, a temporal loop of events, and a spatial loop of events in x and y, and each event and each loop of events from the innermost event loop, x loop, and y loop to the outermost scan loop is timed.

[0112]

[0128] Clause 6. An image processing system according to any of Clauses 2 to 5, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

[0129] Article 7. An image processing system according to any of Articles 2 to 6, wherein the image processing system and the ultrasonic transducer are integrated.

[0113]

[0130] Article 8. An image processing system of any of the preceding articles, wherein autonomous scanning includes beamforming processed by a beamformer.

[0131] Section 9. An image processing system of any of the preceding sections, wherein the processor is a central controller dedicated to ultrasound.

[0114]

[0132] Clause 10. The image processing system of Clause 9, wherein a central controller dedicated to ultrasound is configured to generate a scan sequence based on scan sequence commands and parameters.

[0115]

[0133] Clause 11. The image processing system of Clause 9, wherein a central controller dedicated to ultrasound is configured to execute each event of the transducer in a scan sequence based on scan sequence commands and parameters.

[0116]

[0134] Paragraph 12. The image processing system of Paragraph 11, wherein the events are transmit and receive events, transmit-only events, or receive-only events.

[0135] Paragraph 13. An image processing system of any of the preceding paragraphs, wherein scan sequence instructions and parameters are provided by an external process outside the chip.

[0117]

[0136] Paragraph 14. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters include timing for each event in the scan sequence.

[0118]

[0137] Paragraph 15. An image processing system of any of the preceding paragraphs, wherein the scan sequence command and parameters include image processing parameters for each event in the scan sequence.

[0119]

[0138] Paragraph 16. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters are included in multiple scan designs.

[0139] Clause 17. The image processing system described in Clause 16, wherein each of the multiple scan designs is customized for different image processing modes, functions, or clinical applications, which can be selected by the user.

[0120]

[0140] Paragraph 18. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters include programmable nested loops.

[0141] Clause 19. The image processing system of Clause 18, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

[0121]

[0142] Clause 20. The image processing system of Clause 19, wherein, prior to the transmission and / or reception events, image processing parameters and timing parameters are updated at that point in the scan sequence.

[0122]

[0143] Clause 21. The image processing system of Clause 20, wherein the updated image processing parameters and timing parameters are provided from an external user device.

[0144] Paragraph 22. The image processing system of Paragraph 20, wherein the image processing parameters are optimized according to the input memory.

[0123]

[0145] Clause 23. An image processing system of any of Clauses 2 to 22, wherein the scan sequence instructions and parameters include the spatial and temporal dimensions of the transducer's transmitted and / or received events.

[0124]

[0146] Paragraph 24. An image processing system of any of the preceding paragraphs, wherein the scan sequence commands and parameters are for B-mode.

[0147] Paragraph 25. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters are for mixed mode.

[0125]

[0148] Paragraph 26. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters include scan geometry.

[0149] Clause 27. The image processing system of Clause 26, wherein the scan geometry is for processing images of a plane, two planes, or multiple planes.

[0126]

[0150] Clause 28. The image processing system of Clause 26, wherein the scan geometry is sector, vector, trapezoid, linear, or steering linear.

[0151] Clause 29. The image processing system of Clause 26, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

[0127]

[0152] Clause 30. The image processing system of Clause 26, wherein the scan geometry is a pyramidal

[0153] Paragraph 31. An image processing system of any of the preceding paragraphs, wherein the scan sequence instructions and parameters include instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

[0128]

[0154] Paragraph 32. An image processing system according to any of the preceding paragraphs, further comprising a processor and a detector coupled to a beamformer.

[0155] Clause 33. The image processing system of Clause 32, further comprising an output memory coupled to a detector and a processor.

[0129]

[0156] Clause 34. The image processing system of Clause 33, further comprising an output memory, an input memory, a processor, and a transceiver coupled to a beamformer.

[0157] Paragraph 35. The image processing system of Paragraph 34, wherein the transceiver is coupled to an external computing device.

[0130]

[0158] Paragraph 36. An image processing system according to any of paragraphs 2 through 35, wherein the number of transducers is between 500 and 5000.

[0159] Paragraph 37. An image processing system according to any of paragraphs 2 through 36, wherein the number of transducers is between 100 and 9000.

[0131]

[0160] Item 38. An image processing system according to any of items 2 through 37, wherein the number of transducers is 2k, and k is a non-negative integer.

[0161] Paragraph 39. An image processing system of any of the preceding paragraphs, wherein the processor is configured to execute a scan design, including scan sequence instructions and parameters, without any prior knowledge of the scan use case.

[0132]

[0162] Clause 40. An integrated image processing system for autonomous scanning, comprising an on-chip input memory configured to store scan design data, and an on-chip controller configured to read the scan design data from the input memory and to program and time the beamforming of a transducer according to the scan design data.

[0133]

[0163] Clause 41. An on-chip ultrasonic imaging system comprising an on-chip controller configured to receive scan design data and to program and time beamforming according to the scan design data.

[0134]

[0164] Clause 42. The image processing system of Clause 41, further comprising an on-chip input memory configured to store scan design data.

[0165] Paragraph 43. An image processing system according to any of paragraphs 40 to 42, wherein the scan design data includes scan sequence instructions and parameters.

[0135]

[0166] Paragraph 44. An image processing system of Paragraph 43, further comprising an on-chip beamformer configured to be programmed and timed by a controller to perform beamforming according to scan sequence instructions and parameters.

[0136]

[0167] Paragraph 45. An image processing system according to any of paragraphs 40 to 44, wherein the image processing system is coupled to an ultrasonic transducer.

[0168] Paragraph 46. An on-chip ultrasonic imaging system, which is an image processing system under any of paragraphs 40 to 45, is an application-specific integrated circuit (ASIC).

[0137]

[0169] Paragraph 47. The image processing system described in Paragraph 45, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

[0170] Paragraph 48. The image processing system of Paragraph 45, wherein the image processing system and the ultrasonic transducer are integrated.

[0138]

[0171] Paragraph 49. An image processing system according to any of paragraphs 40-48, wherein beamforming is included in an autonomous scanning process.

[0172] Paragraph 50. An image processing system according to any of paragraphs 40-49, wherein the controller is a central controller dedicated to ultrasound.

[0139]

[0173] Paragraph 51. The image processing system of Paragraph 50, wherein a central controller dedicated to ultrasound is configured to generate a scan sequence based on scan design data.

[0174] Paragraph 52. The image processing system of Paragraph 50, wherein a central controller dedicated to ultrasound is configured to execute each event of the transducer in the scan sequence based on scan design data.

[0140]

[0175] Paragraph 53. The image processing system of Paragraph 52, wherein the events are transmit and receive events, transmit-only events, or receive-only events.

[0176] Paragraph 54. An image processing system according to any of the paragraphs 40 to 53, wherein the scan design data is provided by an external process outside the chip.

[0141]

[0177] Paragraph 55. An image processing system according to any of the paragraphs 40 to 54, wherein the scan design data includes timing for each event in the scan sequence.

[0178] Paragraph 56. An image processing system according to any of the paragraphs 40 to 55, wherein the scan design data includes image processing parameters for each event in the scan sequence.

[0142]

[0179] Paragraph 57. An image processing system according to any of paragraphs 40 to 56, wherein the scan design data includes a programmable nested loop.

[0180] Paragraph 58. An image processing system according to Paragraph 57, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

[0143]

[0181] Paragraph 59. The image processing system of Paragraph 58, wherein image processing parameters and timing parameters are updated at that point in the scan sequence prior to the transmission and / or reception events.

[0144]

[0182] Paragraph 60. The image processing system of Paragraph 59, wherein the updated image processing parameters and timing parameters are provided from an external user device.

[0183] Paragraph 61. The image processing system of Paragraph 59, wherein the image processing parameters are optimized according to an input memory integrated within an on-chip ultrasonic image processing system.

[0145]

[0184] Paragraph 62. An image processing system according to any of the paragraphs 40 to 60, wherein the scan design data includes the spatial and temporal dimensions of the transducer's transmitted and / or received events.

[0146]

[0185] Paragraph 63. An image processing system according to any of paragraphs 40 to 62, wherein the scan design data is for B-mode.

[0186] Paragraph 64. An image processing system according to any of paragraphs 40-63, wherein the scan design data is for mixed modes.

[0147]

[0187] Paragraph 65. An image processing system according to any of paragraphs 40 to 64, wherein the scan design data includes scan geometry.

[0188] Paragraph 66. The image processing system described in Paragraph 65, wherein the scan geometry is for processing images of a plane, two planes, or multiple planes.

[0148]

[0189] Paragraph 67. The image processing system of Paragraph 65, wherein the scan geometry is sector, vector, trapezoid, linear, or steering linear.

[0190] Paragraph 68. The image processing system described in Paragraph 65, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

[0149]

[0191] Paragraph 69. The image processing system of Paragraph 65, wherein the scan geometry is a pyramidal

[0192] Paragraph 70. An image processing system according to any of paragraphs 40 to 69, wherein the scan design data includes instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

[0150]

[0193] Clause 71. An image processing system according to any of Clauses 40 to 70, further comprising a controller and a detector coupled to a beamformer.

[0194] Clause 72. The image processing system of Clause 71, further comprising an output memory coupled to a detector and a controller.

[0151]

[0195] Paragraph 73. The image processing system of Paragraph 72 further comprises an output memory, an input memory, a controller, and a transceiver coupled to a beamformer, wherein the input memory is configured to store scan design data.

[0152]

[0196] Paragraph 74. The image processing system of Paragraph 73, wherein the transceiver is coupled to an external computing device.

[0197] Paragraph 75. An image processing system according to any of paragraphs 40 to 74, wherein the number of transducers is between 500 and 5000.

[0153]

[0198] Paragraph 76. An image processing system according to any of paragraphs 40 to 75, wherein the number of transducers is between 100 and 9000.

[0199] Item 77. An image processing system according to any of items 40-76, wherein the number of transducers is 2k, and k is a non-negative integer.

[0154]

[0200] Paragraph 78. An image processing system according to any of paragraphs 40-77, wherein the controller is configured to perform scan design based on scan design data without any knowledge of the scan use case.

[0155]

[0201] Paragraph 79. A method for autonomous scanning, comprising an image processing system integrated on an application-specific integrated circuit (ASIC) chip having input memory and a processor, the method comprising: storing scan sequence instructions and parameters in input memory; the processor reading scan sequence instructions and parameters from input memory; and the processor programming and timing beamforming according to the scan sequence instructions and parameters.

[0156]

[0202] Paragraph 80. The method of paragraph 79, wherein the image processing system is coupled to an ultrasonic transducer.

[0203] Paragraph 81. The method of paragraph 80, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

[0157]

[0204] Paragraph 82. The method of paragraph 80, wherein the image processing system and the ultrasonic transducer are integrated.

[0205] Paragraph 83. Any method described in paragraphs 79 to 82, wherein the autonomous scan includes beamforming processed by a beamformer.

[0158]

[0206] Paragraph 84. Any method according to paragraphs 79 to 83, wherein the processor is a central controller dedicated to ultrasound.

[0207] Paragraph 85. The method of Paragraph 84, further comprising generating a scan sequence based on scan sequence instructions and parameters.

[0159]

[0208] Paragraph 86. The method of Paragraph 84, further comprising performing each event of a transducer in a scan sequence based on scan sequence instructions and parameters.

[0160]

[0209] Paragraph 87. The method of paragraph 86, wherein the event is a transmit and receive event, a transmit-only event, or a receive-only event.

[0210] Paragraph 88. Any method described in paragraphs 79 to 87, wherein the scan sequence instructions and parameters are provided by an external process outside the chip.

[0161]

[0211] Paragraph 89. Any method of paragraphs 79 to 88, wherein the scan sequence instruction and parameters include timing for each event in the scan sequence.

[0162]

[0212] Paragraph 90. Any method of paragraphs 79 to 89, wherein the scan sequence command and parameters include image processing parameters for each event in the scan sequence.

[0163]

[0213] Paragraph 91. Any method of paragraphs 79-90, wherein the scan sequence instruction and parameters include a programmable nested loop.

[0214] Paragraph 92. The method of Paragraph 91, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in the scan sequence.

[0164]

[0215] Paragraph 93. The method of Paragraph 92, wherein, prior to the transmission and / or reception events, the image processing parameters and timing parameters are updated at that point in the scan sequence.

[0165]

[0216] Paragraph 94. The method of Paragraph 93, wherein the updated image processing parameters and timing parameters are provided from an external user device.

[0217] Paragraph 95. The method of Paragraph 93, wherein the image processing parameters are optimized according to the input memory.

[0166]

[0218] Paragraph 96. Any method of paragraphs 80 to 95, wherein the scan sequence instruction and parameters include the spatial and temporal dimensions of the transducer's transmitted and / or received events.

[0167]

[0219] Paragraph 97. Any method described in paragraphs 79 to 96, wherein the scan sequence instructions and parameters are for B-mode.

[0220] Paragraph 98. Any method described in paragraphs 79 to 97, wherein the scan sequence instructions and parameters are for mixed mode.

[0168]

[0221] Paragraph 99. Any method described in paragraphs 79 to 98, wherein the scan sequence instruction and parameters include scan geometry.

[0222] Paragraph 100. The method of paragraph 99, wherein the scan geometry is for the processing of a planar, two-planar, or multi-planar image.

[0169]

[0223] Paragraph 101. The method of paragraph 99, wherein the scan geometry is sectoral, trapezoidal, linear, or steering-linear.

[0224] Paragraph 102. The method of paragraph 99, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

[0170]

[0225] Paragraph 103. The method of paragraph 99, wherein the scan geometry is a pyramid, cone, truncated pyramid, truncated cone, cuboid, or oblique cuboid.

[0226] Paragraph 104. Any method described in paragraphs 79 to 103, wherein the scan sequence instructions and parameters include instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

[0171]

[0227] Paragraph 105. A method according to any of paragraphs 79 to 104, wherein the image processing system further comprises a detector and a beamformer, the detector being coupled to a processor and a beamformer.

[0172]

[0228] Paragraph 106. The method of paragraph 105, wherein the image processing system further comprises an output memory coupled to a detector and a processor.

[0229] Paragraph 107. The method of paragraph 106, wherein the image processing system further comprises an output memory, an input memory, a processor, and a transceiver coupled to a beamformer.

[0173]

[0230] Paragraph 108. The method of paragraph 107, wherein the transceiver is coupled to an external computing device.

[0231] Paragraph 109. Any method according to paragraphs 80 to 108, wherein the number of transducers is between 100 and 9000.

[0174]

[0232] Paragraph 110. Any method according to paragraphs 80 to 109, wherein the number of transducers is between 500 and 5000.

[0233] Item 111. One of the methods described in items 80 through 110, where the number of transducers is 2k, and k is a non-negative integer.

[0175]

[0234] Paragraph 112. Any method described in paragraphs 79-111, further comprising having the processor perform a scan design, including scan sequence instructions and parameters, without any prior knowledge of the scan use case.

[0176]

[0235] Paragraph 113. Non-transient computer-readable storage comprising any of the steps disclosed in any of the preceding paragraphs.

[0236] Paragraph 114. A method comprising any of the steps disclosed in any of the preceding paragraphs.

[0177]

[0237] Paragraph 115. A system comprising one or more devices configured to perform any of the methods disclosed in any of the preceding paragraphs.

[0238] Paragraph 116. An image processing system according to any of paragraphs 1 to 78, wherein the chip comprises analog circuitry for transmitting and receiving ultrasonic signals.

[0178]

[0239] Paragraph 117. An image processing system according to any of paragraphs 1-40 and 42, wherein the on-chip input memory is factory-programmed non-volatile memory.

[0240] Paragraph 118. An image processing system according to any of paragraphs 1-39 and 43-44, wherein scan sequence instructions and parameters are stored in a factory-programmed non-volatile input memory.

[0179]

[0241] Paragraph 119. A method according to any of paragraphs 79 to 112, wherein the chip comprises analog circuitry for transmitting and receiving ultrasonic signals.

[0242] Paragraph 120. Any method described in paragraphs 79 to 112, wherein the chip's input memory is factory-programmed non-volatile memory.

[0180]

[0243] Paragraph 121. Any method described in paragraphs 79 to 112, wherein the scan sequence instructions and parameters are stored in factory-programmed non-volatile input memory.

[0244] In some embodiments, any of the claims herein may depend on any one of the independent claims or any one of the dependent claims. In one embodiment, any of the claims (e.g., a dependent or independent claim) may be combined with one or more other claims (e.g., dependent or independent claims). In one embodiment, a claim may include some or all of the terms (e.g., steps, actions, means, or components) contained in a claim, sentence, phrase, or paragraph. In one embodiment, a claim may include some or all of the terms contained in one or more claims, sentences, phrases, or paragraphs. In one embodiment, some of the terms in each of the claims, sentences, phrases, or paragraphs may be deleted. In one embodiment, additional terms or elements may be added to a claim, sentence, phrase, or paragraph. In one embodiment, the subject art may be carried out without utilizing any of the components, elements, functions, or actions described herein. In one embodiment, the subject art may be carried out utilizing additional components, elements, functions, or actions.

[0181]

[0245] As used herein, the terms “loop” or “component” refer to logic embedded in hardware or firmware, or a set of software instructions written in a programming language such as C++, which may have entry and exit points. Software loops or components may be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpretive language such as BASIC. It will be recognized that software loops or components may be callable from other loops or components, or from themselves, and / or in response to detected events or interrupts. Software instructions may be embedded in firmware such as EPROM or EEPROM. It will also be recognized that hardware components may consist of connected logic units such as gates and flip-flops, and / or programmable units such as programmable gate arrays or processors. Loops or components described herein are preferably implemented as software loops or components, but may be represented in hardware or firmware.

[0182]

[0246] It is assumed that a loop or component can be consolidated into fewer loops or components. A single loop or component can be split into multiple loops or components. The described loops or components can be implemented as hardware, software, firmware, or any combination thereof. In addition, the described loops or components can reside in different locations connected via wired or wireless networks, or the internet.

[0183]

[0247] In general, it will be recognized that a processor can include, by way of example, a computer, program logic, or other substrate configuration that operates as described herein to represent data and instructions. In other embodiments, the processor can include a controller circuit configuration, a processor circuit configuration, a processor, a general-purpose single-chip or multi-chip microprocessor, a digital signal processor, an embedded microprocessor, a microcontroller, and the like.

[0184]

[0248] Furthermore, in one embodiment, it will be recognized that program logic can be advantageously implemented as one or more components. The components can be advantageously configured to execute on one or more processors. The components include, but are not limited to, software or hardware components, modules such as software modules, object-oriented software components, class components and task components, process methods, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuit configurations, data, databases, data structures, tables, arrays, and variables.

[0185]

[0249] The foregoing description is provided to enable a person of ordinary skill in the art to make and use the various configurations described herein. The subject technology has been particularly described with reference to various figures and configurations, which are for illustrative purposes only and should not be construed as limiting the scope of the subject technology.

[0186]

[0250] There are many other ways to implement the subject technology. The various functions and elements described in this specification can be divided differently from those illustrated without departing from the scope of the subject technology. Various modifications to these configurations will be readily apparent to those skilled in the art, and the general principles defined herein can also be applied to other configurations. Therefore, without departing from the scope of the subject technology, many changes and modifications can be made to the subject technology by those skilled in the art.

[0187]

[0251] It is understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary approach. Based on design choices, it is understood that the specific order or hierarchy of steps in a process can be rearranged. Some steps can be executed simultaneously. The appended method claims present the elements of various steps in a sample order and are not intended to be limited to the specific order or hierarchy presented.

[0188]

[0252] Some of the various figures illustrate many logical stages in a particular order, but stages that are not order-dependent can be rearranged, and other stages can be combined or split. Although some rearrangements and other groupings are specifically described, others will be apparent to those skilled in the art, so the orderings and groupings presented herein are not an exhaustive list of alternatives. Further, it should be recognized that these stages can be implemented in hardware, firmware, software, or any combination thereof.

[0189]

[0253] Furthermore, while terms such as "first," "second," etc., are used herein in some cases to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without deviating from the scope of the various implementations described, a first transducer can be referred to as a second transducer, and similarly, a second transducer can be referred to as a first transducer. Both the first sensor and the second sensor are sensors, but they are not of the same type.

[0190]

[0254] To the extent that words such as “including” or “having” are used in the description or claims, such words are intended to be inclusive, just as “equipped with” is interpreted as “equipped with” when applied as a transitional term in the claims.

[0191]

[0255] As used herein, the term "possessed" indicates the existence of a specified perfect being, but also takes into account the possibility of other unspecified perfect beings. This term does not imply a specific proportion of the specified perfect beings. Variations of the term "possessed," such as "possessed," have correspondingly similar meanings.

[0192]

[0256] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any embodiment described herein as “exemplary” is not necessarily construed to be preferable or advantageous to any other embodiment.

[0193]

[0257] References to singular elements are intended to mean "one or more" and not "one and unique" unless otherwise specified. Masculine pronouns (e.g., his) include feminine and neuter pronouns (e.g., her and its), and vice versa. The phrase "several" refers to one or more. Underlined and / or italicized headings and subheadings are used for convenience only and do not limit the subject art and are not referenced in relation to the interpretation of the description of the subject art. All structural and functional equivalents of elements of the various configurations described throughout this disclosure, which are known to those skilled in the art or will become known later, are expressly incorporated herein by reference and are intended to be encompassed by the subject art. Furthermore, nothing disclosed herein is intended to be made public, whether or not such disclosure is expressly stated in the above description.

Claims

1. An image processing system integrated into a chip for autonomous scanning, An on-chip input memory configured to store scan sequence instructions and parameters, An on-chip processor configured to read the scan sequence instructions and parameters in the input memory, An on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters, An image processing system equipped with the following features.

2. The image processing system according to claim 1, wherein the image processing system is coupled to an ultrasonic transducer.

3. The image processing system according to claim 1 or 2, wherein the chip is an application-specific integrated circuit (ASIC).

4. The image processing system according to any one of claims 1 to 3, wherein the processor is configured to autonomously perform a scan, and the scan includes a sequence of events that are periodically repeated.

5. The image processing system according to claim 4, wherein the sequence of events includes individual events, a temporal loop of events, and a spatial loop of events in x and y, and each event and each loop of events from the innermost event loop, x loop, and y loop to the outermost scan loop is time-coordinated.

6. The image processing system according to claim 2, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

7. The image processing system according to claim 2, wherein the image processing system and the ultrasonic transducer are integrated.

8. The image processing system according to any one of claims 1 to 7, wherein the autonomous scan includes beamforming processed by the beamformer.

9. The image processing system according to any one of claims 1 to 8, wherein the processor is a central controller dedicated to ultrasound.

10. The image processing system according to claim 9, wherein the central controller dedicated to ultrasound is configured to generate a scan sequence based on the scan sequence command and parameters.

11. The image processing system according to claim 9, wherein the central controller dedicated to ultrasound is configured to execute each event in the scan sequence based on the scan sequence commands and parameters.

12. The image processing system according to claim 11, wherein the event is a transmission and reception event, a transmission-only event, or a reception-only event.

13. The image processing system according to any one of claims 1 to 12, wherein the scan sequence instructions and parameters are provided by an external processor outside the chip.

14. The image processing system according to any one of claims 1 to 13, wherein the scan sequence command and parameters include timing for each event in the scan sequence.

15. The image processing system according to any one of claims 1 to 14, wherein the scan sequence command and parameters include image processing parameters for each event in the scan sequence.

16. The image processing system according to any one of claims 1 to 15, wherein the scan sequence instructions and parameters are included in a plurality of scan designs.

17. The image processing system according to claim 16, wherein each of the plurality of scan designs is customized for different image processing modes, functions, or clinical applications that can be selected by the user.

18. The image processing system according to any one of claims 1 to 17, wherein the scan sequence instructions and parameters include programmable nested loops.

19. The image processing system according to claim 18, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

20. The image processing system according to claim 19, wherein image processing parameters and timing parameters are updated at that point in the scan sequence prior to the transmission and / or reception events.

21. The image processing system according to claim 20, wherein the updated image processing parameters and timing parameters are provided by an external user device.

22. The image processing system according to claim 20, wherein the image processing parameters are optimized according to the input memory.

23. The image processing system according to any one of claims 2 to 22, wherein the scan sequence command and parameters include the spatial and temporal dimensions of the transmit and / or receive events of the transducer.

24. The image processing system according to any one of claims 1 to 23, wherein the scan sequence command and parameters are for B-mode.

25. The image processing system according to any one of claims 1 to 24, wherein the scan sequence command and parameters are for mixed mode.

26. The image processing system according to any one of claims 1 to 25, wherein the scan sequence command and parameters include scan geometry.

27. The image processing system according to claim 26, wherein the scan geometry is for image processing of a plane, two planes, or multiple planes.

28. The image processing system according to claim 26, wherein the scan geometry is a sector, vector, trapezoid, linear, or steering linear.

29. The image processing system according to claim 26, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

30. The image processing system according to claim 26, wherein the scan geometry is a pyramid, a cone, a truncated pyramid, a truncated cone, a rectangular prism, or an oblique rectangular prism.

31. The image processing system according to any one of claims 1 to 30, wherein the scan sequence command and parameters include commands for sampling in a spatial domain, a temporal domain, and a parameter domain.

32. The image processing system according to any one of claims 1 to 31, further comprising a detector coupled to the processor and the beamformer.

33. The image processing system according to claim 32, further comprising an output memory coupled to the detector and the processor.

34. The image processing system according to claim 33, further comprising the output memory, the input memory, the processor, and a transceiver coupled to the beamformer.

35. The image processing system according to claim 34, wherein the transceiver is coupled to an external computing device.

36. The image processing system according to any one of claims 2 to 35, wherein the number of transducers is between 500 and 5000.

37. The image processing system according to any one of claims 2 to 36, wherein the number of transducers is between 100 and 9000.

38. The image processing system according to any one of claims 2 to 37, wherein the number of transducers is 2k, where k is a non-negative integer.

39. The image processing system according to any one of claims 1 to 38, wherein the processor is configured to execute a scan design including the scan sequence instructions and parameters without any prior knowledge of the scan use case.

40. An image processing system integrated into an application-specific integrated circuit (ASIC) coupled to an ultrasonic transducer for autonomous scanning, An on-chip input memory configured to store scan design data, An on-chip controller configured to read the scan design data in the input memory and to program and time the beamforming of the transducer according to the scan design data, An image processing system equipped with the following features.

41. An on-chip ultrasonic imaging system comprising an on-chip controller configured to receive scan design data and to program and time beamforming according to the scan design data.

42. The image processing system according to claim 41, further comprising an on-chip input memory configured to store the aforementioned scan design data.

43. The image processing system according to any one of claims 40 to 42, wherein the scan design data includes scan sequence instructions and parameters.

44. The image processing system according to claim 43, further comprising an on-chip beamformer configured to be programmed and timed by the controller to perform the beamforming according to the scan sequence instructions and parameters.

45. The image processing system according to any one of claims 40 to 44, wherein the image processing system is coupled to an ultrasonic transducer.

46. The on-chip ultrasonic image processing system is an application-specific integrated circuit (ASIC), according to any one of claims 40 to 45.

47. The image processing system according to claim 45, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

48. The image processing system according to claim 45, wherein the image processing system and the ultrasonic transducer are integrated.

49. The image processing system according to any one of claims 40 to 48, wherein the beamforming is included in an autonomous scanning process.

50. The image processing system according to any one of claims 40 to 49, wherein the controller is a central controller dedicated to ultrasound.

51. The image processing system according to claim 50, wherein the central controller dedicated to ultrasound is configured to generate a scan sequence based on the scan design data.

52. The image processing system according to claim 50, wherein the central controller dedicated to ultrasound is configured to execute each event of the transducer in the scan sequence based on the scan design data.

53. The image processing system according to claim 52, wherein the event is a transmission and reception event, a transmission-only event, or a reception-only event.

54. The image processing system according to any one of claims 40 to 53, wherein the scan design data is provided by an external process outside the chip.

55. The image processing system according to any one of claims 40 to 54, wherein the scan design data includes timing for each event in the scan sequence.

56. The image processing system according to any one of claims 40 to 55, wherein the scan design data includes image processing parameters for each event in the scan sequence.

57. The image processing system according to any one of claims 40 to 56, wherein the scan design data includes a programmable nested loop.

58. The image processing system according to claim 57, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

59. The image processing system according to claim 58, wherein image processing parameters and timing parameters are updated at that point in the scan sequence prior to the transmission and / or reception events.

60. The image processing system according to claim 59, wherein the updated image processing parameters and timing parameters are provided by an external user device.

61. The image processing system according to claim 59, wherein the image processing parameters are optimized according to an input memory integrated within the on-chip ultrasonic image processing system.

62. The image processing system according to any one of claims 40 to 60, wherein the scan design data includes the spatial and temporal dimensions of the transmit and / or receive events of the transducer.

63. The image processing system according to any one of claims 40 to 62, wherein the scan design data is for B-mode.

64. The image processing system according to any one of claims 40 to 63, wherein the scan design data is for mixed mode.

65. The image processing system according to any one of claims 40 to 64, wherein the scan design data includes scan geometry.

66. The image processing system according to claim 65, wherein the scan geometry is for image processing of a plane, two planes, or multiple planes.

67. The image processing system according to claim 65, wherein the scan geometry is a sector, vector, trapezoid, linear, or steering linear.

68. The image processing system according to claim 65, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

69. The image processing system according to claim 65, wherein the scan geometry is a pyramid, a cone, a truncated pyramid, a truncated cone, a rectangular prism, or an oblique rectangular prism.

70. The image processing system according to any one of claims 40 to 69, wherein the scan design data includes instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

71. The image processing system according to any one of claims 40 to 70, further comprising a detector coupled to the controller and the beamformer.

72. The image processing system according to claim 71, further comprising an output memory coupled to the detector and the controller.

73. The image processing system according to claim 72, further comprising a transceiver coupled to the output memory, input memory, controller and beamformer, wherein the input memory is configured to store the scan design data.

74. The image processing system according to claim 73, wherein the transceiver is coupled to an external computing device.

75. The image processing system according to any one of claims 40 to 74, wherein the number of transducers is between 500 and 5000.

76. The image processing system according to any one of claims 40 to 75, wherein the number of transducers is between 100 and 9000.

77. The image processing system according to any one of claims 40 to 76, wherein the number of transducers is 2k, where k is a non-negative integer.

78. The image processing system according to any one of claims 40 to 77, wherein the controller is configured to perform a scan design based on the scan design data without any knowledge of the scan use case.

79. The image processing system according to any one of claims 1 to 78, wherein the chip comprises an analog circuit for transmitting and receiving ultrasonic signals.

80. The image processing system according to any one of claims 1 to 44 and 42, wherein the on-chip input memory is a factory-programmed non-volatile memory.

81. The image processing system according to any one of claims 1 to 39 and 43 to 44, wherein the scan sequence instructions and parameters are stored in a factory-programmed non-volatile input memory.

82. A method for autonomous scanning, In an image processing system integrated on an application-specific integrated circuit (ASIC) chip equipped with input memory and a processor, The steps include storing scan sequence instructions and parameters in the input memory, The processor performs the steps of reading the scan sequence instruction and parameters in the input memory, The processor performs the steps of programming and timing beamforming according to the scan sequence instructions and parameters. A method that includes [a certain feature].

83. The method according to claim 82, wherein the image processing system is coupled to an ultrasonic transducer.

84. The method according to claim 83, wherein the image processing system and the ultrasonic transducer are packaged within the same ultrasonic probe.

85. The method according to claim 83, wherein the image processing system and the ultrasonic transducer are integrated.

86. The method according to any one of claims 79 to 85, wherein the autonomous scan includes beamforming processed by a beamformer.

87. The method according to any one of claims 79 to 86, wherein the processor is a central controller dedicated to ultrasound.

88. The method according to claim 87, further comprising the step of generating a scan sequence based on the scan sequence command and parameters.

89. The method according to claim 87, further comprising the step of executing each event of a transducer in a scan sequence based on the scan sequence command and parameters.

90. The method according to claim 89, wherein the event is a transmit and receive event, a transmit-only event, or a receive-only event.

91. The method according to any one of claims 79 to 90, wherein the scan sequence instructions and parameters are provided by an external process outside the chip.

92. The method according to any one of claims 79 to 91, wherein the scan sequence command and parameters include timing for each event in the scan sequence.

93. The method according to any one of claims 79 to 92, wherein the scan sequence command and parameters include image processing parameters for each event in the scan sequence.

94. The method according to any one of claims 79 to 93, wherein the scan sequence instruction and parameters include a programmable nested loop.

95. The method according to claim 94, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

96. The method according to claim 95, wherein image processing parameters and timing parameters are updated at that point in the scan sequence prior to the transmission and / or reception events.

97. The method according to claim 96, wherein the updated image processing parameters and timing parameters are provided by an external user device.

98. The method according to claim 96, wherein the image processing parameters are optimized according to the input memory.

99. The method according to any one of claims 83 to 98, wherein the scan sequence command and parameters include the spatial and temporal dimensions of the transmit and / or receive events of the transducer.

100. The method according to any one of claims 79 to 99, wherein the scan sequence command and parameters are for B-mode.

101. The method according to any one of claims 79 to 100, wherein the scan sequence command and parameters are for mixed mode.

102. The method according to any one of claims 79 to 101, wherein the scan sequence command and parameters include scan geometry.

103. The method according to claim 102, wherein the scan geometry is for image processing of a plane, two planes, or multiple planes.

104. The method according to claim 102, wherein the scan geometry is a sector, vector, trapezoid, linear, or steering linear.

105. The method according to claim 102, wherein the scanned geometry is for 3D image processing or real-time 3D image processing.

106. The method according to claim 102, wherein the scan geometry is a pyramid, a cone, a truncated pyramid, a truncated cone, a rectangular prism, or an oblique rectangular prism.

107. The method according to any one of claims 79 to 106, wherein the scan sequence command and parameters include commands for sampling in the spatial domain, the temporal domain, and the parameter domain.

108. The method according to any one of claims 79 to 107, wherein the image processing system further comprises a detector and a beamformer, the detector being coupled to the processor and the beamformer.

109. The method according to claim 108, wherein the image processing system further comprises an output memory coupled to the detector and the processor.

110. The method according to claim 109, further comprising the image processing system, the output memory, the input memory, the processor, and a transceiver coupled to the beamformer.

111. The method according to claim 110, wherein the transceiver is coupled to an external computing device.

112. The method according to any one of claims 83 to 111, wherein the number of transducers is between 500 and 5000.

113. The method according to any one of claims 83 to 112, wherein the number of transducers is between 100 and 9000.

114. The method according to any one of claims 83 to 113, wherein the number of transducers is 2k, where k is a non-negative integer.

115. The method according to any one of claims 79 to 114, comprising the step of having the processor perform a scan design including the scan sequence instructions and parameters without any prior knowledge of the use cases of the scan.

116. The method according to any one of claims 79 to 115, wherein the chip comprises an analog circuit for transmitting and receiving ultrasonic signals.

117. The method according to any one of claims 79 to 116, wherein the input memory of the chip is a factory-programmed non-volatile memory.

118. The method according to any one of claims 79 to 117, wherein the scan sequence instructions and parameters are stored in a factory-programmed non-volatile input memory.

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