Host bandwidth optimized data stream memory write

JP2026518644APending Publication Date: 2026-06-09SK HYNIX NAND PRODUCT SOLUTIONS CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
SK HYNIX NAND PRODUCT SOLUTIONS CORP
Filing Date
2024-05-01
Publication Date
2026-06-09

Smart Images

  • Figure 2026518644000001_ABST
    Figure 2026518644000001_ABST
Patent Text Reader

Abstract

A system and associated method comprising memory and processing circuitry for writing data from a data stream. The memory has a first memory portion of a first density and a second memory portion of a second density. The processing circuitry receives a write request. The processing circuitry then selects to write the data to the first memory portion based on the characteristics of the data stream, where both the first and second memory portions are available for writing, and the processing circuitry then causes the data to be written to the first memory portion. The processing circuitry may select to write the data to the first memory portion based on the size of the data stream and / or based on the bandwidth for writing the data of the data stream to memory.
Need to check novelty before this filing date? Find Prior Art