Compressible membrane for large-area gap fill

Abstract

An exemplary semiconductor processing method may include supplying a silicon-containing precursor to a processing area in a semiconductor processing chamber. A substrate may be placed in the semiconductor processing chamber. The method may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of about -200 MPa or higher. The method may include annealing the substrate at a temperature of about 700°C or higher.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit and priority of U.S. Patent Application No. 18 / 192,549, filed on March 29, 2023, entitled "COMPRESSIVE FILMS FOR LARGE AREA GAPFILL", which is incorporated herein by reference in its entirety.

[0002] Technical Field The present technology relates to methods and components for semiconductor processing. More particularly, the present technology relates to systems and methods for depositing silicon - containing materials with increased compressive stress.

Background Art

[0003] Integrated circuits are enabled by a process of manufacturing complexly patterned material layers on a substrate surface. To manufacture patterned materials on a substrate, controlled methods for depositing and removing materials are required. As device sizes continue to shrink, features within an integrated circuit become smaller and the aspect ratio of the structures can increase, making it difficult to maintain the dimensions of these structures during processing operations. Depending on the process, films that may not withstand further processing can be generated. As device sizes increase, the development of materials that can withstand further processing after deposition can become more difficult.

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. The present technology addresses these and other needs.

Summary of the Invention

[0005] An exemplary semiconductor processing method may include supplying a silicon-containing precursor to a processing area in a semiconductor processing chamber. A substrate may be placed in the semiconductor processing chamber. The method may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of about -200 MPa or higher. The method may include annealing the substrate at a temperature of about 700°C or higher.

[0006] In some embodiments, the silicon-containing precursor may be or may include silane (SiH4), disilane (Si2H6), or trisilane (Si3H8). The temperature in the semiconductor processing chamber can be maintained at about 600°C or less while forming the silicon-containing material. The pressure in the semiconductor processing chamber can be maintained at about 350 Torr or less. The method may include supplying an oxygen-containing precursor together with the silicon-containing precursor. The semiconductor processing chamber can be kept plasma-free while forming the silicon-containing material. After annealing the silicon-containing material, the silicon-containing material may be characterized by a shrinkage rate of about 5% or less. After forming the silicon-containing material, the method may include supplying an inert precursor to the processing area of ​​the semiconductor processing chamber, forming a plasma emission of the inert precursor, and contacting the silicon-containing material with the plasma emission of the inert precursor. The inert precursor may be or may include argon. The method may include supplying an oxygen-containing precursor together with the inert precursor.

[0007] Some embodiments of this technology may include a semiconductor processing method. The method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed in the semiconductor processing chamber. The silicon-containing precursor may be disilane (Si2H6) or contain thereof. The method may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of about -200 MPa or higher. The method may include annealing the substrate at a temperature of about 700°C or higher. The silicon-containing material may be characterized by a shrinkage rate of about 5% or less.

[0008] In some embodiments, the substrate may include one or more features. The silicon-containing material may be characterized by a dielectric breakdown of about 5 MV / cm or more. Annealing the substrate may involve bringing the substrate into contact with a nitrogen-containing precursor. The method may include performing a plasma treatment with an inert precursor after forming the silicon-containing material. The plasma treatment can be performed at a lower pressure than that used for forming the silicon-containing material. The inert precursor may be or may contain argon.

[0009] Some embodiments of this technology may include a semiconductor processing method. The method may include supplying a silicon-containing precursor and an oxygen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed in the semiconductor processing chamber. The method may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of about -200 MPa or higher. The method may include supplying an inert precursor to the processing area of ​​the semiconductor processing chamber. The method may include forming a plasma emission of the inert precursor. The method may include bringing the silicon-containing material into contact with the plasma emission of the inert precursor. The method may include annealing the substrate.

[0010] In some embodiments, the silicon-containing material may be characterized by a shrinkage rate of about 5% or less. The thickness of the silicon-containing material may be about 30 Å or less.

[0011] Such technologies can offer many advantages compared to conventional systems and techniques. For example, embodiments of this technology can deposit silicon-containing films characterized by high compressive stress. Furthermore, this technology can produce silicon-containing films that may feature reduced shrinkage after, for example, annealing. These properties can provide films for gap-fill applications, as well as any other applications where deposited films with high compressive stress and / or reduced shrinkage may be beneficial. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying drawings.

[0012] Further understanding of the nature and advantages of the disclosed technology can be gained by referring to the remainder of the specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] Schematic cross-sectional view of an exemplary plasma system according to several embodiments of this technology. [Figure 2] Figures illustrating the operation of a semiconductor processing method according to several embodiments of this technology. [Figure 3A-D] A diagram showing an exemplary schematic cross-sectional structure, which includes material layers and is manufactured according to several embodiments of the present technology. [Modes for carrying out the invention]

[0014] Several diagrams are included as schematic representations. These diagrams are for illustrative purposes only, and scale should not be considered unless explicitly stated otherwise. Furthermore, the diagrams are provided as schematic representations to aid understanding and may not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0015] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016] As device size decreases, the thickness and size of many material layers are reduced, enabling device scaling up. The overall feature size of the semiconductor structure decreases, and the aspect ratio of features may increase. If the aspect ratio of features increases, the film produced in the deposition process may not be able to withstand subsequent processing operations such as annealing.

[0017] Conventional techniques related to 3D NAND have made it difficult to manufacture compressible films, such as silicon-containing films, for large-area gap-fill applications. Depositing silicon-containing materials onto a 3D NAND structure can result in tensile films that are prone to cracking during subsequent processes, including annealing. Conventional precursors used in large-area gap-fill applications for 3D NAND include tetraethyl orthosilicate (TEOS) and ozone (O3), which can inherently form tensile films. These tensile silicon-containing films can crack and / or shrink during annealing operations, such as the annealing process that forms memory cells in the 3D NAND structure. Therefore, many conventional techniques have limitations in their ability to prevent structural defects in the final device.

[0018] This technology overcomes these problems by forming a film using specific precursors selected to increase the compressive stress of the film. By utilizing specific precursors, compressible films can be formed, as opposed to tensile films. Furthermore, this technology can perform film processing to further improve the properties of the film. This processing may be a plasma strengthening treatment that reorganizes the film bonds. By reorganizing the film bonds, the compressive stress can be further increased. Film processing can also result in a reduction of the film's shrinkage rate during further processing, such as annealing for forming 3D NAND memory cells. By depositing silicon-containing materials with increased compressive stress and / or reduced shrinkage rate, this technology can prevent problems in subsequent integration processes and / or defects in the final device, such as cracks in the silicon-containing material.

[0019] The remaining disclosure will, as is customary, identify specific deposition processes utilizing the disclosed technology and describe one type of semiconductor processing chamber, although it will be readily apparent that the processes described can be carried out in any number of semiconductor processing chambers. Therefore, the technology should not be considered limited to use in only these specific deposition processes or chambers. Before describing a semiconductor processing method using the technology, this disclosure will discuss one possible chamber that can be used to carry out the process according to embodiments of the technology.

[0020] Figure 1 shows a cross-sectional view of an exemplary semiconductor processing chamber 100 according to several embodiments of the present technology. The figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or a system that can be specifically configured to perform one or more operations according to embodiments of the present technology. Further details of the chamber 100 or the method being carried out may be described further below. The chamber 100 can be used to form a film layer according to several embodiments of the present technology, but it should be understood that the method can be similarly carried out in any chamber capable of film formation. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and surrounding the substrate support 104 in a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126 that can be conventionally sealed for processing using a slit valve or door. The substrate 103 can be seated on the surface 105 of the substrate support 104 during processing. The substrate support 104 may be rotatable along an axis 147 on which the shaft 144 of the substrate support 104 may be located, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0021] The plasma profile modulator 111 is positioned within the semiconductor processing chamber 100 and can control the plasma distribution across the entire substrate 103 placed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that can be positioned adjacent to the chamber body 102, and the chamber body 102 may be separated from the other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member or may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the semiconductor processing chamber 100 surrounding the processing volume 120 or may be discontinuous at positions selected as needed. The first electrode 108 may also be a porous electrode such as a porous ring or mesh electrode, or may be a plate electrode such as in a secondary gas distributor.

[0022] One or more isolators 110a, 110b, which may be ceramic or metal oxides, such as dielectric materials such as aluminum oxide and / or aluminum nitride, are in contact with the first electrode 108 and can electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define openings 118 for distributing the processing precursor into the processing volume 120. The gas distributor 112 can be connected to a first power source 142, such as an RF generator, RF power supply, DC power supply, pulsed DC power supply, pulsed RF power supply, or any other power supply that can be connected to the semiconductor processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0023] The gas distributor 112 can be either a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the faceplate of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered, for example, by a first power source 142 as shown in FIG. 1, or, in some embodiments, the gas distributor 112 can be coupled to ground.

[0024] The first electrode 108 can be coupled to a first tuning circuit 128 that can control the ground path of the semiconductor processing chamber 100. The first tuning circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit element. The first tuning circuit 128 can be or include one or more inductors 132. The first tuning circuit 128 can be any circuit that enables a variable or controllable impedance under plasma conditions present within the processing volume 120 during processing. In some of the illustrated embodiments, the first tuning circuit 128 can include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg can include a first inductor 132A. The second circuit leg can include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node that connects both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage sensor or a current sensor and can be coupled to the first electronic controller 134, thereby providing a degree of closed-loop control of the plasma state within the processing volume 120.

[0025] The second electrode 122 can be connected to the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or connected to the surface 105 of the substrate support 104. The second electrode 122 can be a plate, a porous plate, a mesh, a wire screen, or any other random distribution of conductive elements. The second electrode 122 can be a tuning electrode and can be connected to the second tuning circuit 136 by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms, disposed on the shaft 144 of the substrate support 104). The second tuning circuit 136 can include a second electronic sensor 138 and a second electronic controller 140 that can be a second variable capacitor. The second electronic sensor 138 can be a voltage sensor or a current sensor and can be connected to the second electronic controller 140 to provide further control over the plasma state within the processing volume 120.

[0026] A third electrode 124, which can be a bias electrode and / or an electrostatic chuck electrode, can be connected to the substrate support 104. The third electrode can be connected to a second power source 150 through a filter 148, which can be an impedance matching circuit. The second power source 150 can be DC power, pulsed DC power, RF bias power, pulsed RF power, or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 can be RF bias power. The substrate support 104 can also include one or more heating elements configured to heat the substrate to a processing temperature that can be between about 25°C and about 800°C or higher.

[0027] The lid assembly 106 and substrate support 104 of Figure 1 can be used with any processing chamber for plasma processing or heat processing. During operation, the semiconductor processing chamber 100 can provide real-time control of the plasma state within the processing volume 120. The substrate 103 can be placed on the substrate support 104, and the processing gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the semiconductor processing chamber 100 through the outlet 152. Power can be coupled with the gas distributor 112 to establish plasma within the processing volume 120. In some embodiments, the substrate can be subjected to electrical bias using a third electrode 124.

[0028] When energy is supplied to the plasma in the processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Next, electronic controllers 134 and 140 can be used to adjust the flow characteristics of the ground path represented by two tuning circuits 128 and 136. Setpoints can be supplied to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and independent control of the uniformity of plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, the electronic sensors can adjust the variable capacitors to maximize the deposition rate and independently minimize thickness non-uniformity.

[0029] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor, as well as the inductances of the first inductor 132A and the second inductor 132B, may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimal air or lateral coverage over the substrate support 104. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma increases to its maximum, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, potentially reducing the air coverage of the substrate support 104. The second electronic controller 140 may have a similar effect, increasing or decreasing the air coverage of the plasma on the substrate support 104 as its capacitance changes.

[0030] Electronic sensors 130 and 138 can be used to tune the respective closed-loop circuits 128 and 136. Depending on the type of sensor used, a current or voltage setpoint can be installed on each sensor, and the sensors may have control software that determines adjustments to the respective electronic controllers 134 and 140 to minimize deviations from the setpoint. As a result, the plasma shape can be selected and dynamically controlled during processing. The above discussion is based on electronic controllers 134 and 140, which may be variable capacitors, but it should be understood that any electronic component with adjustable characteristics can be used to provide adjustable impedance to the tuning circuits 128 and 136.

[0031] Figure 2 shows exemplary operation in processing method 200 according to several embodiments of the present technology. Method 200 can be carried out in various processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chambers, including non-plasma chambers, in which the operation may be performed. Method 200 may include one or more pre-initiation operations of the method, including front-end processing, deposition, etching, polishing, cleaning, or other operations that can be performed before the operations described. Method 200 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. For example, many operations are described to provide a broader range of processes to be performed, but are not critical to the technology, or may be carried out by alternative methodologies, which will be discussed further below. Method 200 may describe the operations schematically shown in Figures 3A to 3D, and this description will be given in conjunction with the operation of Method 200. The figures are only partial schematics, and it should be understood that the substrate may include any number of additional materials and features having various properties and embodiments, as shown in the figures.

[0032] Method 200 may or may not include any operations for developing a semiconductor structure to suit a specific manufacturing operation. Method 200 should be understood to be applicable to any number of semiconductor structures or substrates 305, including exemplary structures 300 on which one or more silicon-containing materials can be formed on the substrate 305, as shown in Figure 3A. As shown in Figure 3A, the substrate 305 may be processed to form one or more features 315 that may have recesses, such as trenches, openings, or any other structures in the semiconductor process. The substrate 305 can be any number of materials, including a base wafer or substrate 305 made of silicon or a silicon-containing material, other substrate 305 materials, and one or more materials that may be formed in layers on the substrate 305 during the semiconductor process. For example, in some embodiments, the substrate 305 may be processed to include one or more materials or structures for the semiconductor process. The substrate 305 may be or may include dielectric materials such as oxides or nitrides of any number of materials. In embodiments, one or more layers of material 310 can be deposited on the substrate 305. In the embodiment, one or more layers of material 310 may be one or more materials for 3D NAND, such as oxide and / or metallic materials, or may include them.

[0033] As shown, one or more features 315, such as trenches, openings, or other concave features, may be defined by one or more layers of material 310 and / or substrate 305. In embodiments, the feature 315 may feature tapered sidewalls, as shown in Figure 3A. In embodiments, the feature 315 may be characterized by having a larger diameter or width at the top of the feature 315 than at the bottom of the feature 315. The aspect ratio of the feature 315, or the ratio of the depth of the feature to the width or diameter of the formed feature, may be about 1:1 or greater, and may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater. Although only one feature 315 is shown in the figure, it should be understood that the exemplary structure may have any number of features 315 defined along the structure according to embodiments of the Art.

[0034] In operation 205, method 200 may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor can be supplied to the same processing area of ​​the semiconductor processing chamber before the start of method 200 to carry out the operation. The deposition precursor may include silicon-containing precursors, oxygen-containing precursors, and any other precursors useful for forming silicon-containing materials.

[0035] The silicon-containing precursors that can be used in Method 200 may be any number of silicon-containing precursors or may include them. For example, the silicon-containing precursors may be any other precursors capable of forming silicon-containing films, such as silane (SiH4), dislane (Si2H6), trisilane (Si3H8), silicon tetrachloride (SiCl4), tetraethyl orthosilicate (TEOS), or silicon oxide (SiO), or may include them. In embodiments of the present technique, higher-order silanes are used, which may result in increased fluidity of the deposited material, but the increased hydrogen content in the deposited material may lead to gas release in subsequent operation. The oxygen-containing precursors that can be used in Method 200 may be any number of oxygen-containing precursors or may include them. For example, the oxygen-containing precursors may be any other precursors capable of forming silicon- and oxygen-containing films, such as nitric oxide (NO), nitrous oxide (N2O), diatomic oxygen (O2), or silicon oxide (SiO), or may include them. In some embodiments, one or more additional precursors, such as one or more carrier gases or inert gases, such as argon or helium, may be supplied along with the silicon-containing precursor and / or oxygen-containing precursor.

[0036] During operation 205, the flow rate of the silicon-containing precursor can be maintained at a flow rate of approximately 500 sccm or less. Increasing the flow rate may increase the deposition rate and lead to reduced conformation. Therefore, the flow rate of the silicon-containing precursor can be maintained at a flow rate of approximately 400 sccm or less, approximately 300 sccm or less, approximately 200 sccm or less, approximately 100 sccm or less, approximately 75 sccm or less, approximately 50 sccm or less, approximately 25 sccm or less, or less. Furthermore, if present, the flow rate of the oxygen-containing precursor can be maintained at approximately 500 sccm or higher, for example, approximately 750 sccm or higher, approximately 1,000 sccm or higher, approximately 1,250 sccm or higher, approximately 1,500 sccm or higher, approximately 1,750 sccm or higher, approximately 2,000 sccm or higher, approximately 2,250 sccm or higher, approximately 2,500 sccm or higher, approximately 2,750 sccm or higher, approximately 3,000 sccm or higher, approximately 3,250 sccm or higher, approximately 3,500 sccm or higher, approximately 3,750 sccm or higher, approximately 4,000 sccm or higher, approximately 4,250 sccm or higher, approximately 4,500 sccm or higher, approximately 4,750 sccm or higher, approximately 5,000 sccm or higher, or higher.

[0037] In operation 210, as shown in Figure 3B, method 200 may include depositing silicon-containing material 320a on the substrate 305 and, if present, on one or more layers of material 310. The deposition precursor may be in contact with the substrate 305 and, if present, one or more layers of material 310. As shown in Figure 3B, if exposed, the silicon-containing material 320a may extend along any and / or all exposed surfaces along the substrate 305, and along any other incorporated material, such as one or more layers of material 310. During operation 225, growth may occur from the sidewall defining feature 315 toward the feature 315.

[0038] The deposition of silicon-containing material 320a onto the substrate 305 in operation 215 can be carried out as a non-plasma operation. By carrying out operation 215 without the use of plasma, the deposition of silicon-containing material 320a can be highly conformable. In embodiments, the deposition of silicon-containing material 320a may be characterized by conformability of about 60% or more, about 65% or more, about 70% or more, about 75% or more, about 80% or more, or higher. This high level of conformability can be beneficial during feature filling, preventing the feature 315 from becoming blocked before it is filled with silicon-containing material 320a. Blocking the feature 315 before it is filled with silicon-containing material 320a may result in the formation of seams and / or voids in the silicon-containing material 320a.

[0039] As feature 315 begins to be filled with silicon-containing material 320a, the opposite surface of the silicon-containing material 320a along the substrate 305 (if exposed), or any other incorporated material such as one or more layers of material 310, may feature terminal hydroxyl (-OH) groups. If left untreated, these hydroxyl groups can result in a less compressible film that is prone to cracking during subsequent processing, such as annealing or other rapid heat treatments. The technique can incorporate one or more treatments to increase the compressive stress of the material and reduce the likelihood of cracking, as will be further described below.

[0040] During the above deposition, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at a variety of temperatures at which film deposition can be carried out. In some embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at approximately 650°C or lower, approximately 600°C or lower, approximately 550°C or lower, approximately 500°C or lower, or lower. In embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at approximately 300°C or higher, approximately 350°C or higher, approximately 400°C or higher, approximately 450°C or higher, approximately 500°C or higher, or higher, thereby promoting the thermal decomposition of the precursor and enabling plasma-free deposition.

[0041] Furthermore, during the deposition process, the semiconductor processing chamber can be maintained at various pressures that enable deposition. For example, the pressure inside the semiconductor processing chamber can be maintained at approximately 10 Torr or higher while depositing the silicon-containing material 320a, and can be maintained at approximately 20 Torr or higher, approximately 30 Torr or higher, approximately 50 Torr or higher, approximately 75 Torr or higher, approximately 100 Torr or higher, approximately 150 Torr or higher, approximately 200 Torr or higher, approximately 250 Torr or higher, or higher. Similarly, the pressure inside the semiconductor processing chamber can be maintained at approximately 350 Torr or lower while depositing the silicon-containing material 320a, and can be maintained at approximately 300 Torr or lower, approximately 250 Torr or lower, approximately 200 Torr or lower, approximately 150 Torr or lower, approximately 100 Torr or lower, approximately 75 Torr or lower, approximately 50 Torr or lower, approximately 30 or lower, approximately 20 Torr or lower, or lower.

[0042] Silicon-containing material 320a can be deposited under high compressive stress. Low-stress materials can be characterized by internal stress levels close to neutral stress (i.e., 0 MPa), while high-stress materials can be characterized by internal stress levels significantly higher than 0 MPa (i.e., high positive (tensile) stress) or significantly lower than 0 MPa (i.e., high negative (compressive) stress). High positive stress can be characterized as tensile stress, causing expansion of adjacent materials and generating outward pushing forces on adjacent substrate features. High negative stress can be characterized as compressive stress, causing contraction of adjacent materials and generating inward tensile forces on adjacent substrate features. In other words, high-stress materials can be characterized by an absolute value of the stress level significantly higher than 0 MPa. Therefore, when a material is characterized by a stress level "greater than -1000 MPa", this refers to the absolute value of the stress level, including levels such as -1500 MPa and -2000 MPa. Similarly, when a material is characterized by a stress level of "less than -1000 MPa," this refers to a stress level close to neutral stress (i.e., 0 MPa), including levels such as -500 MPa and -100 MPa, but not reaching positive values ​​of approximately 1000 MPa or higher.

[0043] The exemplary stress values ​​of the deposited silicon-containing material 320a can range from approximately -50 MPa or lower, with a more negative stress value indicating greater stress, and a stress value closer to 0 MPa indicating smaller stress. Additional exemplary stress ranges may include approximately -60 MPa or higher, approximately -70 MPa or higher, approximately -80 MPa or higher, approximately -90 MPa or higher, approximately -100 MPa or higher, approximately -125 MPa or higher, approximately -150 MPa or higher, approximately -175 MPa or higher, approximately -200 MPa or higher, or greater. In embodiments, amorphous silicon-containing material can be deposited and then oxidized. Oxidation can cause volume expansion of the silicon-containing material 320a, potentially making the silicon-containing material 320a compressible. In conventional silicon-containing material deposition operations using TEOS and O3, volume expansion does not occur, and the deposited material may be tensile rather than compressible.

[0044] In an optional operation 215, after depositing the silicon-containing material 320a, method 200 may include treating the deposited silicon-containing material 320a. Treating the silicon-containing material 320a during the optional operation 215 may include contacting the material with plasma emissions of a treatment precursor. In embodiments, the treatment precursor may be an oxygen-containing precursor or may contain an oxygen-containing precursor. Contact may rearrange the bonds in the silicon-containing material, for example, by cleaving hydroxyl groups and forming Si-O-Si bonds. This rearrangement of bonds in the silicon-containing material 320a may further increase the compressive stress of the film.

[0045] The treatment precursor supplied in the optional operation 215 may be any precursor capable of converting Si-OH bonds to Si-O-Si bonds. The treatment precursor that can be used in the optional operation 215 may be or may contain any number of inert precursors. For example, the treatment precursor may be or may contain argon, helium, nitrogen, xenon, diatomic oxygen (O2), ozone (O3), or any other precursor capable of rearranging bonds in the silicon-containing material 320a to increase the compressive stress of the film.

[0046] During processing, plasma can be formed from the processing precursor. The plasma output can affect the depth of the precursor's penetration, which can affect the increase in the compressive stress of the film. Therefore, in some embodiments, the plasma output applied when generating the plasma of the processing precursor can be about 100W or more, about 200W or more, about 300W or more, about 400W or more, about 500W or more, about 600W or more, about 700W or more, about 800W or more, about 900W or more, about 1,000W or more, about 1,100W or more, about 1,200W or more, about 1,300W or more, about 1,400W or more, about 1,500W or more, or greater. However, higher plasma power can increase the impact, potentially causing sputtering and / or etching of the silicon-containing material 320a. Therefore, in some embodiments, the plasma power can be less than or equal to about 1,500 W, 1,400 W, 1,300 W, 1,200 W, 1,000 W, or less. The plasma can be generated at frequencies from about 350 kHz to about 100 MHz (e.g., 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz). While forming the plasma of the processing precursor and processing the silicon-containing material, the temperature in the semiconductor processing chamber can be maintained at the same temperature as the deposition operation, or it can be adjusted to a different temperature within the range described above with respect to the deposition operation.

[0047] Conversely, the processing in operation 215 can be carried out at a lower pressure than the formation of the silicon-containing material in operation 210. During operation 215, while processing the silicon-containing material 320a, the pressure can be maintained at approximately 50 Torr or less, approximately 40 Torr or less, approximately 30 Torr or less, approximately 25 Torr or less, approximately 20 Torr or less, approximately 15 Torr or less, approximately 10 Torr or less, approximately 5 or less, approximately 3 Torr or less, or lower, which can promote an increase in the mean free path and / or radical energy during deposition. The increase in mean free path may allow the plasma ejecta of the processing precursor to reach the bottom of feature 315. Furthermore, the increase in radical energy may increase the interaction between the plasma ejecta of the processing precursor and the silicon-containing material 320a.

[0048] Exemplary stress values ​​for the treated silicon-containing material 320a may include values ​​of approximately -100 MPa or less, approximately -125 MPa or more, approximately -150 MPa or more, approximately -175 MPa or more, approximately -200 MPa or more, approximately -225 MPa or more, approximately -250 MPa or more, approximately -275 MPa or more, approximately -300 MPa or more, approximately -325 MPa or more, approximately -350 MPa or more, or greater. While there is no intention to be bound by any particular theory regarding the cause of the increased compressive stress level of the treated material, it is thought that the treatment may cause an impact on the material, leading to the rearrangement of Si-OH bonds into Si-O-Si bonds, further increasing the density of the film, thereby increasing the compressive stress.

[0049] In one embodiment, feature 315 may be filled with a single deposit of silicon-containing material 320a. However, as shown in Figures 3C-3D, embodiments of the art may include sequentially filling feature 315 with silicon-containing material. For example, additional silicon-containing material 320b may be deposited and then processed. After processing, the additional silicon-containing material 320b can be mixed and harmonized with the previously deposited and optionally processed silicon-containing material 320a. This process can be repeated any number of times. As shown in Figure 3D, during each cycle, additional silicon-containing material 320c may be deposited so that one or more features 315 are repeatedly filled higher and higher in a bottom-up gap filling, for example, towards the top of feature 315.

[0050] The number of iterations of sequentially depositing the film and selectively processing the film may depend on a variety of factors, including but not limited to the depth of feature 315, the aspect ratio of feature 315, and / or the amount of silicon-containing material deposited. In some embodiments, the method 200 for depositing silicon-containing material and selectively processing the silicon-containing material may be repeated at least twice, and may include at least three, at least four, at least five, at least six, at least seven, at least ten, at least fifteen, or more iterations of the operation. During each iteration, the thickness of the deposited silicon-containing material may be about 30 Å or less. At thicknesses greater than 30 Å, the selective processing in operation 215 may not be able to process the entire thickness of the silicon-containing material. Therefore, during each iteration, the thickness of the deposited silicon-containing material may be about 28 Å or less, about 26 Å or less, about 24 Å or less, about 22 Å or less, about 20 Å or less, or thinner.

[0051] In operation 220, method 200 may include annealing the substrate 305. Annealing the substrate in operation 220 may include supplying a nitrogen-containing precursor or an oxygen-containing precursor to the processing area of ​​the semiconductor processing chamber. In embodiments, method 200 may include stopping the flow of the silicon-containing precursor before operation 220. By stopping the flow of the silicon-containing precursor, deposition is stopped and annealing of the deposited silicon-containing material can be carried out. The nitrogen-containing precursor or oxygen-containing precursor can be supplied to the same processing area of ​​the semiconductor processing chamber for deposition of the silicon-containing material and can also be continued from one or more deposition operations as described above. In other embodiments, the structure 300 may be moved to another chamber before operation 220. The nitrogen-containing precursor that can be used in method 200 may be any number of nitrogen-containing precursors or may include any number of nitrogen-containing precursors. For example, the nitrogen-containing precursor may be or may contain nitrous oxide (N2O), diatomic nitrogen (N2), ammonia (NH3), a combination of one or more of these, or any other nitrogen-containing material. The oxygen-containing precursor that can be used in Method 200 may be or may contain any number of oxygen-containing precursors. For example, the oxygen-containing precursor may be or may contain nitrous oxide (N2O), water (H2O), diatomic oxygen (O2), ozone (O3), a combination of one or more of these, or any other oxygen-containing material.

[0052] Annealing in operation 220 can be performed to form memory cells within a structure that may be a 3D NAND structure. During annealing, the temperature may rise compared to the temperature used during the previous deposition and / or processing operation. The temperature in the semiconductor processing chamber in which annealing is performed can be maintained at about 600°C or higher, and can be maintained at about 650°C or higher, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, or higher while annealing the substrate 305. However, at higher temperatures, one or more layers of the substrate 305 and / or material 310, if present, may also be affected by annealing. For example, in embodiments where an oxygen-containing precursor is used in operation 220 and the substrate 305 is silicon or contains silicon, the substrate 305 may also begin to oxidize. Therefore, the temperature inside the semiconductor processing chamber can be maintained at approximately 1,000°C or lower, approximately 950°C or lower, approximately 900°C or lower, approximately 850°C or lower, or even lower, while the silicon-containing material is being annealed.

[0053] Annealing of the silicon-containing material using a nitrogen-containing precursor or an oxygen-containing precursor in operation 220 can be continued for a sufficient time to form memory cells within the structure. In embodiments, annealing can be performed for about 15 minutes or more, and may be about 30 minutes or more, about 45 minutes or more, about 60 minutes or more, or longer. Embodiments of the present technology can result in a reduction in the shrinkage rate of the silicon-containing material during annealing. For example, the shrinkage rate of the silicon-containing material after annealing may be about 5% or less, such as about 4.5% or less, about 4% or less, about 3.5% or less, about 3% or less, about 2.5% or less, about 2% or less, about 1.5% or less, about 1% or less, about 0.5% or less, about 0.1% or less, or smaller.

[0054] This technology can provide silicon-containing materials that exhibit reduced stress changes compared to conventional technologies. After annealing in operation 220, the silicon-containing material may exhibit stress changes of approximately 50 MPa or less, for example, approximately 40 MPa or less, approximately 30 MPa or less, for example, approximately 20 MPa or less, approximately 10 MPa or less, for example, approximately 5 MPa or less, approximately 1 MPa or less, or smaller. Furthermore, this technology can provide silicon-containing materials that exhibit dielectric breakdown of approximately 5 MV / cm or more. This breakdown voltage makes the material suitable for many semiconductor applications, not just 3D NAND applications. In embodiments, the silicon-containing material may exhibit dielectric breakdown of approximately 6 MV / cm or more, for example, approximately 7 MV / cm or more, approximately 8 MV / cm or more, approximately 9 MV / cm or more, approximately 10 MV / cm or more, or larger.

[0055] In the preceding description, many details have been given for illustrative purposes to facilitate understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be carried out without some of these details, or with further details.

[0056] While several embodiments have been disclosed, it will be apparent to those skilled in the art that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, several well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the Art.

[0057] Where a range of values ​​is presented, it is understood that each intervention value up to the smallest unit of the lower limit between the upper and lower limits of that range is also specifically disclosed, unless the context explicitly indicates otherwise. Any narrow range between any listed value or unlisted intervention value within a listed range and any other listed value or intervention value within that listed range is also included. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range that includes one, neither, or both of the limit values ​​is also included in this technical scope and is subject to any specifically excluded limit values ​​within the specified range. Where one or both limit values ​​are included in the specified range, ranges that exclude one or both of those included limit values ​​are also included.

[0058] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” refer to multiple objects unless otherwise specified in the context. Thus, for example, “a precursor” includes multiple such precursors, and “the material” includes one or more materials and their equivalents known to those skilled in the art.

[0059] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used in this specification and the appended claims, are intended to identify the presence of a described feature, integer, component, or process, but do not exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, The method involves supplying a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber, wherein the substrate is placed inside the semiconductor processing chamber. Forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of approximately -200 MPa or higher, and Annealing the substrate at a temperature of approximately 700°C or higher. A semiconductor processing method, including the following.

2. The silicon-containing precursor is silane (SiH ４ ), disilane (Si ２ H ６ ), or trisilane (Si ３ H ８ The semiconductor processing method according to claim 1, including ).

3. The semiconductor processing method according to claim 1, wherein the temperature inside the semiconductor processing chamber is maintained at approximately 600°C or less while the silicon-containing material is being formed.

4. The semiconductor processing method according to claim 1, wherein the pressure inside the semiconductor processing chamber is maintained at approximately 350 Torr or less.

5. The oxygen-containing precursor is supplied together with the silicon-containing precursor. The semiconductor processing method according to claim 1, further comprising:

6. The semiconductor processing method according to claim 1, wherein the semiconductor processing chamber is kept plasma-free while the silicon-containing material is being formed.

7. The semiconductor processing method according to claim 1, wherein, after annealing the silicon-containing material, the silicon-containing material is characterized by a shrinkage rate of about 5% or less.

8. After forming the silicon-containing material, an inert precursor is supplied to the processing region of the semiconductor processing chamber. Forming plasma emissions of the inert precursor, and The silicon-containing material is brought into contact with the plasma emitter of the inert precursor. The semiconductor processing method according to claim 1, further comprising:

9. The semiconductor processing method according to claim 8, wherein the inert precursor contains argon.

10. The oxygen-containing precursor is supplied together with the inert precursor. The semiconductor processing method according to claim 8, further comprising:

11. A semiconductor processing method, The method involves supplying a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber, wherein a substrate is placed inside the semiconductor processing chamber, and the silicon-containing precursor is disilane (Si ２ H ６ To supply a silicon-containing precursor, including ) Forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of approximately -200 MPa or higher, and Annealing the substrate at a temperature of approximately 700°C or higher, wherein the silicon-containing material is characterized by a shrinkage rate of approximately 5% or less. A semiconductor processing method, including the following.

12. The semiconductor processing method according to claim 11, wherein the substrate includes one or more features.

13. The semiconductor processing method according to claim 11, wherein the silicon-containing material is characterized by a dielectric breakdown of about 5 MV / cm or more.

14. The semiconductor processing method according to claim 11, wherein annealing the substrate includes bringing the substrate into contact with a nitrogen-containing precursor.

15. After forming the silicon-containing material, plasma treatment is performed using an inert precursor. The semiconductor processing method according to claim 11, further comprising:

16. The semiconductor processing method according to claim 15, wherein the plasma processing is carried out at a pressure lower than that used for forming the silicon-containing material.

17. The semiconductor processing method according to claim 15, wherein the inert precursor contains argon.

18. A semiconductor processing method, Supplying silicon-containing precursors and oxygen-containing precursors to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed inside the semiconductor processing chamber. Forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of approximately -200 MPa or higher. To supply an inert precursor to the processing region of the semiconductor processing chamber, Forming plasma emissions of the inert precursor, The silicon-containing material is brought into contact with the plasma emitter of the inert precursor, and Annealing the aforementioned substrate A semiconductor processing method, including the following.

19. The semiconductor processing method according to claim 18, wherein the silicon-containing material is characterized by a shrinkage rate of about 5% or less.

20. The semiconductor processing method according to claim 18, wherein the thickness of the silicon-containing material is about 30 Å or less.

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