Dry development of metal oxide photoresists

Abstract

Embodiments disclosed herein include methods for dry developing metal oxide photoresists. In one embodiment, a method for patterning a metal oxide photoresist, such as a Sn-based photoresist, includes depositing the metal oxide photoresist on a substrate, exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure to form exposed and unexposed regions, and developing the exposed metal oxide photoresist using an electron donor ligand-based dry etching process.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 528,196, filed on July 21, 2023, and claims the priority of U.S. Patent Application No. 18 / 653,340, filed on May 2, 2024, the entire content of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to the field of semiconductor processing, and more particularly, to methods of performing dry development of metal oxide photoresists.

Background Art

[0003] Description of Related Art Lithography has been used for decades in the semiconductor industry to generate two - dimensional and three - dimensional patterns on microelectronic devices. The lithography process involves spin - on deposition of a film (photoresist), irradiating (exposing) the film with a selected pattern using an energy source (exposure), dissolving in a solvent to remove (etch) the exposed regions (positive tone) or unexposed regions (negative tone) of the film, and baking to remove the remaining solvent.

[0004] The photoresist should be a radiation - sensitive material. When irradiated, a chemical change occurs in the exposed portion of the film, enabling a change in solubility between the exposed and unexposed regions. Utilizing this change in solubility, either the exposed or unexposed regions of the photoresist are removed (etched). Then, the photoresist is developed and the pattern can be transferred to the underlying thin film or substrate by etching. After the pattern is transferred, the remaining photoresist is removed, and by repeating this process multiple times, two - dimensional and three - dimensional structures used in microelectronic devices are generated.

[0005] Several properties are important in the lithography process. These important properties include sensitivity, resolution, lower line-edge roughness (LER), etching resistance, and the ability to form thinner layers. Higher sensitivity means that less energy is required to change the solubility of the deposited film, which allows for increased efficiency in the lithography process. Resolution and LER determine how narrow features can be achieved in the lithography process. Pattern transfer to form deep structures requires materials with higher etching resistance. Materials with higher etching resistance can also enable thinner films. Thinner films increase the efficiency of the lithography process. [Overview of the project]

[0006] Embodiments disclosed herein include methods for patterning metal oxide photoresists using a dry development process. In one embodiment, the method includes depositing a metal oxide photoresist on a substrate, exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure to form exposed and unexposed regions, and developing the exposed metal oxide photoresist using an electron donor ligand-based dry etching process.

[0007] In one embodiment, another method includes depositing a metal oxide photoresist on a substrate; exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure to form exposed and unexposed regions; treating the exposed metal oxide photoresist with a fluorination process; and developing the exposed fluorinated metal oxide photoresist using an electron donor ligand-based dry etching process.

[0008] Embodiments may further include depositing a metal oxide photoresist on a substrate, exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure to form exposed and unexposed regions, and developing the exposed metal oxide photoresist by repeatedly (1) treating the exposed metal oxide photoresist with a fluorination process and (2) using an electron donor ligand-based dry etching process. [Brief explanation of the drawing]

[0009] [Figure 1A] The diagram shows a cross-sectional view illustrating various steps in a patterning process using a positive photoresist material formed by the process described herein, according to one embodiment of this disclosure. [Figure 1B] The following is a cross-sectional view illustrating various steps in a patterning process using a negative photoresist material formed by the process described herein, according to one embodiment of this disclosure. [Figure 2A-2C] This invention presents a possible volatile Sn-based compound resulting from a dry development process performed on a Sn-based photoresist according to one embodiment of this disclosure. [Figure 3] This is a schematic diagram of a ligand, which is a non-limiting example of a stable ligand with a reasonable boiling point supplied to the gas phase as a reactant for removing more reactive SnOC species from a Sn oxide-based photoresist film, according to one embodiment of the present disclosure. [Figure 4] This diagram shows cross-sectional views illustrating various steps in a method for patterning a photoresist layer according to one embodiment of the present disclosure. [Figure 5] The following are cross-sectional views illustrating various steps in a method for patterning a photoresist layer according to another embodiment of the present disclosure. [Figure 6] This is a cross-sectional view of a processing tool that may be used to carry out the dry developing process described herein, according to one embodiment of the present disclosure. [Figure 7]This is a cross-sectional view of a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate using a dry development process, according to one embodiment of the present disclosure. [Figure 8] This is a magnified view of the edge of a displaceable column in a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate using a dry development process, according to one embodiment of the present disclosure. [Figure 9A] This is a close-up view of the edge of a displaceable column in a processing tool, according to one embodiment of the present disclosure, where the shadow ring is not engaged with the edge ring. [Figure 9B] This is a close-up view of the edge of a displaceable column in a processing tool, according to one embodiment of the present disclosure, in which a shadow ring is engaged with an edge ring. [Figure 10A] This is a cross-sectional view of a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate using a dry development process, according to one embodiment of the present disclosure. [Figure 10B] This is a cross-sectional view of a processing tool according to one embodiment of the present disclosure, in which the pedestal has been removed to expose a channel in the base plate. [Figure 11] A block diagram of an exemplary computer system according to one embodiment of the present disclosure is shown. [Modes for carrying out the invention]

[0010] This specification describes methods for developing positive or negative metal oxide photoresists. The following description includes numerous specific details, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes, and material states for depositing positive or negative metal oxide photoresists, in order to provide a complete understanding of the embodiments of this disclosure. Those skilled in the art will see that embodiments of this disclosure can be implemented without these specific details. In other instances, well-known embodiments, such as the manufacture of integrated circuits, are not described in detail to avoid unnecessarily obscuring the embodiments of this disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative and not necessarily drawn to scale.

[0011] To explain the background, the photoresist systems used in extreme ultraviolet (EUV) lithography suffer from low efficiency. Specifically, existing photoresist material systems for EUV lithography require high doses to provide the necessary solubility switch to enable the development of the photoresist material. Traditionally, carbon-based films called organic chemically amplified photoresists (CARs) have been used as photoresists. However, more recently, organic-inorganic hybrid materials (metal-oxo) have been used as photoresists for extreme ultraviolet (EUV) radiation. Such materials typically contain metals (Sn, Hf, Zr, etc.), oxygen, and carbon. The shift from deep ultraviolet (DUV) to EUV in the lithography industry has facilitated the creation of narrow features with high aspect ratios. Metal-oxo-based organic-inorganic hybrid materials have been shown to exhibit lower line-edge roughness (LER) and higher resolution, which are necessary for forming narrow shapes. Furthermore, such films have higher sensitivity and etching resistance, and can be implemented to fabricate relatively thin films.

[0012] Currently, organotin oxo compounds are entering mainstream semiconductor industry processes as a way to mitigate the low absorption of extreme ultraviolet (EUV) radiation by thin films of organic resists, which have low sensitivity and cannot handle the severity of development and etching conditions. However, each lithography performance needs to achieve a better line width roughness (LWR) index (LER is one of the most important performance metrics to improve for EUV lithography) to enable high-resolution patterning.

[0013] Wet development is a common technique for developing resists in the track process. Because the developer interacts with the Sn-based resist at the cluster level, partially exposed PRs at the edges may / may not dissolve (determined by the experienced degree of exposure). Thus, there are resolution limitations imposed by the cluster size under development, which can lead to roughness issues. According to one or more embodiments of this disclosure, dry development techniques are implemented to provide atomic-level interaction with the PRs instead of cluster-level interaction.

[0014] According to one or more embodiments of this disclosure, dry development is performed on a metal-oxide photoresist (e.g., SnPR is described as an exemplary film). Volatile organic and inorganic molecules are used to etch the Sn-O system film. Embodiments may include aiming to form known stable volatile Sn precursors from SnO photoresist. This approach can be explored in two ways: (1) reaction of a ligand with a SnOC photoresist (e.g., Figure 4 described below), and (2) conversion of SnOC to SnFx, followed by reaction of the ligand with SnFx (SnFx must be more reactive than SnOx, Ediss(Sn-F) = 467 kJ / mol, and Ediss(Sn-O) = 548 kJ / mol) (examples are described below).

[0015] The advantages of implementing the embodiments described herein can include the ability to provide a pathway for atomic-level photoresist (PR) development in the gas phase. This can replace wet development or be used as post-dry development after wet development to finely etch remaining portions that have not been removed within a cluster and remain behind a partial cluster.

[0016] To provide further background, FIG. 1A shows a cross-sectional view depicting various steps in a patterning process using a positive photoresist material formed by the process described herein, according to one embodiment of the present disclosure.

[0017] Referring to part (a) of FIG. 1A, the starting structure 100 includes a positive photoresist layer 104 on a substrate or lower layer 102. In one embodiment, the positive photoresist layer 104 is deposited using dry or wet deposition. Referring to part (b) of FIG. 1A, the starting structure 100 is irradiated 106 at selected locations, forming an irradiated photoresist layer 104A having an irradiated region 105B and a non-irradiated region 105A. Referring to part (c) of FIG. 1A, a removal or etching process 108 is used to provide a developed photoresist layer in the non-irradiated region 105A. Referring to part (d) of FIG. 1A, an etching process 110 using the non-irradiated region 105A as a mask is used to pattern the substrate or lower layer 102, forming a patterned substrate or patterned lower layer 102A that includes etched features 112.

[0018] Referring back to FIG. 1A, the positive photoresist 104 is a radiation-sensitive material that, when irradiated, undergoes a chemical transformation in the exposed portion of the film, enabling a change in solubility between the exposed and unexposed regions. Utilizing the change in solubility, the exposed regions of the positive photoresist are removed (etched). Next, the positive photoresist is developed, and the pattern can be transferred to the underlying thin film or substrate by etching. After the pattern is transferred, the remaining positive photoresist is removed. By repeating this process multiple times, 2D and 3D structures for use in, for example, microelectronic devices can be fabricated.

[0019] To provide further background, FIG. 1B shows a cross-sectional view depicting various steps in a patterning process using a negative photoresist material formed by the process described herein, according to one embodiment of the present disclosure.

[0020] Referring to part (a) of FIG. 1B, the starting structure 100 includes a negative photoresist layer 103 on a substrate or lower layer 102. In one embodiment, the negative photoresist layer 103 is deposited using dry or wet deposition. Referring to part (b) of FIG. 1B, the starting structure 100 is irradiated 106 at selected locations, forming an irradiated photoresist layer 103A having irradiated regions 105B and non-irradiated regions 105A. Referring to part (c) of FIG. 1B, a removal or etching process 108 is used to provide a developed photoresist layer in the irradiated regions 105B. Referring to part (d) of FIG. 1B, an etching process 110 using the irradiated regions 105B as a mask is used to pattern the substrate or lower layer 102, forming a patterned substrate or patterned lower layer 102A that includes etched features 112.

[0021] Referring again to Figure 1B, the negative photoresist 103 is a radiation-sensitive material. When irradiated, a chemical transformation occurs in the exposed areas of the film, allowing for a change in solubility between the exposed and unexposed areas. This change in solubility is used to remove (etch) the unexposed areas of the negative photoresist. The negative photoresist is then developed, and the pattern can be transferred to the underlying thin film or substrate by etching. After the pattern has been transferred, any remaining negative photoresist is removed. By repeating this process multiple times, 2D and 3D structures can be manufactured, for example, for use in microelectronic devices.

[0022] As will be explained in more detail below, both positive and negative resists may be metal oxide photoresist films. In some cases, the same material system may be used for both positive and negative resists. That is, either a positive or negative resist can be formed using dry or wet deposition by EUV exposure.

[0023] As described above, metal oxide films (for example, Sn-O based films) can be etched using volatile organic and inorganic molecules.

[0024] It should be understood that amine-based, oxygen-based, and alkyl-based Sn precursors can be stable and volatile. In one embodiment, the development approach effectively provides reverse engineering for removing SnOx as SnRx(NR'2)y, Sn(NR-CR'-NR)x, SnRx, and Sn(OR)x species. For example, the film can be effectively developed by etching the Sn film using NH4Cl and / or NH4Br as the etchant. Both amines and halides form volatile Sn species when they react with SnO2 or SnF4 films. NH4Cl and / or NH4Br can be delivered into the gas phase in the etching chamber to etch the Sn film.

[0025] It should be understood that the reaction of metal oxide photoresists, such as tin oxide photoresists, effectively forms volatile metal compounds, and these compounds can be developed (etched) by volatilizing them as byproducts of the development process. As exemplary volatile species, Figures 2A to 2C show volatile tin-based compounds resulting from a dry development process performed on a tin-based photoresist according to one embodiment of this disclosure.

[0026] Specifically, Figure 2A is a schematic diagram 200 of N-based Sn-containing volatile compounds (a), (b), (c), (d), and (e). Figure 2B is a schematic diagram 210 of O-based Sn-containing volatile compounds (a) and (b). Figure 2C is a schematic diagram 220 of C-based Sn-containing volatile compounds (a) and (b).

[0027] Referring again to Figures 2A-2C, these are fully coordinated Sn centers with stable and volatile ligands (these are characterized by Sn complexes used as CVD / ALD precursors). In other embodiments, mixed ligands and oxygen or alkyl Sn centers (still volatile species such as SnO(NR2)2 or SnR(NR2)3) may be used.

[0028] As exemplary etching ligands, Figure 3 is a schematic diagram of ligands (a), (b), (c), (d), (e), (f), and (g), which are non-limiting examples of stable ligands with reasonable boiling points supplied to the gas phase as a reactant for removing more reactive SnOC species from a Sn oxide-based photoresist film according to one embodiment of the present disclosure. In one embodiment, one or more such ligands are supplied into a chamber on a PR-coated wafer after exposure to EUV light. Sn in the unexposed areas react with the incident ligand, leaving the PR and effectively etching and patterning the surface based on the mask used for EUV exposure. In some embodiments, hexafluoroacetylacetone (hfacH) (i.e., ligand (g)) has been shown to enable high contrast between exposed and unexposed areas. The advantages of using hfacH may be more apparent at higher temperatures and / or pressures. A fluorination process prior to ligand application can also improve the etching selectivity of hfacH. However, it should be understood that increasing the temperature and / or pressure may also improve the etching selectivity of any of ligands (a) to (f).

[0029] As a first exemplary process flow, Figure 4 shows a cross-sectional view illustrating various steps in a method for patterning a photoresist layer according to one embodiment of the present disclosure.

[0030] Referring to Figure 4, a method 400 for patterning a metal oxide photoresist such as a Sn-based photoresist comprises (a) depositing a metal oxide photoresist 406 on a substrate 402 (with an optional underlayer 404 in between). The method also comprises (b) exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure 408 to form exposed regions 410 and unexposed regions 412. The method also comprises (c) developing the exposed metal oxide photoresist 406A using an electron-donor ligand-based dry etching process 414, which may be rendered to volatile byproducts such as exemplary SnOyLx. In one embodiment, one or more electron-donor ligands are ligands as shown in Figures 2A-2C and Figure 3, and may be Lewis base ligands.

[0031] In one embodiment, development of the exposed metal oxide photoresist 406A can be carried out under any suitable processing conditions. For example, the chamber pressure may be up to 25 Torr, up to 10 Torr, or up to 1 Torr. The temperature inside the chamber (e.g., the substrate temperature) may be between 50°C and 200°C. In one embodiment, the chemical immersion time may be up to 10 minutes, up to 30 minutes, or up to 1 hour. In some embodiments, it has been shown that higher temperatures and / or higher pressures can provide improved etching selectivity between the exposed region 410 and the unexposed region 412.

[0032] In one embodiment, developing the exposed metal oxide photoresist 406A further includes a wet development process before performing an electron donor ligand-based dry etching process 414. In another embodiment, developing the exposed metal oxide photoresist 406A does not involve using a wet development process in conjunction with the electron donor ligand-based dry etching process 414.

[0033] In one embodiment, the metal oxide photoresist 406 is a positive-type photoresist. In another embodiment, the metal oxide photoresist 406 is a negative-type photoresist.

[0034] In one embodiment, developing the exposed metal oxide photoresist 406A includes removing the unexposed region 412, as shown in the figure. However, in another embodiment, developing the exposed metal oxide photoresist 406A includes removing the exposed region 410.

[0035] As a second exemplary process flow, Figure 5 shows cross-sectional views illustrating various steps in a method for patterning a photoresist layer according to another embodiment of the present disclosure.

[0036] Referring to Figure 5, a method 500 for patterning a metal oxide photoresist, such as a Sn-based photoresist, comprises (a) depositing a metal oxide photoresist 506 onto a substrate 502 (with an optional underlayer 504 in between). The method also comprises (b) exposing the metal oxide photoresist with extreme ultraviolet (EUV) exposure 508 to form exposed regions 510 and unexposed regions 512. The method also comprises (c) processing the exposed metal oxide photoresist 506A with a fluorination process 514 to form, for example, a fluorinated unexposed region 512A. The method also comprises (d) developing the exposed and fluorinated metal oxide photoresist 506B using an electron-donor ligand-based dry etching process 516, which can provide volatile byproducts such as exemplary SnFzOyLx. In one embodiment, one or more electron-donor ligands are ligands as shown in Figures 2A-2C and 3, and may be Lewis base ligands.

[0037] In one embodiment, the development of the exposed and fluorinated metal oxide photoresist 506B can be carried out under any suitable processing conditions. For example, the chamber pressure may be up to 25 Torr, up to 10 Torr, or up to 1 Torr. The temperature inside the chamber (e.g., the substrate temperature) may be between 50°C and 200°C. In one embodiment, the chemical immersion time may be up to 10 minutes, up to 30 minutes, or up to 1 hour. In some embodiments, it has been shown that higher temperatures and / or higher pressures can provide improved etching selectivity between the exposed region 510 and the fluorinated unexposed region 512A. In some cases, the fluorination process has been shown to further improve the etching selectivity between the exposed region 510 and the fluorinated unexposed region 512A.

[0038] In one embodiment, developing the exposed and fluorinated metal oxide photoresist 506B further includes a wet development process before performing an electron donor ligand-based dry etching process 516. In another embodiment, developing the exposed and fluorinated metal oxide photoresist 506B does not involve using a wet development process in conjunction with the electron donor ligand-based dry etching process 516.

[0039] In one embodiment, the metal oxide photoresist 506 is a positive-type photoresist. In another embodiment, the metal oxide photoresist 506 is a negative-type photoresist.

[0040] In one embodiment, as shown in the figure, developing the exposed fluorinated metal oxide photoresist 506B includes removing the fluorinated unexposed region 512A. However, in another embodiment, developing the exposed and fluorinated metal oxide photoresist 506B includes removing the exposed region 510.

[0041] Referring again to Figure 5, in one embodiment, the exposed metal oxide photoresist 506A is treated with a fluorination process 514 and an electron donor ligand-based dry etching process 516 is repeated two or more times to complete the dry development process 599.

[0042] According to one embodiment of this disclosure, positive or negative photoresists are manufactured by using a metal precursor or a specific type of R group in plasma-assisted deposition. While the lithography industry is generally familiar with handling positive PRs, it should be understood that almost all novel metal oxo PRs are negative PRs. The embodiments described herein can be implemented for dry development of both positive and negative PRs.

[0043] In another embodiment, when a photoresist is exposed by an energy source (e.g., EUV) in an exposure environment, the exposure chamber (environment) may be oxygen-containing or inert. In one embodiment, exposure is performed under vacuum using an oxygen source such as O2, H2O, CO2, CO, NO2, or NO. In one embodiment, the number of repetitions of EUV exposure and subsequent oxygen exposure may be between one and 100.

[0044] In another embodiment, post-annealing is performed in an oxygen-containing environment. In one embodiment, the oxygen source is O3, NO2, NO, or O2, which can be used for plasma formation and / or can be used together with N2, Ar, or He. In one embodiment, post-annealing is performed at a temperature in the range of 25 to 200 degrees Celsius. In one embodiment, post-annealing is performed at a pressure of less than 200 torr. In a particular embodiment, post-annealing is performed using ozone (O3) as the oxygen source gas, at a temperature in the range of 25 to 250 degrees Celsius, and at a pressure of less than 200 torr.

[0045] Regarding the deposition of metal oxide photoresists according to one embodiment of the present disclosure, in the first approach, a chemical vapor deposition (CVD) method for forming a positive or negative photoresist is provided: (A) One or more metal precursors and one or more oxidizers are vaporized into a vacuum chamber in which a substrate wafer is maintained at a predetermined substrate temperature. The substrate temperature can vary from 0°C to 500°C. Once the precursors / oxidizers are vaporized in the chamber, they can be diluted with an inert gas such as Ar, N2, or He. Due to the reactivity of the precursors and oxidizers, a metal oxo film is deposited on the wafer. Evaporation into the chamber can be performed by simultaneously vaporizing all precursors or by alternately vaporizing the metal precursors and oxidizers in pulses. This process can be described as thermal CVD. (B) A plasma can also be turned on during this process, in which case this process can be described as plasma-enhanced (PE)-CVD. Examples of plasma sources include CCP, ICP, remote plasma, and microwave plasma. (C) The photoresist film can be deposited by plasma treatment after thermal deposition. In this case, the film is thermally deposited, and then a plasma treatment operation is performed. The plasma treatment can include plasma from inert gases such as Ar, N2, and He, which can be mixed with O2, CO2, CO, NO, NO2, and H2O. The treatment can be performed periodically, with plasma treatment following thermal deposition and this cycle being repeated, or with plasma treatment performed once after the deposition portion is complete (post-treatment). PECVD followed by plasma treatment is also possible. In any case, in one embodiment, post-annealing is performed in an oxygen-containing environment. In one embodiment, post-annealing is performed using ozone (O3) as the oxygen source gas, at a temperature in the range of 25 to 250 degrees Celsius and a pressure of less than 200 torr.

[0046] In a second approach according to one embodiment of the present disclosure, an atomic layer deposition (ALD) method for forming a positive or negative photoresist is performed by vaporizing a metal precursor from (A) into a vacuum chamber where the substrate wafer is maintained at a predetermined substrate temperature. The substrate temperature can vary in the range of 0 to 500°C. Next, a gas purge is provided to remove by-products and excess metal precursor. Next, one or more oxidizers are evaporated into the chamber. The oxidizers react with the metal precursors absorbed on the surface. Next, an inert gas purge is applied to remove by-products and unreacted oxidizers. This cycle can be repeated to achieve a desired thickness. When the precursor or oxidizer evaporates in the chamber, it can be diluted with an inert gas such as Ar, N2, or He. This process can be called thermal ALD. Using this method, multiple metals can be incorporated into the film by incorporating additional metal precursor pulses into the ALD cycle. Another oxidizer can also be pulsed after the first oxidizer. (B) Plasma can be turned on during the oxidizer pulse, and this process can be described as PE-ALD. (C) Alternatively, deposition can be carried out by thermal ALD followed by plasma treatment. In this case, plasma treatment is performed after thermal deposition. The plasma treatment can include plasma from inert gases such as Ar, N2, and He, which can be mixed with O2, CO2, CO, NO, NO2, and H2O. This treatment can be carried out periodically. Plasma treatment is performed after X thermal ALD cycles (X=1 to 5000), and the entire cycle is repeated the required number of times, or plasma treatment is performed once after the deposition part is completed. PE-ALD followed by plasma treatment is also possible. In either case, in one embodiment, post-annealing is performed in an oxygen-containing environment. In one embodiment, post-annealing is performed using ozone (O3) as the oxygen source gas, at a temperature in the range of 25 to 250 degrees Celsius and a pressure of less than 200 torr.

[0047] In a third approach, according to embodiments of the present disclosure, an atomic layer deposition (ALD) or chemical vapor deposition (CVD) method for forming a positive or negative photoresist includes providing a compositional gradient across the entire film. For example, the first few nanometers of the film have a different composition from the rest of the film. While the main portion of the film can be optimized dose-dependently, targeting a different composition near the interface layer can improve defect resistance and modify adhesion, sensitivity to EUV photons, sensitivity to chemical reactions that improve post-lithography profile control (especially fouling), and resist decay / lift-off. The gradient may be optimized depending on the pattern type. For example, pillars require improved adhesion, while line / space patterns may require reduced adhesion for increased dose.

[0048] In one embodiment, the vacuum deposition process relies on a chemical reaction between a metal precursor and an oxidant. The metal precursor and oxidant are vaporized toward a vacuum chamber. In some embodiments, the metal precursor and oxidant are supplied together to the vacuum chamber. In other embodiments, the metal precursor and oxidant are supplied to the vacuum chamber in alternating pulses. The process may be stopped after a metal oxo-positive or negative photoresist film of the desired thickness has been formed. In one embodiment, an optional plasma treatment step may be performed after a metal oxo-positive or negative photoresist film of the desired thickness has been formed.

[0049] In one embodiment, a metal oxo-positive or negative photoresist film of a desired thickness can be provided by repeating a cycle including pulses of metal precursor vapor and pulses of oxidant vapor multiple times. In one embodiment, the order of the cycles can be changed. For example, the oxidant vapor can be pulsed first, followed by the metal precursor vapor. In one embodiment, the pulse duration of the metal precursor vapor may be substantially the same as that of the oxidant vapor. In other embodiments, the pulse duration of the metal precursor vapor may differ from that of the oxidant vapor. In one embodiment, the pulse duration may be between 0 seconds and 1 minute. In a particular embodiment, the pulse duration may be between 1 second and 5 seconds. In one embodiment, each iteration of the cycle uses the same process gas. In other embodiments, the process gas may be changed between cycles. For example, the first cycle may utilize a first metal precursor vapor, and the second cycle may utilize a second metal precursor vapor. Subsequent cycles may continue alternately between the first and second metal precursor vapors. In one embodiment, multiple oxidant vapors may alternate between cycles in a similar manner. In one embodiment, any plasma treatment of the operation may be performed after all cycles. That is, each cycle may include a pulse of metal precursor vapor, a pulse of oxidizer vapor, and plasma treatment. In an alternative embodiment, any plasma treatment of the operation may be performed after multiple cycles. In yet another embodiment, any plasma treatment operation may be performed after the completion of all cycles (i.e., as post-treatment).

[0050] In one embodiment, the vacuum chamber used in the dry development process is any suitable chamber capable of providing a pressure below atmospheric pressure. In one embodiment, the vacuum chamber may include temperature control features for controlling the chamber wall temperature and / or the substrate temperature. In one embodiment, the vacuum chamber may further include features for supplying plasma into the chamber. A more detailed description of a suitable vacuum chamber is presented below with reference to Figure 6. Figure 6 is a schematic diagram of a vacuum chamber configured to perform dry development of a metal oxophotoresist according to one embodiment of the present disclosure.

[0051] The vacuum chamber 600 includes a grounded chamber 605. The substrate 610 is loaded through an opening 615 and clamped to a temperature-controlled chuck 620. In one embodiment, the substrate 610 may be temperature-controlled during the dry development process. For example, the temperature of the substrate 610 may be between approximately -40°C and 200°C. In a particular embodiment, the substrate 610 may be held at a temperature between room temperature and 150°C.

[0052] Process gases are supplied from a gas source 644 to the interior of the chamber 605 via respective mass flow controllers 649. In certain embodiments, a gas distribution plate 635 provides distribution of the process gases 644, such as ligands and inert gases. The chamber 605 is exhausted via an exhaust pump 655. In one embodiment, one or more process gases are contained in / stored in one or more ampoules. In one embodiment, the dry developing process is a chemical vapor condensation process, and one or more ampoules are maintained at a temperature above the substrate temperature (e.g., 25 degrees Celsius or above the substrate temperature).

[0053] When RF power is applied during processing of the substrate 610, plasma is formed within the chamber processing area on the substrate 610. A bias power RF generator 625 is coupled to a temperature-controlled chuck 620. The bias power RF generator 625 provides bias power to energize the plasma as needed. The bias power RF generator 625 may have a low frequency, for example, between about 2 MHz and 60 MHz, and in a particular embodiment, it is in the 13.56 MHz band. In a particular embodiment, the vacuum chamber 600 includes a third bias power RF generator 626 with a frequency in the about 2 MHz band, and this third bias power RF generator 626 is connected to the same RF matcher 627 as the bias power RF generator 625. A source power RF generator 630 is coupled to a plasma generating element (e.g., a gas distribution plate 635) via a match (not shown) to provide source power to energize the plasma. The source RF generator 630 may have a frequency between 100 and 180 MHz, for example, in a particular embodiment, it is in the 162 MHz band. Since substrate diameters have evolved over time from 150mm, 200mm, 300mm, etc., it is common practice in this field to normalize the source power and bias power of the plasma etching system relative to the substrate area.

[0054] The vacuum chamber 600 is controlled by a controller 670. The controller 670 may include a CPU 672, memory 673, and an I / O interface 674. The CPU 672 can execute processing operations within the vacuum chamber 600 according to instructions stored in memory 673. For example, one or more processes, such as processes 120 and 440 described above, may be executed within the vacuum chamber by the controller 670.

[0055] In another embodiment, embodiments disclosed herein include a processing tool having an architecture particularly suited for optimizing dry development. For example, the processing tool may include a pedestal for supporting a temperature-controlled wafer. In some embodiments, the temperature of the pedestal can be maintained between about -40°C and about 300°C. In addition, edge-purge flow and shadowing may be provided around the outer circumference of the column supporting the substrate. Edge-purge flow and shadowing prevent positive or negative metal oxide photoresist from depositing along the edges or back of the wafer. In one embodiment, the pedestal may provide any desired chuck structure, including but not limited to a vacuum chuck, a unipolar chuck, or a bipolar chuck, depending on the operating area of ​​the processing tool.

[0056] In some embodiments, the processing tool may be suitable for deposition processes that do not use plasma. Alternatively, the processing tool may include a plasma source that enables plasma-enhanced processing. Furthermore, while the embodiments disclosed herein are particularly suitable for the deposition of metal oxo positive or negative photoresists for EUV patterning, it should be understood that embodiments are not limited to such configurations. For example, the processing tools described herein may be suitable for the deposition of any positive or negative photoresist material for any regime of lithography using a dry development process.

[0057] Referring here to Figure 7, a cross-sectional view of the processing tool 700 is shown according to an embodiment. In one embodiment, the processing tool 700 may include a chamber 705. The chamber 705 can be any suitable chamber capable of supporting low atmospheric pressure (e.g., vacuum pressure). In an embodiment, an exhaust system (not shown) including a vacuum pump may be connected to the chamber 705 to supply low atmospheric pressure. In an embodiment, a lid may seal the chamber 705. For example, the lid may include a showerhead assembly 740. The showerhead assembly 740 may include a fluid path to allow the processing gas and / or inert gas to flow into the chamber 705. In some embodiments where the processing tool 700 is suitable for plasma enhancement operation, the showerhead assembly 740 may be electrically connected to an RF source and a matching circuit 750. In yet another embodiment, the tool 700 may consist of an RF bottom-fed architecture, i.e., a pedestal 730 is connected to an RF source and the showerhead assembly 740 is grounded. In such an embodiment, a filtering circuit may still be connected to the pedestal. In one embodiment, the precursor gas is stored in the ampoule 799.

[0058] In some embodiments, a displaceable column for supporting a wafer 701 is provided within the chamber 705. In one embodiment, the wafer 701 may be any substrate on which a positive or negative metal oxide photoresist material is deposited. For example, the wafer 701 may be a 300 mm wafer or a 450 mm wafer, but other wafer diameters may also be used. In addition, in some embodiments, the wafer 701 may be replaced with a substrate having a non-circular shape. The displaceable column may include a pillar 714 extending from the chamber 705. The pillar 714 may have ports for providing electrical and fluid pathways to various components of the column from outside the chamber 705.

[0059] In one embodiment, the column may include a base plate 710. The base plate 710 may be grounded. As will be described in more detail below, the base plate 710 may include fluid channels for allowing the flow of an inert gas and providing an edge-purging flow.

[0060] In embodiments, the insulating layer 715 is placed on the base plate 710. The insulating layer 715 may be any suitable dielectric material. For example, the insulating layer 715 may be a ceramic plate or the like. In embodiments, the pedestal 730 is placed on the insulating layer 715. The pedestal 730 may consist of a single material or be formed from different materials. In embodiments, the pedestal 730 may utilize any suitable chucking system to secure the wafer 701. For example, the pedestal 730 may be a vacuum chuck or a unipolar chuck. In embodiments where plasma is not generated in the chamber 705, the pedestal 730 may utilize a bipolar chucking architecture.

[0061] The pedestal 730 may include a plurality of cooling channels 731. The cooling channels 731 may be connected to a fluid input section and a fluid output section (not shown) passing through a pillar 714. In an embodiment, the cooling channels 731 enable control of the temperature of the wafer 701 during the operation of the processing tool 700. For example, the cooling channels 731 may enable control of the temperature of the wafer 701 between approximately -40°C and approximately 300°C. In one embodiment, the pedestal 730 is connected to ground via a filtering circuit 745, thereby enabling DC and / or RF biasing of the pedestal to ground.

[0062] In an embodiment, the edge ring 720 surrounds the outer periphery of the insulating layer 715 and the pedestal 730. The edge ring 720 may be made of a dielectric material such as ceramic. In an embodiment, the edge ring 720 is supported by a base plate 710. The edge ring 720 may support a shadow ring 735. The shadow ring 735 has an internal diameter smaller than the diameter of the wafer 701. In this way, the shadow ring 735 prevents positive-tone metal oxide photoresist or negative-tone metal oxide photoresist from being deposited on a portion of the outer edge of the wafer 701. A gap is provided between the shadow ring 735 and the wafer 701. This gap prevents the shadow ring 735 from contacting the wafer 701 and provides an outlet for the edge purge flow, which will be described in more detail below. In one embodiment, a dual-channel showerhead can be used in a positive-type or negative-type metal oxide photoresist manufacturing process.

[0063] The shadow ring 735 provides some protection to the top surface and edges of the wafer 701, but the processing gas can flow / diffuse downward along the path between the edge ring 720 and the wafer 701. Thus, embodiments disclosed herein may include a fluid path between the edge ring 720 and the pedestal 730 to enable edge purging flow. By supplying an inert gas into the fluid path, the local pressure within the fluid path is increased, preventing the processing gas from reaching the edges of the wafer 701. Therefore, deposition of positive or negative metal oxide photoresist along the edges of the wafer 701 is prevented.

[0064] Referring now to Figure 8, an enlarged cross-sectional view of a portion of column 860 in the processing tool according to the embodiment is shown. In Figure 8, only the left edge of column 860 is shown. However, it will be understood that the right edge of column 860 can substantially mirror the left edge.

[0065] In one embodiment, the column 860 may include a base plate 810. An insulating layer 815 may be placed on the base plate 810. In one embodiment, the pedestal 830 may include a first portion 830A and a second portion 830B. A cooling channel 831 may be located in the second portion 830B. The first portion 830A may include features for chucking the wafer 801.

[0066] In one embodiment, the edge ring 820 surrounds the base plate 810, the insulating layer 815, the pedestal 830, and the wafer 801. In one embodiment, the edge ring 820 is positioned at a distance from other components of the column 850 to provide a fluid path 812 from the base plate 810 to the upper surface of the column 850. For example, the fluid path 812 may exit the column between the wafer 801 and the shadow ring 835. In a particular embodiment, the inner surface of the fluid path 812 includes the edge of the insulating layer 815, the edge of the pedestal 830 (i.e., the first portion 830A and the second portion 830B), and the edge of the wafer 801. In one embodiment, the outer surface of the fluid path 812 includes the inner edge of the edge ring 820. In one embodiment, the fluid path 812 may also continue on the upper surface of a portion of the pedestal 830 as it progresses to the edge of the wafer 801. In this way, by flowing an inert gas (e.g., helium, argon, etc.) through the fluid path 812, the processing gas is prevented from flowing down / diffusing along the side of the wafer 801.

[0067] In one embodiment, the width W of the fluid path 812 is minimized to prevent plasma collisions along the fluid path 812. For example, the width W of the fluid path 812 may be about 1 mm or less. In an embodiment, a seal 817 prevents the fluid path 812 from exiting the bottom of the column 860. The seal 817 may be positioned between the edge ring 820 and the base plate 810. The seal 817 may be made of a flexible material such as gasket material. In certain embodiments, the seal 817 includes silicone.

[0068] In this embodiment, the channel 811 is located on the base plate 810. The channel 811 routes an inert gas from the center of the column 860 to the inner edge of the edge ring 820. It will be understood that only a portion of the channel 811 is illustrated in Figure 8. A more comprehensive diagram of the channel 811 is provided below with respect to Figure 10B.

[0069] In one embodiment, the edge ring 820 and the shadow ring 835 may have features suitable for aligning the shadow ring 835 with respect to the wafer 801. For example, a notch 821 on the upper surface of the edge ring 820 may interface with a projection 836 on the lower surface of the shadow ring 835. The notch 821 and the projection 836 may have tapered surfaces to allow for rough alignment of the two components, which is sufficient for more accurate alignment when the edge ring 820 contacts the shadow ring 835. In an additional embodiment, alignment features (not shown) may be provided between the pedestal 830 and the edge ring 820. The alignment features between the pedestal 830 and the edge ring 820 may include tapered notches and projection structures similar to those of the alignment features between the edge ring 820 and the shadow ring 835.

[0070] Referring now to Figures 9A and 9B, a pair of cross-sectional views are shown illustrating a portion of a processing tool having a pedestal at different positions (in the Z direction) according to one embodiment. In Figure 9A, the pedestal is in a lower position within the chamber. The position of the pedestal in Figure 9A is where the wafer is inserted into or removed from the chamber through the slit valve. In Figure 9B, the pedestal is in an elevated position within the chamber. The position of the pedestal in Figure 9B is where the wafer is processed.

[0071] Referring now to Figure 9A, a cross-sectional view of a displaceable column 960 in a first position according to the embodiment is shown. As shown in Figure 9A, the column includes a base plate 910, an insulating layer 915, a pedestal 930 (i.e., a first portion 930A and a second portion 930B), and an edge ring 920. Such components may be substantially similar to the components of similar names described above. For example, a cooling channel 931 may be provided in the second portion 930B of the pedestal 930, a channel 911 may be located within the base plate 910, and a seal 917 may be provided between the edge ring 920 and the base plate 910.

[0072] As shown in Figure 9A, the wafer 901 is placed on the upper surface of the pedestal 930. The wafer 901 can be inserted into the chamber through a slit valve (not shown). In addition, the shadow ring 935 is positioned higher than the edge ring 920. Since the inner diameter of the shadow ring 935 is smaller than the diameter of the wafer 901, the wafer 901 must be placed on the pedestal before the shadow ring 935 can come into contact with the edge ring 920.

[0073] In one embodiment, the shadow ring 935 is supported by a chamber liner 970, which may surround the outer circumference of the column 960. In one embodiment, a holder 971 is positioned on the upper surface of the chamber liner 970. The holder 971 is configured to hold the shadow ring 935 in an elevated position above the edge ring 920 when the column 960 is in a first position. In one embodiment, the shadow ring 935 includes a projection 936 for alignment with a notch 921 of the edge ring 920.

[0074] Referring now to Figure 9B, a cross-sectional view of the column 960 after the shadow ring 935 has been engaged is shown according to one embodiment. As shown, the column 960 is displaced vertically (i.e., in the Z direction) until the shadow ring 935 engages with the edge ring 920. Further vertical displacement of the column 960 lifts the shadow ring 935 from the holder 971 on the chamber liner 970. In one embodiment, the shadow ring 935 is properly aligned as a result of alignment features (i.e., notches 921 and protrusions 936) between the shadow ring 935 and the edge ring 920. In an additional embodiment, alignment features (not shown) may be provided between the pedestal 930 and the edge ring 920. The alignment features between the pedestal 930 and the edge ring 920 may include tapered notches and protrusions similar to those of the alignment features between the edge ring 920 and the shadow ring 935.

[0075] While in the second position, the wafer 901 may be processed. In particular, the processing may include depositing a positive or negative metal oxide photoresist material onto the upper surface of the wafer 901. For example, the process may be a dry development process with or without plasma assistance. In certain embodiments, the positive or negative photoresist is a metal oxo-type positive or negative photoresist suitable for EUV patterning. However, it should be understood that the positive or negative photoresist may be any type of positive or negative photoresist, and the patterning may include any lithography method. During the deposition of the positive or negative metal oxide photoresist on the wafer 901, an inert gas may be flowed along the fluid channels between the inner surface of the edge ring 910 and the insulating layer 915, the pedestal 930, and the outer surface of the wafer 901. Thus, the deposition of the positive or negative metal oxide photoresist along the edge or back side of the wafer 901 is substantially eliminated. In one embodiment, the wafer temperature 901 can be maintained between approximately -40°C and approximately 200°C by the cooling channel 931 of the second portion of the pedestal 930B.

[0076] Referring here to Figure 10A, a cross-sectional view of a processing tool 1000 according to an additional embodiment is shown. As shown in Figure 10A, the column includes a base plate 1010. The base plate 1010 may be supported by pillars 1014 extending from the chamber. That is, in some embodiments, the base plate 1010 and pillars 1014 may be discrete components instead of a single, integrated component as shown in Figure 7. The pillars 1014 may have a central channel for electrical connections and routing of fluids (e.g., cooling fluid and inert gas for purge flow).

[0077] In one embodiment, an insulating layer 1015 is placed on a base plate 1010, and a pedestal 1030 (i.e., a first portion 1030A and a second portion 1030B) is placed on top of the insulating layer 1015. In one embodiment, a coolant channel 1031 is provided in the second portion 1030B of the pedestal 1030. A wafer 1001 is placed on top of the pedestal 1030.

[0078] In one embodiment, a base plate 1010, an insulating layer 1015, a pedestal 1030, and an edge ring 1020 are provided around the wafer 1001. The edge ring 1020 can be connected to the base plate 1013 by a fastening mechanism 1013 such as bolts, pins, or screws. In one embodiment, a seal 1017 prevents purge gas from escaping the column from the bottom of the gap between the base plate 1010 and the edge ring 1020.

[0079] In the illustrated embodiment, the pedestal 1030 is in a first position. Thus, the shadow ring 1035 is supported by the holder 1071 and the chamber liner 1070. When the pedestal 1030 is displaced vertically, the edge ring 1020 engages with the shadow ring 1035, lifting the shadow ring 1035 from the holder 1071.

[0080] Referring now to Figure 10B, a cross-sectional view of the chamber 1000 according to an additional embodiment is shown. In the diagram of Figure 10B, the insulating layer 1015 and pedestal 1030 are omitted to more clearly see the structure of the base plate 1010. As shown, the base plate 1010 may include a plurality of channels 1011 that provide fluid routing from the center of the base plate 1010 to the edges of the base plate 1010. In the illustrated embodiment, a plurality of first channels connect the center of the base plate 1010 to a first ring channel, and a plurality of second channels connect the first ring channel to the outer edges of the base plate 1010. In one embodiment, the first and second channels are offset from each other. Although a specific configuration of the channels 1011 is shown in Figure 10B, it should be understood that any channel configuration can be used to route an inert gas from the center of the base plate 1010 to the edges of the base plate 1010.

[0081] Figure 11 shows a schematic diagram of an exemplary machine, computer system 1100, but within computer system 600, a set of instructions may be executed to cause the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine may be connected to other machines (e.g., network-connected) in a local area network (LAN), intranet, extranet, or internet. The machine may operate in a client-server network environment as a server or client machine, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), tablet PC, set-top box (STB), portable information terminal (PDA), mobile phone, web device, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or different) that specify the operation to be performed by the machine. Furthermore, although only a single machine is shown, the term “machine” may be interpreted to include any collection of machines (e.g., computers) that individually or collectively execute a set (or more sets) of instructions to perform any one or more of the methods described herein.

[0082] An exemplary computer system 1100 includes a processor 1102, main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (synchronous DRAM (SDRAM) or rhombus DRAM (RDRAM), etc.)), static memory 1106 (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and secondary memory 1118 (e.g., data storage device), all communicating with each other via a bus 1130.

[0083] The processor 1102 represents one or more general-purpose processing devices, such as a microprocessor or a central processing device. More specifically, the processor 1102 may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processor 1102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processor 1102 is configured to execute processing logic 1126 for performing the operations described herein.

[0084] The computer system 1100 may further include a network interface device 1108. The computer system 1100 may also include a video display unit 1110 (e.g., a liquid crystal display (LCD), a light-emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), and a signal generation device 1116 (e.g., a speaker).

[0085] The secondary memory 1118 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 1132 storing one or more sets of instructions (e.g., software 1122) that embody one or more of the methods or functions described herein. This software 1122 may also reside, all or at least partially, in the main memory 1104 and / or the processor 1102 while being executed by the computer system 1100. The main memory 1104 and the processor 1102 further constitute a machine-readable storage medium. The software 1122 may also be transmitted and received over the network 1120 via the network interface device 1108.

[0086] In the exemplary embodiments, the machine-accessible storage medium 1132 is shown as a single medium, but the term “machine-readable storage medium” should be understood to include a single medium or multiple mediums that store one or more sets of instructions (e.g., a centralized or distributed database, and / or associated caches and servers). The term “machine-readable storage medium” should be interpreted to include any medium capable of storing or encoding a set of instructions executed by a machine, which causes the machine to execute any one or more of the methods of the Disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted to include, but not be limited to, solid memory, optical media, and magnetic media.

[0087] According to one embodiment of the present disclosure, a machine-accessible storage medium stores instructions causing a data processing system to perform a dry development method for a positive or negative metal oxide photoresist layer.

[0088] Therefore, a method for dry development of positive or negative photoresist is disclosed.

Claims

1. A method for patterning metal oxide photoresists, The process involves depositing the aforementioned metal oxide photoresist onto a substrate, The metal oxide photoresist is exposed to extreme ultraviolet (EUV) light to form exposed and unexposed regions. Develop the exposed metal oxide photoresist using an electron donor ligand-based dry etching process. A method that includes this.

2. The method according to claim 1, further comprising developing the exposed metal oxide photoresist, which includes a wet development process prior to performing the electron donor ligand-based dry etching process.

3. The method according to claim 1, wherein developing the exposed metal oxide photoresist does not involve using a wet development process in conjunction with the electron donor ligand-based dry etching process.

4. The method according to claim 1, wherein the metal oxide photoresist is a positive-type photoresist or a negative-type photoresist.

5. The method according to claim 1, wherein the electron donor ligand-based dry etching process includes the use of hexafluoroacetylacetone (hfacH).

6. The method according to claim 1, wherein developing the exposed metal oxide photoresist includes removing the unexposed region.

7. The method according to claim 1, wherein developing the exposed metal oxide photoresist includes removing the exposed region.

8. A method for patterning metal oxide photoresists, The process involves depositing the aforementioned metal oxide photoresist onto a substrate, The metal oxide photoresist is exposed to extreme ultraviolet (EUV) light to form exposed and unexposed regions. The process involves treating the exposed metal oxide photoresist using a fluorination process, Develop the exposed and fluorinated metal oxide photoresist using an electron donor ligand-based dry etching process. A method that includes this.

9. The method according to claim 8, further comprising a wet development process prior to performing the electron donor ligand-based dry etching process, wherein the exposed and fluorinated metal oxide photoresist is developed.

10. The method according to claim 8, wherein developing the exposed and fluorinated metal oxide photoresist does not involve using a wet development process in conjunction with the electron donor ligand-based dry etching process.

11. The method according to claim 8, wherein the metal oxide photoresist is a positive-type photoresist or a negative-type photoresist.

12. The method according to claim 8, wherein the electron donor ligand-based dry etching process includes the use of hexafluoroacetylacetone (hfacH).

13. The method according to claim 8, wherein developing the exposed and fluorinated metal oxide photoresist includes removing the unexposed regions.

14. The method according to claim 8, wherein developing the exposed and fluorinated metal oxide photoresist includes removing the exposed region.

15. A method for patterning metal oxide photoresists, The process involves depositing the aforementioned metal oxide photoresist onto a substrate, The metal oxide photoresist is exposed to extreme ultraviolet (EUV) light to form exposed and unexposed regions. (1) The exposed metal oxide photoresist is developed by repeatedly processing it using a fluorination process, and (2) using an electron donor ligand-based dry etching process. A method that includes this.

16. The method according to claim 15, wherein developing the exposed metal oxide photoresist does not involve using a wet development process.

17. The method according to claim 15, wherein the metal oxide photoresist is a positive-type photoresist or a negative-type photoresist.

18. The method according to claim 15, wherein the electron donor ligand-based dry etching process includes the use of hexafluoroacetylacetone (hfacH).

19. The method according to claim 15, wherein developing the exposed metal oxide photoresist includes removing the unexposed region.

20. The method according to claim 15, wherein developing the exposed metal oxide photoresist includes removing the exposed region.

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