Display board and method for manufacturing the same, display device

Abstract

The present invention relates to a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a base, a plurality of subpixels and a plurality of transparent conductive layers 300 installed on the base, each subpixel includes at least one transparent conductive layer 300, at least some subpixels include at least a second transistor and a third transistor, and the second pole of the second transistor and the second pole of the third transistor located in the same subpixel are electrically connected via at least one transparent conductive layer 300.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly relates to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] An organic light emitting diode (abbreviated as OLED) is an active light emitting display device, which has advantages such as light emission, ultra-thin, wide viewing angle, high brightness, high contrast ratio, low power consumption, and extremely high response speed. With the continuous development of display technology, OLED technology is increasingly widely applied in flexible display devices and has become a next-generation display technology with great development potential. According to the driving method, OLEDs can be divided into two types: passive matrix driving (abbreviated as PM) type and active matrix driving (abbreviated as AM) type. AMOLED is a current-driven device, and each sub-pixel is controlled by an independent thin film transistor (abbreviated as TFT), and each sub-pixel can be continuously and individually driven to emit light.

Summary of the Invention

[0003] The following is an overview of the subject matter that will be described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, including a base, and a plurality of sub-pixels and a plurality of transparent conductive layers disposed on the base. Each sub-pixel includes at least one transparent conductive layer. At least some sub-pixels include at least a second transistor and a third transistor. The second electrode of the second transistor and the second electrode of the third transistor located in the same sub-pixel are electrically connected through at least one transparent conductive layer.

[0005] In exemplary embodiments, at least a portion of the transparent conductive layer includes an anode, a first connecting electrode, and a second connecting electrode, and within the same transparent conductive layer, the anode is electrically connected to the first connecting electrode and the second connecting electrode. In the same subpixel, the second pole of the second transistor is electrically connected to the corresponding anode via the first connecting electrode, the second pole of the third transistor is electrically connected to the corresponding anode via the second connecting electrode, and the second pole of the second transistor and the second pole of the third transistor are electrically connected via the corresponding first connecting electrode, second connecting electrode, and anode.

[0006] In an exemplary embodiment, the first connecting electrode and the second connecting electrode and the corresponding anode are integrally molded structures.

[0007] In an exemplary embodiment, the display substrate further includes a pixel definition layer, the pixel definition layer located on the side of the transparent conductive layer away from the base, the pixel definition layer having a plurality of pixel apertures formed thereon, each subpixel including at least one pixel aperture, there being an overlapping region between the orthographic projection of the pixel aperture on the base and the orthographic projection of the corresponding anode on the base, and the transparent conductive layer is located in the light-emitting region of the corresponding subpixel.

[0008] In an exemplary embodiment, the second pole of the second transistor is electrically connected to the corresponding first connecting electrode via a first relay via, the orthographic projection of the first relay via on its base lies within the range of the orthographic projection of the first connecting electrode on its base; the second pole of the third transistor is electrically connected to the corresponding second connecting electrode via a second relay via, the orthographic projection of the second relay via on its base lies within the range of the orthographic projection of the second connecting electrode on its base; the minimum distance from the first relay via to the corresponding pixel aperture edge is less than the minimum distance from the second relay via to the corresponding pixel aperture edge; and the first and second relay vias are located on either side of the corresponding pixel aperture.

[0009] In an exemplary embodiment, the plurality of subpixels are arranged along row and column directions, and in the row direction, the distance between two adjacent subpixels and a first relay via includes a first distance and a second distance, the first distance being greater than the second distance, and the first and second distances are arranged alternately along the row direction.

[0010] In an exemplary embodiment, in the row direction, the distance between two adjacent subpixels and a second relay via includes a third distance and a fourth distance, wherein the third distance is greater than the fourth distance, and the third and fourth distances are arranged alternately along the row direction.

[0011] In an exemplary embodiment, in the same subpixel, the second and third transistors are located on opposite sides of the corresponding anode in the column direction, and the distance between the second and third transistors is greater than 0.5 times the size along the column direction of the subpixel.

[0012] In an exemplary embodiment, the display board further includes a plurality of data signal lines and a plurality of auxiliary data lines, each of the plurality of data signal lines being electrically connected to the plurality of auxiliary data lines, the data signal lines and the auxiliary data lines being located on different conductive layers, and in a direction perpendicular to the plane on which the display board is located, the conductive layers on which the data signal lines and the auxiliary data lines are located are located between the base and the transparent conductive layer, and the orthographic projection of the plurality of data signal lines on the base at least partially overlaps with the orthographic projection of the plurality of auxiliary data lines on the base.

[0013] In an exemplary embodiment, the display substrate includes a gate metal layer mounted on the base, and at least some of the auxiliary data lines are located on the gate metal layer.

[0014] In an exemplary embodiment, the display substrate further includes a shielding metal layer, wherein, in a direction perpendicular to the plane on which the display substrate is located, the gate metal layer is located on the side of the shielding metal layer away from the base, and the plurality of data signal lines are located on the shielding metal layer.

[0015] In an exemplary embodiment, the shield metal layer is further provided with a plurality of first power lines, the gate metal layer is further provided with a plurality of first auxiliary power lines, each of the plurality of first power lines is electrically connected to the plurality of first auxiliary power lines, and the orthographic projection of each of the plurality of first power lines on the base overlaps at least partially with the orthographic projection of each of the plurality of first auxiliary power lines on the base.

[0016] In an exemplary embodiment, the plurality of subpixels form a plurality of pixel units arranged in an array, each pixel unit comprising at least three subpixels, the gate metal layer further comprising a plurality of first power supply connection lines, each pixel unit comprising two of the first power supply auxiliary lines, both ends of the first power supply connection lines located in the same pixel unit being connected to two of the first power supply auxiliary lines, the main portion of the first power supply auxiliary lines extending along a second direction in a plane parallel to the display substrate, the main portion of the first power supply connection lines extending along a first direction, and the first and second directions intersect.

[0017] In an exemplary embodiment, the display substrate further includes a semiconductor layer, the semiconductor layer being located away from the base of the shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer being provided with a plurality of compensation connection lines, the shield metal layer being provided with a plurality of compensation signal lines, the compensation connection lines being in a stripe structure extending along a first direction in a plane parallel to the display substrate, the compensation signal lines being in a stripe structure extending along a second direction, the first and second directions intersecting, and the compensation connection lines being electrically connected to at least one compensation signal line.

[0018] In an exemplary embodiment, the display substrate further includes a source-drain metal layer, the source-drain metal layer being located away from the base of the gate metal layer in a direction perpendicular to the plane on which the display substrate is located, and the plurality of data signal lines being located on the source-drain metal layer.

[0019] In an exemplary embodiment, the display substrate further includes a second shield metal layer, the second shield metal layer located between the base and the gate metal layer in a direction perpendicular to the plane on which the display substrate is located, the plurality of auxiliary data lines include a plurality of first auxiliary data lines and a plurality of second auxiliary data lines, the plurality of first auxiliary data lines are located in the second shield metal layer, the plurality of second auxiliary data lines are located in the gate metal layer, there is an overlapping region between the orthographic projection of the plurality of first auxiliary data lines and the plurality of second auxiliary data lines on the base and the orthographic projection of the corresponding plurality of data signal lines on the base, and the plurality of first auxiliary data lines and the plurality of second auxiliary data lines are electrically connected to the corresponding plurality of data signal lines.

[0020] In an exemplary embodiment, the source-drain metal layer is further provided with a plurality of first power lines, the gate metal layer is further provided with a plurality of first auxiliary power lines, each of the plurality of first power lines is electrically connected to the plurality of first auxiliary power lines, and the orthographic projection of each of the plurality of first power lines on the base overlaps at least partially with the orthographic projection of each of the plurality of first auxiliary power lines on the base.

[0021] In an exemplary embodiment, the plurality of subpixels form a plurality of pixel units arranged in an array, each pixel unit comprising at least three subpixels, the display substrate further comprising a semiconductor layer, the semiconductor layer located away from the base of the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer is provided with a plurality of first power supply lines, each pixel unit comprises two of the first power supply lines, both ends of the first power supply lines located in the same pixel unit are electrically connected to the two first power supply lines, the main portion of the first power supply lines extends along a second direction in a plane parallel to the display substrate, and the first and second directions intersect.

[0022] In an exemplary embodiment, the second shield metal layer is further provided with a plurality of compensation connection lines, and the source drain metal layer is further provided with a plurality of compensation signal lines, wherein in a plane parallel to the display substrate, the compensation connection lines have a stripe structure extending along a first direction, and the compensation signal lines have a stripe structure extending along a second direction, the first and second directions intersect, and the compensation connection lines are electrically connected to at least one compensation signal line.

[0023] In an exemplary embodiment, the display substrate further includes a first shield metal layer, the first shield metal layer positioned between the base and the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the first shield metal layer is provided with a plurality of first scan signal lines, the second shield metal layer is provided with a plurality of first scan signal auxiliary lines, each electrically connected to the plurality of first scan signal lines, and the orthographic projection of the plurality of first scan signal lines on the base at least partially overlaps with the orthographic projection of the plurality of first scan signal auxiliary lines on the base.

[0024] In an exemplary embodiment, the thickness of the first shield metal layer is greater than the thickness of the second shield metal layer.

[0025] In an exemplary embodiment, the display substrate further includes a first conductive layer, the first conductive layer located between the base and the transparent conductive layer, the subpixel further includes a capacitor, the first conductive layer includes a first plate of the capacitor, the first plate is transparent, the anode is reused as a second plate of the capacitor, and in the same subpixel, there is a first overlapping region between the orthographic projection of the first plate on the base and the orthographic projection of the second plate on the base, the first overlapping region located in the light-emitting region of the subpixel.

[0026] In an exemplary embodiment, the display substrate further includes a first conductive layer, the first conductive layer being located between the base and the transparent conductive layer, the subpixel further includes a capacitor, the first conductive layer includes a first plate of the capacitor, the first plate having a transparent structure, The display substrate further includes a gate metal layer, the transparent conductive layer is located on the gate metal layer, the transparent conductive layer is reused as the second electrode plate of the capacitor, and there is a first overlapping region between the orthographic projection of the first electrode plate on the base and the orthographic projection of the second electrode plate on the base, and the first overlapping region is located in the light-emitting region of the sub-pixel.

[0027] In another aspect, the present disclosure further provides a display device including the above-mentioned display substrate.

[0028] In another aspect, the present disclosure further provides a method for manufacturing a display substrate, including forming a plurality of sub-pixels and a plurality of transparent conductive layers on one side of a base, at least some of the sub-pixels including at least a second transistor and a third transistor, and the second electrodes of the second transistor and the third transistor located in the same sub-pixel being electrically connected through at least one transparent conductive layer.

[0029] After reading and understanding the drawings and the detailed description, other aspects can be understood.

Brief Description of the Drawings

[0030] The drawings are provided for a further understanding of the technical solutions of the present disclosure, and are part of the specification. They are used to interpret the technical solutions of the present disclosure together with the embodiments of the present disclosure, rather than to limit the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual proportions, but are for schematically explaining the content of the present disclosure. [Figure 1] It is a schematic structural diagram of a display device. [Figure 2] It is a schematic plan view of a display substrate. [Figure 3] It is a schematic cross-sectional view of a display substrate. [Figure 4] It is a schematic equivalent circuit diagram of a pixel driving circuit. [Figure 5a] It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 5b] It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 5c] Figures 5a and 5b show schematic equivalent circuits of the pixel driving circuits for the four subpixels. [Figure 6] This is a schematic diagram after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure. [Figure 7a] This is a schematic diagram of the second conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 7b] This is a schematic plan view of the second conductive layer in Figure 7a. [Figure 8a] This is a schematic diagram of a semiconductor layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 8b] This is a schematic plan view of the semiconductor layer in Figure 8a. [Figure 9] This is a schematic diagram of the second insulating layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 10a] This is a schematic diagram of the third conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 10b] This is a schematic plan view of the third conductive layer in Figure 10a. [Figure 10c] This is a schematic diagram of the cross-sectional structure at position A1-A1 in Figure 10a. [Figure 10d] This is a schematic diagram of the cross-sectional structure at position A2-A2 in Figure 10a. [Figure 11] This is a schematic diagram of a flat layer pattern formed according to an exemplary embodiment of the present disclosure. [Figure 12a] This is a schematic diagram of the fourth conductive layer pattern after formation according to the exemplary embodiment of the present disclosure. [Figure 12b] This is a schematic plan view of the fourth conductive layer in Figure 12a. [Figure 13a] This is a schematic diagram of the pixel definition layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 13b] Figure 13a is a schematic plan view of the pixel definition layer. [Figure 14] This is a schematic diagram after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure. [Figure 15]This is a schematic diagram of the second conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 16a] This is a schematic diagram of the third conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 16b] This is a schematic plan view of the third conductive layer in Figure 16a. [Figure 17a] This is a schematic diagram of a semiconductor layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 17b] Figure 17a is a schematic plan view of the semiconductor layer. [Figure 18a] This is a schematic diagram of the fourth conductive layer pattern after formation according to the exemplary embodiment of the present disclosure. [Figure 18b] This is a schematic plan view of the fourth conductive layer in Figure 18a. [Figure 19] This is a schematic diagram after the formation of the third insulating layer pattern according to an exemplary embodiment of the present disclosure. [Figure 20a] This is a schematic diagram showing the fifth conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 20b] This is a schematic plan view of the fifth conductive layer in Figure 20a. [Figure 21] This is a schematic diagram of a flat layer pattern formed according to an exemplary embodiment of the present disclosure. [Figure 22a] This is a schematic diagram of the sixth conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 22b] This is a schematic plan view of the sixth conductive layer in Figure 20a. [Figure 23a] This is a schematic diagram of the pixel definition layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 23b] Figure 23a is a schematic plan view of the pixel definition layer. [Figure 23c] This is a schematic diagram of the cross-sectional structure at position A3-A3 in Figure 22a. [Figure 24a] This is a schematic plan view of a semiconductor layer according to an exemplary embodiment of the present disclosure. [Figure 24b] This is a schematic diagram of the fourth conductive layer pattern after formation according to the exemplary embodiment of the present disclosure. [Figure 24c]This is a schematic plan view of the fourth conductive layer in Figure 24b. [Figure 24d] This is a schematic diagram after the formation of the third insulating layer pattern according to an exemplary embodiment of the present disclosure. [Figure 24e] This is a schematic diagram showing the fifth conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 24f] This is a schematic plan view of the fifth conductive layer in Figure 24e. [Figure 25a] This is a schematic diagram of the fourth conductive layer pattern after formation according to the exemplary embodiment of the present disclosure. [Figure 25b] This is a schematic diagram showing the fifth conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Figure 25c] This is a schematic diagram of the sixth conductive layer pattern after formation according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0031] To further clarify the purpose, technical proposals, and advantages of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments can be carried out in many different forms. The methods and content can be transformed into various forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, embodiments and features of embodiments of this disclosure can be combined with each other.

[0032] The proportions in the drawings in this disclosure may, but are not limited to, those shown in the drawings for reference in actual processes. For example, the ratio of channel width to length, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels on the display substrate and the number of subpixels in each pixel are not limited to those shown in the drawings, and the drawings described in this disclosure are merely schematic diagrams of the structure. One aspect of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0033] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion regarding the constituent elements and do not limit them in terms of quantity.

[0034] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0035] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or an electrical connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the specific meaning of these terms in this disclosure depending on the specific context.

[0036] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0037] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be converted to each other, and the "source terminal" and the "drain terminal" can be converted to each other.

[0038] In this specification, "electrically connected" includes cases where components are connected via an element having an electrical function. The "element having an electrical function" is not particularly limited and only needs to be capable of transmitting and receiving electrical signals between the connected components. Examples of "elements having an electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements with various other functions.

[0039] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0040] In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0041] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0042] In this disclosure, "approximately" means that the boundary is not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0043] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device comprises a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to the data driver and the scan driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to D), and the scan driver is connected to a plurality of scan signal lines (S1 to Sm). The pixel array includes a plurality of sub-pixels Pxij, where i and j are natural numbers. At least one sub-pixel Pxij includes a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit includes at least one scan signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller provides the data driver with gray values ​​and control signals conforming to the data driver's specifications, and provides the scan driver with a clock signal, a scan start signal, etc., conforming to the scan driver's specifications. The data driver uses the gray values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., D. For example, a data driver can use a clock signal to sample gray values ​​and apply data voltages corresponding to the gray values ​​to data signal lines D1-D, with n being a natural number. A scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving a clock signal, scan start signal, etc., from a timing controller. For example, a scan driver can sequentially provide scan signals having turn-on level pulses to scan signal lines S1-Sm. For example, a scan driver can be configured in the form of a shift register and generate scan signals by sequentially transporting scan start signals, provided in the form of turn-on level pulses, to the next level of circuitry under the control of a clock signal, with m being a natural number.

[0044] Figure 2 is a schematic diagram of the planar structure of a display board. As shown in Figure 2, the display board includes a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color ray, a second subpixel P2 that emits a second color ray, a third subpixel P3 that emits a third color ray, and a fourth subpixel P4 that emits a fourth color ray. Each of the four subpixels may include a circuit unit and a light-emitting device. The circuit unit includes a scan signal line, a data signal line, and a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive a data voltage transported from the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in each subpixel is connected to the pixel driving circuit of the subpixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output from the pixel driving circuit of the subpixel in which it is located.

[0045] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light rays, the second subpixel P2 may be a white subpixel (W) that emits white light rays, the third subpixel P3 may be a blue subpixel (B) that emits blue light rays, and the fourth subpixel P4 may be a green subpixel (G) that emits green light rays.

[0046] In exemplary embodiments, the shape of the subpixels may be rectangular, rhombus, pentagonal, or hexagonal. In one exemplary embodiment, four subpixels may be arranged in a horizontal parallel manner to constitute an RWBG pixel arrangement. In other exemplary embodiments, the four subpixels may be arranged in a square, diamond, or vertical parallel manner, etc., and are not limited to the present disclosure.

[0047] In a representative embodiment, multiple subpixels arranged sequentially in the horizontal direction are called pixel rows, and multiple subpixels arranged sequentially in the vertical direction are called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array.

[0048] Figure 3 is a schematic cross-sectional view of the display substrate, showing the structure of the four subpixels of the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, each subpixel on the display substrate may include a drive circuit layer 102 installed on the base 101, a light-emitting structure layer 103 installed on the side of the drive circuit layer 102 away from the base, and an encapsulation layer 104 installed on the side of the light-emitting structure layer 103 away from the base.

[0049] In exemplary embodiments, the base 101 may be a flexible base or a rigid base. The drive circuit layer 102 of each subpixel may include a pixel drive circuit consisting of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each subpixel may include a light-emitting device consisting of a plurality of film layers, the plurality of film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304, the anode 301 being connected to the pixel drive circuit, the organic light-emitting layer 303 being connected to the anode 301 and the cathode 304 being connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emitting light rays of the corresponding colors by driving the anode 301 and the cathode 304. The encapsulation layer 104 includes a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 which are stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 employ inorganic materials, and the second encapsulation layer 402 employs an organic material. The second encapsulation layer 402 is installed between the first encapsulation layer 401 and the third encapsulation layer 403, preventing external water vapor from entering the light-emitting structure layer 103.

[0050] In exemplary embodiments, the organic light-emitting layer may include a stacked hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), light-emitting layer (EML), hole blocking layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In exemplary embodiments, the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all subpixels may be a connected common layer, the light-emitting layers of all subpixels may be a connected common layer or may be separated from each other, and the light-emitting layers of adjacent subpixels may have a small overlap. In several possible realizations, the display substrate may include other film layers, and is not limited to these.

[0051] In exemplary embodiments, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 is a schematic equivalent circuit diagram of the pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 3T1C structure and may include three transistors (first transistor T1, second transistor T2, and third transistor T3), one storage capacitor C, and six signal lines (data signal line D, first scan signal line S1, second scan signal line S2, compensation signal line S, first power line VDD, and second power line VSS). In Figure 4, C_e is the intrinsic capacitance of the OLED.

[0052] In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor. The first pole of the storage capacitor C is coupled to the control pole of the second transistor T2, and the second pole of the storage capacitor C is coupled to the second pole of the second transistor T2. The storage capacitor C is used to store the potential of the control pole of the second transistor T2. The control pole of the first transistor T1 is coupled to the first scan signal line S1, the first pole of the first transistor T1 is coupled to the data signal line D, and the second pole of the first transistor T1 is coupled to the control pole of the second transistor T2. The first transistor T1 is used to receive a data signal transmitted from the data signal line D under the control of the first scan signal line S1, and to cause the control pole of the second transistor T2 to receive the data signal. The control pole of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power line VDD, and the second pole of the second transistor T2 is coupled to the first pole of the light-emitting device. The second transistor T2 is used to generate a corresponding current in its second pole under the control of the data signal received by its control pole. The control pole of the third transistor T3 is coupled to the second scan signal line S2, the first pole of the third transistor T3 is connected to the compensation signal line S, and the second pole of the third transistor T3 is coupled to the second pole of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing and to compensate the threshold voltage Vth.

[0053] In exemplary embodiments, the light-emitting device may be an OLED and includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). The first electrode of the OLED is coupled to the second electrode of a second transistor T2, and the second electrode of the OLED is coupled to a second power line VSS. The OLED is used to emit light of a corresponding brightness in response to the current in the second electrode of the second transistor T2.

[0054] In an exemplary embodiment, the signal on the first power line VDD is a continuously supplied high-level signal, and the signal on the second power line VSS is a low-level signal. The first transistor T1 to the third transistor T3 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved.

[0055] In exemplary embodiments, the first to third transistors T1 to T3 may be low-temperature polysilicon film transistors, oxide film transistors, or both low-temperature polysilicon film transistors and oxide film transistors. The active layer of the low-temperature polysilicon film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide film transistor is made of oxide. Low-temperature polysilicon film transistors have advantages such as high mobility and fast charging, while oxide film transistors have advantages such as low leakage current. In exemplary embodiments, by integrating low-temperature polysilicon film transistors and oxide film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized to achieve high resolution (Pixels Per Inch, PPI), low-frequency driving, reduce power consumption, and improve display attributes. In exemplary embodiments, the light-emitting device may be an organic light-emitting transistor (OLED), and includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0056] In an exemplary embodiment, taking the case where all three transistors are N-type transistors, the operation process of the pixel driving circuit shown in Figure 4 may include the following steps.

[0057] In the first stage A1, the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals, the data signal line D outputs a data voltage, the compensation signal line S outputs a compensation voltage, the signal on the first power line VDD is high-level, and the signal on the second power line VSS is low-level. The signal on the first scan signal line S1 is a high-level signal, turning on the first transistor T1, the data voltage output from the data signal line D is written to the first node N1, the potential of the first node N1 is pulled up, and the storage capacitor C is charged, at which point the potential of the first node N1 is V1=V data Therefore, the signal on the second scan signal line S2 is a high-level signal, which turns on the third transistor T3, and the compensation voltage output from the compensation signal line S is written to the second node N2, at which point the potential of the second node N2 is V2 = V s The potential difference between the first node N1 and the second node N2 is the threshold voltage V of the second transistor T2. th Because it is greater than the first transistor T2, the second transistor T2 is turned on, and the power supply voltage output from the first power line VDD provides a drive voltage to the first pole of the OLED via the turned-on second transistor T2, driving the OLED to emit light.

[0058] In the second stage A2, the signals on the first scan signal line S1 and the second scan signal line S2 are low-level signals, turning off the first transistor T1 and the third transistor T3. The voltage across the storage capacitor C still turns on the second transistor T2, and the power supply voltage output from the first power supply line VDD continues to pull up the potential of the second node N2. Due to the presence of the storage capacitor C, the potential of the first node N1 increases as the potential of the second node N2 increases until the next data voltage is written, and the OLED continues to emit light.

[0059] In the exemplary embodiment, both the OLED and the second transistor T2 are forward-biased to drive the normal emission of light from the OLED. In the first stage, the power supply voltage output from the first power supply line VDD is greater than the data voltage output from the data signal line D, the data voltage output from the data signal line D is greater than the compensation voltage output from the compensation signal line S, and the compensation voltage output from the compensation signal line S is greater than the power supply voltage output from the second power supply line VSS.

[0060] As the size of the display board increases, the influence of in-planar capacitor resistance (abbreviated as RC) on the charge rate increases, and the uniformity of the charge rate deteriorates. RC that affects the uniformity of the in-planar charge rate includes at least one of the following: RC due to the first power line (abbreviated as VDD RC), RC due to the scan line (abbreviated as Gate RC), and RC due to the data line (i.e., data signal line) (abbreviated as Data RC). Furthermore, because the capacitor plates and circuit wiring on the display board occupy a certain amount of space, the aperture ratio of the display board is not high, resulting in a low pixel density (pixels per inch, PPI), which significantly affects the display effect of the display board. Anode vias are usually placed at one end of a subpixel, and the problem of display non-uniformity at both ends of the subpixel exists.

[0061] Embodiments of the present disclosure provide a display substrate which may include a base and a plurality of subpixels and a plurality of transparent conductive layers set on the base, each subpixel including at least one transparent conductive layer, and at least some subpixels including at least a second transistor and a third transistor, wherein the second pole of the second transistor and the second pole of the third transistor located in the same subpixel are electrically connected via at least one transparent conductive layer.

[0062] In the display substrate according to this embodiment, the second pole of the second transistor and the second pole of the third transistor located in the same subpixel are electrically connected via at least one transparent conductive layer, and the transparent conductive layer does not obstruct the aperture, thereby improving the aperture ratio and PPI of the display substrate.

[0063] Figures 5a and 5b are schematic diagrams of the structure of a display substrate according to an exemplary embodiment of the present disclosure, the display substrate comprising a base, a plurality of subpixels and a plurality of transparent conductive layers 300 mounted on the base, each subpixel comprising at least one transparent conductive layer 300, at least some subpixels comprising at least a second transistor T2 and a third transistor T3, the second pole of the second transistor T2 and the second pole of the third transistor T3 located in the same subpixel are electrically connected via at least one transparent conductive layer 300.

[0064] In exemplary embodiments, as shown in Figures 12b and 22b, at least a portion of the transparent conductive layer 300 includes an anode 301, a first connecting electrode 3011, and a second connecting electrode 3012, and in the same transparent conductive layer 300, the anode 301 is electrically connected to the first connecting electrode 3011 and the second connecting electrode 3012.

[0065] In the same subpixel, the second pole of the second transistor T2 is electrically connected to the corresponding anode 301 via the first connecting electrode 3011, the second pole of the third transistor T3 is electrically connected to the corresponding anode 301 via the second connecting electrode 3012, and the second pole of the second transistor T2 and the second pole of the third transistor T3 are electrically connected via the corresponding first connecting electrode 3011, second connecting electrode 3012, and anode 301.

[0066] In exemplary embodiments, as shown in Figures 12b and 22b, the first connecting electrode 3011 and the second connecting electrode 3012 and the corresponding anode 301 are integrally molded structures. In exemplary embodiments, the first connecting electrode 3011, the second connecting electrode 3012, and the anode 301 in the transparent conductive layer 300 are all transparent conductive structures, do not occupy the pixel aperture ratio, do not obstruct the aperture, and improve the aperture ratio and PPI of the display substrate.

[0067] In exemplary embodiments, as shown in Figures 5a, 5b, 13b, and 23b, the display substrate may further include a pixel definition layer located away from the base of the transparent conductive layer, and a plurality of pixel apertures 302 are formed in the pixel definition layer, each subpixel including at least one pixel aperture 302, and there is an overlapping region between the orthographic projection of the pixel aperture 302 on the base and the orthographic projection of the corresponding anode 301 on the base, and the transparent conductive layer 300 is located in the light-emitting region of the corresponding subpixel. In embodiments of this disclosure, the transparent conductive layer 300 is located in the light-emitting region of the subpixel, and because the transparent conductive layer 300 is transparent, it does not obstruct the light emission of the subpixel. In exemplary embodiments, the region corresponding to the pixel aperture 302 in the subpixel may be the light-emitting region of the subpixel.

[0068] In exemplary embodiments, as shown in Figures 11 and 21, the second pole of the second transistor T2 is electrically connected to the corresponding first connection electrode 3011 via a first relay via V21, and the orthographic projection of the base of the first relay via V21 lies within the range of the orthographic projection of the base of the first connection electrode 3011; the second pole of the third transistor T3 is electrically connected to the corresponding second connection electrode 3012 via a second relay via V20, and the orthographic projection of the base of the second relay via V20 lies within the range of the orthographic projection of the base of the second connection electrode 3012; the minimum distance from the first relay via V21 to the edge of the corresponding pixel aperture 302 is less than the minimum distance from the second relay via V21 to the edge of the corresponding pixel aperture 302; and the first relay via V21 and the second relay via V20 are located on either side of the corresponding pixel aperture 302. In the embodiments of this disclosure, the first relay via V21 and the second relay via V20 are located on both sides of the corresponding pixel aperture 302 as anode vias, thereby avoiding display non-uniformity at both ends of subpixels caused by the relay via being located on one side of the pixel aperture 302, and improving display uniformity.

[0069] In exemplary embodiments, as shown in Figures 11 and 21, the subpixels may be arranged along the row direction X and the column direction Y, where the distance between two adjacent subpixels' first relay vias V21 in the row direction X includes a first distance R1 and a second distance R2, where the first distance R1 is greater than the second distance R2, and the first distance R1 and the second distance R2 are arranged alternately along the row direction X. As shown in Figure 11, the distance between the first relay via V21 in the first subpixel P1 and the first relay via V21 in the second subpixel P2, the distance between the first relay via V21 in the third subpixel P3 and the first relay via V21 in the fourth subpixel P4 is the first distance R1, and the distance between the first relay via V21 in the second subpixel P2 and the first relay via V21 in the third subpixel P3 is the second distance R2. As shown in Figure 21, the distance between the first relay via V21 in the first subpixel P1 and the first relay via V21 in the second subpixel P2, the distance between the first relay via V21 in the third subpixel P3 and the first relay via V21 in the fourth subpixel P4 is the second distance R2, and the distance between the first relay via V21 in the second subpixel P2 and the first relay via V21 in the third subpixel P3 is the first distance R1.

[0070] In exemplary embodiments, as shown in Figures 11 and 21, in the row direction X, the distance between two adjacent subpixels' second relay vias V20 includes a third distance R3 and a fourth distance R4, where the third distance R3 is greater than the fourth distance R4, and the third distance R3 and the fourth distance R4 are arranged alternately along the row direction X. As shown in Figure 11, the distance between the second relay via V20 in the first subpixel P1 and the second relay via V20 in the second subpixel P2, the distance between the second relay via V20 in the third subpixel P3 and the second relay via V20 in the fourth subpixel P4 is the fourth distance R4, and the distance between the second relay via V20 in the second subpixel P2 and the second relay via V20 in the third subpixel P3 is the third distance R3. As shown in Figure 21, the distance between the second relay via V20 in the first subpixel P1 and the second relay via V20 in the second subpixel P2, the distance between the second relay via V20 in the third subpixel P3 and the second relay via V20 in the fourth subpixel P4 is the third distance R3, and the distance between the second relay via V20 in the second subpixel P2 and the second relay via V20 in the third subpixel P3 is the fourth distance R4. In an exemplary embodiment, as shown in Figures 5a and 5b, in the same subpixel, the second transistor T2 and the third transistor T3 are located on either side of the corresponding anode 301 in the column direction X, and the distance between the second transistor T2 and the third transistor T3 is greater than 0.5 times the size along the column direction Y of the subpixel.

[0071] In exemplary embodiments, as shown in Figures 5a, 5b, 6, and 15, the display substrate may further include a first conductive layer, the first conductive layer located between the base and the transparent conductive layer 300, and the subpixels may further include capacitors, the first conductive layer may include a first electrode plate 11 of the capacitor, the first electrode plate 11 having a transparent structure. In embodiments of this disclosure, by making the first electrode plate 11 of the capacitor transparent, the pixel aperture is not obstructed, and the aperture ratio and PPI of the display substrate can be improved.

[0072] In an exemplary embodiment, as shown in Figure 25c, the anode 301 may be reused as the second electrode plate of the capacitor, and in the same subpixel, there is a first overlapping region between the orthographic projection of the base of the first electrode plate 11 and the orthographic projection of the base of the second electrode plate, and the first overlapping region is located in the light-emitting region of the subpixel. The light-emitting region of the subpixel corresponds to the corresponding pixel aperture 302, or the orthographic projection of the base of the light-emitting region overlaps with the orthographic projection of the base of the corresponding pixel aperture 302. In the configuration shown in Figure 25c, both the first electrode plate 11 in the first conductive layer and the anode 301 reused as the second electrode plate in the transparent conductive layer are transparent structures, thereby the two electrodes of the capacitor do not occupy the aperture ratio of the display substrate, and the aperture ratio and PPI of the display substrate are improved to a large extent.

[0073] In exemplary embodiments, as shown in Figures 24b and 24c, the display substrate may further include a gate metal layer, the transparent conductive layer 300 may be located on the gate metal layer, and the transparent conductive layer 300 may be reused as the second electrode plate of a capacitor, and there is a first overlapping region between the orthographic projection on the base of the first electrode plate 11 and the orthographic projection on the base of the second electrode plate, and the first overlapping region is located in the light-emitting region of the subpixel. In the configuration shown in Figures 24b and 24c, both the first electrode plate 11 in the first conductive layer and the transparent conductive layer 30 reused as the second electrode plate are transparent structures, thereby the two electrodes of the capacitor do not occupy the aperture ratio of the display substrate, and the aperture ratio and PPI of the display substrate are improved to a great extent.

[0074] In exemplary embodiments, as shown in Figures 5a and 5b, the display substrate may further include a plurality of data signal lines 25 and a plurality of auxiliary data lines 45, each of which is electrically connected to the plurality of auxiliary data lines 45, the data signal lines 25 and auxiliary data lines 45 are located on different conductive layers, and in a direction perpendicular to the plane on which the display substrate is located, the conductive layers on which the data signal lines 25 and auxiliary data lines 45 are located are located between the base and the transparent conductive layer 300, and the orthographic projection of the plurality of data signal lines 25 on the base at least partially overlaps with the orthographic projection of each of the plurality of auxiliary data lines 45 on the base.

[0075] In the embodiments of this disclosure, data signal lines located in different conductive layers are electrically connected to auxiliary data lines, thereby reducing the RC of the data signal lines and improving the uniformity of charging of the display substrate.

[0076] Figures 5a and 5b are schematic diagrams of the structure of a display substrate according to an exemplary embodiment of the present disclosure, showing the structure of the drive circuit layer in four subpixels (one pixel unit) of a bottom emission display substrate, and Figure 5c is a schematic equivalent circuit diagram of the pixel drive circuit in the four subpixels shown in Figures 5a and 5b. As shown in Figures 5a to 5c, in a direction parallel to the display substrate, at least one pixel unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged sequentially along a first direction X, and each subpixel includes a pixel drive circuit and a storage capacitor. In the following, the term "subpixel" refers to the area in which the pixel drive circuit is installed. In the exemplary embodiment, at least one pixel unit may further include one first scan signal line 41, two first power lines 21, four data signal lines 25, one compensation signal line 22, and four pixel drive circuits.

[0077] As shown in Figures 5a and 5b, the display substrate according to the embodiment of the present disclosure may include a base and a plurality of data signal lines 25 and a plurality of auxiliary data lines 45 installed on the base, wherein each of the plurality of data signal lines 25 is electrically connected to the plurality of auxiliary data lines 45, the data signal lines 25 and the auxiliary data lines 45 are located on different conductive layers, and the orthographic projection of each of the plurality of data signal lines 25 on the base at least partially overlaps with the orthographic projection of each of the plurality of auxiliary data lines 45 on the base.

[0078] In exemplary embodiments, as shown in Figures 5a and 5b, the display substrate may include a gate metal layer mounted on a base, and at least some of the auxiliary data lines 45 are located on the gate metal layer.

[0079] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10b, the display substrate may further include a shielding metal layer, and in a direction perpendicular to the plane on which the display substrate is located, the gate metal layer may be located away from the base of the shielding metal layer, and the plurality of data signal lines 25 may be located on the shielding metal layer. As shown in Figures 7a-7b and 10a-10b, the plurality of auxiliary signal lines 45 and the plurality of data signal lines 25 may extend along a second direction Y and be arranged along a first direction X.

[0080] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10b, the shield metal layer may be further provided with a plurality of first power lines 21, and the gate metal layer may be further provided with a plurality of first auxiliary power lines 44, each of the plurality of first power lines 21 being electrically connected to the plurality of first auxiliary power lines 44, and the orthographic projection of the base of each of the plurality of first power lines 21 at least partially overlaps with the orthographic projection of the base of each of the plurality of first auxiliary power lines 44. In embodiments of the present disclosure, the plurality of first power lines 21 are each electrically connected to the plurality of first auxiliary power lines 44 to form a two-layer power wiring, ensuring the reliability of power signal transmission, reducing the resistance of the first power lines 21, and reducing RC in the first power lines.

[0081] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10b, the subpixels on the display substrate may form a plurality of pixel units arranged in an array, each pixel unit may include at least three subpixels (for example, each pixel unit may include four subpixels P1-P4 arranged along a first direction X), the gate metal layer may further include a plurality of first power supply connection lines 43, each pixel unit may include two first power supply auxiliary lines 44, both ends of a first power supply connection line 43 located in the same pixel unit are each connected to two first power supply auxiliary lines 44, the main portion of the first power supply auxiliary line 44 extends along a second direction Y, and the main portion of the first power supply connection line 43 extends along a first direction X, and the first direction X and the second direction Y intersect.

[0082] In exemplary embodiments, a first power supply connection line 43 located in the same pixel unit may be integrally molded with two first power supply auxiliary lines 44. In embodiments of the present disclosure, a plurality of first power supply lines 21 may extend along a second direction Y, and one first power supply line 21 may be electrically connected to a plurality of first power supply auxiliary lines 44 in a row of pixel units. Since two first power supply auxiliary lines 44 located in the same pixel unit are electrically connected via the first power supply connection line 43, the first power supply lines 21 and the first power supply connection line 43 can form a grid structure across the entire display substrate, thereby reducing the load on the first power supply lines. This ensures that the first power supply voltages supplied to multiple subpixels on the display substrate are as consistent as possible, contributing to improved panel uniformity, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0083] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 8a-8b, the display substrate may further include a semiconductor layer, the semiconductor layer being located away from the base of the shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer being provided with a plurality of compensation connection lines 35, and the shield metal layer being provided with a plurality of compensation signal lines 22, the compensation connection lines 35 being a stripe structure extending along a first direction X in a plane parallel to the display substrate, the compensation signal lines 22 being a stripe structure extending along a second direction Y, the first direction X and the second direction Y intersect, and the compensation connection lines 35 are electrically connected to at least one of the compensation signal lines 22. As shown in Figures 7a and 7b, one pixel unit may include one compensation connection line 35, and the four subpixels in one pixel unit may be symmetrical with respect to the compensation signal line 22. That is, the first subpixel P1 and the fourth subpixel P4 located in the same pixel unit may be symmetrical with respect to the compensation signal line 22, and the second subpixel P2 and the third subpixel P3 may be symmetrical with respect to the compensation signal line 22. In embodiments of this disclosure, the same compensation signal line 22 may be electrically connected to multiple compensation signal lines 22 located in the same row of pixel units, and one compensation connection line 35 may be installed in one pixel unit to transport the signal of the compensation signal line 22 to the four subpixels in one pixel unit. Therefore, a net-like structure of compensation signal lines can be formed from multiple compensation signal lines 22 and multiple compensation connection lines 35, thereby reducing the load on the compensation signal line 22. As a result, the compensation signals provided to multiple subpixels on the display board will be as consistent as possible, contributing to improved panel uniformity, avoiding display defects on the display board, and ensuring the display effect of the display board.

[0084] In exemplary embodiments, the configuration shown in Figures 5a, 6 to 13b may include a base and, in a direction perpendicular to the display substrate, a first conductive layer, a second conductive layer (shield metal layer), a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer (gate metal layer), a third insulating layer, a flat layer, a fourth conductive layer, and a pixel definition layer, which are sequentially installed on the base. The second conductive layer may be the shield metal layer, and the third conductive layer may be the gate metal layer. In embodiments of this disclosure, data signal lines are installed on the shield metal layer, the source and drain metal layers are omitted, the process flow is simplified, and the manufacturing cost of the display substrate is reduced.

[0085] In exemplary embodiments, as shown in Figures 5b, 20a, and 20b, the display substrate may further include a source-drain metal layer, the source-drain metal layer may be located away from the base of the gate metal layer in a direction perpendicular to the plane on which the display substrate is located, and a plurality of data signal lines 25 may be located on the source-drain metal layer.

[0086] In exemplary embodiments, as shown in Figures 5b, 16a, 16b, 18a, 18b, 20a, and 20b, the display substrate may further include a second shielding metal layer, which may be located between the base and the gate metal layer in a direction perpendicular to the plane on which the display substrate is located, and the plurality of auxiliary data lines 45 may include a plurality of first auxiliary data lines 451 and a plurality of second auxiliary data lines 452, the plurality of first auxiliary data lines 451 may be located on the second shielding metal layer, and the plurality of second auxiliary data lines 452 may be located on the gate metal layer, and there is an overlapping region between the orthographic projection of the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 on the base and the orthographic projection of the corresponding plurality of data signal lines 25 on the base, and the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 are electrically connected to the corresponding plurality of data signal lines 25.

[0087] In exemplary embodiments, as shown in Figures 5b, 18a, 18b, 20a, and 20b, the source-drain metal layer is further provided with a plurality of first power lines 21, and the gate metal layer is further provided with a plurality of first power auxiliary lines 44, each of the plurality of first power lines 21 being electrically connected to the plurality of first power auxiliary lines 44, and the orthographic projection of the base of each of the plurality of first power lines 21 at least partially overlaps with the orthographic projection of the base of each of the plurality of first power auxiliary lines 44. In embodiments of the present disclosure, the plurality of first power lines 21 are each electrically connected to the plurality of first power auxiliary lines 44 to form a two-layer power wiring, ensuring reliability of power signal transport, reducing the resistance of the first power lines 21, and reducing RC in the first power lines.

[0088] In exemplary embodiments, as shown in Figures 5b, 16a to 20b, the subpixels on the display substrate may form a plurality of pixel units arranged in an array, each pixel unit may include at least three subpixels (for example, each subpixel may include four subpixels arranged along a first direction X), the display substrate may further include a semiconductor layer, the semiconductor layer located away from the base of the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer is provided with a plurality of first power supply lines 43, each pixel unit may include two first power supply lines, both ends of a first power supply line 43 located in the same pixel unit are electrically connected to two first power supply lines 21, the main portion of the first power supply line 21 extends along a second direction Y, and the main portion of the first power supply line 43 extends along a first direction X, and the first direction X and the second direction Y intersect. In embodiments of this disclosure, a plurality of first power lines 21 may extend along a second direction Y, and one first power line 21 may be electrically connected to a plurality of first auxiliary power lines 44 in a row of pixel units. Since two first power lines 21 located in the same pixel unit are electrically connected via a first power connection line 43, the first power lines 21 and the first power connection line 43 form a grid structure across the entire display board, thereby reducing the load on the first power lines. As a result, the first power supply voltages provided to multiple sub-pixels on the display board are made as consistent as possible, contributing to improved panel uniformity, avoiding display defects on the display board, and ensuring the display effect of the display board.

[0089] In exemplary embodiments, as shown in Figures 5b and 16a to 20b, the second shield metal layer may be further provided with a plurality of compensation connection lines 35, and the source-drain metal layer may be further provided with a plurality of compensation signal lines 22. In a plane parallel to the display substrate, the compensation connection lines 35 have a stripe structure extending along a first direction X, and the compensation signal lines 22 have a stripe structure extending along a second direction Y. The first direction X and the second direction Y intersect, and the compensation connection lines 35 are electrically connected to at least one compensation signal line 22. As shown in Figures 16a to 20b, one pixel unit may include one compensation connection line 35, and the four subpixels in one pixel unit may be symmetrical with respect to the compensation signal line 22. That is, the first subpixel P1 and the fourth subpixel P4 located in the same pixel unit may be symmetrical with respect to the compensation signal line 22, and the second subpixel P2 and the third subpixel P3 may be symmetrical with respect to the compensation signal line 22. In the embodiments of this disclosure, the same compensation signal line 22 may be electrically connected to multiple compensation signal lines 22 located in the same row of pixel units, or one compensation connection line 35 may be installed in one pixel unit to transport the signal of the compensation signal line 22 to four sub-pixels in one pixel unit. Therefore, a net-like structure of compensation signal lines can be formed from multiple compensation signal lines 22 and compensation connection lines 35, thereby reducing the load on the compensation signal line 22. As a result, the compensation signals provided to multiple sub-pixels on the display board will be as consistent as possible, contributing to improved panel uniformity, avoiding display defects on the display board, and ensuring the display effect of the display board.

[0090] In exemplary embodiments, as shown in Figures 5b and 15, the display substrate may further include a first shield metal layer, which may be located between the base and a second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, and which may be provided with a plurality of first scan signal lines 41, and which may be provided with a plurality of first scan signal auxiliary lines 410, each electrically connected to the plurality of first scan signal lines 41, and the orthographic projection of the plurality of first scan signal lines 41 on the base at least partially overlaps with the orthographic projection of the plurality of first scan signal auxiliary lines 410 on the base. In embodiments of the present disclosure, the plurality of first scan signal lines 41 are each electrically connected to the plurality of first scan signal auxiliary lines 410 to form a two-layer power supply wiring, ensuring the reliability of the first scan signal lines, reducing the resistance of the first scan signal lines 41, and reducing RC in the first power supply lines.

[0091] In an exemplary embodiment, the orthographic projections at the base of each of the multiple first scan signal lines 41 each cover the orthographic projections at the base of each of the multiple first scan signal auxiliary lines 410, preventing damage to the first scan signal auxiliary lines 410 during the subsequent etching process, and allowing the first scan signal auxiliary lines 410 to provide protection to the first scan signal lines 41.

[0092] In an exemplary embodiment, the thickness of the first shield metal layer is greater than the thickness of the second shield metal layer. That is, in the direction perpendicular to the plane on which the display substrate is located, the size of the first scan signal line 41 is greater than the size of the first scan signal auxiliary line 410. On the one hand, because the thickness of the first scan signal line 41 is greater, the impedance of the first scan signal line can be reduced and RC can be reduced. On the other hand, because the thickness of the second shield metal layer is smaller, it is possible to prevent the semiconductor layer from being cut off by the large thickness of the second shield metal layer in the region where the semiconductor layer and the second shield metal layer partially overlap. As shown in Figure 17b, the second shield metal layer may include a shield structure 23, and there is a region where the orthographic projection of the base of the shield structure 23 and the orthographic projection of the base of the pattern in the semiconductor layer (e.g., the second plate 34 of the capacitor and the active layer 32 of the second transistor T2) overlap. If the shield structure 23 is thick, the edges of the second electrode plate 34 and the active layer 32 of the second transistor T2 that overlap with the shield structure 23 are prone to cutting, leading to defects in the display substrate. Therefore, by making the second shield metal layer thin, it is possible to prevent cutting of the semiconductor layer in the region where the semiconductor layer and the second shield metal layer partially overlap.

[0093] In exemplary embodiments, the configuration shown in Figures 5b and 14 to 23b may include, in a direction perpendicular to the display substrate, a base and sequentially installed on the base a first conductive layer, a second conductive layer (first shield metal layer), a third conductive layer (second shield metal layer), a first insulating layer, a semiconductor layer, a second insulating layer, a fourth conductive layer (gate metal layer), a third insulating layer, a fifth conductive layer (source-drain metal layer), a fourth insulating layer, a flat layer, a sixth conductive layer, and a pixel definition layer. The second conductive layer may be the first shield metal layer, the third conductive layer may be the second shield metal layer, and the fourth conductive layer may be the gate metal layer.

[0094] In the embodiments of this disclosure, in the configuration shown in Figures 5b and 14 to 23b, the first conductive layer is provided with the first electrode plates of capacitors in a plurality of subpixels, the semiconductor layer is provided with the second electrode plates of capacitors in a plurality of subpixels, and the first scanning signal line 41 is placed on the shield metal layer and not on the gate metal layer. This reduces the capacitance between the data signal line 25 located in the source-drain metal layer and the gate metal layer, thereby reducing RC, and also reduces the thickness of the first insulating layer, thereby increasing the capacitance value of the capacitors in the subpixels.

[0095] In exemplary embodiments, as shown in Figures 5a to 5c, each pixel unit may include four subpixels arranged along a first direction X, each subpixel may include a pixel driving circuit, the pixel driving circuit of each subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C, and in the second direction Y, the third transistor T3, the first transistor T1, the capacitor C, and the second transistor T2 are arranged sequentially along the second direction Y. In the same pixel unit, the second subpixel P2 and the third subpixel P3 may be arranged symmetrically with respect to the compensation signal line 22, and the first subpixel P1 and the fourth subpixel P4 may be arranged symmetrically with respect to the compensation signal line 22. In embodiments of the present disclosure, the display area of ​​the display board may include a plurality of subpixels arranged in an array, at least three subpixels may constitute one pixel unit, and both the plurality of pixel units and the plurality of subpixels may be arranged in an array, and the plurality of signal lines 25 are each electrically connected to a plurality of rows of subpixels and configured to provide data signals to the connected subpixels. The compensation signal line 22 may be electrically connected to multiple rows of pixel units and configured to provide compensation signals to multiple subpixels in the electrically connected pixel units. The first power line 21 may be electrically connected to one row of pixel units and configured to provide a first power signal to multiple subpixels in the electrically connected pixel unit. The first scan signal line 41 may be electrically connected to one row of subpixels and configured to provide scan signals to the connected subpixels.

[0096] Embodiments of this disclosure further provide a method for manufacturing a display substrate, comprising forming a plurality of subpixels and a plurality of transparent conductive layers 300 on one side of a base, wherein at least some of the subpixels include at least a second transistor T2 and a third transistor T3, and the second pole of the second transistor T2 and the second pole of the third transistor T3 located in the same subpixel are electrically connected via at least one transparent conductive layer 300.

[0097] In exemplary embodiments, the manufacturing method may further include forming a plurality of data signal lines 25 and a plurality of auxiliary data lines 45 on one side of a base, wherein each of the plurality of data signal lines 25 is electrically connected to the plurality of auxiliary data lines 45, the data signal lines 25 and the auxiliary data lines 45 are located in different conductive layers, the conductive layers on which the data signal lines 25 and the auxiliary data lines 45 are located are located between the base and the transparent conductive layer 300 in a direction perpendicular to the plane on which the display substrate is located, and the orthographic projection of the plurality of data signal lines 25 on the base at least partially overlaps with the orthographic projection of each of the plurality of auxiliary data lines 45 on the base.

[0098] In exemplary embodiments, forming a plurality of auxiliary data lines 45 on the base may include forming a gate metal layer on one side of the base, with at least some of the auxiliary data lines 45 located in the gate metal layer.

[0099] In exemplary embodiments, as shown in Figures 10c and 10d, Figure 10c is a schematic cross-sectional view of the A1-A1 position in Figure 10a, and Figure 10d is a schematic cross-sectional view of the A2-A2 position in Figure 10a. A shield metal layer SHL may be formed on the side of the base 101 closer to the gate metal layer GT before forming the gate metal layer on one side of the base, and in a direction perpendicular to the plane on which the display substrate is located, the gate metal layer GT is located on the side of the shield metal layer SHL away from the base 101, and a plurality of data signal lines 25 are located on the shield metal layer SHL.

[0100] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10c, the shield metal layer may be further provided with a plurality of first power lines 21, and the gate metal layer may be further provided with a plurality of first power auxiliary lines 44, each of the plurality of first power lines 21 being electrically connected to the plurality of first power auxiliary lines 44, and the orthographic projection of the base of each of the plurality of first power lines 21 at least partially overlaps with the orthographic projection of the base of each of the plurality of first power auxiliary lines 44. In embodiments of the present disclosure, each of the plurality of first power lines 21 is electrically connected to the plurality of first power auxiliary lines 44 to form a two-layer power wiring, ensuring reliability of power signal transmission, reducing the resistance of the first power lines 21, and reducing RC in the first power lines.

[0101] In exemplary embodiments, as shown in Figures 5a, 7a-7b, and 10a-10b, the display substrate may further include a plurality of pixel units arranged in an array mounted on a base, each pixel unit may include four sub-pixels P1-P4 arranged along a first direction X, and the gate metal layer may further include a plurality of first power supply connection lines 43, each pixel unit may include two first power supply auxiliary lines 44, and both ends of a first power supply connection line 43 located in the same pixel unit are each connected to two first power supply auxiliary lines 44, and in a plane parallel to the display substrate, the main portion of the first power supply auxiliary line 44 extends along a second direction Y, and the main portion of the first power supply connection line 43 extends along a first direction X, and the first direction X and the second direction Y intersect.

[0102] In exemplary embodiments, after forming a shield metal layer SHL on one side of the base 101, and before forming a gate metal layer GT on the same side of the base 101, a semiconductor layer ACT may be formed on the side of the shield metal layer SHL away from the base 101. The semiconductor layer ACT is provided with a plurality of compensation connection lines 35, and the shield metal layer SHL is further provided with a plurality of compensation signal lines 22. In a plane parallel to the display substrate, the compensation connection lines 35 may be in a stripe structure extending along a first direction X, and the compensation signal lines 22 may be in a stripe structure extending along a second direction Y, the first direction X and the second direction Y intersect, and the compensation connection lines 35 are electrically connected to at least one of the compensation signal lines 22.

[0103] In an exemplary embodiment, as shown in Figure 10c, a gate metal layer GT is formed on one side of the base 101. A second insulating thin film is formed on the side of the semiconductor layer ACT that is away from the base 101, The patterning process patterns the second insulating thin film to form a second insulating layer c2 including the second insulating layer pattern, the pattern of the second insulating layer c2 may include a plurality of first connection vias K1, and the plurality of first connection vias K1 expose the surface of the semiconductor layer ACT. The semiconductor layer exposed by the first connecting via K1 is subjected to a conductive treatment to form a plurality of first conductive regions d1, and the orthogonal projection of each of the plurality of first conductive regions d1 on the base 101 covers the orthogonal projection of each of the plurality of first connecting vias K1 on the base 101. This may include forming a gate metal layer GT on the side of the second insulating layer c2 that is away from the base 101.

[0104] In an exemplary embodiment, as shown in Figure 10d, the semiconductor layer ACT is formed on the side of the shield metal layer SHL away from the base 101. The first insulating layer c1 is formed on the side of the shield metal layer SHL that is away from the base 101, This may include forming a semiconductor layer ACT on the side of the first insulating layer c1 that is away from the base 101, The process of patterning the second insulating thin film by a patterning process to form a second insulating layer c2 including a second insulating layer pattern may further include patterning the first insulating thin film to form a plurality of second connection vias K2 that expose the surface of the shielding metal layer SHL and the surface of the semiconductor layer ACT. The process of making the semiconductor layer exposed by the first connection via K1 conductive to form a plurality of first conductive regions may further include making the semiconductor layer ACT exposed by the second connection via K2 conductive to form a plurality of second conductive regions d2, and the orthogonal projection of the plurality of second conductive regions d2 on the base 101 covers the orthogonal projection of the semiconductor layer ACT exposed by the plurality of second connection vias K2 on the base 101.

[0105] In an exemplary embodiment, after forming the gate metal layer GT on the side away from the base of the second insulating layer c2, The second insulating thin film c2 outside the region covered by the gate metal layer GT is removed to expose the region in the semiconductor layer ACT that is to be made conductive, The method may further include forming a third conductive region by conducting a conductive treatment on a region in a semiconductor layer, and ensuring that the base orthographic projections of the multiple first conductive regions d1 and second conductive regions d2 overlap at least partially with the base orthographic projection of the third conductive region.

[0106] In embodiments of this disclosure, the third conductive region may be a semiconductor layer ACT not covered by the gate metal layer GT, and the orthographic projections of the multiple first conductive regions d1 and second conductive regions d2 at the base at least partially overlap with the orthographic projection at the base of the third conductive region, so that the first conductive regions d1 located at multiple first connection vias K1 and the second conductive regions d2 located at multiple second connection vias K2 can be electrically connected to the third conductive region (i.e., the first conductive regions d1 and second conductive regions d2 can be superimposed on the third conductive region), and the first conductive regions d1 and second conductive regions d2 avoid having non-conductive regions with the third conductive region.

[0107] In the embodiments of this disclosure, the orthographic projections of the multiple second conductive regions d2 on the base 101 cover the orthographic projections of the semiconductor layer ACT exposed at the multiple second connection vias K2 on the base 101, thereby enabling the multiple second conductive regions d2 to be electrically connectable to the third conductive region, and avoiding the existence of non-conductive regions between the first conductive region d1 and the second conductive region d2. The orthographic projections of the multiple first conductive regions d1 on the base 101 cover the orthographic projections of the multiple first connection vias K1 on the base 101, thereby enabling the first conductive regions d1 located at the multiple first connection vias K1 to be electrically connectable to the third conductive region (i.e., the first conductive region d1 can be superimposed on the third conductive region), and avoiding the existence of non-conductive regions between the first conductive region d1 and the third conductive region.

[0108] In exemplary embodiments, as shown in Figures 10c and 10d, the orthographic projection of the second conductive region d2 at the base at least partially overlaps with the orthographic projection of at least a portion of the gate metal layer GT at the base, thereby enabling the second conductive region d2 to be electrically connectable to the gate metal layer GT and increasing the reliability of the electrical connection between the second conductive region d2 and the gate metal layer GT pattern.

[0109] In an exemplary embodiment, as shown in Figure 23c, Figure 23c is a schematic cross-sectional view of the A3-A3 position in Figure 23a. After forming a gate metal layer GT on one side of the base 101, a source-drain metal layer SD may be formed on the side of the gate metal layer GT away from the base 101, and a plurality of data signal lines 25 may be located in the source-drain metal layer SD.

[0110] In exemplary embodiments, a second shield metal layer SHL2 may be formed on the side of the base 101 closer to the gate metal layer GT before forming the gate metal layer GT on one side of the base 101. The plurality of auxiliary data lines 45 include a plurality of first auxiliary data lines 451 and a plurality of second auxiliary data lines 452, where the plurality of first auxiliary data lines 451 are located in the second shield metal layer SHL2 and the plurality of second auxiliary data lines 452 are located in the gate metal layer GT. There is an overlapping region between the orthographic projection of the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 on the base 101 and the orthographic projection of the corresponding plurality of data signal lines 25 on the base 101, and the plurality of first auxiliary data lines 451 and the plurality of second auxiliary data lines 452 are electrically connected to the corresponding plurality of data signal lines 25.

[0111] In exemplary embodiments, as shown in Figures 5b, 18a, 18b, 20a, 20b, and 23c, the source-drain metal layer is further provided with a plurality of first power lines 21, and the gate metal layer is further provided with a plurality of first power auxiliary lines 44, each of the plurality of first power lines 21 being electrically connected to the plurality of first power auxiliary lines 44, and the orthographic projection of the base of each of the plurality of first power lines 21 at least partially overlaps with the orthographic projection of the base of each of the plurality of first power auxiliary lines 44. In embodiments of the present disclosure, the plurality of first power lines 21 are each electrically connected to the plurality of first power auxiliary lines 44 to form a two-layer power wiring, ensuring reliability of power signal transport, reducing the resistance of the first power lines 21, and reducing RC in the first power lines.

[0112] In exemplary embodiments, as shown in Figures 5b, 16a to 20b, and 23c, the display substrate may include a plurality of pixel units arranged in an array mounted on a base, each pixel unit may include four subpixels arranged along a first direction X, the display substrate may further include a semiconductor layer, the semiconductor layer located away from the base of the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer is provided with a plurality of first power supply lines 43, each pixel unit may include two first power supply lines, both ends of a first power supply line 43 located in the same pixel unit are electrically connected to two first power supply lines 21, the main portion of the first power supply line 21 extends along a second direction Y, and the main portion of the first power supply line 43 extends along a first direction X, and the first direction X and the second direction Y intersect.

[0113] In exemplary embodiments, as shown in Figures 5b, 16a to 20b, and 23c, the second shield metal layer may be further provided with a plurality of compensation connection lines 35, and the source drain metal layer may be further provided with a plurality of compensation signal lines 22. In a plane parallel to the display substrate, the compensation connection lines 35 have a stripe structure extending along a first direction X, and the compensation signal lines 22 have a stripe structure extending along a second direction Y. The first direction X and the second direction Y intersect, and the compensation connection lines 35 are electrically connected to at least one compensation signal line 22.

[0114] In exemplary embodiments, the first shield metal layer SHL1 may be formed on the side of the base 101 closer to the second shield metal layer SHL2 before forming the second shield metal layer SHL2 on the side of the base 101 closer to the gate metal layer GT. In a direction perpendicular to the plane on which the display substrate is located, the first shield metal layer SHL1 is located between the base 101 and the second shield metal layer SHL2, and the first shield metal layer SHL1 is provided with a plurality of first scan signal lines 41, and the second shield metal layer SHL2 is provided with a plurality of first scan signal auxiliary lines 410 each electrically connected to the plurality of first scan signal lines 41, and the orthographic projection of the plurality of first scan signal lines 41 on the base 101 at least partially overlaps with the orthographic projection of the plurality of first scan signal auxiliary lines 410 on the base 101.

[0115] In the embodiments of this disclosure, as shown in Figure 23c, c1 to c5 are the first to fifth insulating layers, ITO1 is the first conductive layer, ITO2 is the sixth conductive layer, the first conductive layer ITO1 and the sixth conductive layer ITO2 may be conductive glass, and SD is the source-drain metal layer. You may also refer to Figure 14 for a schematic diagram of the planar structure of the first conductive layer ITO1, Figure 15 for a schematic diagram of the planar structure of the first shielding layer SHL1, Figure 16b for a schematic diagram of the planar structure of the second shielding layer SHL2, Figure 17b for a schematic diagram of the planar structure of the semiconductor layer ACT, Figure 18b for a schematic diagram of the planar structure of the gate metal layer GT, Figure 19 for a schematic diagram of the planar structure of the second insulating layer c2 and the third insulating layer c3, Figure 20b for a schematic diagram of the planar structure of the source-drain metal layer SD, Figure 21 for a schematic diagram of the planar structure of the fourth insulating layer c4 and the flat layer c5, Figure 22b for a schematic diagram of the planar structure of the sixth conductive layer ITO2, and Figure 23b for a schematic diagram of the planar structure of the pixel definition layer PDL.

[0116] In embodiments of this disclosure, as shown in Figures 23c and 21, the orthographic projections of the vias in the fourth insulating layer c4 and the flat layer c5 overlap on the base, and the vias in the fourth insulating layer c4 and the flat layer c5 may be formed in a single patterning process, eliminating the need for two manufacturing processes, simplifying the manufacturing flow, and reducing the manufacturing cost of the display substrate.

[0117] The manufacturing process of a display substrate will be described below with illustrative examples. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, but is not limited to these. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the manufacturing process, the “thin film” may also be referred to as a “layer.” If the “thin film” requires a patterning process throughout the manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process includes at least one “pattern.” As described in this disclosure, “A and B are placed on the same layer” means that A and B are formed simultaneously by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0118] In an exemplary embodiment, using four subpixels (first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4) as an example, the process of fabricating the drive circuit layer may include the following operations.

[0119] (11) Form a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 6, the formation of the first conductive layer pattern may include depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern on the base, the first conductive layer pattern including at least a first electrode plate 11 formed on each subpixel. In an exemplary embodiment, the first conductive layer may be referred to as a first transparent (ITO1) layer.

[0120] In an exemplary embodiment, the first electrode plate 11 in each subpixel is configured to form one of the transparent electrodes of a storage capacitor, and the first electrode plate 11 may be rectangular, and the edges of the rectangle may be polylines.

[0121] (12) Forming a second conductive layer pattern. In exemplary embodiments, as shown in Figures 7a and 7b, the formation of the second conductive layer pattern may include depositing a second conductive thin film on a base on which the aforementioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern on the first conductive layer, the second conductive layer pattern including at least a first power line 21, a compensation signal line 22, and a shield structure 23 and data signal line 25 formed on each subpixel, and Figure 7b is a schematic plan view of the second conductive layer in Figure 7a. In exemplary embodiments, the second conductive layer may be referred to as a shield metal (SHL) layer.

[0122] In exemplary embodiments, the two first power lines 21 may be a stripe structure extending along a second direction Y and sequentially arranged along a first direction X. In a single pixel unit, the first electrode plates 11 in a plurality of subpixels may be located between the two first power connection lines 21 in the first direction X, and the two first power lines 21 are each electrically connected to subsequently formed first power connection lines to provide a power supply voltage to the second transistor T2 in the first subpixels P1 to the fourth subpixels P4, respectively.

[0123] In an exemplary embodiment, the compensation signal line 22 may be a stripe structure extending along a second direction Y. The compensation signal line 22 is located between two first power supply connection lines 21, and in the first direction X, the two first power supply connection lines 21 may be symmetrical with respect to the compensation signal line 22, and the second subpixel P2 and the third subpixel P3 may be symmetrical with respect to the compensation signal line 22. Each of the compensation signal lines 22 is connected to a subsequently formed compensation signal line and is configured to provide a compensation voltage to the third transistor T3 of the first subpixels P1 to the fourth subpixels P3.

[0124] In an exemplary embodiment, the shield structure 23 may be installed on each subpixel, the orthographic projection of the base of the shield structure 23 at least partially overlaps with the orthographic projection of the base of the first electrode plate 11, and the shield structure 23 is electrically connected to the first electrode plate 11.

[0125] In the exemplary embodiment, each data signal line 25 is provided for each subpixel, and the main portion of the data signal line 25 extends along the second direction Y. The data signal line 25 is connected via vias to the first area 31-1 of the active layer of the subsequently formed first transistor, enabling the writing of data signals to the first transistor T1.

[0126] (13) Forming a semiconductor layer pattern. In exemplary embodiments, as shown in Figures 8a and 8b, the formation of a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base on which the aforementioned pattern is formed, and patterning the semiconductor thin film by a patterning process to form a first insulating layer covering a second conductive layer and a semiconductor layer pattern placed on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer 31 of a first transistor T1, an active layer 32 of a second transistor T2, an active layer 33 of a third transistor T3, a second electrode plate 34, and compensation connection lines 35 formed on each subpixel, and Figure 8b is a schematic plan view of the semiconductor layer in Figure 8a.

[0127] In an exemplary embodiment, there is an overlapping region between the orthographic projection of the base of the second plate 34 and the orthographic projection of the base of the first plate 11 in each subpixel, the second plate 34 is configured to form the other transparent plate of the storage capacitor, and the first plate 11 and the second plate 34 form a transparent storage capacitor.

[0128] In exemplary embodiments, the shape of the second electrode plate 34 may be rectangular, and the edges of the rectangle may be broken lines.

[0129] In exemplary embodiments, in each subpixel, the shape of the second electrode plate 34 may be similar to the shape of the first electrode plate 11 in the subpixel where it is located, and the orthographic projection of the base of the second electrode plate 34 may cover the orthographic projection of the base of the first electrode plate 11.

[0130] In the exemplary embodiment, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, and the active layer 33 of the third transistor T3 all include a channel region and a first area and a second area located on both sides of the channel region.

[0131] In exemplary embodiments, the shape of the active layer 31 of the first transistor T1 may be L-shaped, and in the second direction Y, the active layer 31 of the first transistor T1 may be located on one side of the second electrode plate 34. In the first direction X, the first area 31-1 of the active layer 31 of the first transistor T1 is located on the side away from the second electrode plate 34 of the channel region, and the second area 31-2 of the active layer 31 of the first transistor T1 is located on the side closer to the second electrode plate 34 of the channel region. In each subpixel, the orthogonal projection of the first area 31-1 of the active layer 31 of the first transistor T1 at the base at least partially overlaps with the orthogonal projection of the data signal line 25 at the base.

[0132] In an exemplary embodiment, the second area 31-2 of the active layer 31 of the first transistor T1 may be connected to the second electrode plate 34, and the active layer 31 of the first transistor T1 and the second electrode plate 34 are an integrated structure connected to each other.

[0133] In an exemplary embodiment, the first area 31-1 of the active layer 31 of the first transistor T1 is a stripe structure extending along a first direction X, and the stripe structure extends from the second area 31-2 of the active layer 31 of the first transistor T1 toward adjacent subpixels. The stripe structure at the first subpixel P1 extends toward the second subpixel P2, the stripe structure at the third subpixel P3 extends toward the fourth subpixel P4, the stripe structure at the second subpixel P2 extends toward the first subpixel P1, and the stripe structure at the fourth subpixel P3 extends toward the third subpixel P3. The second area 31-2 of the active layer 31 of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2 via the second electrode of the first transistor T1 which is formed subsequently, thereby realizing interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate of the storage capacitor.

[0134] In exemplary embodiments, the shape of the active layer 32 of the second transistor T2 may be I-shaped, and in the second direction Y, the second active layer 32 may be located on the side of the second electrode plate 34 away from the active layer 31 of the first transistor T1, and the orthographic projection of the active layer 32 of the second transistor T2 on the base and the orthographic projection of the second electrode plate 34 on the base are spaced apart, that is, there is no overlapping region between the second active layer 32 and the second electrode plate 34, which contributes to the design of a proportional width and length of the channel of the second transistor to meet relevant requirements. The first area 32-1 of the active layer 32 of the second transistor T2 is located on the side of the channel region away from the second electrode plate 34, and there is an overlapping region between the orthographic projection of the portion of the first area 32-1 of the active layer 32 of the second transistor T2 on the base that is close to the channel region and the orthographic projection of the shield structure 23 on the base. The second area 32-2 of the active layer 32 of the second transistor T2 is located on the side closer to the second electrode plate 34 of the channel region, and there is an overlapping region between the orthographic projection of the second area 32-2 of the active layer 32 of the second transistor T2 at the base and the orthographic projection of the shield structure 23 at the base. In this way, the shield structure 23 can block the channel region of the second active layer 32, avoiding the influence of light on the channel, reducing leakage current, and avoiding the influence of light irradiation on transistor characteristics.

[0135] In exemplary embodiments, the shape of the active layer 33 of the third transistor T3 may be an L-shaped bent structure, and in the second direction Y, the active layer 33 of the third transistor T3 may be located on the side of the active layer 31 of the first transistor T1 away from the second electrode plate 34, and the orthographic projection of the base of the active layer 33 of the third transistor T3 and the orthographic projection of the base of the second electrode plate 34 are spaced apart, that is, there is no overlapping region between the third active layer 33 and the second electrode plate 42, which contributes to the design of a proportional width and length of the channel of the third transistor to meet relevant requirements. The first area 33-1 of the active layer 33 of the third transistor T3 is located on the side of the channel region away from the second electrode plate 34, and the first area 33-1 of the active layer 33 of the third transistor T3 and the compensation connection line 35 may be an integrally molded structure connected to each other.

[0136] In an exemplary embodiment, the compensation connection line 35 may be a stripe structure extending along a first direction X, and in a second direction Y, the compensation connection line 35 is located on the side away from the second electrode plate 34 of the active layer of the third transistor T3, and there is an overlapping region between the orthographic projection of the base of the compensation connection line 35 and the orthographic projection of the base of the compensation signal line 22. The compensation connection line 35 may be connected to a first area 33-1 of the active layer 33 of the third transistor T3 and be integrally molded with the active layer 33 of the third transistor T3.

[0137] In exemplary embodiments, the semiconductor layer can be made of metal oxides, such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multi-layer layer.

[0138] (14) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in Figure 9, the formation of the second insulating layer pattern may include depositing a second insulating thin film on a base on which the aforementioned pattern is formed, and patterning the second insulating thin film by a patterning process to form a second insulating layer covering the semiconductor layer, wherein the second insulating layer has a plurality of vias, the plurality of vias including at least a first via V1, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8 and a ninth via V9.

[0139] In an exemplary embodiment, the first via V1 may be placed on each subpixel, and the orthographic projection of the base of the first via V1 at least partially overlaps with the orthographic projection of the base of the first area 31-1 of the active layer 31 of the first transistor T1, and at least partially overlaps with the orthographic projection of the base of the data signal line 25, and the second and first insulating layers within the first via V1 are etched to simultaneously expose the surface of the first area 31-1 of the active layer 31 of the first transistor T1 and the surface of the data signal line 25. The first via V1 is a relay via, which consists of two half vias, one half via formed on the first area 31-1 of the active layer 31 of the first transistor T1, and the other half via formed on the data signal line 25, thereby the relay via consisting of two half vias simultaneously exposes the surface of the first area 31-1 of the active layer 31 of the first transistor T1 and the surface of the data signal line 25. In an exemplary embodiment, the first via V1 is configured such that the first pole of the active layer 31 of the subsequently formed first transistor T1 is simultaneously connected to the data signal line 25 and the active layer 31 of the first transistor T1 via the via.

[0140] In an exemplary embodiment, the third via V3 may be provided on each subpixel, and the orthographic projection of the base of the third via V3 lies within the orthographic projection of the base of the first area 32-1 of the active layer 32 of the second transistor T2, and the second insulating layer within the third via V3 is etched to expose the surface of the first area 32-1 of the active layer 32 of the second transistor T2. In an exemplary embodiment, the third via V3 is configured such that a subsequently formed first power supply connection line is connected to the active layer 32 of the second transistor T2 via the via.

[0141] In an exemplary embodiment, the fourth via V4 may be provided on each subpixel, and the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the second area 32-2 of the active layer 32 of the second transistor T2, and at least partially overlaps with the orthographic projection of the base of the shield structure 23, and the second and first insulating layers within the fourth via V4 are etched to simultaneously expose the surface of the second area 32-2 of the active layer 32 of the second transistor T2 and the surface of the shield structure 23. In an exemplary embodiment, the fourth via V4 is configured such that the second pole of the subsequently formed second transistor T2 is simultaneously connected to the shield structure 23 and the active layer 32 of the second transistor T2 via the via.

[0142] In an exemplary embodiment, the fifth via V5 may be located between the second subpixel P2 and the third subpixel P3, and the orthographic projection of the base of the fifth via V5 at least partially overlaps with the orthographic projection of the base of the compensation connection line 35 and at least partially overlaps with the orthographic projection of the base of the compensation signal line 22, and the second and first insulating layers within the fifth via V5 are etched to simultaneously expose the surfaces of the compensation connection line 35 and the compensation signal line 22. In an exemplary embodiment, the fifth via V5 is configured such that the first pole of a subsequently formed third transistor T3 is simultaneously connected to the compensation signal line 22 and the compensation connection line 35 via the via.

[0143] In an exemplary embodiment, the sixth via V6 may be provided on each subpixel, and the orthographic projection of the base of the sixth via V6 lies within the orthographic projection of the base of the second area 33-2 of the active layer 33 of the third transistor T3, and the second insulating layer within the sixth via V6 is etched to expose the surface of the second area 33-2 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the sixth via V6 is configured such that the second pole of the subsequently formed third transistor T3 is connected to the active layer 33 of the third transistor T3 via the via.

[0144] In an exemplary embodiment, the seventh via V7 may be located between the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the base of the seventh via V7 is within the range of the orthographic projection of the base of the first power line 21, and the second insulating layer within the seventh via V7 is etched to expose the surface of the first power line 21. In an exemplary embodiment, the seventh via V7 is configured such that a subsequently formed first power auxiliary line is connected to the first power line 21 via the via.

[0145] In an exemplary embodiment, the eighth via V8 may be installed on each subpixel, the orthographic projection of the base of the eighth via V8 is within the range of the orthographic projection of the base of the data signal line 25, and the second and first insulating layers within the eighth via V8 are etched to expose the surface of the data signal line 25. In an exemplary embodiment, the eighth via V8 is configured so that a subsequently formed auxiliary data line is connected to the data signal line 25 through the via. In an exemplary embodiment, there may be a plurality of eighth vias V8, and the plurality of eighth vias V8 may be arranged sequentially along the second direction Y, thereby improving the connection reliability between the data signal line and the auxiliary data line.

[0146] In an exemplary embodiment, the ninth via V9 may be located on each subpixel, the orthographic projection of the base of the ninth via V9 is located within the range of the orthographic projection of the base of the second electrode plate 34, and the second insulating layer within the ninth via V9 is etched to expose the surface of the second electrode plate 25. In an exemplary embodiment, the ninth via V9 is configured such that the gate electrode of a subsequently formed second transistor T2 is connected to the second electrode plate 34 via the via.

[0147] In an exemplary embodiment, the plurality of first connecting vias K1 may include a third via V3, a sixth via V6, and a ninth via V9, and the plurality of second connecting vias K2 may include a first via V1, a fourth via V4, and a fifth via V5.

[0148] In exemplary embodiments, the present process further includes a conduction treatment. In the conduction treatment, after forming a second insulating layer pattern, plasma treatment is performed using the second insulating layer as a shield. The semiconductor layer in the region shielded by the second insulating layer remains unconductive, while the semiconductor layer in the region not shielded by the second insulating layer in multiple vias is treated to become a conduction layer. Thus, the first conduction region d1 and the second conduction region d2 undergo the conduction treatment in the present process.

[0149] (15) Forming a third conductive layer pattern. In exemplary embodiments, as shown in Figures 10a and 10b, the formation of the third conductive layer pattern may include depositing a third conductive thin film on a base on which the aforementioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern to be placed on the second insulating layer, wherein the third conductive layer pattern includes at least a first scanning signal line 41, a second gate electrode 42, a first power supply connection line 43, a first power supply auxiliary line 44, an auxiliary data line 45, a second relay connection electrode 47, a third relay connection electrode 48, and a fourth relay connection electrode 411, and Figure 10b is a schematic plan view of the third conductive layer in Figure 10a. In exemplary embodiments, the third conductive layer may be referred to as a gate metal (GATE) layer.

[0150] In the exemplary embodiment, the first scan signal line 41 has a stripe structure in which the main body extends along the first direction X, and in the second direction Y, the first scan signal line 41 is located on the side of the second electrode plate 34 away from the active layer of the second transistor T2. The first scan signal line 41 is provided across the first subpixels P1 to the fourth subpixels P4, and a first gate electrode 41-1 and a third gate electrode 41-3 are provided on the first scan signal line 41 of each subpixel. The first gate electrode 41-1 serves as the gate electrode of the first transistor T1, and there is an overlapping region between the orthographic projection of the base of the first gate electrode 41-1 and the orthographic projection of the base of the active layer 31 of the first transistor T1. The third gate electrode 41-3 serves as the gate electrode of the third transistor T31, and there is an overlapping region between the orthographic projection of the base of the third gate electrode 41-3 and the orthographic projection of the base of the active layer 33 of the third transistor T31. In the exemplary embodiment, in the second direction Y, the first gate electrode 41-1 and the third gate electrode 41-3 may be located on opposite sides of the main portion of the first scan signal line 41, and the third gate electrode 41-3 is located on the side of the main portion of the first scan signal line 41 away from the second electrode plate 34. In the exemplary embodiment, the first scan signal line 41 is configured to be shared by the third transistor T2 and the first transistor T1, saving space.

[0151] In the exemplary embodiment, the second gate electrode 42 is formed within each subpixel and serves as the gate electrode of the second transistor T2. In each subpixel, there is an overlapping region between the orthographic projection of the base of the second gate electrode 42 and the orthographic projection of the base of the active layer 32 of the second transistor T2, and on the other hand, there is an overlapping region between the orthographic projection of the base of the second gate electrode 42 and the second electrode plate 34. The second gate electrode 42 has a stripe structure extending along the first direction X, and in the second direction Y, the second gate electrode 42 is located on the side of the second electrode plate 34 away from the first scan signal line 41. The second gate electrode 42 may also be connected to the second electrode plate 34 via a ninth via V9, thereby the second gate electrode 42 and the second electrode plate 34 having the same potential.

[0152] In exemplary embodiments, the first power supply connection line 43 may be a stripe structure extending along a first direction X, and the first power supply connection line 43 may be extended across first subpixels P1 to fourth subpixels P4 and integrally molded with the first power supply auxiliary line 44. In the second direction Y, the first power supply connection line 43 may be located on the side of the second gate electrode 42 away from the second electrode plate 34. The orthographic projection of the first power supply connection line 43 at the base at least partially overlaps with the active layer 32 of the second transistor T2, and the first power supply connection line 43 is electrically connected to the active layer 32 of the second transistor T2 via a third via V3, providing the first power supply signal to the second transistor T2. In exemplary embodiments, the first power supply connection line 43 may be reused as the first electrode of the second transistor T2.

[0153] In an exemplary embodiment, the first power supply auxiliary line 44 is formed on the first subpixel P1 and the fourth subpixel P4 and has a stripe structure extending along the second direction Y. At the first subpixel P1, in the first direction X, the first power supply auxiliary line 44 is located on the side of the second electrode plate 34 away from the second subpixel P2. At the fourth subpixel P4, in the first direction X, the first power supply auxiliary line 44 is located on the side of the second electrode plate 34 away from the third subpixel P3. The first power supply auxiliary line 44 is connected to the first power supply line 21 via a seventh via V7 to form a double-layer wiring, ensuring the reliability of power signal transport and reducing the resistance of the first power supply line 21.

[0154] In an exemplary embodiment, the auxiliary data lines 45 are formed in each subpixel and have a stripe structure extending along the second direction Y. Within the first subpixel P1 and the third subpixel P3, the auxiliary data lines 45 are located on the first direction X side of the second electrode plate 34. Within the second subpixel P2 and the fourth subpixel P4, the auxiliary data lines 45 are located on the side of the second electrode plate 34 opposite to the first direction X. The auxiliary data lines 45 are connected to the data signal lines 25 to form a double-layer wiring, ensuring the reliability of data signal transport and reducing the resistance of the data signal lines.

[0155] In an exemplary embodiment, the main portions of the first power supply auxiliary line 44 and the auxiliary data line 45 may be installed in parallel.

[0156] In an exemplary embodiment, the second relay connection electrode 47 is formed on each subpixel, and the orthographic projection of the second relay connection electrode 47 on the base at least partially overlaps with the orthographic projection of the second area 32-2 on the base of the active layer 32 of the second transistor T2, and at least partially overlaps with the orthographic projection of the base of the shield structure 23, and the second relay connection electrode 47 is configured to be connected to the second area 32-2 of the active layer 32 of the second transistor T2 and the shield structure 23 via a second via V4. In an exemplary embodiment, the second relay connection electrode 47 may also be the second electrode of the second transistor T2.

[0157] In an exemplary embodiment, a third relay connection electrode 48 is formed on each subpixel, and the orthographic projection of the base of the third relay connection electrode 48 at least partially overlaps with the orthographic projection of the base of the second area 33-2 of the active layer 33 of the third transistor T3, and the third relay connection electrode 48 is configured to be connected to the second area 33-2 of the active layer 33 of the third transistor T3 via a sixth via V6. In an exemplary embodiment, the third relay connection electrode 48 may also be the second electrode of the third transistor T3.

[0158] In an exemplary embodiment, the fourth relay connection electrode 411 is positioned between the second subpixel P2 and the third subpixel P3, the orthographic projection of the base of the fourth relay connection electrode 411 at least partially overlaps with the orthographic projection of the base of the compensation signal line 22 and at least partially overlaps with the orthographic projection of the base of the compensation connection line 35, the fourth relay connection electrode 411 is configured to be connected to the compensation signal line 22 and the compensation connection line 35 via the fifth via V5, and the fourth relay connection electrode 411 may also be the first pole of the third transistor T3.

[0159] In exemplary embodiments, the present process further includes a conduction treatment. In the conduction treatment, after forming a third conductive layer pattern, plasma treatment is performed using the third conductive layer as a shield. The semiconductor layer in the region shielded by the first gate electrode, second gate electrode, and third gate electrode becomes the channel region of the transistor, and the semiconductor layer in the region not shielded by the third conductive layer is treated to become a conduction layer, forming a conductionized second electrode plate 34 and a conductionized source-drain region. The third conductionized region is subjected to the conduction treatment by the present process.

[0160] (16) Forming a third insulating layer and a flat layer pattern. In an exemplary embodiment, as shown in Figure 11, the formation of the flat layer pattern may include sequentially applying a third insulating thin film and a flat thin film to a base on which the aforementioned pattern has been formed, and patterning the third insulating thin film and the flat thin film by a patterning process to form a third insulating layer and a flat layer pattern covering the third conductive layer, wherein a plurality of vias are opened in the third insulating layer and the flat layer, and the plurality of vias include at least a 20th via V20 and a 21st via V21 located in each subpixel.

[0161] In an exemplary embodiment, the 20th via V20 may be installed in each subpixel, and the orthographic projection of the base of the 20th via V20 lies within the orthographic projection of the base of the third relay connection electrode 48, and the flat layer and third insulating layer within the 20th via V20 are removed to expose the surface of the third relay connection electrode 48. In an exemplary embodiment, the 20th via V20 is configured such that a subsequently formed anode is connected to the third relay connection electrode 48 via the via.

[0162] In an exemplary embodiment, the 21st via V21 may be installed in each subpixel, the orthographic projection of the base of the 21st via V21 is within the range of the orthographic projection of the base of the second relay connection electrode 47, and the flat layer and third insulating layer within the 21st via V21 are removed to expose the surface of the second relay connection electrode 47. In an exemplary embodiment, the 21st via V21 is configured such that a subsequently formed anode is connected to the second relay connection electrode 47 via the via.

[0163] At this point, the manufacturing of the drive circuit layer on the base is complete. In a plane parallel to the display substrate, the drive circuit layer may include multiple subpixels, each subpixel may include a pixel drive circuit and a first scan signal line, a first power line, a data signal line, and a compensation signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a flat layer that are sequentially stacked on the base.

[0164] In an exemplary embodiment, after the manufacturing of the drive circuit layer is completed, a light-emitting structure layer is manufactured on the drive circuit layer, and the manufacturing process of the light-emitting structure layer may include the following operations.

[0165] (17) Forming a fourth conductive layer pattern. In exemplary embodiments, as shown in Figures 12a and 12b, the formation of the fourth conductive layer pattern may include depositing a fourth conductive thin film on a base on which the aforementioned pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern to be placed on a flat layer, the fourth conductive layer pattern including at least an anode 301 located at each subpixel, and Figure 12b is a schematic plan view of the fifth conductive layer in Figure 12a. In exemplary embodiments, the fourth conductive layer may be referred to as a second transparent (ITO2) layer.

[0166] In the embodiments of this disclosure, the second transparent layer may be the transparent conductive layer described above.

[0167] In an exemplary embodiment, the fourth conductive layer pattern may include a first anode 301R located at the first subpixel P1, a second anode 301W located at the second subpixel P2, a third anode 301G located at the third subpixel P3, and a fourth anode 301B located at the fourth subpixel P4. The anode 301 at each subpixel is connected to a third relay connection electrode 48 via a 20th via V20. The third relay connection electrode 48 serves as the second pole of the third transistor T3, thereby realizing a connection between the anode 301 and the third transistor T3. The anode 301 at each subpixel is connected to a second relay connection electrode 47 via a 21st via V21. The second relay connection electrode 47 serves as the second pole of the second transistor T2, thereby realizing a connection between the anode 301 and the second transistor T2.

[0168] In exemplary embodiments, the first anode 301R, second anode 301W, third anode 301B, and fourth anode 301G may be stripes extending along the second direction Y. In the second direction Y, a first connection electrode 3011 and a second connection electrode 3012 are provided on both sides of the anode in each subpixel, the first connection electrode 3011 is connected to the third relay connection electrode 48 via the 20th via V20, and the second connection electrode 3012 is connected to the second relay connection electrode 47 via the 21st via V21. The anode and the first and second connection electrodes 3011 and 3012 in each subpixel may be integrally molded structures.

[0169] In an exemplary embodiment, the orthographic projection of the anode base at each subpixel includes the orthographic projection of the storage capacitor base at the subpixel where it is located.

[0170] In an exemplary embodiment, the 20th via V20 may be the second relay via, and the 21st via V21 may be the first relay via.

[0171] (18) Forming a pixel definition layer pattern. In exemplary embodiments, as shown in Figures 13a and 13b, the formation of a pixel definition layer pattern may include coating a pixel definition thin film onto a base on which the aforementioned pattern is formed, and patterning the pixel definition thin film by a patterning process to form a pattern for the pixel definition layer 302, the pattern for the pixel definition layer 302 including at least a pixel aperture located at each subpixel, and Figure 13b is a schematic plan view of the pixel definition layer in Figure 13a.

[0172] In an exemplary embodiment, the pattern of the pixel definition layer 302 may include a red pixel aperture 302R that exposes a red anode 301R located at the first subpixel P1, a white pixel aperture 302W that exposes a white anode 301W located at the second subpixel P2, a green aperture 302G that exposes a green anode 301G located at the third subpixel P3, and a blue pixel aperture 302B that exposes a blue anode 301B located at the fourth subpixel P4.

[0173] In exemplary embodiments, the shape and area of ​​the pixel apertures of different subpixels may differ. In exemplary embodiments of the present disclosure, by designing the four subpixels to have different aperture ratios, it is possible to adapt to the transmittance of different subpixel color film layers, the four subpixel light-emitting devices can emit the same brightness at different currents, and the lifespan of the four subpixel light-emitting devices is optimized to the maximum extent and ensure product life.

[0174] In an exemplary embodiment, the orthographic projection of the pixel aperture at the base of each subpixel at least partially overlaps with the orthographic projection of the storage capacitor at the base of the subpixel where it is located.

[0175] In exemplary embodiments, the subsequent manufacturing flow may include forming an organic light-emitting layer by employing a vapor deposition coating or inkjet printing process, connecting the organic light-emitting layer to an anode via a pixel aperture, forming a cathode in the organic light-emitting layer, connecting the cathode to the organic light-emitting layer, and forming an encapsulation layer. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is placed between the first and third encapsulation layers to prevent external water vapor from entering the light-emitting structure layer.

[0176] In exemplary embodiments, the first and fourth conductive layers may be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second and third conductive layers may be made of metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multi-layer structure, or composite layer. The first insulating layer is called the buffer layer, the second insulating layer is called the gate insulating (GI) layer, and the third insulating layer is called the interlayer insulating (PVX) layer. The flat layer may be made of an organic material, such as resin. The pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate.

[0177] The display substrate manufactured by steps (11) to (18) above consists of six array substrate masks (Array MASK) and five color film substrate masks (CF MASK). The Array MASK includes samples of the first conductive layer (CF_ITO), shield metal layer (SHIELD), semiconductor layer (ACT), second insulating layer (GI), gate metal layer (GT), and sixth conductive layer (ITO). The five CF MASKs include a planar layer (RESIN), pixel definition layer (PDL), red light-emitting layer (Red), green light-emitting layer (Green), and blue light-emitting layer (Blue). The number of masks used is small, the manufacturing flow is simplified, and manufacturing costs can be reduced. Compared to pixel designs in related technologies, the wiring of data signal lines and the first power line VDD has been changed from the source-drain metal layer SD to the shield layer SHIELD, reducing the mask of the source-drain metal layer SD, eliminating CNT holes and ILD holes, adding GI holes, and the flat layer (RESIN) and the third insulating layer PVX layer sharing one mask, thereby simplifying the manufacturing flow to a great extent and reducing manufacturing costs. The GT layer and ACT layer, and the GT layer and SHIELD layer are connected to each other via GI holes. In addition, the data signal lines employ a two-layer wiring of SHIELD and GT to reduce the impedance of the data signal lines. The first power line VDD employs a two-layer wiring of SHIELD and GT in the vertical direction (second direction Y) to reduce impedance and reduce RC between the first power line and the data signal lines. The capacitors employ a transparent capacitor CF_ITO / SHIELD-ACT capacitor structure, with CF_ITO and SHIELD in direct contact, and their conductivity is connected to each other, and the RGB capacitors are the same size.

[0178] In an exemplary embodiment, taking four subpixels (first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4) as an example, other fabrication processes for the drive circuit layer may include the following operations.

[0179] (21) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 14, the formation of the first conductive layer pattern may include depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern on the base, the first conductive layer pattern including at least a first electrode plate 11 formed on each subpixel. In an exemplary embodiment, the first conductive layer may be referred to as a first transparent (ITO1) layer.

[0180] In exemplary embodiments, the first electrode plate 11 in each subpixel is configured to form one of the transparent electrodes of a storage capacitor, and the first electrode plate 11 may be rectangular, and the edges of the rectangle may be polylines. In exemplary embodiments, the size of the first electrode plate 11 located at the second subpixel P2 and the first electrode plate 11 located at the third subpixel P3 along the second direction Y is smaller than the size of the first electrode plate located at the first subpixel P1 and the first electrode plate located at the fourth subpixel P4 along the second direction Y.

[0181] (22) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in Figure 15, the formation of the second conductive layer pattern may include depositing a second conductive thin film on a base on which the aforementioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern covering the first conductive layer, wherein the second conductive layer pattern includes at least a first scanning signal line 41, and Figure 15 is a schematic plan view of the second conductive layer and the first conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as a first shield metal (SHL1) layer.

[0182] In an exemplary embodiment, the first scan signal line 41 has a stripe structure extending along a first direction X, and in the first direction X, the first scan signal line 41 is provided across the first subpixel P1 to the fourth subpixel P4. In the second direction Y, the first scan signal line 41 is located on one side of the first electrode plate 11.

[0183] (23) Forming a third conductive layer pattern. In exemplary embodiments, as shown in Figures 16a and 16b, the formation of the third conductive layer pattern may include depositing a third conductive thin film on a base on which the aforementioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the base, the third conductive layer pattern including at least a shield structure 23, a first scanning signal auxiliary line 410, a compensation connection line 35, and a first auxiliary data line 451, and Figure 16b is a schematic plan view of the third conductive layer in Figure 16a. In exemplary embodiments, the third conductive layer may be referred to as a second shield metal (SHL2) layer.

[0184] In exemplary embodiments, the shield structure 23 may be installed on each subpixel, and the shield structure 23 may be rectangular, and the rectangular structure may have a chamfer. In the second direction Y, the shield structure 23 may be located on the side of the first auxiliary data line 451 away from the first scan signal auxiliary line 410. In exemplary embodiments, the orthographic projection of the base of the shield structure 23 at least partially overlaps with the orthographic projection of the base of the first electrode plate 11, and the shield structure 23 is connected to the first electrode plate.

[0185] In an exemplary embodiment, the first scan signal auxiliary line 410 is a stripe structure extending along a first direction X, and in the first direction X, the first scan signal line 41 is provided across the first subpixels P1 to the fourth subpixels P4. In a second direction Y, the first scan signal line 41 is located on one side of the first electrode plate 11 and between the first electrode plate 11 and the compensation connection line 35. In an exemplary embodiment, the orthographic projection of the base of the first scan signal auxiliary line 410 at least partially overlaps with the orthographic projection of the base of the first scan signal line 41, and the first scan signal auxiliary line 410 is connected to the first scan signal line 41 to form a double-layer wiring, thereby reducing the resistance of the scan signal line 41.

[0186] In an exemplary embodiment, in the second direction Y, the compensation connection line 35 is located on the side of the first scanning signal auxiliary line 410 away from the first electrode plate 11, and the compensation connection line 35 may be a stripe structure extending along the first direction X, and in the first direction X, the compensation connection line 35 is provided across the first subpixel P1 to the fourth subpixel P4.

[0187] In exemplary embodiments, the first auxiliary data lines 451 are provided for each subpixel, and the first auxiliary data lines 451 may be in the form of a stripe structure extending along a second direction Y, and in the second direction Y, the first auxiliary data lines 451 may be located between the first scan signal auxiliary line 410 and the shield structure 23. In exemplary embodiments, the first auxiliary data lines 451 are configured to be electrically connected to subsequently formed data signal lines 25 to form a double-layer wiring, thereby reducing the resistance of the data signal lines.

[0188] (24) Forming a semiconductor layer pattern. In exemplary embodiments, as shown in Figures 17a and 17b, the formation of a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base, and patterning the semiconductor thin film by a patterning process to form a first insulating layer covering a third conductive layer and a semiconductor layer pattern placed on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer 31 of a first transistor T1, an active layer 32 of a second transistor T2, an active layer 33 of a third transistor T3, a second electrode plate 34 and a first power supply connection line 43 formed on each subpixel, and Figure 17b is a schematic plan view of the semiconductor layer in Figure 17a.

[0189] In an exemplary embodiment, there is an overlapping region between the orthographic projection of the base of the second plate 34 and the orthographic projection of the base of the first plate 11 in each subpixel, the second plate 34 is configured to form the other transparent plate of the storage capacitor, and the first plate 11 and the second plate 34 form a transparent storage capacitor.

[0190] In exemplary embodiments, the shape of the second electrode plate 34 may be rectangular, and the edges of the rectangle may be broken lines.

[0191] In exemplary embodiments, in each subpixel, the shape of the second electrode plate 34 may be similar to the shape of the first electrode plate 11 in the subpixel where it is located, and the orthographic projection of the base of the second electrode plate 34 may cover the orthographic projection of the base of the first electrode plate 11.

[0192] In the exemplary embodiment, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, and the active layer 33 of the third transistor T3 all include a channel region and a first area and a second area located on both sides of the channel region.

[0193] In exemplary embodiments, the shape of the active layer 31 of the first transistor T1 may be L-shaped, and in the second direction Y, the active layer 31 of the first transistor T1 may be located on one side of the second electrode plate 34.

[0194] In an exemplary embodiment, the second area 31-2 of the active layer 31 of the first transistor T1 may be connected to the second electrode plate 34, and the active layer 31 of the first transistor T1 and the second electrode plate 34 are an integrated structure connected to each other.

[0195] In an exemplary embodiment, the first area 31-1 of the active layer 31 of the first transistor T1 is a stripe structure extending along a first direction X, and the stripe structure extends from the second area 31-2 of the active layer 31 of the first transistor T1 toward adjacent subpixels. The stripe structure at the first subpixel P1 extends toward the second subpixel P2, the stripe structure at the third subpixel P3 extends toward the fourth subpixel P4, the stripe structure at the second subpixel P2 extends toward the first subpixel P1, and the stripe structure at the fourth subpixel P3 extends toward the third subpixel P3. The second area 31-2 of the active layer 31 of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2 via the second electrode of the first transistor T1 which is formed subsequently, thereby realizing interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate of the storage capacitor.

[0196] In exemplary embodiments, the shape of the active layer 32 of the second transistor T2 may be T-shaped, and in the second direction Y, the second active layer 32 may be located on the side of the second electrode plate 34 away from the active layer 31 of the first transistor T1, and the orthographic projection of the base of the active layer 32 of the second transistor T2 and the orthographic projection of the base of the second electrode plate 34 are spaced apart, that is, there is no overlapping region between the second active layer 32 and the second electrode plate 34, which contributes to the design of a proportional width and length of the channel of the second transistor to meet relevant requirements. The first area 32-1 of the active layer 32 of the second transistor T2 is located on the side of the channel region away from the second electrode plate 34, and there is an overlapping region between the orthographic projection of the base of the portion of the first area 32-1 of the active layer 32 of the second transistor T2 that is close to the channel region and the orthographic projection of the base of the shield structure 23. The second area 32-2 of the active layer 32 of the second transistor T2 is located on the side closer to the second electrode plate 34 of the channel region, and there is an overlapping region between the orthographic projection of the second area 32-2 of the active layer 32 of the second transistor T2 at the base and the orthographic projection of the shield structure 23 at the base. In this way, the shield structure 23 can block the channel region of the second active layer 32, avoiding the influence of light rays on the channel, reducing leakage current, and avoiding the influence of light irradiation on transistor characteristics. In an exemplary embodiment, the first areas of the active layer 32 of the second transistor T2 and the first power supply connection line 43 of multiple subpixels in the same pixel unit may be integrally molded structures that connect to each other.

[0197] In exemplary embodiments, the shape of the active layer 33 of the third transistor T3 may be I-shaped, and in the second direction Y, the active layer 33 of the third transistor T3 may be located on the side of the active layer 31 of the first transistor T1 away from the second plate 34, and the orthographic projection of the base of the active layer 33 of the third transistor T3 and the orthographic projection of the base of the second plate 34 are spaced apart, i.e., there is no overlapping region between the third active layer 33 and the second plate 42, which contributes to the design of a proportional width-to-length channel of the third transistor to meet relevant requirements. In exemplary embodiments, in the second direction Y, the active layer 31 of the first transistor T1 and the active layer 33 of the third transistor T3 are located on either side of the first scan signal auxiliary line 410.

[0198] In exemplary embodiments, the first power supply connection line 43 may be a stripe structure extending along a first direction X, and the first power supply connection line 43 may be extended across the first subpixels P1 to the fourth subpixels P4 and integrally molded with the active layer 33 of the third transistor T3. In the second direction Y, the first power supply connection line 43 may be located on the side away from the second electrode plate 34 of the active layer 32 of the second transistor T2.

[0199] In exemplary embodiments, the semiconductor layer can be made of metal oxides, such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multi-layer layer.

[0200] (25) Forming a fourth conductive layer pattern. In exemplary embodiments, as shown in Figures 18a and 18b, the formation of the fourth conductive layer pattern may include sequentially depositing a second insulating thin film and a fourth conductive thin film on a base, and patterning the second insulating thin film and the fourth conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer and a fourth conductive layer pattern placed on the second insulating layer, wherein the fourth conductive layer pattern includes at least a second gate electrode 42, a first power auxiliary line 44, a second auxiliary data line 452, and a first gate electrode 49, and Figure 18b is a schematic plan view of the fourth conductive layer in Figure 18a. In exemplary embodiments, the fourth conductive layer may be referred to as a gate metal (GATE) layer.

[0201] In the exemplary embodiment, the second gate electrode 42 is formed within each subpixel and serves as the gate electrode of the second transistor T2. In each subpixel, on the one hand, there is an overlapping region between the orthographic projection of the base of the second gate electrode 42 and the orthographic projection of the base of the active layer 32 of the second transistor T2, and on the other hand, there is an overlapping region between the orthographic projection of the base of the second gate electrode 42 and the shield structure 23. The second gate electrode 42 is a stripe structure extending along the first direction X, and in the second direction Y, the second gate electrode 42 is located on the side of the second electrode plate 34 away from the first transistor T1.

[0202] In an exemplary embodiment, the first power supply auxiliary line 44 is formed within the first subpixel P1 and the fourth subpixel P4 and has a stripe structure extending along the second direction Y. Within the first subpixel P1, in the first direction X, the first power supply auxiliary line 44 is located on the side of the second electrode plate 34 away from the second subpixel P2. Within the fourth subpixel P4, in the first direction X, the first power supply auxiliary line 44 is located on the side of the second electrode plate 34 closer to the third subpixel P3. The second power supply auxiliary line 452 is configured to be connected to the subsequently formed first power line to form a double-layer wiring, ensuring the reliability of power signal transmission and reducing the resistance of the first power line.

[0203] In an exemplary embodiment, the second auxiliary data line 452 is formed in each subpixel and has a stripe structure extending along the second direction Y. Within the first subpixel P1 and the third subpixel P3, the second auxiliary data line 452 is located on the first direction X side of the second electrode plate 34. Within the second subpixel P2 and the fourth subpixel P4, the second auxiliary data line 452 is located on the side of the second electrode plate 34 opposite to the first direction X. The second auxiliary data line 452 is connected to the first auxiliary data line 451 and the subsequently formed data signal line to form a three-layer wiring, ensuring the reliability of data signal transport and reducing the resistance of the data signal line. In an exemplary embodiment, there is an overlapping region between the orthographic projection at the base of the second auxiliary data line 452 and the orthographic projection at the base of the first auxiliary data line 451.

[0204] In an exemplary embodiment, the main portions of the first power supply auxiliary line 44 and the second auxiliary data line 452 may be installed in parallel.

[0205] In the exemplary embodiment, a first gate electrode 49 is formed in each subpixel and serves as the gate electrode for the first transistor T1 and the third transistor T3. In each subpixel, on the one hand, there is an overlapping region between the orthographic projection of the base of the first gate electrode 49 and the orthographic projection of the base of the active layer 32 of the first transistor T1, and on the other hand, there is an overlapping region between the orthographic projection of the base of the first gate electrode 49 and the active layer of the third transistor T3. The first gate electrode 49 has a stripe structure and a bent structure extending along the second direction Y, and in the second direction Y, the first gate electrode 49 is located on the side of the second electrode plate 34 away from the second transistor T2. Within the first subpixel P1 and the fourth subpixel P4, the first gate electrode 49 has a stripe structure, and within the second subpixel P2 and the third subpixel P3, the first gate electrode 49 has a bent structure.

[0206] In exemplary embodiments, the process further includes a conduction treatment. In the conduction treatment, after forming a third conductive layer pattern, plasma treatment is performed using the third conductive layer as a shield. The semiconductor layer in the region shielded by the first gate electrode and the second gate electrode becomes the channel region of the transistor, and the semiconductor layer in the region not shielded by the third conductive layer is treated to become a conduction layer, forming a conductionized second electrode plate 34 and a conductionized source-drain region.

[0207] (26) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in Figure 19, the formation of the third insulating layer pattern may include depositing a third insulating thin film on a base on which the aforementioned pattern is formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer covering the fourth conductive layer, wherein the third insulating layer has a plurality of vias, the plurality of vias including at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0208] In an exemplary embodiment, the first via V1 may be placed on each subpixel, the orthographic projection of the base of the first via V1 is located within the range of the orthographic projection of the base of the first area 31-1 of the active layer 31 of the first transistor T1, and the third and second insulating layers within the first via V1 are etched to expose the surface of the first area 31-1 of the active layer 31 of the first transistor T1. In an exemplary embodiment, the first via V1 is configured such that a subsequently formed data signal line is connected to the active layer 31 of the first transistor T1 via the via.

[0209] In an exemplary embodiment, the second via V2 may be placed on each subpixel, and the orthographic projection of the base of the second via V2 lies within the orthographic projection of the base of the second area 31-2 of the active layer 31 of the first transistor T1, and the third and second insulating layers within the second via V2 are etched to simultaneously expose the surface of the second area 31-2 of the first active layer 31. In an exemplary embodiment, the second via V2 is configured such that the second pole of the subsequently formed first transistor T1 is connected to the active layer 31 of the first transistor T1 via the via.

[0210] In an exemplary embodiment, the third via V3 may be placed on each subpixel, and the orthographic projection of the base of the third via V3 lies within the orthographic projection of the base of the first area 32-1 of the active layer 32 of the second transistor T2, and the third and second insulating layers within the third via V3 are etched to expose the surface of the first area 32-1 of the active layer 32 of the second transistor T2. In an exemplary embodiment, the third via V3 is configured such that a subsequently formed first power line is electrically connected to the active layer 32 of the second transistor T2.

[0211] In an exemplary embodiment, the fourth via V4 may be provided on each subpixel, and the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the second area 32-2 of the active layer 32 of the second transistor T2, and at least partially overlaps with the orthographic projection of the base of the shield structure 23, and the third insulating layer, second insulating layer and first insulating layer within the fourth via V4 are etched to simultaneously expose the surface of the second area 32-2 of the active layer 32 of the second transistor T2 and the surface of the shield structure 23. In an exemplary embodiment, the second area 32-2 is configured such that the second pole of the subsequently formed second transistor T2 is simultaneously connected to the shield structure 23 and the active layer 32 of the second transistor T2 via the via.

[0212] In an exemplary embodiment, the fifth via V5 may be provided on each subpixel, and the orthographic projection of the base of the fifth via V5 at least partially overlaps with the orthographic projection of the base of the first area 33-1 of the active layer 33 of the third transistor T3, and the third and second insulating layers within the fifth via V5 are etched to expose the surface of the first area 33-1 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the fifth via V5 is configured such that the first pole of the subsequently formed third transistor T3 is connected to the active layer 33 of the third transistor T2 via the via.

[0213] In an exemplary embodiment, the sixth via V6 may be provided on each subpixel, and the orthographic projection of the base of the sixth via V6 at least partially overlaps with the orthographic projection of the base of the second area 33-2 of the active layer 33 of the third transistor T3, and the third and second insulating layers within the sixth via V6 are etched to expose the surface of the second area 33-2 of the active layer 33 of the third transistor T3. In an exemplary embodiment, the sixth via V6 is configured such that the second pole of the subsequently formed third transistor T3 is connected to the active layer 33 of the third transistor T2 via the via.

[0214] In an exemplary embodiment, the seventh via V7 may be installed between the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the base of the seventh via V7 is within the range of the orthographic projection of the base of the first power supply auxiliary line 44, and the third insulating layer within the seventh via V7 is etched to expose the surface of the first power supply auxiliary line 44. In an exemplary embodiment, the seventh via V7 is configured so that a subsequently formed first power supply line is connected to the first power supply auxiliary line 44 through the via. In an exemplary embodiment, multiple seventh vias V7 may be installed. Multiple seventh vias V7 are arranged sequentially along a second direction Y to improve the connection reliability between the first power supply line and the first power supply auxiliary line 44.

[0215] In an exemplary embodiment, the eighth via V8 may be located on the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the base of the eighth via V8 is within the range of the orthographic projection of the base of the compensation connection line 35, and the third, second, and first insulating layers within the eighth via V8 are etched to expose the surface of the compensation connection line 35. In an exemplary embodiment, the eighth via V8 is configured such that the first pole of a subsequently formed third transistor T3 is connected to the compensation connection line 35 via the via.

[0216] In an exemplary embodiment, the ninth via V9 may be installed on each subpixel, and the orthographic projection of the base of the ninth via V9 lies within the orthographic projection of the base of the first scan signal auxiliary line 410 and within the orthographic projection of the base of the first gate electrode 49, and the third, second, and first insulating layers within the ninth via V9 are etched to expose the surfaces of the first scan signal auxiliary line 410 and the first gate electrode 49. In an exemplary embodiment, the ninth via V9 is configured such that a subsequently formed gate electrode relay connection electrode is connected to the first scan signal auxiliary line 410 and the first gate electrode 49 via the via.

[0217] In an exemplary embodiment, the 10th via V10 may be installed on each subpixel, and the orthographic projection of the 10th via V10 on its base lies within the orthographic projection range of the second gate electrode 42 on its base and within the orthographic projection range of the second electrode plate 34 on its base, and the third and second insulating layers within the 10th via V10 are etched to expose the surfaces of the second electrode plate 34 and the second gate electrode 42. In an exemplary embodiment, the 10th via V10 is configured such that the second pole of a subsequently formed second transistor T2 is connected to the second gate electrode 42 and the second electrode plate 34.

[0218] In an exemplary embodiment, the 11th via V11 may be installed on each subpixel, the orthographic projection of the base of the 11th via V11 is within the range of the orthographic projection of the base of the second auxiliary data line 452, and the third insulating layer within the 11th via V11 is etched to expose the surface of the second auxiliary data line 452. In an exemplary embodiment, the 11th via V11 is configured such that a subsequently formed data signal line is connected to the second auxiliary data line 452 through the via. In an exemplary embodiment, there may be a plurality of 11th vias V11, which are arranged sequentially along a second direction Y to improve the connection reliability between the data signal line and the second auxiliary data line 452.

[0219] In an exemplary embodiment, the 12th via V12 may be installed on each subpixel, the orthographic projection of the 12th via V12 at its base lies within the range of the orthographic projection of the first auxiliary data line 451 at its base, and the third, second, and first insulating layers within the 12th via V12 are etched to expose the surface of the first auxiliary data line 451. In an exemplary embodiment, the 12th via V12 is configured such that a subsequently formed data signal line is connected to the first auxiliary data line 451 through the via.

[0220] In an exemplary embodiment, the 13th via V13 may be located between the second subpixel P2 and the third subpixel P3, the orthographic projection of the base of the 13th via V13 is within the range of the orthographic projection of the base of the compensation connection line 35, and the third, second, and first insulating layers within the 13th via V13 are etched to expose the surface of the compensation connection line 35. In an exemplary embodiment, the 13th via V13 is configured such that a subsequently formed compensation signal line is connected to the compensation connection line 35 via the via.

[0221] (27) Forming a fifth conductive layer pattern. In exemplary embodiments, as shown in Figures 20a and 20b, the formation of the fifth conductive layer may include depositing a fifth conductive thin film on a base on which the aforementioned pattern is formed, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer to be placed on the third insulating layer, wherein the fifth conductive layer includes at least a first power line 21, a compensation signal line 22, a data signal line 25, a gate electrode relay connection electrode 26, a first relay connection electrode 46, a second relay connection electrode 47, a third relay connection electrode 48, a fourth relay connection electrode 411, and a fifth relay connection electrode 412, and Figure 20b is a schematic plan view of the fifth conductive layer in Figure 20a. In exemplary embodiments, the fifth conductive layer may be referred to as a source-drain metal (SD) layer.

[0222] In an exemplary embodiment, the first power line 21 is installed in the first sub-pixel P1 and the fourth sub-pixel P4, respectively, and the main portion of the first power line 21 extends along the second direction Y. On the one hand, the first power line 21 is connected to the first area 32-1 of the second active layer 32 via the third via V3, enabling the writing of the power signal to the second transistor T2. On the other hand, the first power line 21 is connected to the first auxiliary power line 44 via a plurality of seventh vias V7, thereby forming a double-layer wiring between the first power line 21 and the first auxiliary power line 44. Furthermore, the first power line 21 is connected to the first power connection line 43 via the third via V3, thereby enabling the first power connection line 43 to transport the power signal to the second sub-pixel P2 and the third sub-pixel P3, respectively.

[0223] In the exemplary embodiment, each data signal line 25 is installed in each subpixel, and the main portion of the data signal line 25 extends along the second direction Y. On the one hand, the data signal line 25 is connected to the first area 31-1 of the first active layer 31 via the first via V1, enabling the writing of the data signal to the first transistor T1. On the other hand, the data signal line 25 is connected to the second auxiliary data line 452 via a plurality of eleventh vias V11, thereby forming a two-layer wiring between the data signal line 25 and the second auxiliary data line 452. Furthermore, the data signal line 25 is connected to the first auxiliary data line 451 via a plurality of twelfth vias V12, thereby forming a three-layer wiring between the data signal line 25, the first auxiliary data line 451, and the second auxiliary data line 452.

[0224] In an exemplary embodiment, the compensation signal line 22 is located between the second subpixel P2 and the third subpixel P3, and the main portion of the compensation signal line 22 extends along the second direction Y. The compensation signal line 22 is connected to the compensation connection line 35 via the 13th via V13 and to the first area of ​​the active layer of the third transistor T3 via the 5th via V5, and the compensation signal line 22 is configured to write a compensation signal to the third transistor T3. In an exemplary embodiment, the compensation signal line 22 may also be the first pole of the third transistor T3. In embodiments of this disclosure, the orthographic projection of the base of the compensation signal line 22 at least partially overlaps with the orthographic projection of the base of the first area of ​​two adjacent third transistors T3, and the two adjacent third transistors T3 may share a first pole, effectively utilizing layout space and saving space on the display substrate.

[0225] In an exemplary embodiment, the gate electrode relay connection electrode 26 is installed in each subpixel, and the gate electrode relay connection electrode 26 may have a rectangular structure. The gate electrode relay connection electrode 26 is connected to the first gate electrode 49 and the first scan signal auxiliary line 410 via the ninth via V9.

[0226] In an exemplary embodiment, a first relay connection electrode 46 is formed on each subpixel, and the orthographic projection of the first relay connection electrode 46 at its base at least partially overlaps with the orthographic projection of the second area 31-2 at its base on the active layer 31 of the first transistor T1, and the first relay connection electrode 46 is configured to be connected to the second area 31-2 of the active layer 31 of the first transistor T1 via a second via V2. In an exemplary embodiment, the first relay connection electrode 46 may also be the second electrode of the first transistor T1.

[0227] In an exemplary embodiment, the second relay connection electrode 47 is formed on each subpixel, and the orthographic projection of the second relay connection electrode 47 on the base at least partially overlaps with the orthographic projection of the second area 32-2 on the base of the active layer 32 of the second transistor T2, and at least partially overlaps with the orthographic projection of the base of the shield structure 23, and the second relay connection electrode 47 is configured to be connected to the second area 32-2 of the active layer 32 of the second transistor T2 and the shield structure 23 via a second via V4. In an exemplary embodiment, the second relay connection electrode 47 may also be the second electrode of the second transistor T2.

[0228] In an exemplary embodiment, a third relay connection electrode 48 is formed on each subpixel, and the orthographic projection of the base of the third relay connection electrode 48 at least partially overlaps with the orthographic projection of the base of the second area 33-2 of the active layer 33 of the third transistor T3, and the third relay connection electrode 48 is configured to be connected to the second area 33-2 of the active layer 33 of the third transistor T3 via a sixth via V6. In an exemplary embodiment, the third relay connection electrode 48 may also be the second electrode of the third transistor T3.

[0229] In an exemplary embodiment, the fourth relay connection electrode 411 is installed on the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the base of the fourth relay connection electrode 411 at least partially overlaps with the orthographic projection of the base of the first area 33-1 of the active layer 33 of the third transistor T3, and at least partially overlaps with the orthographic projection of the base of the compensation connection line 35, the fourth relay connection electrode 411 is connected to the active layer 33 of the third transistor T3 via a fifth via V5 and to the compensation connection line 35 via an eighth via V8, and the fourth relay connection electrode 411 may also be the first pole of the third transistor T3.

[0230] In an exemplary embodiment, a fifth relay connection electrode 412 is installed in each subpixel, and the orthographic projection of the base of the fifth relay connection electrode 412 at least partially overlaps with the orthographic projection of the base of the second gate electrode 42 and at least partially overlaps with the orthographic projection of the base of the second electrode plate 34, and the fifth relay connection electrode 412 is connected to the second gate electrode 42 and the second electrode plate 34 via a tenth via V10.

[0231] In exemplary embodiments of the present disclosure, power signals are written to the second transistors T2 of four subpixels by providing two first power lines 21 extending along a second direction Y and one power connection line 43 extending along a first direction X. In the first subpixel P1 and the fourth subpixel P4, the first power lines 21 are directly connected to the second transistors T2 via vias. In the second subpixel P2 and the third subpixel P3, the first power lines 21 are connected to the second transistors T2 via power connection lines 43.

[0232] In exemplary embodiments of the present disclosure, the main body provides one compensation signal line 22 extending along a second direction Y and one compensation connection line 35 extending along a first direction X, thereby enabling the writing of compensation signals to the third transistor T3 of four subpixels, respectively. In the second subpixel P2 and the third subpixel P3, the compensation signal line 22 is directly connected to the third transistor T3 via vias. In the first subpixel P1 and the fourth subpixel P4, the compensation signal line 21 is connected to the third transistor T3 via compensation connection line 35. By providing a single compensation signal line to the four subpixels, the present disclosure ensures that the RC delays are approximately the same before the compensation signals are written to the transistors, thereby ensuring uniformity of the display.

[0233] In the exemplary embodiments of this disclosure, a data signal line 25 extending along a second direction Y is provided in each subpixel, and the data signal line 25 is connected to the first transistor T1 of the subpixel via a via, thereby enabling the writing of data signals to the first transistor T1 of each of the four subpixels.

[0234] In exemplary embodiments, the first power line 21, data signal line 25, and compensation signal line 22 may be straight lines or polylines of equal width, or straight lines or polylines of unequal width. By employing straight lines or polylines with variable width settings for the first power line 21, data signal line 25, and compensation signal line 22, it is possible not only to contribute to the layout of the pixel structure but also to reduce parasitic capacitors.

[0235] (28) Forming a fourth insulating layer and a planar layer pattern. In an exemplary embodiment, as shown in Figure 21, the formation of the planar layer pattern may include coating a fourth insulating layer thin film and a planar layer thin film onto a base on which the aforementioned pattern has been formed, and patterning the fourth insulating layer thin film and the planar layer thin film by a patterning process to form a fourth insulating layer and a planar layer pattern covering the fifth conductive layer, wherein a plurality of vias are opened in the fourth insulating layer and the planar layer, and the plurality of vias include at least a 20th via V20 and a 21st via V21 located in each subpixel.

[0236] In an exemplary embodiment, the 20th via V20 may be installed in each subpixel, the orthographic projection of the base of the 20th via V20 is within the range of the orthographic projection of the base of the third relay connection electrode 48, and the flat layer and fourth insulating layer within the 20th via V20 are removed to expose the surface of the third relay connection electrode 48. In an exemplary embodiment, the 20th via V20 is configured such that a subsequently formed anode is connected to the third relay connection electrode 48 via the via.

[0237] In an exemplary embodiment, the 21st via V21 may be installed in each subpixel, the orthographic projection of the base of the 21st via V21 is within the range of the orthographic projection of the base of the second relay connection electrode 47, and the flat layer and the fourth insulating layer within the 21st via V21 are removed to expose the surface of the second relay connection electrode 47. In an exemplary embodiment, the 21st via V21 is configured such that a subsequently formed anode is connected to the second relay connection electrode 47 via the via.

[0238] In the embodiments of this disclosure, the fourth insulating layer and the planar layer pattern are formed in a single patterning process, simplifying the flow, reducing manufacturing costs, and increasing manufacturing efficiency.

[0239] At this point, the manufacturing of the drive circuit layer on the base is complete. In a plane parallel to the display substrate, the drive circuit layer may include multiple subpixels, each subpixel may include a pixel drive circuit and a first scan signal line, a first power line, a data signal line, and a compensation signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive circuit layer may include a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a fourth conductive layer, a third insulating layer, a fifth conductive layer, a fourth insulating layer, and a flat layer, which are sequentially stacked on the base.

[0240] In an exemplary embodiment, after the manufacturing of the drive circuit layer is completed, a light-emitting structure layer is manufactured on the drive circuit layer, and the manufacturing process of the light-emitting structure layer may include the following operations.

[0241] (29) Forming a sixth conductive layer pattern. In exemplary embodiments, as shown in Figures 22a and 22b, the formation of the sixth conductive layer pattern may include depositing a sixth conductive thin film on a base on which the aforementioned pattern is formed, and patterning the sixth conductive thin film by a patterning process to form a sixth conductive layer pattern to be placed on a flat layer, the sixth conductive layer pattern including at least an anode 301 located at each subpixel, and Figure 22b is a schematic plan view of the sixth conductive layer in Figure 22a. In exemplary embodiments, the sixth conductive layer may be referred to as a second transparent (ITO2) layer.

[0242] In exemplary embodiments, the second transparent layer may be the transparent conductive layer described above.

[0243] In an exemplary embodiment, the sixth conductive layer pattern may include a first anode 301R located at the first subpixel P1, a second anode 301W located at the second subpixel P2, a third anode 301G located at the third subpixel P3, and a fourth anode 301B located at the fourth subpixel P4. The anode 301 at each subpixel is connected to a third relay connection electrode 48 via a 20th via V20. The third relay connection electrode 48 serves as the second pole of the third transistor T3, thereby realizing a connection between the anode 301 and the third transistor T3. The anode 301 at each subpixel is connected to a second relay connection electrode 47 via a 21st via V21. The second relay connection electrode 47 serves as the second pole of the second transistor T2, thereby realizing a connection between the anode 301 and the second transistor T2.

[0244] In the embodiments of this disclosure, the anode 301 in the sixth conductive layer is electrically connected to the second poles of the second transistor T2 and the third transistor T3, thereby effectively utilizing the layout space, saving space on the display substrate, and increasing the light-emitting area of ​​the pixel unit on the bottom emission display substrate.

[0245] In exemplary embodiments, the first anode 301R, second anode 301W, fourth anode 301B, and third anode 301G may be stripes extending along the second direction Y. In the second direction Y, a first connection electrode 3011 and a second connection electrode 3012 are provided on both sides of the anode in each subpixel, the first connection electrode 3011 is connected to the third relay connection electrode 48 via the 20th via V20, and the second connection electrode 3012 is connected to the second relay connection electrode 47 via the 21st via V21. The anode and the first and second connection electrodes 3011 and 3012 in each subpixel may be integrally molded structures.

[0246] In an exemplary embodiment, the orthographic projection of the anode base at each subpixel includes the orthographic projection of the storage capacitor base at the subpixel where it is located.

[0247] In an exemplary embodiment, the 20th via V20 may be the second relay via, and the 21st via V21 may be the first relay via.

[0248] (210) Forming a pixel definition layer pattern. In exemplary embodiments, as shown in Figures 23a and 23b, the formation of the pixel definition layer pattern may include coating a pixel definition thin film onto a base on which the aforementioned pattern is formed, and then patterning the pixel definition thin film by a patterning process to form a pattern for the pixel definition layer 302, the pattern for the pixel definition layer 302 including at least a pixel aperture located at each subpixel, and Figure 23b is a schematic plan view of the pixel definition layer in Figure 23a.

[0249] In an exemplary embodiment, the pattern of the pixel definition layer 302 may include a red pixel aperture 302R that exposes a red anode 301R located at the first subpixel P1, a white pixel aperture 302W that exposes a white anode 301W located at the second subpixel P2, a green aperture 302G that exposes a green anode 301G located at the third subpixel P3, and a blue pixel aperture 302B that exposes a blue anode 301B located at the fourth subpixel P4.

[0250] In exemplary embodiments, the shape and area of ​​the pixel apertures of different subpixels may differ. In exemplary embodiments of the present disclosure, by designing the four subpixels to have different aperture ratios, it is possible to adapt to the transmittance of different subpixel color film layers, the four subpixel light-emitting devices can emit the same brightness at different currents, and the lifespan of the four subpixel light-emitting devices is optimized to the maximum extent and ensure product life.

[0251] In an exemplary embodiment, the orthographic projection of the pixel aperture at the base of each subpixel at least partially overlaps with the orthographic projection of the storage capacitor at the base of the subpixel where it is located.

[0252] In exemplary embodiments, the subsequent manufacturing flow may include forming an organic light-emitting layer by employing a vapor deposition coating or inkjet printing process, connecting the organic light-emitting layer to an anode via a pixel aperture, forming a cathode in the organic light-emitting layer, connecting the cathode to the organic light-emitting layer, and forming an encapsulation layer. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is placed between the first and third encapsulation layers to prevent external water vapor from entering the light-emitting structure layer.

[0253] In exemplary embodiments, the first and sixth conductive layers may be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second, third, fourth, and fifth conductive layers may be made of metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multi-layer structure, or composite layer. The first insulating layer is called the buffer layer, the second insulating layer is called the gate insulating (GI) layer, the third insulating layer is called the interlayer insulating (ILD) layer, and the fourth insulating layer is called the blunting (PVX) layer. The flat layer may be made of an organic material, such as resin. The pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate.

[0254] Since the resistance coefficient (RC) of data signal lines and scan signal lines is the main limiting factor for the feasibility of the refresh frequency of the display board, reducing their RC is one of the requirements for the layout design of the display board. In the display board obtained by the manufacturing method of steps (21) to (210) above, the second shield metal layer transports the signal of the first scan signal line and reduces the capacitance of the first scan signal line by increasing the distance from the source drain metal layer. In exemplary embodiments, the first shield metal layer employs thick Cu wiring to reduce the resistance of the first scan signal line. To prevent the thick first shield metal layer from cutting the active layer at the edge position of the overlapping portion between the first shield metal layer and the active layer, the shield metal layer employs a two-layer design and is deposited in two stages. The portion for the first scan signal line employs a thick first shield metal layer, and the shield structure employs a thin second shield metal layer. In embodiments of this disclosure, the data signal line employs a three-layer structure of the second shield metal layer, gate metal layer, and source drain metal layer SD to reduce the RC of the data signal line and achieve the feasibility standard for the refresh frequency. The shield metal layer, gate metal layer, and source / drain metal layer may be made of copper to reduce impedance and make them suitable for large-size designs. In the display board according to the embodiment of this disclosure, the data signal line employs a three-layer wiring structure of source / drain metal layer SD / gate metal layer GT / second shield metal layer SHIELD, the first power line VDD employs a two-layer wiring structure of source / drain metal layer SD / gate metal layer GT, and the first scan signal line employs a two-layer wiring structure of the first shield layer and the second shield metal layer. This reduces the load on the data signal line, first power line, and first scan signal line, and provides technical support for medium- and large-size high-PPI display boards.

[0255] In exemplary embodiments, the capacitors in the display substrate may be transparent capacitors, that is, the first and second plates may have a transparent structure, thereby increasing the aperture ratio and PPI of the display substrate. In the display substrate manufactured by steps (11) to (18) and steps (21) to (210), the two plates of the capacitor in the subpixel are located in the first conductive layer and the semiconductor layer, and both the first plate 11 and the second plate 34 have a transparent structure, so the two plates of the capacitor do not occupy the aperture ratio. By connecting the second pole of the second transistor T2 and the second pole of the third transistor T3 via the transparent conductive layer 300, the wiring connecting the two transistors does not occupy the aperture ratio, does not obstruct the pixel aperture 302, increases the light-emitting area, and improves the aperture ratio and PPI of the display substrate.

[0256] In some other embodiments, the semiconductor layer pattern formed in step (24) is shown in Figure 24a, i.e., the second electrode plate 34 of the capacitor is not placed in the semiconductor layer. The planar structure after the formation of the fourth conductive layer pattern in step (25) is shown in Figure 24b, and the fourth conductive layer pattern in Figure 24b is shown in Figure 24c, where the second electrode plate 34 of the capacitor is placed in the fourth conductive layer, and there is an overlapping region between the orthographic projection of the base of the second electrode plate 34 and the orthographic projection of the base of the first electrode plate 11, and the second electrode plate 34 and the second gate electrode 42 may be integrally molded structures. The third insulating layer pattern formed in step (26) is shown in Figure 24d, and the difference between Figure 24d and Figure 19 is that the third insulating layer in the second via V2 and the tenth via V10 is etched to expose the surface of the second electrode plate 34. The structure after the formation of the fifth conductive layer in step (27) above is shown in Figure 24e, and a schematic diagram of the planar structure of the fifth conductive layer in Figure 24e is shown in Figure 24f. The difference between Figures 24e and 24f and Figures 20a and 20b is that the first relay connection electrode 46 and the third relay connection electrode 48 may be integrally molded structures, and the second electrode plate 34 and the second electrode of the third transistor T3 are electrically connected via the first relay connection electrode 46 and the third relay connection electrode 48, thereby realizing an electrical connection between the second electrode of the third transistor T3 and the second electrode plate 34. The second relay connection electrode 47 is electrically connected to the second electrode plate 34 via the tenth via V10, thereby realizing an electrical connection between the second electrode of the second transistor T2 and the second electrode plate 34. The structure of the first conductive layer pattern to the third conductive layer pattern is the same as in steps (21) to (23) above, and the fourth insulating layer and planar layer pattern, the sixth conductive layer pattern, and the pixel definition layer pattern are the same as in steps (28) to (210) above, and detailed explanation is omitted in the embodiments of this disclosure. In the embodiments of this disclosure, the two plates of the capacitor are transparent structures placed on the first conductive layer and the fourth conductive layer, and do not obstruct the pixel aperture 302, thereby increasing the aperture ratio and PPI of the display substrate.

[0257] In some other embodiments, the semiconductor layer pattern formed in the above step (24) is shown in FIG. 24a, that is, the second electrode plate 34 of the capacitor is not provided on the semiconductor layer. The plan view after forming the fourth conductive layer pattern in the above step (25) is shown in FIG. 25a, and the fourth conductive layer pattern in FIG. 25a may have the same structure as that shown in FIG. 18b. The schematic plan view of the structure after forming the fifth conductive layer pattern in the above step (27) is shown in FIG. 25b, and the schematic plan view of the fifth conductive layer pattern in FIG. 25b may be shown in FIG. 20b. The schematic plan view of the structure after forming the sixth conductive layer pattern in the above step (29) is shown in FIG. 25c, and the schematic plan view of the sixth conductive layer pattern in FIG. 25c may be shown in FIG. 22b. In the embodiments of the present disclosure, the difference from the above steps (21) to (210) is that the second electrode plate 34 of the capacitor in the semiconductor layer is removed, and the anode 301 is reused as the second electrode plate of the capacitor, that is, there are differences between the formed semiconductor layer and the above step (24), and the other structural film layers are the same as those in the above steps (21) to (23), steps (25) to (210). In the embodiments of the present disclosure, the transparent conductive layer 300 is reused as the second electrode plate of the capacitor, and by connecting the second pole of the second transistor T2 and the second pole of the third transistor T3 through the transparent conductive layer, the layout space can be saved, and the aperture ratio and PPI of the display substrate can be increased.

[0258] In the technical solution according to the embodiments of the present disclosure, since the first connection via V21 and the second connection via V20 are located on both sides of the pixel aperture 302, the problem of display non-uniformity caused by one pixel aperture being located on one side of the pixel aperture 302 can be avoided.

[0259] The structure according to the present disclosure and its manufacturing process are merely exemplary. In exemplary embodiments, the corresponding structure can be changed according to actual needs, or the patterning process can be increased or decreased. For example, the display area may include three sub-pixels. Also, for example, the pixel driving circuit may be 5T1C or 7T1C, etc., and the present disclosure does not limit it thereto.

[0260] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), etc., and the present disclosure is not limited thereto.

[0261] The present disclosure further provides a display device comprising the display substrate of the above embodiment. The display device may be a product or component having a display function, such as a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, a navigator, etc.

[0262] In the display substrate, the manufacturing method thereof, and the display device according to this embodiment, the second electrodes of the second transistor and the second electrodes of the third transistor located in the same sub-pixel on the display substrate are electrically connected through at least one transparent conductive layer. The transparent conductive layer does not block the aperture ratio, and can increase the aperture ratio and PPI of the display substrate.

[0263] The above are the embodiments disclosed in the present disclosure. However, the above content is for the purpose of facilitating the understanding of the present disclosure and is not for limiting the present disclosure. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure. The patent protection scope of the present disclosure shall be subject to the appended claims.

Claims

1. A display substrate comprising a base, and a plurality of subpixels and a plurality of transparent conductive layers set on the base, wherein each subpixel comprises at least one transparent conductive layer, at least some subpixels comprises at least a second transistor and a third transistor, and the second pole of the second transistor and the second pole of the third transistor located in the same subpixel are electrically connected via at least one transparent conductive layer.

2. At least a portion of the transparent conductive layer includes an anode, a first connecting electrode, and a second connecting electrode, and in the same transparent conductive layer, the anode is electrically connected to the first connecting electrode and the second connecting electrode. The display substrate according to claim 1, wherein in the same subpixel, the second pole of the second transistor is electrically connected to the corresponding anode via the first connecting electrode, the second pole of the third transistor is electrically connected to the corresponding anode via the second connecting electrode, and the second pole of the second transistor and the second pole of the third transistor are electrically connected via the corresponding first connecting electrode, second connecting electrode, and anode.

3. The display substrate according to claim 2, wherein the anode corresponding to the first connecting electrode and the second connecting electrode is integrally molded.

4. The display substrate according to claim 2, further comprising a pixel definition layer, the pixel definition layer being located on the side of the transparent conductive layer away from the base, a plurality of pixel apertures formed in the pixel definition layer, each subpixel comprising at least one pixel aperture, there being an overlapping region between the orthographic projection of the pixel aperture on the base and the orthographic projection of the corresponding anode on the base, and the transparent conductive layer being located in the light-emitting region of the corresponding subpixel.

5. The display substrate according to claim 4, wherein the second pole of the second transistor is electrically connected to the corresponding first connecting electrode via a first relay via, the orthographic projection of the first relay via on its base lies within the range of the orthographic projection of the first connecting electrode on its base, the second pole of the third transistor is electrically connected to the corresponding second connecting electrode via a second relay via, the orthographic projection of the second relay via on its base lies within the range of the orthographic projection of the second connecting electrode on its base, the minimum distance from the first relay via to the corresponding pixel aperture edge is smaller than the minimum distance from the second relay via to the corresponding pixel aperture edge, and the first and second relay vias are located on either side of the corresponding pixel aperture.

6. The display board according to claim 5, wherein the plurality of subpixels are arranged along row and column directions, and in the row direction, the distance between two adjacent subpixels and a first relay via includes a first distance and a second distance, the first distance being greater than the second distance, and the first distance and the second distance are arranged alternately along row directions.

7. The display board according to claim 6, wherein, in the row direction, the distance between two adjacent subpixels and a second relay via includes a third distance and a fourth distance, the third distance being greater than the fourth distance, and the third distance and the fourth distance are arranged alternately along the row direction.

8. The display substrate according to claim 6, wherein in the same subpixel, in the column direction, the second transistor and the third transistor are located on opposite sides of the corresponding anode, and the distance between the second transistor and the third transistor is greater than 0.5 times the size along the column direction of the subpixel.

9. The display substrate according to claim 2, further comprising a plurality of data signal lines and a plurality of auxiliary data lines, wherein each of the plurality of data signal lines is electrically connected to the plurality of auxiliary data lines, the data signal lines and the auxiliary data lines are located in different conductive layers, and in a direction perpendicular to the plane on which the display substrate is located, the conductive layers on which the data signal lines and the auxiliary data lines are located are located between the base and the transparent conductive layer, and the orthographic projection of each of the plurality of data signal lines on the base at least partially overlaps with the orthographic projection of each of the plurality of auxiliary data lines on the base.

10. The display board according to claim 9, comprising a gate metal layer installed on the base, wherein at least some of the auxiliary data lines are located in the gate metal layer.

11. The display substrate according to claim 10, further comprising a shield metal layer, wherein in a direction perpendicular to the plane on which the display substrate is located, the gate metal layer is located on the side away from the base of the shield metal layer, and the plurality of data signal lines are located in the shield metal layer.

12. The display substrate according to claim 11, wherein the shield metal layer is further provided with a plurality of first power lines, the gate metal layer is further provided with a plurality of first auxiliary power lines, each of the plurality of first power lines is electrically connected to the plurality of first auxiliary power lines, and the orthographic projection of each of the plurality of first power lines on the base at least partially overlaps with the orthographic projection of each of the plurality of first auxiliary power lines on the base.

13. The display substrate according to claim 12, wherein the plurality of subpixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three subpixels, the gate metal layer is further provided with a plurality of first power connection lines, each pixel unit includes two of the first auxiliary power lines, both ends of the first power connection lines located in the same pixel unit are each connected to two of the first auxiliary power lines, and in a plane parallel to the display substrate, the main portion of the first auxiliary power lines extends along a second direction, the main portion of the first power connection lines extends along a first direction, and the first and second directions intersect.

14. The display substrate according to claim 11, further comprising a semiconductor layer, wherein in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer is located away from the base of the shield metal layer, the semiconductor layer is provided with a plurality of compensation connection lines, the shield metal layer is further provided with a plurality of compensation signal lines, and in a plane parallel to the display substrate, the compensation connection lines have a stripe structure extending along a first direction, the compensation signal lines have a stripe structure extending along a second direction, the first direction and the second direction intersect, and the compensation connection lines are electrically connected to at least one compensation signal line.

15. The display substrate according to claim 9, further comprising a source-drain metal layer, wherein in a direction perpendicular to the plane on which the display substrate is located, the source-drain metal layer is located away from the base of the gate metal layer, and the plurality of data signal lines are located in the source-drain metal layer.

16. The display substrate according to claim 15, further comprising a second shield metal layer, the second shield metal layer being located between the base and the gate metal layer in a direction perpendicular to the plane on which the display substrate is located, the plurality of auxiliary data lines comprising a plurality of first auxiliary data lines and a plurality of second auxiliary data lines, the plurality of first auxiliary data lines being located in the second shield metal layer, the plurality of second auxiliary data lines being located in the gate metal layer, the presence of an overlapping region between the orthographic projection of the plurality of first auxiliary data lines and the plurality of second auxiliary data lines on the base and the orthographic projection of the corresponding plurality of data signal lines on the base, and the plurality of first auxiliary data lines and the plurality of second auxiliary data lines being electrically connected to the corresponding plurality of data signal lines.

17. The display substrate according to claim 16, wherein the source drain metal layer is further provided with a plurality of first power lines, the gate metal layer is further provided with a plurality of first power auxiliary lines, each of the plurality of first power lines is electrically connected to the plurality of first power auxiliary lines, and the orthographic projection of each of the plurality of first power lines on the base at least partially overlaps with the orthographic projection of each of the plurality of first power auxiliary lines on the base.

18. The display substrate according to claim 17, wherein the plurality of subpixels form a plurality of pixel units arranged in an array, each pixel unit includes at least three subpixels, the display substrate further includes a semiconductor layer, the semiconductor layer is located away from the base of the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the semiconductor layer is provided with a plurality of first power supply lines, two of the first power supply lines are included in the same pixel unit, both ends of the first power supply lines located in the same pixel unit are electrically connected to the two first power supply lines, the main portion of the first power supply lines extends along a second direction in a plane parallel to the display substrate, the main portion of the first power supply lines extends along a first direction, and the first and second directions intersect.

19. The display substrate according to claim 16, wherein the second shield metal layer is further provided with a plurality of compensation connection lines, the source drain metal layer is further provided with a plurality of compensation signal lines, and in a plane parallel to the display substrate, the compensation connection lines have a stripe structure extending along a first direction, the compensation signal lines have a stripe structure extending along a second direction, the first direction and the second direction intersect, and the compensation connection lines are electrically connected to at least one compensation signal line.

20. The display substrate according to claim 16, further comprising a first shield metal layer, wherein the first shield metal layer is located between the base and the second shield metal layer in a direction perpendicular to the plane on which the display substrate is located, the first shield metal layer is provided with a plurality of first scan signal lines, the second shield metal layer is provided with a plurality of first scan signal auxiliary lines each electrically connected to the plurality of first scan signal lines, and the orthographic projection of the plurality of first scan signal lines on the base at least partially overlaps with the orthographic projection of the plurality of first scan signal auxiliary lines on the base.

21. The display substrate according to claim 20, wherein the thickness of the first shield metal layer is greater than the thickness of the second shield metal layer.

22. The display substrate according to claim 2, further comprising a first conductive layer, the first conductive layer being located between the base and the transparent conductive layer, the subpixel further comprising a capacitor, the first conductive layer comprising a first plate of the capacitor, the first plate having a transparent structure, the anode being reused as a second plate of the capacitor, and in the same subpixel, there is a first overlapping region between the orthographic projection of the first plate on the base and the orthographic projection of the second plate on the base, the first overlapping region being located in the light-emitting region of the subpixel.

23. The subpixel further comprises a first conductive layer, the first conductive layer being located between the base and the transparent conductive layer, the subpixel further comprises a capacitor, the first conductive layer comprising a first electrode plate of the capacitor, the first electrode plate having a transparent structure, The display substrate according to claim 1, further comprising a gate metal layer, the transparent conductive layer located on the gate metal layer, the transparent conductive layer being reused as a second electrode plate of a capacitor, and a first overlapping region existing between the orthographic projection of the first electrode plate on the base and the orthographic projection of the second electrode plate on the base, the first overlapping region located in the light-emitting region of the subpixel.

24. A display device comprising a display board according to any one of claims 1 to 23.

25. A method for manufacturing a display substrate, comprising forming a plurality of subpixels and a plurality of transparent conductive layers on one side of a base, wherein at least some of the subpixels include at least a second transistor and a third transistor, and the second pole of the second transistor and the second pole of the third transistor located in the same subpixel are electrically connected via at least one transparent conductive layer.

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