Display panels and display devices
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2023-12-29
- Publication Date
- 2026-06-23
AI Technical Summary
【0173】 本開示はさらに、表示パネルを含む表示装置を提供する。該表示パネルは上記いずれかの実施形態の表示パネルであり、その具体的な構造と有益な効果は上記表示パネルの実施形態を基準されたいので、ここでは詳述しない。本開示の表示装置は、携帯電話、タブレット、テレビ、あるいはスマートウォッチ、スマートグラス、車載ディスプレイなどの表示機能を有する電子機器であり、ここでは列挙しない。
Smart Images
Figure 2026520251000001_ABST
Abstract
Claims
1. A display panel including a plurality of pixel circuits distributed in an array along the row and column directions, The pixel circuit includes a plurality of transistors, a first capacitor and a second capacitor, each of which includes a drive transistor, a write transistor, a light emission control transistor, a first reset transistor, a second reset transistor and a third reset transistor. The first pole of the light-emitting control transistor is used to receive a first power signal, the second pole of the light-emitting control transistor is connected to the second pole of the drive transistor, the first pole of the write transistor is used to receive a data signal, the second pole of the write transistor is connected to the gate of the drive transistor and the first plate of the first capacitor, the second plate of the first capacitor is connected to the first plate of the second capacitor, and the second plate of the second capacitor is connected to the first pole of the drive transistor. The first pole of the first reset transistor and the first pole of the second reset transistor are used to receive a reference signal, the second pole of the first reset transistor is connected to the gate of the drive transistor, the second pole of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor, the first pole of the third reset transistor is used to receive a reset signal, and the second pole of the third reset transistor is connected to the first pole of the drive transistor and the second plate of the second capacitor, The display panel includes a substrate, a semiconductor layer, and a plurality of light-emitting elements. The semiconductor layer is provided on one side of the substrate and includes the active portion of each transistor. The plurality of light-emitting elements are provided on the side of the semiconductor layer away from the substrate, and one of the light-emitting elements is connected to the first pole of the driving transistor of one of the pixel circuits. One of the first and second plates of the first capacitor is provided in the same layer as one of the first and second plates of the second capacitor, and one of the first and second capacitors overlaps with the active portion of the drive transistor. A display panel characterized by the following features.
2. The first plate of the first capacitance and the second plate of the second capacitance are provided in the same layer and distributed along the column direction, the second plate of the first capacitance and the first plate of the second capacitance are provided in the same layer and have an integrated structure, and the first plate and the second plate of the second capacitance overlap with the active part of the drive transistor. The display panel according to feature 1.
3. The pixel circuit further includes a data control transistor, the first pole of which is connected to the second pole of the writing transistor and the first plate of the first capacitor, and the second pole of which is connected to the gate of the driving transistor. The display panel according to feature 2.
4. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion distributed at intervals along the row direction, the second semiconductor portion being located between the first semiconductor portion and the third semiconductor portion, and the first semiconductor portion being connected to the second semiconductor portion. The active portions of the writing transistor, the data control transistor, and the first reset transistor are all located in the first semiconductor section and are sequentially connected along the column direction; the active portion of the second reset transistor is located in the second semiconductor section; and the active portions of the light emission control transistor, the drive transistor, and the third reset transistor are located in the third semiconductor section and are sequentially connected along the column direction. The display panel according to feature 3.
5. The third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction, and the active portion of the drive transistor is connected between the first semiconductor segment and the second semiconductor segment. The width in the row direction of the active portion of the drive transistor is greater than the width in the row direction of the first semiconductor segment and the second semiconductor segment. The display panel according to feature 4.
6. The width of the active portion of the drive transistor in the direction of the row is 6 μm or more and 20 μm or less. The display panel according to feature 5.
7. The third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction, and the active portion of the drive transistor is connected between the first semiconductor segment and the second semiconductor segment. The active portion of the drive transistor is curved along the direction of the row, facing and / or away from the first semiconductor portion. The display panel according to feature 4.
8. The length of the active portion of the drive transistor in the extending direction is 20 μm or more and 30 μm or less. The display panel according to feature 7.
9. The ratio of the width to the length of the aforementioned drive transistor is 20 / 6 or less and 4 / 30 or more. The display panel according to feature 1.
10. The first electrode plate and the second electrode plate of the first capacitance overlap the third semiconductor portion and the first semiconductor portion. The display panel according to feature 4.
11. The capacity value of the second capacity is greater than the capacity value of the first capacity. The display panel according to feature 1.
12. The display panel further includes a light emission control line, a first reset control line, a second reset control line, a scan line, a data control line, a first reset line, and a second reset line. The light emission control line extends along the direction of the row, overlaps with the active portion of the light emission control transistor, and is used to transmit the light emission control signal. The first reset control line extends along the row direction, overlaps with the active portion of the third reset transistor, and is used to transmit a reset control signal. The second reset control line is connected to the gates of the first reset transistor and the second reset transistor and is used to transmit a reference control signal. The scan line extends along the row direction, is connected to the gate of the writing transistor, and is used to transmit the scan signal. The data control line extends along the row direction, is connected to the gate of the data control transistor, and is used to transmit data control signals. The first reset wire extends along the row direction and is connected to the first pole of the first reset transistor and the first pole of the second reset transistor, and is used to transmit the reference signal. The second reset wire extends along the row direction and is connected to the first pole of the third reset transistor and is used to transmit the reset signal. The display panel according to feature 4.
13. The orthographic projections of the light emission control line, the scan line, the data control line, the second reset control line, the first reset control line, and the second reset line onto the substrate are distributed at intervals along the column direction, and the first reset line overlaps with the first reset control line. The orthographic projection of the active portion of the drive transistor onto the substrate is located between the orthographic projections of the data control line and the second reset control line onto the substrate. The active portion of the writing transistor and the orthographic projection of the first capacitance onto the substrate are at least partially located between the orthographic projections of the light emission control line and the data control line onto the substrate. The orthographic projection of the active portions of the first reset transistor and the second reset transistor onto the substrate is located between the orthographic projection of the data control line and the first reset control line onto the substrate. The display panel according to feature 12.
14. The display panel further includes a plurality of first auxiliary power lines, a plurality of first power lines, and a plurality of data lines. The plurality of first auxiliary power lines extend along the row direction and are distributed along the column direction, with the first auxiliary power lines provided between two adjacent rows of the pixel circuits, and the first auxiliary power lines are connected to the first pole of the light emission control transistor of one of the pixel circuits. The plurality of first power lines are provided on the side of the first auxiliary power line away from the substrate, each first power line extends along the column direction and is distributed at intervals along the row direction, one of the first power lines is connected to each of the first auxiliary power lines and overlaps with one row of the pixel circuit, The plurality of data lines are provided on the side of the first auxiliary power line away from the substrate, each data line extends along the column direction and is distributed at intervals along the row direction, one data line overlaps with one row of the pixel circuit and is connected to the first pole of the writing transistor and used to transmit the data signal. The display panel according to feature 13.
15. The display panel further includes a plurality of second power lines, a first auxiliary reset line and a second auxiliary reset line extending along the column direction and distributed along the row direction, the first auxiliary power lines being provided on the side of the first auxiliary power line away from the substrate, the second power lines being used to transmit a second power signal, the first auxiliary reset line being connected to the first reset line, and the second auxiliary reset line being connected to the second reset line. The first power line and the data line connected to the pixel circuit in the same row are defined as a line group, and between two adjacent line groups, one of the second power line, the first auxiliary reset line, and the second auxiliary reset line is provided. The light-emitting element has a first electrode and a second electrode, the first electrode being connected to the first pole of the drive transistor and the second pole being connected to the second power line. The display panel according to feature 14.
16. The light emission control line includes a first sub-light emission control line and a second sub-light emission control line provided along the direction away from the substrate, and both the first sub-light emission control line and the second sub-light emission control line extend along the row direction and are connected to each other. The first reset control line includes a first sub-reset control line and a second sub-reset control line provided along the direction away from the substrate, and both the first sub-reset control line and the second sub-reset control line extend along the row direction and are connected to each other. The display panel according to feature 15.
17. The display panel further includes a light-shielding layer, a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer. The light-shielding layer is provided on one side of the substrate and includes the second electrode plate of the first capacitance and the first electrode plate of the second capacitance. The first gate layer is provided on the side of the light-shielding layer away from the substrate and includes a first electrode plate for the first capacitance, a second electrode plate for the second capacitance, a first sub-light emission control line, and a first sub-reset control line, and the semiconductor layer is provided on the side of the first gate layer away from the substrate, The second gate layer is provided on the side of the semiconductor layer away from the substrate and includes the second sub-light emission control line and the second sub-reset control line. The first source-drain layer is provided on the side of the second gate layer away from the substrate and includes the first auxiliary power line, the scan line, the data control line, the second reset control line, the first reset line, and the second reset line. The second source-drain layer is provided on the side of the first source-drain layer away from the substrate and includes the data lines, the first power lines, the second power lines, the first auxiliary reset line, and the second auxiliary reset line. The display panel according to feature 16.
18. The first gate layer further includes a first gate portion, a second gate portion, and a fourth gate portion. The first gate portion overlaps with the active portion of the writing transistor to form the gate of the writing transistor. The second gate portion overlaps with the active portion of the data control transistor to form the gate of the data control transistor, and the first electrode plate of the second capacitor includes a third gate portion. The fourth gate portion overlaps with the active portions of the first and second reset transistors to form the gates of the first and second reset transistors. The display panel according to feature 17.
19. The second gate layer includes a fifth gate portion, a sixth gate portion, a seventh gate portion, and an eighth gate portion. The fifth gate portion overlaps with the active portion of the writing transistor and is connected to the first gate portion to form the gate of the writing transistor. The sixth gate portion overlaps with the active portion of the data control transistor and is connected to the second gate portion to form the gate of the data control transistor. The seventh gate portion overlaps with the active portion of the drive transistor and is connected to the third gate portion to form the gate of the drive transistor. The eighth gate portion overlaps with the active portions of the first and second reset transistors and is connected to the fourth gate portion, thereby forming the gates of the first and second reset transistors. The display panel according to feature 18.
20. The first source-drain layer includes a first connection, a second connection, a third connection, a fourth connection, and a fifth connection. The first connection point is located between the first auxiliary power line and the scan line, and is connected to the data line and the first pole of the writing transistor. The second connection portion is located between the scan line and the data control line and is connected to the region located between the first plate of the first capacitor and the active portion of the writing transistor and the active portion of the data control transistor among the first semiconductor portion. The third connection portion is located between the data control line and the second reset control line, and is connected to the region located between the active portion of the first reset transistor and the active portion of the data control transistor among the seventh gate portion and the first semiconductor portion. The fourth connection is located between the third connection and the second reset control line, and is connected to the first plate of the second capacitor and one end of the second semiconductor part that is close to the active part of the drive transistor, while the other end of the second semiconductor part that is away from the active part of the drive transistor is connected to the first semiconductor part. The fifth connection point is located between the first reset control line and the second reset control line and is connected to the region of the second plate of the second capacitor and the third semiconductor part located between the active part of the drive transistor and the active part of the third reset transistor. The display panel according to feature 19.
21. The material of the semiconductor layer includes a metal oxide. A display panel according to any one of claims 1 to 20.
22. Includes a display panel according to any one of claims 1 to 21 A display device characterized by the following features.