Microdisplay

Abstract

The microdisplay architecture (10) comprises an optical plane (20) having several pixel elements and a circuit plane (30) on which the optical plane (20) is arranged, the circuit plane (30) including one or more interfaces (32a, 32b), a pixel matrix control unit (34), and an image memory (36) for controlling (34) several light-emitting or light-modulating elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) in a dynamically selectable operating mode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to microdisplays and operating methods. Preferred embodiments relate to microdisplays having at least one memory-based operating mode. Further embodiments relate to microdisplays having a leakage circuit. According to embodiments, the operating method can be computer-implemented. In general, the present invention belongs to the field of scalable microdisplay architectures. [Background technology]

[0002] Microdisplays refer to displays with a typical display diagonal ranging from 0.1 inches to typically 1.5 inches, with some select displays reaching up to 2.5 inches. Such microdisplays are usually structured in a stacked manner, meaning the control circuitry is located directly beneath (hereinafter referred to as the backplane) the controlled elements (hereinafter collectively referred to as the frontplane). Depending on the application field and optical use of the microdisplay, these controlled elements may be a layered system for realizing organic LEDs, inorganic LEDs, or LC materials. Thus, they are called OLED microdisplays, microLED microdisplays (uLED or μLED are also common), or LCOS (liquid crystal on silicon) microdisplays.

[0003] Here, the control circuit adapts to the specific characteristics of the controlled element. Examples include precise electrical control in a typical voltage range of 3V or higher, good current injection into layers and aging compensation in OLED microdisplays, and 1A / cm for uLED microdisplays. 2 Examples include a current density exceeding a certain level, or the complete absence of static current flowing into the elements controlled for the LCOS microdisplay.

[0004] To realize an active-matrix display, the backplane includes circuit components such as transistors, capacitors, or resistors. The same can be implemented using different technologies. For example, these are thin-film transistors (TFTs such as IGZO, a-Si, and LTPS) or implementations in single-crystal silicon. The following discussion will focus on single-crystal silicon using CMOS circuit technology, but will not be limited to this (others are also possible). With the continued miniaturization of TFTs, partial implementation on TFTs is also becoming a possibility.

[0005] According to conventional technology, microdisplays based on silicon backplanes are primarily realized at technology nodes ranging from 0.25 μm to 90 nm.

[0006] Microdisplays may be distinguished between different control variants, and depending on the control variant, the architecture, namely the system architecture and the pixel architecture, is usually different. The majority of microdisplays are driven by a video stream with a constant refresh rate, i.e., a video data stream having, for example, 30Hz, 60Hz, 90Hz, 120Hz, or 240Hz. Hereafter, this type of architecture will be referred to as a “refresh rate-based architecture”. There are only a few control schemes that deviate from this, one example being [1], which presents an architecture for partially updating pixels (hereafter, this will always represent the smallest element that can be controlled independently of other elements). Hereafter, this type of architecture will be referred to as a “memory-based architecture”.

[0007] Because the space requirements of each architecture, particularly microdisplays, mean that not all system or pixel architectures can be generated on all technology platforms, the selected architecture is considered in combination with the technology platform.

[0008] All of these architectures share the common feature of including, separately from the control circuits of the optical elements, additional circuit blocks, such as row and column decoders, possibly DAC functions for "converting" digital pixel data into pixel current and voltage values, and blocks for implementing a display data interface (parallel interface, LVDS, SPI, etc.) based on the control principles described above.

[0009] This dependency arises from the required data bandwidth. For example, a "refresh rate-based architecture" requires a much higher data rate because all display pixels are constantly being overwritten, even when it's unnecessary because, for instance, the pixel values ​​haven't changed at all. For this purpose, a parallel interface (i.e., a parallel digital single-ended line that transmits the data values ​​of a pixel or several pixels along with additional control lines, also known as digital RGB) or serial transmission (e.g., LVDS, low-voltage differential signaling) is typically used. Such systems include very expensive external video control electronics that embody the conversion to the described interfaces. This is usually done by a separate integrated circuit or FPGA. This increases the required power consumption and installation space (and thus makes the system ergonomically unfavorable), both of which are very important in many wearable applications.

[0010] However, in the case of a “memory-based architecture,” only the transmission of changing pixels is sufficient. Depending on the application, this significantly reduces the required transmission bandwidth, so less complex interfaces such as SPI can be considered. An example of this can be found in [1]. In all of these cases, an adapted control circuit is required.

[0011] Conventional microdisplays achieve pixel sizes ranging from 4.3 μm × 4.3 μm to 6.3 μm × 2.1 μm to 9.3 μm × 3.1 μm. [Overview of the project] [Problems that the invention aims to solve]

[0012] The objective of the present invention is to provide a microdisplay architecture that improves the trade-offs between control flexibility, display power flexibility, flexibility in combining different display technologies, energy efficiency, and cost efficiency. [Means for solving the problem]

[0013] This objective is resolved by the subject matter of the independent claim.

[0014] Embodiments of the present invention provide a microdisplay architecture having an optical plane and a circuit plane. The optical plane, oriented upward in the discussion, includes, for example, several light-emitting elements or optical modulation elements arranged in an nxm pixel matrix. The underlying circuit plane consists of several circuit components, at least a group of circuit circuits for controlling individual optical elements (also called a pixel circuit), a programming circuit for the group of circuit circuits assigned to the individual optical elements (also called a pixel matrix control unit), an integrated image memory, and one or more interfaces such as wired and wireless interfaces.

[0015] According to one embodiment, the pixel control unit includes one switch and one driver for each pixel.

[0016] In further embodiments, by using smaller technology nodes (e.g., less than 90nm), it is possible to directly integrate more functions into the backplane (circuit plane). This can replace the layered standard display interface connections that were previously made externally, and when such integration is possible, it results in a significant simplification of the system architecture, as the interface can therefore be directly integrated into the backplane.

[0017] In further embodiments, by using small technology nodes (e.g., less than 90 nm) and specific pixel circuits, it is possible to realize very small pixels, such as 3.5 μm × 3.5 μm, 3 μm × 3 μm, 2.5 μm × 2.5 μm, 2 μm × 2 μm or less. Here, the configuration of individual pixels does not necessarily have to be square. For example, it may be advantageous to implement them as rectangles (so that three pixels are combined into one group, or if they are composed of red, green, or blue pixels, they will all be square in any case) or as hexagons.

[0018] In a further embodiment, the pixel matrix control unit may be configured to control several light-emitting / modulating elements in either a refresh-rate-based or memory-based operating mode. Preferably, the operating mode may be switched (for example, depending on the application or current field of use).

[0019] Embodiments of the present invention are based on the finding that by using highly scaled technology (e.g., less than 90 nm), the circuits of external components can be directly integrated into the backplane, eliminating the need for additional driver circuits. By integrating the frame buffer into the backplane, the microdisplay can be operated as a “memory-based architecture” or a “refresh-rate-based architecture” as needed. The definitions of memory-based architecture and refresh-rate-based architecture are given above in the context of the prior art and apply similarly here. Thus, the aspects of the technology platform, system architecture, and pixel architecture are closely related and provide the following advantages, or the basis for obtaining the following advantages.

[0020] • Significant simplification of system architecture complexity · Substantially reducing packaging complexity by using integration options for external components (e.g., frame buffer, CPU / GPU, wireless interface, etc.) · Cost efficiency by 300mm wafer processes that are standard for <90nm technology (more chips / wafers), such as 65nm, 45nm, 32nm, 28nm, 22nm, 12nm, and below · Realizing extremely high refresh rates with an image memory highly parallel-connected to the pixel matrix · Flexible architecture for controlling different front plane technologies OLED / uLED (common cathode, common anode) and LCOS · Flexible adaptation of current consumption to the application by turning off the module or adapting the control

[0021] According to an embodiment, the backplane (circuit plane) defined above can be combined with different front plane architectures (OLED, uLED, LCOS) and can play a role in controlling them. Thereby, a flexible architecture for controlling different front plane technologies OLED / μLED (common cathode, common anode) and LCOS is provided.

[0022] According to an embodiment, the circuit plane or the backplane can directly include one or more interface circuits or switching circuits, a pixel matrix control unit, and an image memory. This means that one or more interface circuits or switching circuits, a pixel matrix control unit, and an image memory are integrated into the circuit plane. Thus, the integrated switching circuit is arranged within the circuit plane, that is, the integrated switching circuit is provided in the form of a backplane having the described functional blocks. According to a further embodiment, additional, i.e., one or several additional functional blocks, may exist as additional components of the integrated switching circuit. For example, each functional block shown in FIG. 6 is basically suitable for it. In this way, a further embodiment provides a circuit plane or a backplane, which has a circuit or an integrated switching circuit including a functional block interface, a pixel control unit, and an image memory, as well as one or more further functional blocks of the example of FIG. 6.

[0023] According to an embodiment, using a highly scaled technology, small pixel cells are realized. The main driving force for this requirement is to continuously achieve a high resolution. Further, due to the flexible configuration of the overall architecture, the backplane may be used for the most diverse plane architectures.

[0024] According to an embodiment, the microdisplay architecture includes not only one, but also several interfaces, for example, several interfaces of different types (wired and wireless) and / or several interfaces of different bandwidths.

[0025] Suitable wired interfaces include HDMI®, DisplayPort, MIPI, Thunderbolt, and USB. Furthermore, wireless interfaces such as Bluetooth, WLAN, openThread, LoRaWAN, AirTag, and RFID can be directly integrated into the backplane. According to the embodiment, a third option exists: transferring information instead of video data, depending on the complexity of the circuitry on the display. The display of information is performed directly on the display, for example, on suitable hardware (e.g., integrated GPU / CPU), and, according to the embodiment, possibly only within the required display area currently used for display (foveated rendering). Common to all examples is a significant simplification of further system electronics, thereby reducing current consumption, and potentially both the transmitted bandwidth and form factor, and thus the cost of the system.

[0026] Furthermore, according to the embodiment, integrating several interfaces directly into the backplane allows for adaptation to the most diverse systems, enabling the same integrated backplane switching circuit to serve several system applications. This offers significant cost advantages in the semiconductor industry, where pricing is heavily dependent on quantity. Moreover, according to the embodiment, implementing several interfaces provides the option to flexibly adapt the interfaces to the current operating mode.

[0027] According to the embodiment, the selection of the transmission interface or the respective transfer mode depends on the selection of the operating mode. In the memory-based operating mode, for example, a low-bandwidth interface such as a Bluetooth interface may be used, while in the refresh rate-based operating mode, a higher-bandwidth interface such as a MIPI interface is used.

[0028] According to the embodiment, it is not only pixel data that can be transmitted through the microdisplay chip interface. Rather, the abstract transmission of the displayed information can occur when it is generated directly by integrating the appropriate CPU / GPU with the backplane pixel data. By transmitting information instead of individual pixel data, the required bandwidth of the interface can be significantly reduced, bringing advantages to the system (reduced current consumption, reduced complexity of external circuit components, and therefore reduced system cost). The CPU / GPU can be turned off, for example, when a memory-based operating mode is activated, or put into sleep mode, for example. In this way, flexible adaptation of current consumption to the application is possible by turning off the module or by adapting to the control.

[0029] According to the embodiment, this conversion of information to display data can be performed directly within the display backplane, either for all pixels or for only some of the pixels currently contributing to the actual display (so-called foveated rendering). Generating only the display data actually used within the backplane allows for flexible adaptation of current consumption to the application.

[0030] According to the embodiment, regions of the microdisplay architecture, i.e., several light-emitting / modulating elements assigned to a first group and several light-emitting / modulating elements assigned to further groups, can operate in different ways (different sequences and / or amplitudes) or in different operating modes (simultaneous control of different regions in video / memory modes). This means that the operation of a first display portion or display area by the display area operates in a refresh rate-based operating mode, and the further display portion operates in a memory-based operating mode. It is also possible that only a portion of the display is operating at the present time. All of these means are advantageous in improving energy efficiency, as the overall current consumption is reduced by turning off components or display areas, or by operating the display areas in a more energy-efficient operating mode. The major difference between the different operating modes is the refresh rate, which can be modified depending on the embodiment. For example, a memory-based operating mode can use a 1Hz refresh rate (or even lower refresh rates), or, for equivalent display content, data updates can be completely omitted, meaning a 0Hz image frequency can be used (resulting in no activity on the external interface and significant energy savings), while higher refresh rates, such as 30Hz, 60Hz, 90Hz, or even >120Hz, are used in refresh rate-based operating modes. Generally, the refresh rate can be changed, i.e., within the range of 30, >60, >90, or >120Hz. Adapting the image frequency to the application allows for flexible adaptation of current consumption, as higher image frequencies result in higher current consumption.

[0031] By using memory, local frame rate adaptation (from memory input to output) and augmentation processing (insertion of intermediate images) can be performed.

[0032] Here, it should be noted the difference between the image frequency, which indicates the provision of new data on the input side of the image memory, and the image refresh rate on the output side of the image memory, which represents the rate at which the data from the image memory is transferred to the pixels. According to the embodiment, in the pixel control unit and the frame buffer, a first refresh rate can be applied to the input side a, and a second refresh rate can be applied to the output side, the second refresh rate being at least equal to or greater than the first.

[0033] According to the embodiment, data transfer from the integrated image memory is performed with very high bandwidth. The same is possible by integrating the memory directly into the backplane, especially when using small technology nodes (<90nm). This allows for significantly higher refresh rates, for example, 240Hz, 480Hz, 1kHz, 5kHz, 10kHz, 20kHz, 50kHz, 100kHz or higher. By adapting the refresh rate to the application, it is also possible to flexibly adapt the current consumption, as higher refresh rates result in higher current consumption.

[0034] According to the embodiment, data transfer from image memory to pixels is performed by a freely programmable cyclic transfer mimic (also called a sequence), which enables augmented processing such as the insertion of a generically generated data frame (without using data from image memory such as a black image) and delay elements for time weighting of the currently displayed data, in addition to the transfer of the data itself.

[0035] According to the embodiment, individual pixel subgroups may be controlled by different sequences (and / or different amplitudes). Different sequences and / or different amplitudes constitute different operating modes. This allows individual groups of optical elements to be controlled differently (including, but not limited to, individual insertions of generically generated data frames and delay elements), thereby realizing the tuning of the optical properties of these pixel subgroups (for example, tuning red, green, and blue subpixels for white point adjustment).

[0036] In further embodiments, the bit depth can be variable, for example, representing the brightness / gradation of each light-emitting element / modulator, or the color of each light-emitting element having subpixels. In some applications, a high bit depth is desirable because high color / gradation resolution is required, while in other applications, individual bit levels can be deactivated. This reduces computational effort and therefore improves energy efficiency.

[0037] In the above-mentioned CMOS technology nodes below 90nm, there is an increase in leakage current, which can be compensated for by a leakage circuit in the circuit plane and therefore does not affect the optical plane. Accordingly, according to a further embodiment of the circuit plane of the microdisplay architecture, the microdisplay architecture includes a leakage circuit. According to the embodiment, the leakage circuit may include two additional transistors.

[0038] It should be noted that, according to the embodiments, image memory can be implemented entirely within a pixel, partially within a pixel, or outside the display pixel but within the same integrated switching circuit. In the minimum configuration, one bit of memory per pixel is integrated into the pixel control circuit. Naturally, several one-bit memories, i.e., memories with higher memory depth, are provided per pixel. Higher memory depth can also be obtained by placing additional bits outside the display pixel but within the same integrated switching circuit (memory partially integrated into the pixel). According to the embodiments, image memory can be switched off partially, completely, or in stages. In particular, in the above modifications by embodiments having different bit depths depending on the operating mode or application, in stages, the entire memory space per cell is no longer needed, so stepwise switching off is useful. According to the embodiments, memory can also be bypassed, for example, in a refresh rate-based operating mode.

[0039] From a geometric standpoint, according to the embodiment, pixels extend to both the circuit plane and the optical plane. In the circuit plane, each pixel comprises, for example, one driver (per pixel) and one or more memory cells (per pixel). In the optical plane, one optical element, such as an OLED, is provided for each pixel.

[0040] Two different embodiments of the optical plane are described below. One variation is a so-called common anode circuit, while the other variation can be embodied by a common cathode circuit.

[0041] According to the embodiment, several light-emitting elements are implemented as a common cathode circuit. Here, the pixel control unit for each light-emitting element may be configured as follows: the pixel control unit includes a transfer gate and a driver (in the simplest case, an inverter), in which case the driver controls a reference voltage V ref The common electrode and LED are switched, and the pixel matrix control unit, for example, the reference voltage V refBy reducing the pixel voltage V pix1 By increasing Vpix, the brightness is increased, and the difference Vpix-Vref is generally changed to alter the brightness of the light-emitting / modulating element. Alternatively, it is configured to control different light-emitting or pixel subelements with different pixel voltages.

[0042] According to one embodiment, several light-emitting elements of the microdisplay architecture are configured as a common anode circuit. Here, the pixel matrix control unit may be configured to control the common anode as a counter electrode having the same backplane. With respect to brightness adjustment, for example, the pixel matrix control unit controls a reference voltage V ref By increasing the pixel voltage V pix It is configured to increase brightness by decreasing [a certain value].

[0043] According to the embodiment, individual pixel subgroups can be controlled with different pixel voltages / currents. This allows individual groups of optical elements to be controlled with different voltages, thereby enabling the tuning of the optical properties of these pixel subgroups (for example, tuning red, green, and blue subpixels for white point adjustment).

[0044] Further embodiments of a further model provide a microdisplay architecture having an optical plane and a circuit plane. The optical plane includes several light-emitting / modulating elements. Furthermore, the circuit plane includes a leakage compensation circuit. According to the embodiment, the leakage circuit may include two additional transistors. According to the embodiment, the microdisplay architecture includes a sub-90nm technology platform.

[0045] The implementation variations described in the context of the primary embodiment can, of course, also be used in this further embodiment.

[0046] Further embodiments provide a method for operating a microdisplay architecture. This method provides A step of operating the pixel matrix control unit in a memory-based operating mode using image memory, or The steps of operating the pixel matrix control unit in a memory-based operating mode using image memory, or operating the pixel matrix control unit in a refresh rate-based operating mode. Includes.

[0047] According to one embodiment, the method can also be implemented in a computer as software on a playback device that instructs the display architecture to activate each operating mode.

[0048] Hereinafter, embodiments of the present invention will be described based on the drawings. [Brief explanation of the drawing]

[0049] [Figure 1] This is a schematic cross-sectional view of a microdisplay structure according to a basic embodiment. [Figure 2] This is a schematic diagram of a simple pixel basic circuit to illustrate an embodiment. [Figure 3a] This is a schematic diagram illustrating a simple pixel basic circuit (a modified example having a common cathode front plane) according to the embodiment, from a circuit engineering perspective. [Figure 3b] This is a schematic diagram illustrating a simple pixel basic circuit (a modified example having a common anode front plane) according to a further embodiment, from a circuit engineering perspective. [Figure 4] This is a schematic diagram illustrating, from a circuit engineering perspective, a simple pixel basic circuit with leakage current compensation, according to further embodiments / appearances. [Figure 5] This is a schematic diagram of a complex example of a pixel cell having a (partial) implementation of a frame buffer within the pixel cell, according to an embodiment. [Figure 6] This is a schematic block diagram of a flexible microdisplay architecture according to an embodiment. [Modes for carrying out the invention]

[0050] Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements and structures are given the same reference numerals, and therefore their descriptions are mutually applicable or interchangeable.

[0051] Figure 1 shows a schematic diagram of a microdisplay architecture 10, which includes an optical plane (front plane) 20 and a circuit plane (back plane) 30. The optical plane 20 is located on the circuit plane 30. The optical plane 20 includes a plurality of optical elements, which may be arranged adjacent to each other or preferably within an nxm pixel matrix, i.e., planarly.

[0052] The circuit plane 30 includes a pixel matrix control unit 34 and memory such as a frame memory 36. The pixel control unit may be provided for each pixel (see 34a-f), so as to form a direct coupling / geometric relationship with the light-emitting elements 22a, 22b, 22c, 22d, 22f. For example, one driver may be provided for each element 34a-34f. The memory 36 may also contain one or more memory cells per pixel. The memory is configured as a minimum of 1-bit memory (1 bit per pixel), but may also contain several memory cells per pixel (e.g., 8 bits). Primarily, the memory is implemented as internal memory. This may be configured in part as external memory, i.e., several memory cells per pixel are located externally. Internal memory cells are located, for example, in the pixel area itself. External memory cells are located, for example, in the edge area of ​​the same integrated switching circuit.

[0053] Furthermore, the backplane 30 is equipped with one or more interfaces, such as communication interfaces designated with reference numbers 32a and 32b, respectively. Interface 32b represents an optional interface.

[0054] The control unit 34 can directly control some light-emitting elements 22a-22f by refresh rate-based operation, or control some light-emitting elements by memory 36 in memory-based operation mode. The processors for memory-based and transfer rate-based operation modes may be separate; that is, separate processors are provided for each mode, so that each processor is deactivated or put into standby mode when the respective mode is not activated. This allows for power savings. Information displayed by some pixels 22a-22f is acquired via one or more interfaces 32a and 32b, for example, in a directly displayed data format (image stream) or a "compressed" data format. Interfaces 32a and 32b typically have different bandwidths, so that different data rates are transferred. For example, the refresh rate-based mode requires a higher data rate than the memory-based mode because the memory-based mode only needs to transfer changes in the image. According to one embodiment, only one piece of information can be transferred, which is then converted into an image by the GPU. The control unit 34 is extended by a GPU / CPU, which functions as an alternative interface and can, for example, graphically display information provided externally by the device 10. The control of the individual light-emitting elements 22 is performed, for example, as shown in Figure 2.

[0055] To illustrate this advantage, a microdisplay 10 having MIPI interface 32a and Bluetooth interface 32b is described in the context of smart glasses applications in a maintenance scenario. This scenario begins with assigning objects (including work assignments and work locations) to maintenance personnel. The smart glasses then guide the maintenance personnel to their work locations. Therefore, the display has the task of supplying the smart glasses with directions. In this operating mode, the information on the display changes only within a very limited range (e.g., directional arrows and time are shown) and only at a very moderate frequency (a display update of 1 Hz is sufficient). Therefore, data can be easily supplied directly from the maintenance personnel's mobile phone via Bluetooth, or by GPS / Galileo / GLONASS / Beidou (or similar satellite navigation system) modules, as well as by the associated data processing and display units (CPU / GPU) integrated into the microdisplay architecture. Finally, the maintenance personnel arrive at their critical work locations. Since the maintenance personnel are responsible for various systems, they require specialized technical support from a central support center. For this video call and support during maintenance, the complete video needs to be displayed on the microdisplay within the smart glasses, meaning all image points on the display need to be written. Furthermore, for satisfactory interaction, it needs to be displayed at a high refresh rate of at least 60Hz, 90Hz, 120Hz, or 240Hz or higher. The data for this is provided, exemplarily, from an external mobile processor via the MIPI interface 32a. After advice from the support agent, the task can be completed, the call can be ended, and the complete video call data processing pipeline, including the mobile processor, can return to sleep mode / standby, allowing navigation to the next work location to proceed.

[0056] This scenario illustrates the advantages of the different operating modes of the present invention when it is possible to flexibly switch between a “memory-based architecture” (e.g., in the navigation case, when there is little or no image change at low refresh rates or when there is no change on the display, data transfer is idle) and a “refresh rate-based architecture” (in the support case, when displaying video or latency-critical interactions). In portable systems, the advantages of each are realized in current consumption, as this allows the system to be used for longer periods between two charging cycles and allows for the integration of smaller energy storage into the system, thereby reducing the size and / or weight of the system, and also improving the system's ergonomics. This presents a critical system requirement for portable systems.

[0057] Data from the standard interface 33a / b (wired or wireless) is stored in the image memory 36 (frame buffer) after reception. Until now, it has been impossible to implement a complete image memory with a memory depth of 8 bits or more per pixel. This is because memory in technologies exceeding 90nm, commonly used in microdisplays, either occupies an excessively large area on the chip or significantly increases the chip size, thus reducing the chip size on the wafer and, in this case as well, excessively increasing the cost per individual backplane chip. This change is particularly pronounced at smaller process nodes <90nm, because memory density (i.e., achievable memory cells per area) increases significantly at smaller process nodes.

[0058] For example, the frame buffer (also called image memory) acts as a definitive intermediate block between the flexible external circuit architecture of the standard interface 32a / b and the internal control unit of the pixel. Here, the image memory can be implemented outside the pixel, partially inside the pixel, or entirely inside the pixel.

[0059] When fully implemented within a pixel, the driver circuitry must also be integrated separately from the memory, which typically results in larger pixels (for example, as dynamic memory DRAM, static memory SRAM, or non-volatile NVRAM). However, variations of the present invention's architecture require less circuitry outside the matrix. Periodic data transfer to the pixels is also eliminated.

[0060] In contrast, there is a second variation of the pixel where the complexity of the pixel circuit is minimized, thus enabling very small pixels (i.e., the maximum pixel density is possible, and therefore higher resolution on a given microdisplay area). Such a minimized pixel circuit contains only one switch that isolates the actual driver from the column line (see Figure 2). For certain applications, the driver may be a simple storage element (e.g., capacitance).

[0061] Figure 2 shows a light-emitting element with associated pixel control units, which here include, for example, a common electrode (common cathode / anode electrode of the optical element). The light-emitting element or optical modulation element 22 is controlled via a driver 34d, which is programmed and controlled again via a row selection switch by column data. The switch is labeled reference number 34sw. For row selection, the switch 34sw receives the respective signal.

[0062] From a circuit engineering perspective, the implementation configurations of these basic elements are shown in Figure 3a. In this example, the switch 34sw is embodied by a transfer gate, and the driver is embodied by an inverter 34t. The common electrode V is used as the load in the front panel elements. ref Assume that a light-emitting diode 22' (corresponding to 22 with a common cathode circuit) is connected to it. In this diagram, since all pixels' (O)LED22' have a common cathode as the opposing electrode, the common electrode is a common cathode.

[0063] In this example, global brightness can be adjusted in two different ways: by reducing Vref or by increasing the Vpix1 voltage. To realize this, both voltages can be configured and controlled separately. For precise control of the pixel cells, when Vpix1 is adapted, the column voltage levels on the vertical data lines (corresponding to the implementation of voltage converters / level shifters in the column heads of the pixel matrix) are also adjusted. In configurations with statically fixed pixel voltages, this can be omitted, and as a result, global brightness can be adjusted, for example, by adapting a sequence, for example, by inserting a black image, or by controlling a common electrode. Note here that, according to the embodiment, when using an integrated pixel matrix control unit in the CPU / GPU or circuit plane, these black images can also be generated locally and not transmitted externally.

[0064] In further embodiments, pixels provided with different front-plane elements can be configured as Vpix1,1, Vpix1,2, Vpix1,3, etc., which can be adjusted separately. This is particularly useful when different electrical control parameters are required for different front-plane elements. One example is a configuration of red, green, and blue front-panel elements having different electrical parameters, which can be appropriately controlled by separate configurations. Furthermore, the brightness of individual pixels, and thus, for example, the white point of a microdisplay, can be adjusted through these different adjustment options. The same advantages can be obtained for separate configurations of Vrefs in the form of Vref1,1, Vref1,2, Vref1,3, etc.

[0065] Furthermore, different embodiments of the pixel group of the present invention can realize individual control, in which case the pixel group is also assigned to different individually adjustable sequences. This embodiment also makes it possible to adjust different groups of front-plane elements (e.g., different current efficiencies) independently of each other (e.g., as described above for white point adjustment of R, G, and B).

[0066] However, according to the embodiment, a “common anode” design, i.e., a front plane having a common anode as the counter electrode, can be controlled by the same back plane. This is shown in Figure 3b based on the circuit of 22'' (where 22'' corresponds to 22 having a common anode circuit). In such an arrangement, the voltage of the common counter electrode is in the positive range (see Figure 3b), i.e., brightness control is V ref This can be embodied by increasing or decreasing Vpix2. It is clear that the digital data of the "common anode" design should be inverted compared to the data of the "common cathode" design. According to the embodiment, this can be done in the column head or before storing in the frame buffer. Furthermore, as described above, implementing different voltages for separate pixel groups can be embodied in a form adapted to the "common anode" design. The same applies to sequences of pixel groups with different configurations as described above.

[0067] In both cases, this simplified pixel cell embodies only two states, referred to below as "on" and "off". To implement gradation, a time impulse sequence of "on" and "off" states must be written to the pixel cell. This time sequence is embodied by a programmable sequencer, which controls both the correct reading of data from the frame buffer and the correct selection of the display row to which the data belongs. The more gradations that must be resolved, the more transfers are required, and the larger the frame buffer is needed. According to the embodiment, this is configured to meet the maximum requirements. In application cases with lower bit depths (e.g., the display of navigation instructions does not require a resolution of 8 bits or more per color channel), the flexible architecture of the present invention includes the option to gradually switch off unnecessary memory cells in the frame buffer (e.g., from 16 bits to 8 bits, 8 bits to 4 bits, or 13 bits to 7 bits per pixel, etc.). This reduces the need to embody "on" and "off" states, resulting in an adapted sequence for transmitting data from the frame buffer to the pixels. Both approaches result in significant savings in current consumption, highlighting the flexibility of the new architecture of the present invention. Even while maintaining the same transmission frequency, a shorter transmission sequence length from the frame buffer to the pixels allows for higher refresh rates by reducing the bit depth.

[0068] The above explanation assumes light-emitting elements such as OLEDs and uLEDs. Alternatively, optical modulation elements such as LCOS may be used.

[0069] Therefore, the above embodiments in Figures 3a and 3b may be summarized as providing one switch 34sw for each pixel or group of pixels to be controlled, the switch 34sw being implemented, for example, by a transfer gate in a driver 34d, and the transfer gate being implemented, for example, by an inverter. A light-emitting diode (e.g., OLED or LED) is coupled to the output of the inverter and thus has an anode or common cathode. In the case of an LCOS (optical modulation element), periodic polarity reversal occurs.

[0070] According to the features of this technology, further transistors are useful in this simplified pixel cell. As with these embodiments, further embodiments of the pixel cell are shown herein, particularly with reference to technologies of smaller structural size (required for implementation of the invention such as flexible interface assemblies and frame buffers). Smaller technology nodes are characterized by so-called leakage currents (e.g., drain-source leakage current, gate leakage current, or bulk leakage current). These parasitic currents are essentially increased by more advanced technology nodes and, according to the prior art, result in an undesirable current flow through the optical elements within the pixel cell, and therefore, in some cases, a decrease in the contrast ratio (because the optical elements cannot be completely turned off). Furthermore, conventional exemplary pixel cells assume that the inner nodes of the pixel cell maintain the stored digital values ​​after programming. However, due to the leakage currents described above, this is probably only true for a limited amount of time and is also highly dependent on circuit conditions (e.g., pixel voltage and temperature). Therefore, Figure 4 shows a pixel circuit extended with two transistors 29 to compensate for these leakage currents. The two transistors 29 form a leakage current compensation circuit.

[0071] The two transistors of the leakage compensation circuit 29 have a common control electrode coupled to the output of the inverter. The transistors, recoupled to the input node of the driver, provide compensation for leakage current. The optical element 22 is controlled by the inverter 34t.

[0072] Furthermore, leakage current (e.g., from the driver) is distributed through the circuit and does not flow out through the front plane. For example, this circuit guarantees two crucial characteristics of the new architecture for compensating for leakage current.

[0073] - Good contrast ratio even with increased leakage current: Leakage current induced through the front plane elements can cause damage to the control unit, especially in the desired "off" state of the pixel cell, thus resulting in "residual illumination" of the pixels even in the "off" state, and thus a decrease in the contrast ratio, a critical parameter of the microdisplay. In this way, this is prevented.

[0074] -Continuous reception of the pixel cell state: Two additional transistors 29 ensure that the programmed state is received even over longer periods.

[0075] Referring to Figure 9, the control of the optical element 22 by the driver 34t and read amplifier 24, which are implemented in the pixel control section of the memory elements (36a-36d) implemented within the pixel, will be described. Switch 34sw is connected to eight memory cells 36a, 36b, 36c, and 36d, exemplary for each pixel. The eight memory cells 36a-36d enable the implementation of an 8-bit memory. Naturally, these memory cells can be increased by further in-pixel and external memory (integrated in the same circuit). Here, the memory cells are (partially) directly implemented within the pixel cell. A read amplifier 24 (for DRAM embedded in the pixel) may be provided between the memory cells 36a-36d and the driver 34t.

[0076] Referring to Figure 6, the front plane of the display architecture (see reference no. 20) and the circuit plane of the display architecture (see reference no. 30), in particular the functional blocks assigned to the control unit 34, will be described in detail. Figure 6 shows a block diagram of a flexible microdisplay architecture. This mainly includes a pixel area 22p that is controlled in a matrix manner via row drivers 23l and column drivers 23r. Furthermore, Figure 6 shows additional functional blocks for controlling the pixel area 22p. For each pixel in the circuit plane, the pixel area 22p includes elements such as drivers 34t and switches 34sw, in addition to the light-emitting elements 22 in the optical plane.

[0077] According to one embodiment, the circuit plane includes a column driver 23r and / or a load driver 23l, which are controlled in the data flow control unit via a sequencer 34sq, in this case as well. The data flow control unit / sequencer 34sq represents an interface with the control unit 34 or memory 36.

[0078] The control unit 34 may further include functional blocks, which can be implemented in either software or hardware as separate components or separate circuit groups, namely, configuration units 34k, a processor (CPU) or graphics processor (GPU) 34p, white compensation 34w, an external synchronization unit 34s, a series of pads for a wired interface 32a, an energy manager 34pwr, a temperature sensor 34temp, a test pattern generator 34tg, a test unit 34test, and an internal clock generator 34cl. Since these units can exist separately, they should be considered optional units.

[0079] The following describes the operating modes of the elements mentioned above. According to the embodiment, the flexible architecture also includes a mode for a display with only one bit. In this case, according to the embodiment, since the pixel cell stores a value until new data is received, there is no need to store data in the frame buffer, and therefore the use of the frame buffer can be completely omitted for this single pixel. To enable complete switching off of the frame buffer, this mode has the option of programming the pixel by writing directly, i.e., by bypassing the frame buffer.

[0080] Therefore, in embodiments where data is partially integrated into a frame buffer for pixel cells (more than 1 bit), limitations are applied to a portion of the frame buffer implemented within the pixel cell.

[0081] The following describes the coupling of the frame buffer 36 to the pixel matrix (see 23l and 23r in Figure 6, or column R and row Z in Figure 2). The coupling of the frame buffer 36 to the pixel matrix 22 by row drivers 23l and 23r can be embodied in various ways. In the prior art, pixels 22 are programmed according to the data stream that subsequently arrives, or a row of data is collected and then written to the pixel matrix 22; therefore, the duration of a row typically includes at least several clocks depending on the number of optical elements in the row. According to the present invention, by fully implementing a complete frame buffer 36, a further option is obtained in which the data for an entire row is fetched in one clock cycle rather than the data being fetched individually from memory 36. Depending on the sequence length (which is determined by the scanning scheme, but also by, for example, the bit depth) and the implemented clock frequency, the refresh rate or data transfer rate of the microdisplay can be unprecedentedly high as a result. This is due to the fact that the new architecture includes all these modules on an integrated switching circuit. In conventional individual implementations, such bandwidth requires a large number of signals between the driver module and the backplane, making it impossible to implement in a useful way (both in terms of wiring and driver current consumption). With highly integrated chips, it is possible to read all columns from memory in parallel, even at high resolution. The actual transfer rate can be influenced by the sequencer, thus corresponding to the fundamental concept of the present invention, which embodies a highly flexible architecture. This transfer range is from 0 Hz to approximately 1, 5, 10, 20, 50, 100 kHz or higher, depending on the resolution and frequency. Depending on the application, the refresh rate can be balanced with the current consumption required by the application. Furthermore, the sequencer enables additional functions important in the fields of augmented reality (AR) and virtual reality (VR), such as inserting black images (to prevent motion blur and motion sickness).

[0082] In other words, this means that, in order to make the microdisplay architecture 10 flexible, the trigger clock can be varied by 36 and 34 sq, and therefore variations in refresh rate and transferred bit depth are possible. Thus, in a flexible microdisplay architecture, the connection of the frame buffer 36 can be influenced by the transferred bit depth, the transmission frequency used, the insertion of generically generated data frames (without using data from the frame buffer such as black images), and delay elements for time weighting of the currently displayed data. All of these parameters allow for a trade-off between the displayed content and the system's current consumption. This is also true when the actual data (including not only the display data itself but also the display data generated from information data on the chip) is adapted. For example, an adapted bit depth provides a reduction in the data bandwidth of the input interface, or a reduction in the load on the CPU / GPU 34p, a reduction in the utilization of the frame buffer 36, a reduction in the required transmission of the pixel matrix 22, and a reduction in current consumption. According to this architecture, this adaptability can be used from the entire system down to individual frames.

[0083] According to the embodiment, one of the following units or functions can be integrated into the microdisplay 10 or the data processing means 34 of the microdisplay 10.

[0084] Implementation of a temperature sensor 34temp for in-system compensation of temperature effects. This enables integrated temperature-dependent tracking of pixel voltage or common counter electrode. In other words, according to the embodiment, the circuit plane includes a temperature sensor 34temp, and the control circuit 34 is configured to track the pixel voltage based on the temperature signal.

[0085] According to a further embodiment, unit 34 or 34k can perform automatic brightness calibration by measuring brightness on a reference structure.

[0086] The functional unit 34test is used for integrated memory for individual system monitoring and system testing. The functional unit 34tg includes a test pattern generator for generating test data for the chip itself. Here, testing during manufacturing, i.e., manufacturing tests by these units 34test or 34tg, can also be performed.

[0087] According to a further embodiment, the functional unit 34pwr includes a central power management unit that implements the above-described scaling of current consumption by appropriate switching off of the power region. According to a further embodiment, external synchronization (see 34s) is also possible. This provides different synchronization signals for external voltage generation, such as an inversion signal in the case of LCOS, or helps to synchronize with the end of a sequence (e.g., for a specific synchronization with an optical system).

[0088] Furthermore, adjustable clock generation 34cl is possible to adapt different frequency regions of the chip to the requirements of each application case (e.g., the clock frequency for controlling the frame buffer and sequence memory). According to a further embodiment, for example, in the case of the operation of the backplane in a quad pixel array consisting of red (r), green (g), blue (b), and white (w), integrated whiteness calculation can be performed (see 34w).

[0089] According to a further embodiment, the backplane can include, for example, an integrated voltage regulator for V in , v ref and pixel voltages. Gamma calibration is also possible. These elements are provided as an assembly on the circuit plane.

[0090] Furthermore, the circuit plane may also include interface 32, in particular interface 32p. This interface controls the selection of interface 32 or interface 32b, 32a, or, in some cases, data transfer to the CPU / GPU 34p, and supplies the display data generated by the CPU / GPU to the frame buffer (in the case of an information data interface). The pad row 32a is configured to be coupled to a physical input. Switching between 32a and 32b is performed using unit 32p (Digital Interface Protocol) as the protocol plane.

[0091] In the following sections, embodiments of the present invention will be examined separately, with particular attention paid to alternative or more detailed implementation configurations.

[0092] One embodiment provides a flexible microdisplay architecture characterized in that one or more front-plane elements can be positioned on a backplane and controlled therethrough, several wired and / or wireless interfaces for data transmission are available, and full or partial image memory is embodied on the backplane.

[0093] According to the embodiment, the backplane can be realized using CMOS technology. Preferably, CMOS technology of 90 nm or less is used.

[0094] According to the embodiment, the backplane can be realized in CFT technology.

[0095] According to the embodiment, the backplane comprises one or more interfaces. According to the embodiment, the interfaces or standard interfaces of one or more interfaces may be selected depending on the application.

[0096] According to the embodiment, the backplane can operate as both a memory-based architecture and a refresh rate-based architecture. According to the embodiment, the operating mode of the microdisplay depends on an algorithm embodied in hardware or software so as to dynamically adapt to the image content and / or current application.

[0097] Regarding image memory, it can be fully, partially, or as a single bit within a pixel cell. Thus, according to the embodiment, instead of fully locating the memory within the pixel, it can also be partially located outside or inside the edge area of ​​the backplane. Note that bit memory can be partially or completely turned off and / or bypassed. According to the embodiment, the controlled bit depth of the pixel can be variably adjusted. According to the embodiment, specific leakage compensation means are provided within the pixel.

[0098] According to the embodiment, a specific leakage compensation means is implemented in the pixel cell. An additional transistor is possible between the optical element driver and the optical element itself.

[0099] It should be noted that the units described above as light-emitting elements can be implemented as LEDs, OLEDs, or μLEDs. Each pixel may include an LED or subpixels (e.g., several LEDs for RGB). According to one embodiment, the front plane may be implemented in a light-modulated LCOS or a light-emitting μLED or OLED.

[0100] According to one embodiment, a driver adapted to the front-plane technology can be implemented separately from the image memory. According to another embodiment, depending on the configuration, the pixel cells are implemented as a common anode and / or common cathode that functions for control. Alternatively, the front-plane may be configured without a common electrode.

[0101] According to one embodiment, a high-bandwidth image memory can be connected to the pixel matrix, enabling the implementation of both refresh rates (e.g., 240Hz, 480Hz, 1kHz, 5kHz, 10kHz, 20kHz, 50kHz, 100kHz or higher). According to the embodiment, the actual bandwidth between the frame buffer and the pixel matrix can be adapted. According to the embodiment, by implementing a temperature sensor, internal system compensation for temperature effects within the backplane becomes possible. Herein, according to the embodiment, integrated temperature-dependent tracking of pixel voltage or common counter electrode can be implemented in the backplane.

[0102] According to one embodiment, automatic luminance calibration is made possible by measuring the luminance on a reference structure.

[0103] According to the embodiment, an integrated memory and system test unit are provided for performing actual system monitoring or simplified product testing.

[0104] According to one embodiment, the test pattern generator is responsible for generating test data on the backplane.

[0105] Further embodiments provide a configuration similar to the one described above, having a central power management unit for scaling current consumption by appropriately switching off power domains.

[0106] Further embodiments provide a unit for synchronizing a microdisplay architecture with additional external components.

[0107] According to the embodiment, adjustable clock generation can be implemented to adapt different frequency domains of the chip to the requirements of their respective application areas (e.g., clock frequencies for controlling frame buffers and sequence memory).

[0108] According to one embodiment, the pixel matrix control unit may include a sequencer configured to provide different refresh rates (e.g., 240 Hz, 480 Hz, 1 kHz, 5 kHz, 10 kHz, 20 kHz, 50 kHz, 100 kHz or higher) from memory to light-emitting elements or optical modulation elements (internal refresh rate).

[0109] According to one embodiment, the pixel matrix control unit may include a programmable and / or dynamically configurable cyclic transfer mimic configured to control (dynamically and / or according to programming) between the memory and the light-emitting element or optical modulation element.

[0110] According to one embodiment, the backplane can be provided for operation with a quad-pixel array consisting of, for example, red (r), green (g), blue (b), and white (w), for which, for example, the data value of the white pixel is determined. According to one embodiment, automatic balancing of the white point of the microdisplay is possible. For this purpose, according to the embodiment, a unit for white balance is provided.

[0111] According to one embodiment, an integrated voltage regulator for generating pixel voltages is provided. According to a further embodiment, gamma calibration on the backplane is provided.

[0112] While several embodiments have been described in the context of the apparatus, it is clear that these embodiments also represent descriptions of the corresponding methods, so that blocks or devices of the apparatus also correspond to each method step or feature of a method step. Similarly, embodiments described in the context of method steps also represent descriptions of the corresponding blocks, details, or features of the corresponding apparatus. Some or all of the method steps may be performed by (or using) hardware devices such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the most important method steps may be performed by such apparatus.

[0113] Depending on specific implementation requirements, embodiments of the present invention may be implemented in hardware or software. The implementation may be carried out using a digital storage medium, such as a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM, or flash memory, a hard drive, or another magnetic or optical memory storing electronically readable control signals, which may or may not cooperate with a programmable computer system to perform the respective method. Thus, the digital storage medium may be computer-readable.

[0114] Some embodiments of the present invention include a data carrier containing electronically readable control signals that can cooperate with a programmable computer system so that one of the methods described herein can be performed.

[0115] Generally, embodiments of the present invention can be implemented as a computer program product having program code, the program code being operable to perform one of the methods when the computer program product is executed on a computer.

[0116] The program code may be stored, for example, in a machine-readable carrier.

[0117] Other embodiments include a computer program for performing one of the methods described herein, the computer program being stored on a machine-readable carrier. In other words, one embodiment of the method of the present invention is a computer program that, when the computer program is executed on a computer, includes program code for performing one of the methods described herein.

[0118] Accordingly, a further embodiment of the method of the present invention is a data carrier (or digital storage medium or computer-readable medium) on which a computer program for performing one of the methods described herein is recorded. The data carrier, digital storage medium, or computer-readable medium is typically tangible or non-volatile.

[0119] Therefore, a further embodiment of the method of the present invention is a data stream or sequence of signals representing a computer program for performing one of the methods described herein. The data stream or sequence of signals may be configured to be transmitted, for example, over a data communication connection, such as the Internet.

[0120] Further embodiments include processing means configured or adapted to perform one of the methods described herein, such as a computer or a programmable logic device.

[0121] Further embodiments include a computer on which a computer program for performing one of the methods described herein is installed.

[0122] Further embodiments of the present invention include an apparatus or system configured to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission may be, for example, electronic or optical. The receiver may be, for example, a computer, a mobile device, a memory device, or a similar device. The apparatus or system may include, for example, a file server for transmitting the computer program to the receiver.

[0123] In some embodiments, programmable logic devices (e.g., field-programmable gate arrays, FPGAs) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field-programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware device. This may be universally applicable hardware such as a computer processor (CPU), or method-specific hardware such as an ASIC.

[0124] The embodiments described above are merely illustrative of the principles of the present invention. Modifications and variations of the configurations and details described herein will be apparent to those skilled in the art. Accordingly, the present invention is intended to be limited only by the appended claims and not by the specific details presented herein.

[0125] References [1] Vogel - 77‐1.pdf, Vogel et al., “Ultra-low Power OLED Microdisplay for Extended Battery Life in NTE Displays”.m

Claims

1. A microdisplay architecture (10), An optical plane (20) including several light-emitting elements or optical modulation elements, The circuit plane (30) on which the optical plane (20) is arranged Equipped with, The circuit plane (30) comprises one or more interfaces (32a, 32b), a pixel matrix control unit (34), and an image memory (36) for controlling some of the light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d). Microdisplay architecture (10).

2. The microdisplay architecture (10) according to claim 1, wherein the circuit of one or more interfaces (32a, 32b), the pixel matrix control unit (34), and the image memory are directly integrated within the circuit plane.

3. The microdisplay architecture (10) according to claim 1 or 2, wherein the pixel matrix control unit (34) is configured to control some of the light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) in a refresh rate-based operating mode.

4. The microdisplay architecture (10) according to claim 1, 2, or 3, wherein the pixel matrix control unit (34) is configured to control some of the light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) in a memory-based operating mode.

5. The pixel matrix control unit (34) is configured to selectively switch between several operating modes, according to any one of claims 1 to 4, the microdisplay architecture (10).

6. The microdisplay architecture (10) according to any one of claims 1 to 4, wherein the microdisplay architecture comprises several interfaces (32a, 32b), and / or several interfaces (32a, 32b) of different bandwidths, and / or several interfaces (32a, 32b) of different communication topologies, including wired or wireless communication topologies (32a, 32b).

7. The selection of the transfer interface and / or transfer mode is made in accordance with an operating mode, including a memory-based operating mode, according to claim 6 (10).

8. The microdisplay architecture (10) according to any one of claims 1 to 7, wherein the pixel matrix control unit (34) comprises a programmable and / or dynamically configurable cyclic transfer mimic configured to control the data flow between the memory (36) and the light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

9. The microdisplay architecture (10) according to any one of claims 1 to 8, further comprising an internal CPU / GPU (34p) configured to convert received or stored information into display pixel data and to display the display pixel data on several light-emitting or light-modulating elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

10. The microdisplay architecture (10) according to any one of claims 1 to 9, comprising an internal graphics processor, the graphics processor configured to control several light-emitting or light-modulating elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) in a refresh rate-based operating mode, and configured to be switch-off and / or put into sleep mode in a memory-based operating mode.

11. The pixel matrix control unit (34) is configured to control several light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) grouped into a first group, and several light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) grouped into a second group, the microdisplay architecture (10) according to any one of claims 1 to 10.

12. The pixel matrix control unit (34) is configured to change the update rate, and / or, in the memory-based operating mode, the microdisplay architecture (10) according to any one of claims 1 to 11, configured to control some of the light-emitting elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) at a lower update rate or no update rate, or in the refresh rate-based operating mode, the microdisplay architecture (10) according to any one of claims 1 to 11, configured to control some of the light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) at a higher update rate, particularly above 30 Hz, above 60 Hz, above 90 Hz, or above 120 Hz.

13. The microdisplay architecture (10) according to any one of claims 1 to 12, wherein the pixel matrix control unit (34) is configured to change and / or reduce the bit depth to control each of the several light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

14. The microdisplay architecture (10) according to any one of claims 1 to 13, wherein some of the light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) of the optical plane (20) and / or the image memory (36) of the circuit plane (30) comprises technology nodes of less than 90 nm or less than 45 nm.

15. The microdisplay architecture (10) according to any one of claims 1 to 14, wherein the circuit plane (30) comprises a transistor having an additional leakage circuit (29).

16. The microdisplay architecture (10) according to claim 15, wherein the leakage circuit (29) comprises two transistors for each light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

17. The image memory (36) is fully integrated within the circuit plane (30) assigned to the light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d), or the image memory (36) is partially located in or outside the edge area of ​​the circuit plane and implemented as an image memory (36) assigned to the light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d), and / or The image memory (36) comprises one or more bits for each light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d), according to any one of claims 1 to 16, the microdisplay architecture (10).

18. The pixel matrix control unit (34) is configured to partially and / or stepwise and / or completely switch off the image memory, or to bypass the image memory, or to bypass the image memory in the refresh rate-based operating mode, according to any one of claims 1 to 17, microdisplay architecture (10).

19. The microdisplay architecture (10) according to any one of claims 1 to 18, wherein the pixel matrix control unit (34) comprises at least one switch (34sw) and one driver (34t) for each light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

20. The aforementioned several light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) are implemented as a common cathode circuit, and / or The pixel matrix control unit (34) controls the reference voltage V ｒｅｆ By reducing the pixel voltage V ｐｉｘ１ The brightness is increased by increasing the pixel voltage V (or the brightness of the light-emitting element / modulator is set to the pixel voltage V ｐｉｘ１ and the aforementioned reference voltage V ｒｅｆ The microdisplay architecture (10) according to any one of claims 1 to 19, wherein the control unit (34) is configured to control different light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) or pixel subelements by different pixel voltages.

21. The aforementioned several light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) are configured as a common anode circuit, and / or The pixel matrix control unit (34) controls the reference voltage V ｒｅｆ By increasing the pixel voltage V ｐｉｘ２ The device is configured to increase the brightness by decreasing the pixel voltage V, or the brightness of the light-emitting element / light-modulating element is configured to increase the brightness by decreasing the pixel voltage V. ｐｉｘ２ and the aforementioned reference voltage V ｒｅｆ A microdisplay architecture (10) according to any one of claims 1 to 20, which is changed by changing the difference between and

22. The microdisplay architecture (10) according to any one of claims 1 to 21, wherein the input frequency of the image data at the input of the pixel matrix control unit (34) and / or the memory (36) is less than or equal to the output frequency of the image data at the output of the pixel matrix control unit (34) and / or the memory (36).

23. The pixel matrix control unit (34) is configured to control several light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) grouped into a first group and several light-emitting or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) grouped into a second group, wherein the sequence and / or amplitude differ when controlling the first group and the second group, according to any one of claims 1 to 22, the microdisplay architecture (10).

24. The microdisplay architecture (10) according to any one of claims 1 to 23, wherein the pixel matrix control unit (34) comprises a sequencer configured to provide different refresh rates from the memory (36) to the light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

25. The light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d) is implemented as an OLED, uLED or μLED, or as an LCOS, according to any one of claims 1 to 24 (10).

26. A microdisplay architecture (10), An optical plane (20) having several light-emitting elements or optical modulation elements (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d), The circuit plane (30) on which the optical plane (20) is arranged The circuit plane (30) includes a pixel matrix control unit (34) for controlling (34) the light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d), and the pixel matrix control unit (34) includes one or more transistors that form an additional leakage circuit (29). Microdisplay architecture (10).

27. The microdisplay architecture (10) according to claim 26, wherein the leakage circuit (29) includes two additional transistors for each light-emitting element or optical modulation element (22, 22', 22'', 22a, 22b, 22c, 22d, 22e, 22d).

28. A method for controlling (34) a microdisplay architecture (10) according to any one of claims 1 to 25, The steps of operating the pixel matrix control unit (34) in the memory-based operating mode using the image memory (36), or The step of operating the pixel matrix control unit (34) in a memory-based operating mode, with or without using the image memory (36). Methods that include...

29. A computer program for performing the method of claim 28 when the method is performed on a pixel matrix control unit (34).

Images