Multiple System-on-Chip Deployment for Vehicle Computing Systems

Abstract

The computing system may include a first system-on-a-chip (SoC) and a second SoC. Each SoC may have memory into which the SoC exposes state information. In the first SoC, the state information may correspond to a set of tasks performed by the first SoC, which executes the set of tasks using multiple computing components. The first SoC may have direct access to its own memory to dynamically read the state information exposed by the first SoC. In a backup role, the second SoC maintains a subset of computing components in a low-power state. If the second SoC detects a trigger while reading the state information exposed in the first memory of the first SoC, the second SoC powers up the subset of computing components and takes over the set of tasks.

Claims

1. A first system-on-a-chip (SoC) comprising a first memory and a first plurality of computing components, wherein the first SoC exposes state information corresponding to a set of tasks being executed by the first SoC into the first memory, A second SoC comprising a second memory and a second plurality of computing components, the second SoC having memory access to the first memory of the first SoC to dynamically read the state information exposed by the first SoC, and maintaining a subset of the second plurality of computing components in a low-power state, When the second SoC detects a trigger while reading the state information exposed in the first memory of the first SoC, the second SoC powers up the subset of the second plurality of computing components to take over the set of tasks. Computing system.

2. The aforementioned set of tasks includes autonomous driving tasks. The computing system according to claim 1.

3. The autonomous driving task includes sensor data perception and inference tasks for autonomously operating the vehicle along a driving route. The computing system according to claim 2.

4. The trigger corresponds to the first SoC suffering a failure or malfunction, and the failure or malfunction corresponds to overheating, power surge, or error in the first SoC. The computing system according to claim 1.

5. The first SoC is powered by the vehicle's first power supply, and the second SoC is powered by the vehicle's second power supply. The computing system according to claim 1.

6. The first power source comprises a battery pack used for propulsion of the vehicle, and the second power source comprises an auxiliary power source for the vehicle. The computing system according to claim 5.

7. The first SoC and the second SoC are electrically coupled to each other via an interconnection having at least one electrical safety switch in order to protect the computing system from power surges from either the first SoC or the second SoC. The computing system according to claim 1.

8. Each time the computing system is rebooted, the first SoC and the second SoC switch between (i) the role of executing the set of tasks and (ii) the role of placing a subset of computing components into the low-power state and dynamically reading the exposed state information. The computing system according to claim 1.

9. The first SoC dynamically reads the second memory of the second SoC and determines whether the second SoC is ready to take over the set of tasks being performed by the first SoC. The computing system according to claim 1.

10. The first and second SoCs, which are arranged to dynamically read the state information and take over the set of tasks, provide redundancy that facilitates the evaluation of the Automotive Safety Integrity Level (ASIL) of the computing system. The computing system according to claim 1.

11. The first and second sets of computing components each include chiplets of the first SoC and the second SoC, The computing system according to claim 1.

12. The subset of the second plurality of computing components of the second SoC in the low-power state includes a plurality of one or more general-purpose computing chiplets, one or more autonomous driving chiplets, one or more machine learning accelerator chiplets, one or more sensor input chiplets, or one or more high-bandwidth memory chiplets. The computing system according to claim 11.

13. Each of the first plurality of computing components of the first SoC and each of the second plurality of computing components of the second SoC includes a FuSa CPU that exposes the state information of the first SoC and the second SoC to the functional safety (FuSa) components of the first memory and the second memory, respectively. The computing system according to claim 12.

14. The first SoC and the second SoC do not place the FuSa CPU in the low-power state. The computing system according to claim 13.

15. The aforementioned status information includes statistical information corresponding to the surrounding environment of the vehicle on which the computing system is installed. The computing system according to claim 1.

16. When the second SoC takes over the set of tasks from the first SoC, the first SoC resets or reboots the first set of computing components. The computing system according to claim 1.

17. At least one non-temporary computer-readable medium for storing instructions, wherein when the instructions are executed by one or more processors of a computing system, the computing system... In a first system-on-a-chip (SoC) comprising a first memory and a first plurality of computing components, state information corresponding to a set of tasks performed by the first SoC is exposed in the first memory. In a second SoC comprising a second memory and a second plurality of computing components, (i) the second SoC accesses the first memory of the first SoC to dynamically read the state information exposed by the first SoC while the subset of the second plurality of computing components is in a low-power state; (ii) detects a trigger while reading the state information exposed in the first memory of the first SoC; and (iii) in response to the detection of the trigger, energizes the subset of the second plurality of computing components to take over the set of tasks from the first SoC. At least one non-temporary computer-readable medium.

18. The aforementioned set of tasks includes autonomous driving tasks. The at least one non-temporary computer-readable medium according to claim 17.

19. The autonomous driving task includes sensor data perception and reasoning tasks for autonomously operating the vehicle along a driving route. The at least one non-temporary computer-readable medium according to claim 18.

20. A computer implementation method, In a first system-on-a-chip (SoC) comprising a first memory and a first plurality of computing components, state information corresponding to a set of tasks performed by the first SoC is exposed in the first memory. In a second SoC comprising a second memory and a second plurality of computing components, (i) accessing the first memory of the first SoC to dynamically read state information exposed by the first SoC while the second SoC is maintaining a subset of the second plurality of computing components in a low-power state, (ii) detecting a trigger while reading the state information exposed in the first memory of the first SoC, and (iii) in response to detecting the trigger, energizing the subset of the second plurality of computing components to take over the set of tasks from the first SoC. Computer implementation method.

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