A display with a gate driver circuit mechanism that reduces power consumption and improves reliability.

Abstract

The present invention provides a display having a gate driver circuit mechanism. [Solution] The display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a mixture of a silicon transistor, one or more semiconductor oxide transistors, and one or more capacitors. Each semiconductor oxide transistor may have a back gate terminal that is shorted to one of its source-drain terminals, shorted to its front gate terminal, or configured to receive a bias voltage. With this configuration, the gate driver circuit may exhibit low threshold voltage drift and therefore improved device reliability over time.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 657,870, filed on May 8, 2024, which claims the benefit of U.S. Provisional Patent Application No. 63 / 507,775, filed on June 13, 2023, and those applications are hereby incorporated by reference in their entirety. The present invention generally relates to electronic devices, and more particularly to electronic devices having a display.

Background Art

[0002] An electronic device may include a display. For example, mobile phones, tablets, wristwatches, and portable computers often include a display for presenting image content to a user. Displays, such as organic light-emitting diode (OLED) displays, have an array of display pixels formed by light-emitting diodes. In this type of display, a gate driver circuit mechanism can be used to provide control signals to each row within the array of display pixels. Designing the gate driver circuit mechanism can be difficult.

Summary of the Invention

[0003] An electronic device may include a display having an array of display pixels. The display pixels may be organic light-emitting diode display pixels. Each display pixel may include at least an organic light-emitting diode (OLED) that emits light and an associated semiconductor oxide transistor. The array of display pixels may receive control signals, such as a gate output signal from a peripheral gate driver circuit mechanism. The gate driver circuit mechanism may include a chain of gate driver circuits.

[0004] One aspect of the present disclosure provides a gate driver circuit comprising: a first transistor having a drain terminal coupled to a first power supply line, a source terminal coupled to the output port of a gate driver circuit, and a gate terminal, wherein a gate output signal is generated at the output port and provided to a plurality of display pixels; a second transistor having a drain terminal coupled to the output port, a source terminal coupled to a second power supply line different from the first power supply line, and a gate terminal; and a semiconductor oxide transistor having a source terminal coupled to the first power supply line or configured to receive a bias voltage, a drain terminal coupled to the gate terminal of the second transistor, a back gate terminal shorted to the source terminal of the semiconductor oxide transistor, and a front gate terminal.

[0005] One aspect of the present disclosure provides a gate driver circuit comprising: a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a gate terminal coupled to a first node, and a source terminal coupled to a second power supply line different from the first power supply line; and a capacitor having a first terminal coupled to the first node and a second terminal coupled to the second power supply line.

[0006] One aspect of the present disclosure provides a gate driver circuit comprising: a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of a gate driver circuit, a front gate terminal, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a source terminal coupled to a second power supply line different from the first power supply line, and a gate terminal; an inverter having an output coupled to the gate terminal of the first silicon transistor; and a capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to the second power supply line.

[0007] One aspect of the present disclosure provides a gate driver circuit comprising: a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of a gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a gate terminal coupled to a first node, and a source terminal coupled to a second power supply line different from the first power supply line; and a logic subcircuit configured to generate a carry signal on the first node to be transmitted to an additional gate driver circuit.

[0008] One aspect of the present disclosure provides a gate driver circuit comprising: a first semiconductor oxide transistor having a first source-drain terminal configured to receive a first clock signal, a second source-drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal; a first capacitor coupled between the first node and the output port; a second semiconductor oxide transistor having a drain terminal coupled to the output port, a source terminal coupled to a first power supply line, a front gate terminal coupled to a second node, and a back gate terminal; and a second capacitor coupled between the second node and the first power supply line. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram of an exemplary electronic device having a display, according to several embodiments.

[0010] [Figure 2] This is a diagram of an exemplary display having an array of organic light-emitting diode display pixels according to several embodiments.

[0011] [Figure 3] This is a schematic diagram of an exemplary display pixel according to several embodiments.

[0012] [Figure 4A] This is a schematic diagram of an exemplary gate driver circuit according to several embodiments. [Figure 4B] This is a schematic diagram of an exemplary gate driver circuit according to several embodiments. [Figure 4C] This is a schematic diagram of an exemplary gate driver circuit according to several embodiments. [Figure 4D] This is a schematic diagram of an exemplary gate driver circuit according to several embodiments.

[0013] [Figure 5] This figure shows a chain of gate driver circuits of the type shown in Figures 4A to 4D, according to several embodiments.

[0014] [Figure 6A] This timing diagram shows the operation of a gate driver circuit of the type shown in Figure 5, according to several embodiments. [Figure 6B] This timing diagram shows the operation of a gate driver circuit of the type shown in Figure 5, according to several embodiments.

[0015] [Figure 7A] This is a schematic diagram of an exemplary gate driver circuit according to several embodiments. [Figure 7B] Circuit diagram of an exemplary gate driver circuit according to some embodiments.

[0016] [Figure 8] Diagram showing a chain of gate driver circuits of the type shown in FIGS. 7A and 7B according to some embodiments.

[0017] [Figure 9A] Timing diagram showing the operation of a gate driver circuit of the type shown in FIG. 8 according to some embodiments. [Figure 9B] Timing diagram showing the operation of a gate driver circuit of the type shown in FIG. 8 according to some embodiments. [Figure 9C] Timing diagram showing the operation of a gate driver circuit of the type shown in FIG. 8 according to some embodiments.

[0018] [Figure 10A] Circuit diagram of an exemplary gate driver circuit having a logic sub-circuit and an output buffer sub-circuit according to some embodiments.

[0019] [Figure 10B] Timing diagram showing the operation of the gate driver circuit shown in FIG. 10A according to some embodiments.

[0020] [Figure 11A] Circuit diagram of an exemplary gate driver circuit having a logic sub-circuit and an output buffer sub-circuit according to some embodiments.

[0021] [Figure 11B] Timing diagram showing the operation of the gate driver circuit shown in FIG. 11A according to some embodiments.

Mode for Carrying Out the Invention

[0022] Figure 1 shows an exemplary electronic device of a type in which a display may be provided. As shown in Figure 1, the electronic device 10 may have a control circuit 16. The control circuit 16 may include storage and processing circuits to support the operation of the device 10. The storage and processing circuits may include storage devices such as hard disk drive storage devices, non-volatile memory (e.g., flash memory, or other electrically programmable read-only memory configured to form a solid-state drive), and volatile memory (e.g., static or dynamic random-access memory). The processing circuits within the control circuit 16 can be used to control the operation of the device 10. The processing circuits may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc.

[0023] Input / output circuits within device 10, such as input / output devices 12, may be used to enable data to be supplied to device 10 and to enable data to be supplied from device 10 to external devices. Input / output devices 12 may include buttons, joysticks, scroll wheels, touchpads, keypads, keyboards, microphones, speakers, sound sources, vibrators, cameras, sensors, light-emitting diodes, and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands via input / output devices 12 and can receive status information and other outputs from device 10 using the output resources of input / output devices 12.

[0024] The input / output device 12 may include one or more displays, such as a display 14. The display 14 may be a touchscreen display including a touch sensor for collecting touch input from the user, or the display 14 may not be touch-sensitive. The touch sensor for the display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, an optical touch sensor, or other suitable touch sensor configuration.

[0025] The control circuit 16 may be used to execute software such as operating system code and applications on the device 10. While the device 10 is operating, the software running on the control circuit 16 can use the array of pixels in the display 14 to display an image on the display 14. The device 10 may be a tablet computer, laptop computer, desktop computer, display, mobile phone, media player, smartwatch or other wearable electronic device, or other suitable electronic device.

[0026] The display 14 may be an organic light-emitting diode (OLED) display, or a display based on other types of display technologies. A configuration in which the display 14 is an organic light-emitting diode (OLED) display may be described herein as an example. However, this is merely illustrative. Any preferred type of display may be used in the device 10 if desired.

[0027] The display 14 may have a rectangular shape (i.e., the display 14 may have a rectangular installation area and a rectangular periphery extending around the rectangular installation area), or it may have another preferred shape. The display 14 may be flat or it may have a curved outer shape.

[0028] Figure 2 shows a top view of a portion of the display 14. As shown in Figure 2, the display 14 may have an array of pixels 22 formed on a substrate 36. The substrate 36 may be made of glass, metal, plastic, ceramic, porcelain, or other substrate material. The pixels 22 can receive data signals via signal paths such as data lines D (sometimes called data signal lines, row lines, etc.) and can receive one or more control signals via control signal paths such as horizontal control lines G (sometimes called gate lines, scan lines, light-emitting lines, row lines, etc.). Within the display 14, there may be any preferred number of rows and columns of pixels 22 (e.g., tens or more, hundreds or more, or thousands or more).

[0029] Each pixel 22 may have a light-emitting diode 26 that emits light 24 under the control of a pixel control circuit formed from a thin-film transistor circuit such as a thin-film transistor 28 and a thin-film capacitor. The thin-film transistor 28 may be a polysilicon thin-film transistor, a semiconductor oxide thin-film transistor such as an indium zinc gallium oxide transistor, or a thin-film transistor formed from another semiconductor. The pixels 22 may include light-emitting diodes of different colors (e.g., red, green, and blue) to give the display 14 the ability to display a color image.

[0030] The display driver circuit 30 may be used to control the operation of the pixels 22. The display driver circuit 30 can be formed from an integrated circuit, a thin-film transistor circuit, or other suitable electronic circuit. The display driver circuit 30 in Figure 2 may include a communication circuit for communicating with a system control circuit, such as the control circuit 16 in Figure 1, via a path 32. The path 32 can be formed from traces on a flexible printed circuit or other cables. During operation, the control circuit (e.g., the control circuit 16 in Figure 1) can supply the circuit 30 with information about the image displayed on the display 14.

[0031] To display an image on the display pixels 22, the display driver circuit 30 can supply image data to data lines D (e.g., data lines flowing down the row of pixels 22) while issuing clock signals and other control signals to auxiliary display driver circuits such as gate driver circuit mechanisms 34 via path 38. If desired, the display driver circuit 30 can also supply clock signals and other control signals to gate driver circuit mechanisms 34 on the opposite edge of the display 14 (for example, gate driver circuit mechanisms may be formed on two or more sides of the display pixel array).

[0032] The gate driver circuit mechanism 34 (sometimes called a horizontal line control circuit or row driver circuit) can be implemented as part of an integrated circuit and / or using thin-film transistor circuits. The horizontal / row control lines G in the display 14 can transmit gate line signals (scan line control signals), light emission enable control signals, and / or other horizontal control signals for controlling the pixels of each row. There may be any suitable number of horizontal control signals for each row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.). The gate driver circuit mechanism 34 may include a plurality of gate driver circuits connected in a chain (e.g., gate drivers 100-1, 100-2, etc.). For example, each gate driver may be configured to generate one or more scan signals and / or carry signals that are fed forward to subsequent gate drivers in the chain and / or fed back to preceding gate drivers in the chain.

[0033] According to some embodiments, the pixel 22 and gate driver circuit mechanism 34 may be implemented using thin-film transistors such as semiconductor oxide transistors. “Semiconductor oxide transistor” may refer to, and may be defined herein as, a thin-film transistor having a channel region formed from a semiconductor oxide material (e.g., indium gallium zinc oxide or IGZO, indium tin zinc oxide or ITZO, indium gallium zinc oxide or IGTZO, indium tin oxide or ITO, or other semiconductor oxide material). Semiconductor oxide transistors are generally considered to be n-type (n-channel) transistors.

[0034] Semiconductor oxide transistors differ significantly from silicon transistors. “Silicon transistor” refers to, and may be defined herein as, a thin-film transistor having a polysilicon channel region deposited using a low-temperature process, sometimes called LTPS or low-temperature polysilicon. Because semiconductor oxide transistors exhibit lower leakage than silicon transistors, integrating at least a portion of the transistors within the pixel 22 can help reduce flicker (for example, by preventing current from leaking out of the gate terminal of the driving transistor Tdrive). In some embodiments, the pixel 22 and gate driver circuitry 34 may be formed using only semiconductor oxide transistors (i.e., the display 14 does not contain silicon transistors). In other embodiments, at least a portion of the transistors within the pixel 22 and / or gate driver circuitry 34 may be implemented as silicon transistors, such that the pixel 22 or gate driver circuitry 34 includes a combination of semiconductor oxide transistors and silicon transistors (e.g., n-type LTPS transistors or p-type LTPS transistors).

[0035] Different transistors within the display 14 may require different device characteristics for optimal display performance and operation. For example, transistors that are primarily in the off state may require higher negative-bias-temperature-stress (NBTS) stability. As another example, transistors that are primarily in the on state may require higher positive-bias-temperature-stress (PBTS) stability. At least some transistors within the gate driver circuit mechanism 34 can benefit from better PBTS and higher mobility to enhance their driving capability.

[0036] Figure 3 is a schematic diagram of an exemplary display pixel, such as an organic light-emitting diode (OLED) pixel 22 in a display 14. As shown in Figure 3, the display pixel 22 may include an OLED 26, a storage capacitor Cst, and associated pixel transistors such as a drive transistor Tdrive, a switching transistor Tsw, and a light-emitting transistor Tem. Any number of these transistors may be implemented as semiconductor oxide transistors (e.g., transistors with n-type channels formed from semiconductor oxides such as indium gallium zinc oxide or IGZO) or as silicon transistors (e.g., transistors with polysilicon channels deposited using a low-temperature process, sometimes called "LTPS" or low-temperature polysilicon transistors). In particular, the switching transistor Tsw may be implemented as a semiconductor oxide transistor (sometimes called an "oxide transistor"). Because semiconductor oxide transistors exhibit lower leakage than silicon transistors, implementing the switching transistor Tsw as a semiconductor oxide transistor helps reduce flicker (e.g., by preventing current from leaking out of the gate terminal of the drive transistor Tdrive).

[0037] In the example shown in Figure 3, the drive transistor Tdrive, the light-emitting transistor Tem, and the diode 26 may be connected in series between power supply terminals 90 and 92. The positive power supply voltage VDDEL may be supplied to the positive power supply terminal 90, while the ground power supply voltage VSSEL may be supplied to the ground power supply terminal 92. The positive power supply voltage VDDEL may be 3V, 4V, 5V, 6V, 7V, 2-8V, greater than 10V, or any suitable positive power supply voltage level. The ground power supply voltage VSSEL may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, less than -10V, or any suitable ground or negative power supply voltage level. The state of the drive transistor Tdrive controls the amount of current flowing from terminal 90 through diode 26 to terminal 92, thereby controlling the amount of light emitted from the display pixel 22.

[0038] Control signals from the display driver circuit, such as the row driver circuit 34 in Figure 2, are supplied to control terminals such as row control terminals 94 and 96. Row control terminal 96 may function as an illumination control terminal (sometimes called an illumination line or illumination control line), and row control terminal 94 may function as a scan control terminal (sometimes called a scan line or scan control line). An illumination control signal EM, sometimes called an illumination signal, may be supplied to terminal 96. The illumination signal EM is asserted to turn on transistor Tem during the illumination phase to allow current to flow from the drive transistor Tdrive to the light-emitting diode 26. A scan control signal SCAN may be applied to scan line 94. Asserting the signal SCAN can turn on transistor Tsw, thereby connecting the gate and drain terminals of transistor Tdrive. Deasserting the signal SCAN turns off transistor Tsw, disconnecting the gate and drain terminals of transistor Tdrive. During the data loading phase, a data signal (voltage) can be loaded into the storage capacitor Cst (for example, using a separate data loading transistor not shown). Image data loaded into pixel 22 can be at least partially stored in pixel 22 by using a capacitor Cst to hold the charge throughout the entire light emission stage.

[0039] The pixel structure in Figure 3 is illustrative and is not intended to limit the scope of this embodiment. If desired, the pixel 22 may include more or fewer thin-film transistors (e.g., one or more additional light-emitting transistors, initialization transistors, data-loading transistors, anode-reset transistors, bias transistors, etc.) and / or more or fewer capacitors.

[0040] Conventional gate driver circuits may consist only of silicon thin-film transistors (i.e., all transistors in the gate driver are p-type LTPS transistors) and a large capacitor coupled to the clock terminal configured to receive the clock signal. Having a large capacitor loading the clock terminal significantly increases the dynamic power consumption of the gate driver circuit because a considerable amount of power is required to charge and discharge the large capacitor in each gate driver circuit when the clock signal toggles. Other types of gate driver circuits that consist only of p-type LTPS transistors and do not have a large capacitor loading the clock terminal may exhibit lower power consumption, but they are less capable of generating short positive gate pulses.

[0041] According to the embodiment, a gate driver circuit is provided, such as a gate driver 100, which has only a minimal capacitive load on the clock terminal (and thus reduces power consumption). The gate driver circuit 100 may also include a mixture of both silicon transistors and one or more semiconductor oxide transistors. At least one of the semiconductor oxide transistors in the gate driver circuit 100 may have a front (top) gate terminal configured to receive a DC (direct current) voltage and optionally a back (bottom) gate terminal, or be coupled to a source-drain terminal to improve reliability.

[0042] Figure 4A is a schematic diagram showing one implementation configuration of the gate driver circuit 100. As shown in Figure 4A, the gate driver circuit 100 may include silicon transistors 110, 112, 114, 116, and 118 (e.g., p-type LTPS transistors), a semiconductor oxide transistor 120 (e.g., an n-type oxide transistor), and capacitors CQ and CB. Transistor 110 may have a drain terminal coupled to a ground power supply line 106 (e.g., a power supply terminal where a low voltage VGL is provided), a gate terminal coupled to node Q, and a source terminal coupled to the output port of the gate driver circuit 100. For example, the power supply voltage VGL may be -5V, -10V, -15V, -20V, -5 to -15V, less than -15V, 0V, +1V, +2V, or other suitable low voltage levels. The terms “source” and “drain” may be used synonymously when referring to the current conduction terminals of thin-film transistors. Capacitor CQ may be coupled between the gate and source terminals of transistor 110. Therefore, the source and drain terminals are sometimes referred to as "source-drain" terminals (for example, a transistor has a gate terminal, a first source-drain terminal, and a second source-drain terminal).

[0043] The gate output signal OUT(n) can be generated on the output port. The gate output signal OUT(n) can represent a scan control signal for controlling the corresponding switching transistors in one or more rows of pixels 22, or a light emission control signal for controlling the corresponding light-emitting transistors in one or more rows of pixels 22. The notation "(n)" represents the current row in the display pixel array. Therefore, the notation "(n-1)" can refer to a circuit associated with a preceding row in the display pixel array, while the notation "(n+1)" can refer to a circuit associated with a subsequent row in the display pixel array.

[0044] Transistor 112 may have a drain terminal coupled to the output port of the gate driver circuit 100, a gate terminal coupled to node QB, and a source terminal coupled to the positive power supply line 108 (e.g., a power supply terminal to which a high voltage VGH is provided). For example, the power supply voltage VGH may be 5V, 10V, 15V, 20V, 5-10V, 10-15V, greater than 15V, or other suitable high voltage levels. Capacitor CB may be coupled between the gate and source terminals of transistor 112. Transistors 110 and 112 directly coupled to the output port may be called output transistors. The voltage at node QB may be inverted with respect to the voltage at node Q (e.g., when the voltage at node Q is high, the voltage at node QB is low, and vice versa).

[0045] Transistor 114 may have a first source-drain terminal connected to node Q, a gate terminal connected to the VGL power line 106, and a second source-drain terminal connected to node Q2. Transistor 116 may have a first source-drain terminal connected to node Q2, a gate terminal configured to receive a clock signal CLK1, and a second source-drain terminal configured to receive a signal OUT(n-1), which is a gate start signal GST (for example, if gate driver circuit 100 is the first or second driver in the gate driver chain) or a gate output signal from a gate driver circuit in a preceding row. Transistor 118 may have a gate terminal connected to node Q2, a first source-drain terminal connected to node QB, and a second source-drain terminal connected to the VGH power line 108.

[0046] According to the embodiment of Figure 4A, the semiconductor oxide transistor 120 may have a front gate terminal coupled to node Q2, a drain terminal coupled to node QB, a source terminal configured to receive a bias voltage VDC, and a back (bottom) gate terminal (see source connection path 121) shorted to the source terminal of the semiconductor oxide transistor 120. In the stacked structure of a thin-film display, the front gate terminal is sometimes called a top gate conductor because it is formed from a conductive layer above the semiconductor oxide layer. On the other hand, the back gate terminal can be sometimes called a bottom gate conductor because it can be formed from a conductive layer below the semiconductor oxide layer. The voltage VDC can preferably represent a static voltage higher than the low voltage VGL. By biasing the transistor 120 in this way, it is possible to enable the transistor 120 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. In other examples, the voltage VDC may be equal to VGL, less than VGL, equal to VGH, between VGL and VGH, or other fixed DC voltage or adjustable voltage. Furthermore, the gate terminal of transistor 116, which receives the clock signal CLK1, has only a minimal capacitive load, which is useful in reducing the overall dynamic power consumption of the gate driver circuit 100.

[0047] The embodiment in Figure 4A, in which the gate driver circuit 100 has a semiconductor oxide transistor 120 configured to receive a voltage VDC, is illustrative. Figure 4B shows another embodiment of the gate driver circuit 100 having a semiconductor oxide transistor 122, which has a drain terminal coupled to node QB, a source terminal coupled to the VGL power line 106, a front gate terminal coupled to node Q, and a back gate terminal (see source connection 123) shorted to the source terminal of the semiconductor oxide transistor 122. The rest of the circuit structure of the gate driver 100 in Figure 4B is identical to that already described in relation to Figure 4A and does not need to be repeated in detail to avoid obscuring this embodiment. Compared to the embodiment in Figure 4A, the gate driver circuit 100 in Figure 4B omits the extra VDC voltage line, which simplifies the overall circuit complexity. By connecting the back gate terminal of the semiconductor oxide transistor 122 to VGL in this way, it is possible for transistor 122 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. Similar to the embodiment in Figure 4A, the gate terminal of transistor 116 that receives the clock signal CLK1 has only a minimal capacitive load, which reduces the overall dynamic power consumption of the gate driver circuit 100 in Figure 4B.

[0048] The embodiment in Figure 4B in which the gate driver circuit 100 includes only one semiconductor oxide transistor 122 is illustrative. Figure 4C shows another embodiment of the gate driver circuit 100 having an additional (second) semiconductor oxide transistor, such as transistor 124. As shown in Figure 4C, the semiconductor oxide transistor 124 may have a source terminal coupled to the VGL power line 106, a drain terminal coupled to the output port of the gate driver circuit 100, a front gate terminal coupled to node QB, and a back gate terminal (see source connection 125) shorted to the source terminal of the semiconductor oxide transistor 124 itself. In this configuration, the n-type semiconductor oxide transistor 124 can function as a dedicated pull-down transistor that drives the gate output signal OUT(n) low when activated.

[0049] The remaining circuit structure of the gate driver 100 in Figure 4C is identical to that already described in relation to Figure 4B and does not need to be repeated in detail to avoid obscuring this embodiment. Compared to the embodiment in Figure 4B, the gate driver circuit 100 in Figure 4C can operate in an even smaller VGH-VGL range, and thus the static power consumption of the gate driver circuit 100 can be minimized. By connecting the back gate terminal of the semiconductor oxide transistor 124 to VGL in this way, it is possible for the transistor 124 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. Similar to the embodiment in Figure 4A, the gate terminal of the transistor 116 that receives the clock signal CLK1 has only a minimal capacitive load, which reduces the overall dynamic power consumption of the gate driver circuit 100 in Figure 4C.

[0050] Figure 4D is a schematic diagram showing another embodiment of the gate driver circuit 100. As shown in Figure 4D, the gate driver circuit 100 may include silicon transistors 112, 116, and 118 (e.g., p-type LTPS transistors), semiconductor oxide transistors 111, 117, and 150 (e.g., n-type oxide transistors), and capacitor CB. The semiconductor oxide transistor 111 may have a source terminal coupled to the VGL power supply line 106, a drain terminal coupled to the output port of the gate driver circuit 100, a front gate terminal coupled to node QB, and a back gate terminal configured to receive a bias voltage VDC. The voltage VDC may preferably represent a static voltage lower than the voltage VGL. By biasing the transistor 111 in this manner, it is possible to enable the transistor 111 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. In other examples, the voltage VDC may be equal to VGL, less than VGL, equal to VGH, between VGL and VGH, or any other fixed DC voltage or adjustable voltage. If desired, the back gate terminal of transistor 111 may be shorted to the source terminal of transistor 111 to receive the low voltage VGL.

[0051] Transistor 112 may have a drain terminal coupled to the output port of the gate driver circuit 100, a gate terminal coupled to node QB, and a source terminal coupled to the positive power supply line 108' (e.g., a power supply terminal to which a high voltage VGH' is provided). For example, the power supply voltage VGH' may be different from VGH, less than VGH, greater than VGH, equal to VGH, or any other high voltage. Capacitor CB may be coupled between the gate and source terminals of transistor 112. Transistors 111 and 112 directly coupled to the output port may be called output transistors.

[0052] Transistor 118 may have a source terminal connected to the power supply line 108', a drain terminal connected to node QB, and a gate terminal connected to node Q2. Semiconductor oxide transistor 150 may have a drain terminal connected to node QB, a source terminal connected to the VGL power line, a front gate terminal connected to node Q2, and a back gate terminal configured to receive a bias voltage VDC. Transistors 118 and 150, thus connected in series, form a complementary inverter. Transistor 116 may have a first source-drain terminal connected to node Q2, a gate terminal configured to receive a clock signal CLK, and a second source-drain terminal configured to receive a signal OUT(n-1), which is a gate start signal GST (for example, if gate driver circuit 100 is the first or second driver in the gate driver chain) or a gate output signal from a gate driver circuit in a preceding row.

[0053] The semiconductor oxide transistor 117 may be coupled in parallel with transistor 116. In particular, the semiconductor oxide transistor 117 may have a first source-drain terminal coupled to node Q2, a second source-drain terminal configured to receive a gate start signal GST or OUT(n-1), a front gate terminal configured to receive an inverting clock signal CLKB (e.g., an inverted version of CLK), and a back gate terminal configured to receive a bias voltage VDC. To generate the inverting clock signal CLKB, the gate driver circuit 100 may include a clock inverter circuit 160. The clock inverter circuit 160 may include a p-type LTPS transistor 162 coupled in series with an n-type semiconductor oxide transistor 164. In particular, transistor 162 has a source terminal coupled to VGH, a gate terminal configured to receive a clock signal CLK, and a drain terminal. On the other hand, the semiconductor oxide transistor 164 has a drain terminal coupled to transistor 162, a source terminal coupled to VGL, a front gate terminal configured to receive a clock signal CLK, and a back gate terminal configured to receive a bias voltage VDC. The inverted clock signal CLKB can be generated at a node connected between transistor 162 and transistor 164.

[0054] The gate driver circuits 100 in Figures 4A, 4B, 4C, and 4D all share the same or similar functions. Figure 5 shows an exemplary gate driver circuit mechanism 34 having a chain of gate driver circuits including at least gate driver circuits 100-1, 100-2, 100-3, and 100-4 according to several embodiments. The gate driver circuit 100 in Figure 5 can represent a gate driver circuit of the type shown in Figures 4A, 4B, 4C, or 4B. As shown in Figure 5, the first gate driver circuit 100-1 is configured to generate a first gate output signal OUT(1), the second gate driver circuit 100-2 is configured to generate a second gate output signal OUT(2), the third gate driver circuit 100-3 is configured to generate a third gate output signal OUT(3), the fourth gate driver circuit 100-4 is configured to generate a fourth gate output signal OUT(4), and so on. Generally, the gate driver circuit mechanism 34 may include hundreds or thousands of gate driver circuits 100 that are linked together in a chain.

[0055] The gate driver circuit mechanism 34 in Figure 5 can be controlled using two global clock signals GCLK1 and GCLK2 and two gate start signals GST_odd and GST_even. Each odd gate driver circuit (e.g., gate drivers 100-1, 100-3, etc.) may have a transistor 116 configured to receive signal GCLK1, while each even gate driver circuit (e.g., gate drivers 100-2, 100-4, etc.) may have a transistor 116 configured to receive signal GCLK2. Thus, each gate driver circuit 100 receives only one clock signal (e.g., either GCLK1 or GCLK2). The first gate driver circuit 100-1 in the chain may receive the first gate start signal GST_odd (e.g., at the source-drain terminals of transistor 116 as shown in Figures 4A, 4B, 4C, and 4D). A second gate driver circuit 100-2 in the chain can receive a second gate start signal GST_even (for example, at the source-drain terminals of transistor 116 as shown in Figures 4A, 4B, 4C, and 4D). A third gate driver circuit 100-3 in the chain can receive a gate output signal OUT(1) from two rows prior. A fourth gate driver circuit 100-4 in the chain can receive a gate output signal OUT(2) from two rows prior. Thus, generally, the embodiment in Figure 5 shows each gate driver circuit in row (n) configured to receive OUT(n-2) from two rows above. This is merely illustrative. The gate driver circuit mechanism 34 can be modified so that gate drivers in row (n) receive gate output signals and / or carry output signals from one row above, two rows above, three rows above, four or more rows above, one row below, two rows below, three rows below, or four or more rows below, etc.

[0056] Figure 6A is a timing diagram showing the operation of a gate driver circuit of the type shown in Figure 5 during an active frame, according to several embodiments. As shown in Figure 6A, GCLK2 is a delayed version of GCLK1. The gate output signals OUT(1), OUT(2), OUT(3), and OUT(4) all overlap at least partially in time (for example, the rising edge of OUT(4) occurs before the falling edge of OUT(1)). The pulse width of the gate output signals is equal to an integer M times the clock period of GCLK1 (or GCLK2). The actual value of the integer M is determined by the pulse width of the gate start signal GST. A longer gate start pulse results in a longer corresponding pulse width for each gate output signal. A shorter gate start pulse truncates the corresponding pulse width for each gate output signal.

[0057] Figure 6B is a timing diagram showing the operation of a gate driver circuit of the type shown in Figure 5 during a blanking frame in several embodiments. As shown in Figure 6B, the gate start signal GST can be driven to either high or low, the global clock signals GCLK1 and GCLK2 must remain high, stopping their toggle during the blanking period, and the output polarity of each gate driver circuit 100 can be matched to the polarity of the GST signal (for example, if GST is held high during the blanking period, all gate output signals are driven to high, or vice versa).

[0058] The examples in Figures 4-6, which collectively employ two clock signals that are partially delayed or offset from each other (see, for example, GCLK1 and GCLK2 in Figures 5-6), are illustrative and not intended to limit the scope of this embodiment. Figure 7A shows another embodiment of gate driver circuit 100 that may be used in a chain of gate drivers that collectively employ two clock signals offset by 180° from each other. As shown in Figure 7A, the gate driver circuit 100 may include silicon transistors 212, 216, and 218 (e.g., p-type LTPS transistors), semiconductor oxide transistors 210, 214, and 220 (e.g., n-type oxide transistors), and capacitor CB.

[0059] The semiconductor oxide transistor 210 may have a source terminal coupled to the VGL power supply line 206, a drain terminal coupled to the output port of the gate driver circuit 100, a front gate terminal coupled to node X, and a back gate terminal configured to receive a bias voltage VDC. The voltage VDC may preferably represent a static voltage lower than the voltage VGL. By biasing the transistor 210 in this manner, it is possible to enable the transistor 210 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. In other examples, the voltage VDC may be equal to VGL, less than VGL, equal to VGH, between VGL and VGH, or other fixed DC voltage or adjustable voltage. If desired, the back gate terminal of the transistor 210 may alternatively be shorted to the source terminal of the transistor 210 to receive a low voltage VGL. Transistor 212 may have a drain terminal coupled to the output port of the gate driver circuit 100, a gate terminal coupled to node X, and a source terminal coupled to the positive power supply line 208 (e.g., a power supply terminal to which a high voltage VGH is provided). Transistors 210 and 212 directly coupled to the output port are sometimes called output transistors.

[0060] Transistor 216 may have a source terminal connected to the power supply line 208, a drain terminal connected to node X, and a gate terminal connected to node X2. Capacitor CB may be coupled between the gate terminal and the source terminal of transistor 216. Capacitor CB is optional. Semiconductor oxide transistor 214 may have a drain terminal connected to node X, a source terminal connected to the VGL power line, a front gate terminal connected to node X2, and a back gate terminal configured to receive a bias voltage VDC. Transistors 214 and 216, thus coupled in series, form a complementary inverter.

[0061] Transistor 218 may have a first source-drain terminal coupled to node X2, a gate terminal configured to receive a clock signal CLK, and a second source-drain terminal configured to receive a signal OUT(n-1), which is either a gate start signal GST (for example, if gate driver circuit 100 is the first or second driver in the gate driver chain) or a gate output signal from a gate driver circuit in a preceding row. Semiconductor oxide transistor 220 may be coupled in parallel with transistor 218. In particular, semiconductor oxide transistor 220 may have a first source-drain terminal coupled to node X2, a second source-drain terminal configured to receive a gate start signal GST or OUT(n-1), a front gate terminal configured to receive an inverted clock signal CLKB (for example, an inverted version of CLK), and a back gate terminal configured to receive a bias voltage VDC.

[0062] The configuration shown in Figure 7A, in which the back gate terminals of semiconductor oxide transistors 210, 214, and 220 are configured to receive a voltage VDC, is illustrative. If desired, one or more back gate terminals of these semiconductor oxide transistors may be shorted to their respective source terminals or to their respective front (top) gate terminals. The gate terminals of transistor 218, which receives the clock signal CLK, and the gate terminal of transistor 220, which receives the clock signal CLKB, have only minimal capacitive loads, thus helping to reduce the overall dynamic power consumption of the gate driver circuit 100 of the type shown in Figure 7A. For the gate driver circuit 100 in Figure 7A to function properly, the clock signal CLK may need to have a 50% duty cycle (for example, the clock signal CLK must have high-clock and low-clock phases of equal duration).

[0063] The embodiment in Figure 7A in which the gate driver circuit 100 includes one inverting circuit formed from transistors 214 and 216 to drive node X is illustrative. Figure 7B shows another embodiment of the gate driver circuit 100 which includes two inverting circuits 230 and 240 for separately driving the gate terminals of output transistors 210 and 212. As shown in Figure 7B, the gate driver circuit 100 may include silicon transistors 212 and 218 (e.g., p-type LTPS transistors), semiconductor oxide transistors 210 and 220 (e.g., n-type oxide transistors), inverting circuits 230 and 240, and capacitor CB.

[0064] The semiconductor oxide transistor 210 may have a source terminal coupled to the VGL power supply line 206, a drain terminal coupled to the output port of the gate driver circuit 100, a front gate terminal coupled to the output of the inverter 230, and a back gate terminal configured to receive a bias voltage VDC. The voltage VDC may preferably represent a static voltage lower than the voltage VGL. By biasing the transistor 210 in this manner, it is possible to enable the transistor 210 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. In other examples, the voltage VDC may be equal to VGL, less than VGL, equal to VGH, between VGL and VGH, or other fixed DC voltage or adjustable voltage. If desired, the back gate terminal of the transistor 210 may alternatively be shorted to the source terminal of the transistor 210 to receive a low voltage VGL, or shorted to the front gate terminal of the transistor 210. Transistor 212 may have a drain terminal coupled to the output port of the gate driver circuit 100, a gate terminal coupled to the output of the inverter 240, and a source terminal coupled to the positive power supply line 208 (e.g., a power supply terminal to which a high voltage VGH is provided). Transistors 210 and 212 directly coupled to the output port are sometimes referred to as output transistors.

[0065] Inverter 230 may have a p-type silicon transistor 232 and an n-type semiconductor oxide transistor 234 coupled in series between VGH and VGL. The semiconductor oxide transistor 234 may have a back gate terminal configured to receive a voltage VDC. The front gate terminals of inverter transistors 232 and 233 may be coupled to node Y. Inverter 240 may have a p-type silicon transistor 242 and an n-type semiconductor oxide transistor 244 coupled in series between VGH and VGL. The semiconductor oxide transistor 244 may have a back gate terminal configured to receive a voltage VDC. The front gate terminals of inverter transistors 242 and 244 may be coupled to node Y. Capacitor CB may be coupled between node Y and the VGH power line 208. Capacitor CB is optional.

[0066] Transistor 218 may have a first source-drain terminal coupled to node Y, a gate terminal configured to receive a clock signal CLK, and a second source-drain terminal configured to receive a signal OUT(n-1), which is either a gate start signal GST (for example, if gate driver circuit 100 is the first or second driver in the gate driver chain) or a gate output signal from a gate driver circuit in a preceding row. Semiconductor oxide transistor 220 may be coupled in parallel with transistor 218. In particular, semiconductor oxide transistor 220 may have a first source-drain terminal coupled to node Y, a second source-drain terminal configured to receive a gate start signal GST or OUT(n-1), a front gate terminal configured to receive an inverted clock signal CLKB (for example, an inverted version of CLK), and a back gate terminal configured to receive a bias voltage VDC. For the gate driver circuit 100 in Figure 7B to operate properly, the clock signal CLK may need to have a 50% duty cycle (for example, the clock signal CLK must have high-clock phases and low-clock phases of equal duration).

[0067] The configuration shown in Figure 7B, in which the back gate terminals of semiconductor oxide transistors 210, 234, 244, and 220 are configured to receive the voltage VDC, is illustrative. If desired, one or more back gate terminals of these semiconductor oxide transistors can be shorted to their respective source terminals or to their respective front (top) gate terminals. The gate terminals of transistor 218, which receives the clock signal CLK, and the gate terminal of transistor 220, which receives the clock signal CLKB, have only minimal capacitive loads, thus helping to reduce the overall dynamic power consumption of the gate driver circuit 100 of the type shown in Figure 7B. Compared to the design in Figure 7A, the gate driver circuit 100 in Figure 7B can operate at an even lower power level, at the cost of a slight increase in circuit area.

[0068] The gate driver circuits 100 in Figures 7A and 7B all share the same or similar functions. Figure 8 shows an exemplary gate driver circuit mechanism 34 having a chain of gate driver circuits including at least gate driver circuits 100-1, 100-2, 100-3, and 100-4 according to several embodiments. The gate driver circuits 100 in Figure 8 can represent the type of gate driver circuit shown in Figure 7A or Figure 7B. As shown in Figure 8, the first gate driver circuit 100-1 is configured to generate a first gate output signal OUT(1), the second gate driver circuit 100-2 is configured to generate a second gate output signal OUT(2), the third gate driver circuit 100-3 is configured to generate a third gate output signal OUT(3), the fourth gate driver circuit 100-4 is configured to generate a fourth gate output signal OUT(4), and so on. Generally, the gate driver circuit mechanism 34 may include hundreds or thousands of gate driver circuits 100 that are linked together in a chain.

[0069] The gate driver circuit mechanism 34 in Figure 8 can be controlled using a first global clock signal GCLK and a second global clock signal GCLKB, which is an inverted version of GCLK (i.e., GCLKB is offset or delayed by 180° relative to GCLK). Each odd gate driver circuit (e.g., gate drivers 100-1, 100-3, etc.) may have a transistor 218 configured to receive the signal GCLK and a transistor 220 configured to receive the signal GCLKB (e.g., the CLK input receives GCLK and the CLKB input receives GCLKB). Each even gate driver circuit (e.g., gate drivers 100-2, 100-4, etc.) may have a transistor 218 configured to receive the signal GCLKB and a transistor 220 configured to receive the signal GCLK (e.g., the CLK input receives GCLKB and the CLKB input receives GCLK).

[0070] The first gate driver circuit 100-1 in the chain can receive a gate start signal GST (for example, at the source-drain terminals of transistor 218 as shown in Figures 7A and 7B). The second gate driver circuit 100-2 in the chain can receive a gate output signal OUT(1) from the previous row. The third gate driver circuit 100-3 in the chain can receive a gate output signal OUT(2) from the previous row. Thus, generally, the embodiment in Figure 8 shows each gate driver circuit in row (n) configured to receive OUT(n-1) from the preceding row. This is merely illustrative. The gate driver circuit mechanism 34 can be modified so that the gate drivers in row (n) receive gate output signals and / or carry output signals from two rows above, three rows above, four or more rows above, one row below, two rows below, three rows below, or four or more rows below, etc.

[0071] Figure 9A is a timing diagram showing the operation of a gate driver circuit of the type shown in Figure 8 during an active frame, according to several embodiments. As shown in Figure 9A, CLKB is a delayed version of CLK. For odd-numbered gate drivers, the signal waveforms of CLK and CLKB are equal to GCLK and GCLKB, respectively. For even-numbered gate drivers, the signal waveforms of CLK and CLKB are equal to GCLKB and GCLK, respectively. The pulse width of the gate output signal OUT is equal to an integer M times the clock period of CLK. The actual value of the integer M is determined by the pulse width of the gate start signal GST. A longer gate start pulse results in a longer corresponding pulse width of the gate output signal. A shorter gate start pulse truncates the corresponding pulse width of the gate output signal.

[0072] Figure 9B is a timing diagram showing the operation of a gate driver circuit 100 of the type shown in Figure 7A during a blanking frame, according to several embodiments. As shown in Figure 9B, the gate start signal GST may be driven high, and the global clock signals CLK and CLKB should stop toggling and remain low during the blanking period.

[0073] Figure 9C is a timing diagram showing the operation of a gate driver circuit 100 of the type shown in Figure 7B during a blanking frame, according to several embodiments. As shown in Figure 9C, the gate start signal GST may be driven low, and the global clock signals CLK and CLKB should remain high during the blanking period, stopping the toggle.

[0074] The embodiments shown in Figures 4 to 9, in which the pulse width of the gate output signal is controlled by the gate start signal, are illustrative. Figure 10A shows another embodiment of the gate driver 100 in which the pulse width of the gate output signal can be adjusted by the pulse width of the clock signal itself. As shown in Figure 10A, the gate driver circuit 100 may include a logic subcircuit (part) 300 and an output buffer subcircuit (part) 302.

[0075] The output buffer subcircuit 302 may include an n-type semiconductor oxide transistor 310 and a p-type silicon transistor 312 coupled in series between power supply lines 306 and 308. The semiconductor oxide transistor 310 may have a source terminal coupled to the low-voltage line 306 (e.g., a power supply terminal from which a low voltage VGL is provided), a drain terminal coupled to the output port of the gate driver circuit 100 (e.g., an output terminal from which a gate output signal OUT(n) is provided), a front gate terminal coupled to node Z, and a back gate terminal configured to receive a bias voltage VDC. The voltage VDC may represent a static voltage preferably lower than the voltage VGL. By biasing the transistor 310 in this manner, it is possible to enable the transistor 310 to exhibit only a smaller threshold voltage shift over time, which is technically advantageous and beneficial by improving the overall reliability of the gate driver circuit 100. In other examples, the voltage VDC may be equal to VGL, less than VGL, equal to VGH, between VGL and VGH, or other fixed DC voltage or adjustable voltage. If desired, the back gate terminal of transistor 310 may be shorted to the source terminal of transistor 310 or to the front gate terminal of transistor 310 to receive a low voltage VGL.

[0076] The silicon transistor 312 may have a drain terminal coupled to the gate driver output port, a gate terminal coupled to node Z, and a source terminal coupled to the high-voltage line 308 (e.g., a power supply terminal supplied with high voltage VGH). A carry signal, such as CARRY(n), may be generated at node Z. The carry signal may be supplied to a gate driver circuit in another line (e.g., via path 350 (reference)). The carry signal CARRY(n) may be generated by the logic subcircuit 300. Thus, the logic subcircuit 300 can perform a shift register function.

[0077] The logic subcircuit 300 may include only capacitors CQ and CQB, and silicon transistors 314, 316, 318, 320, 322, 324, 326, and 328 (e.g., p-type LTPS transistors). Silicon transistor 314 may have a first source-drain terminal coupled to node Z, a second source-drain terminal configured to receive a first clock signal CLK1, and a gate terminal coupled to node Q. Capacitor CQ may be coupled between node Q and node Z. Silicon transistor 316 may have a first source-drain terminal coupled to node Z, a second source-drain terminal coupled to the VGH power line 308, and a gate terminal coupled to node QB. Capacitor CQB may be coupled between node QB and the power line 308. The voltage on node QB may generally be inverted with respect to the voltage on node Q (e.g., nodes Q and QB may be complementary nodes with inverted voltage levels).

[0078] Transistor 318 may have a first source-drain terminal connected to node Q, a gate terminal configured to receive the VGL voltage, and a second source-drain terminal connected to node Q2. Transistor 320 may have a first source-drain terminal connected to node Q2, a gate terminal configured to receive a second clock signal CLK2, and a second source-drain terminal configured to receive the signal CARRY(n-1) (for example, a carry signal output from the gate driver 100 of the preceding row). Transistor 322 may be connected in series with transistor 320. In particular, transistor 322 may have a first source-drain terminal connected to node Q2, a gate terminal configured to receive the clock signal CLK1, and a second source-drain terminal connected to transistor 324. Transistor 324 may be connected in series with transistor 322. Transistor 324 may have a drain terminal connected to transistor 322, a source terminal connected to the VGH power line 308, and a gate terminal connected to node QB. Transistor 326 may have a first source-drain terminal connected to node QB, a gate terminal connected to node Q2, and a second source-drain terminal configured to receive the clock signal CLK2. Transistor 328 may have a first source-drain terminal connected to node QB, a second source-drain terminal configured on the VGL power line, and a gate terminal configured to receive the clock signal CLK2.

[0079] Figure 10B is a timing diagram showing the operation of the type of gate driver circuit 100 described with respect to Figure 10A. As shown in Figure 10B, the carry signal CARRY(n-1) may be synchronized with the CLK2 signal and may have an active low pulse width set by the low clock phase of CLK2. Similarly, the carry signal CARRY(n) may be synchronized with the CLK1 signal and may have an active low pulse width set by the low clock phase of CLK1. The corresponding gate output signal OUT(n) may be synchronized with the carry signal CARRY(n). The gate output signal OUT(n) may have a relatively short positive (active high) pulse width set by the pulse width of the clock signal. As an example, the low-phase pulse width of CLK1 (or CLK2) may be set to 1 microsecond (μs), 2 μs, 3 μs, 4 μs, 5 μs, 1 to 5 μs, greater than 5 μs, less than 1 μs, 5 to 10 μs, greater than 10 μs, 10 to 100 μs, or other programmable durations. The term "active high" can refer to a type of operation in which a high voltage asserts, selects, or activates the corresponding transistor that receives the signal.

[0080] The embodiment shown in Figure 10A, which includes only one semiconductor oxide transistor 310, is illustrative. Figure 11A shows another embodiment of the gate driver circuit 100 in which all thin-film transistors are implemented as semiconductor oxide transistors. As shown in Figure 11A, the gate driver circuit 100 may include only capacitors CQ and CQB, and semiconductor oxide transistors 410, 412, 414, 416, 418, 420, 422, and 424. Transistor 410 may have a first source-drain terminal configured to receive a clock signal CLK1, a second source-drain terminal coupled to the output port of the gate driver circuit 100, a front gate terminal coupled to node Q, and a back gate terminal shorted to the second source-drain terminal of transistor 410 itself. Capacitor CQ may be coupled between node Q and the output port of the gate driver 100. Transistor 412 may have a drain terminal coupled to the output port of the gate driver 100, a source terminal coupled to the power supply line 406 (e.g., a power supply terminal supplied with a low voltage VGL), a front gate terminal coupled to node QB, and a back gate terminal coupled to the VGL power line 406. Capacitor CQB may be coupled between the gate terminal and the source terminal of transistor 412.

[0081] Transistor 408 may have a first source-drain terminal connected to node Q, a second source-drain terminal connected to node Q2, a front gate terminal connected to power supply line 408 (e.g., a power supply terminal to which a high voltage VGH is supplied), and a back gate terminal shorted to the second source-drain terminal of transistor 408 itself. Transistor 416 may have a first source-drain terminal connected to node Q2, a second source-drain terminal configured to receive a signal OUT(n-1) (e.g., a gate output signal generated by the gate driver of the preceding row), a front gate terminal configured to receive a clock signal CLK2, and a back gate terminal shorted to the first source-drain terminal of transistor 416 itself. Transistor 418 may be connected in series with transistor 416. In particular, transistor 418 may have a first source-drain terminal connected to node Q2, a second source-drain terminal connected to transistor 420, a front gate terminal configured to receive the clock signal CLK1, and a back gate terminal shorted to the second source-drain terminal of transistor 418 itself.

[0082] Transistor 420 may be coupled in series with transistor 418. In particular, transistor 420 may have a drain terminal coupled to transistor 418, a source terminal coupled to the VGL ground line 406, a front gate terminal coupled to node QB, and a back gate terminal shorted to the source terminal of transistor 420 itself. Transistor 422 may have a first source-drain terminal coupled to node QB, a second source-drain terminal configured to receive the clock signal CLK2, a front gate terminal coupled to node Q2, and a back gate terminal shorted to the first source-drain terminal of transistor 422 itself. Transistor 424 may have a drain terminal coupled to the VGH power line, a source terminal coupled to node QB, a front gate terminal configured to receive the clock signal CLK2, and a back gate terminal shorted to the source terminal of transistor 424 itself.

[0083] The example in Figure 11A, in which all semiconductor oxide transistors in the gate driver circuit 100 have back gate terminals shorted to the source terminals of all semiconductor oxide transistors themselves, is illustrative. If desired, one or more of these semiconductor oxide transistors can be configured to short their back gate terminals to their top gate terminals, to receive VGL, to receive VGH, or to receive a bias voltage VDC.

[0084] Figure 11B is a timing diagram showing the operation of the type of gate driver circuit 100 described in relation to Figure 11A. As shown in Figure 11B, the signal OUT(n-1) may be synchronized with the CLK2 signal and may have an active high / low pulse width set by the high clock phase of CLK2. The corresponding gate output signal OUT(n) may be synchronized with the CLK1 signal and may have an active high pulse width set by the high clock phase of CLK1. For example, the high-phase pulse width of CLK1 (or CLK2) may be set to 1 microsecond (μs), 2 μs, 3 μs, 4 μs, 5 μs, 1 to 5 μs, greater than 5 μs, less than 1 μs, 5 to 10 μs, greater than 10 μs, 10 to 100 μs, or other programmable durations. The term "active high" may refer to a type of operation in which a high voltage asserts, selects, or activates the corresponding transistor that receives the signal.

[0085] According to the embodiment, a gate driver circuit is provided that includes: a first transistor having a drain terminal coupled to a first power supply line, a source terminal coupled to the output port of the gate driver circuit, and a gate terminal, wherein a gate output signal is generated at the output port and provided to a plurality of display pixels; a second transistor having a drain terminal coupled to the output port, a source terminal coupled to a second power supply line different from the first power supply line, and a gate terminal; and a semiconductor oxide transistor having a source terminal coupled to the first power supply line or configured to receive a bias voltage, a drain terminal coupled to the gate terminal of the second transistor, a back gate terminal shorted to the source terminal of the semiconductor oxide transistor, and a front gate terminal.

[0086] According to another embodiment, the gate driver circuit includes a first capacitor having a first terminal coupled to the gate terminal of a first transistor and a second terminal coupled to an output port, and a second capacitor having a first terminal coupled to the gate terminal of a second transistor and a second terminal coupled to a second power supply line.

[0087] According to another embodiment, the first and second transistors include p-type silicon transistors.

[0088] According to another embodiment, the gate driver circuit includes a third transistor having a first source-drain terminal coupled to the gate terminal of a first transistor, a gate terminal coupled to a first power supply line, and a second source-drain terminal coupled to a node.

[0089] In another embodiment, the front gate terminal of the semiconductor oxide transistor is coupled to a node.

[0090] According to another embodiment, the front gate terminal of a semiconductor oxide transistor is coupled to the gate terminal of a first transistor.

[0091] According to another embodiment, the gate driver circuit includes an additional semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to an output port, a front gate terminal coupled to the gate terminal of a second transistor, and a back gate terminal shorted to the source terminal of the additional semiconductor oxide transistor.

[0092] According to another embodiment, the gate driver circuit includes a fourth transistor having a first source-drain terminal coupled to a node, a second source-drain terminal configured to receive a gate start signal or a gate output signal from an additional gate driver circuit, and a gate terminal configured to receive a clock signal, and a fifth transistor having a drain terminal coupled to the gate terminal of the second transistor, a source terminal coupled to a second power supply line, and a gate terminal coupled to a node.

[0093] According to the embodiment, a gate driver circuit is provided that includes a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a gate terminal coupled to a first node, and a source terminal coupled to a second power supply line different from the first power supply line; and a capacitor having a first terminal coupled to the first node and a second terminal coupled to the second power supply line.

[0094] According to another embodiment, the gate driver circuit includes a second semiconductor oxide transistor having a drain terminal coupled to a first node, a source terminal coupled to a first power supply line, a front gate terminal coupled to a second node, and a back gate terminal configured to receive a bias voltage, and a second silicon transistor having a drain terminal coupled to a first node, a source terminal coupled to a second power supply line, and a gate terminal coupled to a second node.

[0095] According to another embodiment, the gate driver circuit includes a third silicon transistor having a first source-drain terminal coupled to a second node, a gate terminal configured to receive a clock signal, and a second source-drain terminal configured to receive a gate start signal or a gate output signal from an additional gate driver circuit, and a third semiconductor oxide transistor having a first source-drain terminal coupled to a second node, a second source-drain terminal coupled to the second source-drain terminal of the third silicon transistor, a front gate terminal configured to receive an inverted version of the clock signal, and a back gate terminal configured to receive a bias voltage.

[0096] According to the embodiment, a gate driver circuit is provided that includes a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of the gate driver circuit, a front gate terminal, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a source terminal coupled to a second power supply line different from the first power supply line, and a gate terminal; an inverter having an output coupled to the gate terminal of the first silicon transistor; and a capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to the second power supply line.

[0097] According to another embodiment, the inverter includes a second semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output of the inverter, a front gate terminal coupled to the input of the inverter, and a back gate terminal configured to receive a bias voltage, and a second silicon transistor having a source terminal coupled to a second power supply line, a drain terminal coupled to the output of the inverter, and a gate terminal coupled to the input of the inverter.

[0098] According to another embodiment, the gate driver circuit includes a third silicon transistor having a first source-drain terminal coupled to the input of an inverter, a second source-drain terminal configured to receive a gate start signal or a gate output signal from an additional gate driver circuit, and a gate terminal configured to receive a clock signal; and a third semiconductor oxide transistor having a first source-drain terminal coupled to the input of an inverter, a second source-drain terminal coupled to the second source-drain terminal of the third silicon transistor, a front gate terminal configured to receive an inverted version of the clock signal, and a back gate terminal configured to receive a bias voltage.

[0099] According to another embodiment, the gate driver circuit includes an additional inverter having an input coupled to the input of the inverter and an output coupled to the gate terminal of the first semiconductor oxide transistor.

[0100] According to one embodiment, a gate driver circuit is provided that includes a first semiconductor oxide transistor having a source terminal coupled to a first power supply line, a drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal configured to receive a bias voltage; a first silicon transistor having a drain terminal coupled to the output port, a gate terminal coupled to a first node, and a source terminal coupled to a second power supply line different from the first power supply line; and a logic subcircuit configured to generate a carry signal on the first node which is transmitted to an additional gate driver circuit.

[0101] According to another embodiment, the logic subcircuit includes a second silicon transistor having a first source-drain terminal coupled to a first node, a second source-drain terminal configured to receive a first clock signal, and a gate terminal coupled to the second node; a first capacitor coupled between the first node and the second node; a third silicon transistor having a drain terminal coupled to the first node, a source terminal coupled to a second power supply line different from the first power supply line, and a gate terminal coupled to a third node; and a second capacitor coupled between the third node and the second power supply line.

[0102] According to another embodiment, the logic subcircuit includes a fourth silicon transistor having a first source-drain terminal coupled to a second node, a gate terminal coupled to a first power supply line, and a second source-drain terminal coupled to a fourth node; a fifth silicon transistor having a first source-drain terminal coupled to the fourth node, a second source-drain terminal configured to receive a carry signal from another gate driver circuit in the previous row, and a gate terminal configured to receive a second clock signal different from a first clock signal; and a sixth silicon transistor coupled in series with the fifth silicon transistor, having a gate terminal configured to receive a first clock signal.

[0103] According to another embodiment, the logic subcircuit includes a seventh silicon transistor coupled in series with a sixth transistor and having a gate terminal coupled to a third node; an eighth silicon transistor having a first source-drain terminal coupled to the third node, a gate terminal coupled to a fourth node, and a second source-drain terminal configured to receive a second clock signal; and a ninth silicon transistor having a drain terminal coupled to the third node, a source terminal coupled to a first power supply line, and a gate terminal configured to receive a second clock signal.

[0104] According to one embodiment, a gate driver circuit is provided that includes a first semiconductor oxide transistor having a first source-drain terminal configured to receive a first clock signal, a second source-drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to a first node, and a back gate terminal; a first capacitor coupled between the first node and the output port; a second semiconductor oxide transistor having a drain terminal coupled to the output port, a source terminal coupled to a first power supply line, a front gate terminal coupled to a second node, and a back gate terminal; and a second capacitor coupled between the second node and the first power supply line.

[0105] According to another embodiment, the gate driver circuit includes a third semiconductor oxide transistor having a first source-drain terminal coupled to a first node, a second source-drain terminal coupled to a third node, a front gate terminal coupled to a second power supply line different from the first power supply line, and a back gate terminal, and a fourth semiconductor oxide transistor having a first source-drain terminal coupled to a third node, a second source-drain terminal configured to receive a gate output signal from an additional gate driver circuit, a front gate terminal configured to receive a second clock signal different from the first clock signal, and a back gate terminal.

[0106] According to another embodiment, the gate driver circuit includes a fifth semiconductor oxide transistor coupled in series with a fourth semiconductor oxide transistor, the fifth semiconductor oxide transistor having a front gate terminal configured to receive a first clock signal, and a sixth semiconductor oxide transistor coupled in series with the fifth semiconductor oxide transistor, the sixth semiconductor oxide transistor having a front gate terminal coupled to a second node.

[0107] According to another embodiment, the gate driver circuit includes a seventh semiconductor oxide transistor having a first source-drain terminal coupled to a second node, a second source-drain terminal configured to receive a second clock signal, a front gate terminal coupled to a fourth node, and a back gate terminal, and an eighth semiconductor oxide transistor having a source terminal coupled to a second node, a drain terminal coupled to a second power supply line, a front gate terminal configured to receive a second clock signal, and a back gate terminal.

[0108] The above is merely illustrative, and various modifications may be made to the described embodiments. The aforementioned embodiments may be implemented individually or in any combination.

Claims

1. A gate driver circuit, A first transistor having a drain terminal coupled to a first power supply line, a source terminal coupled to the output port of the gate driver circuit, and a gate terminal, wherein a gate output signal is generated at the output port and provided to a plurality of display pixels, A second transistor having a drain terminal connected to the output port, a source terminal connected to a second power supply line different from the first power supply line, and a gate terminal, A semiconductor oxide transistor having a source terminal coupled to the first power supply line or configured to receive a bias voltage, a drain terminal coupled to the gate terminal of the second transistor, a back gate terminal shorted to the source terminal of the semiconductor oxide transistor, and a front gate terminal, A gate driver circuit equipped with the following features.

2. A first capacitor having a first terminal connected to the gate terminal of the first transistor and a second terminal connected to the output port, A second capacitor having a first terminal connected to the gate terminal of the second transistor and a second terminal connected to the second power supply line, The gate driver circuit according to claim 1, further comprising the following:

3. The gate driver circuit according to claim 2, wherein the first transistor and the second transistor include p-type silicon transistors.

4. A third transistor having a first source-drain terminal coupled to the gate terminal of the first transistor, a gate terminal coupled to the first power supply line, and a second source-drain terminal coupled to a node, The gate driver circuit according to claim 2, further comprising the following:

5. The gate driver circuit according to claim 4, wherein the front gate terminal of the semiconductor oxide transistor is coupled to the node.

6. The gate driver circuit according to claim 4, wherein the front gate terminal of the semiconductor oxide transistor is coupled to the gate terminal of the first transistor.

7. An additional semiconductor oxide transistor having a source terminal coupled to the first power supply line, a drain terminal coupled to the output port, a front gate terminal coupled to the gate terminal of the second transistor, and a back gate terminal shorted to the source terminal of the additional semiconductor oxide transistor, The gate driver circuit according to claim 6, further comprising the following:

8. A fourth transistor having a first source-drain terminal connected to the node, a second source-drain terminal configured to receive a gate start signal or gate output signal from an additional gate driver circuit, and a gate terminal configured to receive a clock signal, A fifth transistor having a drain terminal connected to the gate terminal of the second transistor, a source terminal connected to the second power supply line, and a gate terminal connected to the node, The gate driver circuit according to claim 4, further comprising the above.

9. A gate driver circuit, A first semiconductor oxide transistor having a source terminal connected to a first power supply line, a drain terminal connected to the output port of the gate driver circuit, a front gate terminal connected to a first node, and a back gate terminal configured to receive a bias voltage, A first silicon transistor having a drain terminal connected to the output port, a gate terminal connected to the first node, and a source terminal connected to a second power supply line different from the first power supply line, A capacitor having a first terminal connected to the first node and a second terminal connected to the second power supply line, A gate driver circuit equipped with the following features.

10. A second semiconductor oxide transistor having a drain terminal connected to the first node, a source terminal connected to the first power supply line, a front gate terminal connected to the second node, and a back gate terminal configured to receive the bias voltage, A second silicon transistor having a drain terminal connected to the first node, a source terminal connected to the second power supply line, and a gate terminal connected to the second node, The gate driver circuit according to claim 9, further comprising the following:

11. A third silicon transistor having a first source-drain terminal connected to the second node, a gate terminal configured to receive a clock signal, and a second source-drain terminal configured to receive a gate start signal or a gate output signal from an additional gate driver circuit, A third semiconductor oxide transistor having a first source-drain terminal connected to the second node, a second source-drain terminal connected to the second source-drain terminal of the third silicon transistor, a front gate terminal configured to receive an inverted version of the clock signal, and a back gate terminal configured to receive the bias voltage, The gate driver circuit according to claim 10, further comprising the following:

12. A gate driver circuit, A first semiconductor oxide transistor having a source terminal connected to a first power supply line, a drain terminal connected to the output port of the gate driver circuit, a front gate terminal, and a back gate terminal configured to receive a bias voltage, A first silicon transistor having a drain terminal connected to the output port, a source terminal connected to a second power supply line different from the first power supply line, and a gate terminal, An inverter having an output coupled to the gate terminal of the first silicon transistor, A capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to the second power supply line, A gate driver circuit equipped with the following features.

13. The inverter, A second semiconductor oxide transistor having a source terminal connected to the first power supply line, a drain terminal connected to the output of the inverter, a front gate terminal connected to the input of the inverter, and a back gate terminal configured to receive the bias voltage, A second silicon transistor having a source terminal connected to the second power supply line, a drain terminal connected to the output of the inverter, and a gate terminal connected to the input of the inverter, The gate driver circuit according to claim 12, comprising:

14. A third silicon transistor having a first source-drain terminal coupled to the input of the inverter, a second source-drain terminal configured to receive a gate start signal or a gate output signal from an additional gate driver circuit, and a gate terminal configured to receive a clock signal, A third semiconductor oxide transistor having a first source-drain terminal coupled to the input of the inverter, a second source-drain terminal coupled to the second source-drain terminal of the third silicon transistor, a front gate terminal configured to receive an inverted version of the clock signal, and a back gate terminal configured to receive the bias voltage, The gate driver circuit according to claim 13, further comprising the following:

15. The gate driver circuit according to claim 14, further comprising an additional inverter having an input coupled to the input of the inverter and an output coupled to the gate terminal of the first semiconductor oxide transistor.

16. A gate driver circuit, A first semiconductor oxide transistor having a source terminal connected to a first power supply line, a drain terminal connected to the output port of the gate driver circuit, a front gate terminal connected to a first node, and a back gate terminal configured to receive a bias voltage, A first silicon transistor having a drain terminal connected to the output port, a gate terminal connected to the first node, and a source terminal connected to a second power supply line different from the first power supply line, A logic subcircuit configured to generate a carry signal on the first node which is transmitted to an additional gate driver circuit, A gate driver circuit equipped with the following features.

17. The aforementioned logic subcircuit A second silicon transistor having a first source-drain terminal connected to the first node, a second source-drain terminal configured to receive a first clock signal, and a gate terminal connected to the second node, A first capacitor coupled between the first node and the second node, A third silicon transistor having a drain terminal connected to the first node, a source terminal connected to a second power supply line different from the first power supply line, and a gate terminal connected to the third node, A second capacitor coupled between the third node and the second power supply line, The gate driver circuit according to claim 16, comprising:

18. The aforementioned logic subcircuit A fourth silicon transistor having a first source-drain terminal connected to the second node, a gate terminal connected to the first power supply line, and a second source-drain terminal connected to the fourth node, A fifth silicon transistor having a first source-drain terminal connected to the fourth node, a second source-drain terminal configured to receive a carry signal from another gate driver circuit in the previous row, and a gate terminal configured to receive a second clock signal different from the first clock signal, A sixth silicon transistor coupled in series with the fifth silicon transistor, the sixth silicon transistor having a gate terminal configured to receive the first clock signal, The gate driver circuit according to claim 17, further comprising:

19. The aforementioned logic subcircuit A seventh silicon transistor coupled in series with the sixth transistor, the seventh silicon transistor having a gate terminal coupled to the third node, An eighth silicon transistor having a first source-drain terminal connected to the third node, a gate terminal connected to the fourth node, and a second source-drain terminal configured to receive the second clock signal, A ninth silicon transistor having a drain terminal connected to the third node, a source terminal connected to the first power supply line, and a gate terminal configured to receive the second clock signal, The gate driver circuit according to claim 18, further comprising the following:

20. A gate driver circuit, A first semiconductor oxide transistor having a first source-drain terminal configured to receive a first clock signal, a second source-drain terminal coupled to the output port of the gate driver circuit, a front gate terminal coupled to the first node, and a back gate terminal, A first capacitor coupled between the first node and the output port, A second semiconductor oxide transistor having a drain terminal connected to the output port, a source terminal connected to the first power supply line, a front gate terminal connected to the second node, and a back gate terminal, A second capacitor coupled between the second node and the first power supply line, A gate driver circuit equipped with the following features.

21. A third semiconductor oxide transistor having a first source-drain terminal connected to the first node, a second source-drain terminal connected to the third node, a front gate terminal connected to a second power supply line different from the first power supply line, and a back gate terminal, A fourth semiconductor oxide transistor having a first source-drain terminal connected to the third node, a second source-drain terminal configured to receive a gate output signal from an additional gate driver circuit, a front gate terminal configured to receive a second clock signal different from the first clock signal, and a back gate terminal, The gate driver circuit according to claim 20, further comprising:

22. A fifth semiconductor oxide transistor coupled in series with the fourth semiconductor oxide transistor, the fifth semiconductor oxide transistor having a front gate terminal configured to receive the first clock signal, A sixth semiconductor oxide transistor coupled in series with the fifth semiconductor oxide transistor, the sixth semiconductor oxide transistor having a front gate terminal coupled to the second node, The gate driver circuit according to claim 21, further comprising the following:

23. A seventh semiconductor oxide transistor having a first source-drain terminal connected to the second node, a second source-drain terminal configured to receive the second clock signal, a front gate terminal connected to the fourth node, and a back gate terminal, An eighth semiconductor oxide transistor having a source terminal connected to the second node, a drain terminal connected to the second power supply line, a front gate terminal configured to receive the second clock signal, and a back gate terminal, The gate driver circuit according to claim 22, further comprising the following:

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