Array substrate, display panel, and display device

Abstract

This is an array substrate. The array substrate includes a base, a plurality of pixel circuits, a first wiring layer, a bridge wire layer, and a second wiring layer. The first wiring layer includes a first initialization signal line, a second initialization signal line, and a third initialization signal line. Each row of pixel circuits is electrically connected to one first initialization signal line, one second initialization signal line, and one third initialization signal line. The bridge wire layer includes a plurality of transfer blocks and a plurality of first fan-out lines. The second wiring layer includes a plurality of connection lines, a plurality of data lines, and a plurality of second fan-out lines. Each connection line is electrically connected to at least one of the plurality of first initialization signal lines, a plurality of second initialization signal lines, and a plurality of third initialization signal lines via a row of transfer blocks. Multiple data lines include multiple first data lines, each first data line is located in the display area, one end of a second fan-out line near the fan-out area extends into the fan-out area, and each first fan-out line is electrically connected to one first data line and one second fan-out line.

Claims

1. An array substrate having a display area and a fan-out area, wherein the fan-out area is adjacent to one side edge of the display area, and the array substrate is Bass and, A plurality of pixel circuits arranged on the base, wherein the plurality of pixel circuits are arranged in multiple rows and multiple columns, A first wiring layer located on the side of the plurality of pixel circuits away from the base, comprising a plurality of first initialization signal lines, a plurality of second initialization signal lines, and a plurality of third initialization signal lines extending along a first direction, wherein the first direction is the row direction in which the plurality of subpixels are arranged, and each row of pixel circuits comprises a first wiring layer electrically connected to one first initialization signal line, one second initialization signal line, and one third initialization signal line. A bridge wire layer disposed on the side of the first wiring layer away from the base, comprising a plurality of rows of transfer blocks and a plurality of first fan-out lines, each row of transfer blocks comprising a plurality of transfer blocks spaced apart along a second direction, the plurality of first fan-out lines extending along the first direction, the second direction being the row direction in which the plurality of pixel circuits are arranged, An array substrate comprising: a second wiring layer disposed on the side of the bridge wire layer away from the base, including a plurality of connection lines, a plurality of data lines, and a plurality of second fan-out lines extending along a second direction, each connection line being electrically connected to one of the plurality of first initialization signal lines, a plurality of second initialization signal lines, and a plurality of third initialization signal lines via a row of transfer blocks, each data line being electrically connected to a row of pixel circuits, the plurality of data lines including a plurality of first data lines, one end of the first data lines near the fan-out region located in the display region, one end of the second fan-out lines near the fan-out region extending to the fan-out region, and each first fan-out line having a second wiring layer electrically connected to one first data line and one second fan-out line.

2. The array substrate according to claim 1, wherein both ends of at least one of the transfer blocks along the first direction are electrically connected to the first initialization signal line, the second initialization signal line, or the third initialization signal line.

3. At least one of the transfer blocks is arranged symmetrically with respect to the connection lines electrically connected to the transfer block, and the transfer block is, A first sub-part, wherein the orthographic projection of the first sub-part on the base partially overlaps with the orthographic projection of the connecting line on the base, and the first sub-part is electrically connected to the connecting line. A second sub-part, the second sub-part extending along the first direction, connected to the first sub-part, and arranged symmetrically with respect to the center line of the first sub-part along the first direction, The array substrate according to claim 2, comprising a third sub-part connected to one end of the second sub-part away from the first sub-part, the size of the third sub-part being larger than the size of the second sub-part along the second direction, and the third sub-part being electrically connected to the first initialization signal line, the second initialization signal line, or the third initialization signal line.

4. The plurality of transfer blocks include a plurality of rows of first transfer blocks, a plurality of rows of second transfer blocks, and a plurality of rows of third transfer blocks, each row of first transfer blocks includes a plurality of first transfer blocks arranged at intervals along the second direction, and each row of the plurality of first transfer blocks is electrically connected to the plurality of first initialization signal lines, each row of second transfer blocks includes a plurality of second transfer blocks arranged at intervals along the second direction, each row of the plurality of second transfer blocks is electrically connected to the plurality of second initialization signal lines, each row of third transfer blocks includes a plurality of third transfer blocks arranged at intervals along the second direction, and each row of the plurality of third transfer blocks is electrically connected to the plurality of third initialization signal lines, The array substrate according to any one of claims 1 to 3, wherein the plurality of connection lines include a plurality of first connection lines, a plurality of second connection lines, and a plurality of third connection lines, one first connection line being electrically connected to a row of first transfer blocks, one second connection line being electrically connected to a row of second transfer blocks, and one third connection line being electrically connected to a row of third transfer blocks.

5. The array substrate according to claim 4, wherein, along the first direction, the size of the first transfer block is larger than the size of the second transfer block, and the size of the second transfer block is larger than the size of the third transfer block.

6. The array substrate according to claim 4 or 5, wherein the first transfer block, the second transfer block, and the third transfer block are periodically arranged along the first direction, and the first connection line, the second connection line, and the third connection line are periodically arranged.

7. A first source-drain conductive layer disposed between the first wiring layer and the bridge wire layer, further comprising a first source-drain conductive layer including a plurality of first connection patterns, a plurality of second connection patterns, and a plurality of third connection patterns, The first connection pattern includes a first subpattern and a second subpattern, the first subpattern being electrically connected to the first initialization signal line and the pixel circuit, respectively, and the second subpattern being electrically connected to the first transfer block. The second connection pattern includes a third subpattern and a fourth subpattern, the third subpattern being electrically connected to the second initialization signal line and the pixel circuit, respectively, and the fourth subpattern being electrically connected to the second transfer block. The array substrate according to any one of claims 4 to 6, wherein the third connection pattern includes a fifth subpattern and a sixth subpattern, the fifth subpattern being electrically connected to the third initialization signal line and the pixel circuit, respectively, and the sixth subpattern being electrically connected to the third transfer block.

8. The first source-drain conductive layer is A fourth connection pattern, wherein the shape and size of the fourth connection pattern are the same as the shape and size of the first sub-pattern, and the fourth connection pattern is electrically connected to the first initialization signal line and the pixel circuit, respectively. A fifth connection pattern, wherein the shape and size of the fifth connection pattern are the same as the shape and size of the third sub-pattern, and the fifth connection pattern is electrically connected to the second initialization signal line and the pixel circuit, respectively. The array substrate according to claim 7, further comprising a sixth connection pattern, the shape and size of which are the same as those of the fifth sub-pattern, and the sixth connection pattern being electrically connected to the third initialization signal line and the pixel circuit, respectively.

9. The second fan-out wire includes a first opening, the first opening divides the second fan-out wire to form a first wiring segment and a second wiring segment. One end of the first wiring segment extends to the fan-out region, and the other end extends to the first fan-out line and is electrically connected to the first fan-out line. The array substrate according to any one of claims 1 to 8, wherein the second wiring segment is located on the side of the first wiring segment away from the fan-out region and is electrically isolated from the first wiring segment.

10. The second fan-out line includes a plurality of first widening portions and a plurality of first extending portions arranged alternately along the second direction, and the first widening portions and the first fan-out line are arranged offset along the second direction. The array substrate according to claim 9, wherein the bridge wire layer further includes a first connection segment, one end of the first connection segment is connected to the first fan-out line, and the other end is electrically connected to the first widening portion of the first wiring segment that is closest to the first fan-out line.

11. The array substrate according to claim 10, wherein the connecting line includes a plurality of second widening portions and a plurality of second extending portions arranged alternately along the second direction, the size of the second widening portions is larger than the size of the second extending portions along the first direction, and the second widening portions are electrically connected to the transfer block.

12. The first fan-out line is, A second aperture, wherein the second aperture is located away from the first data line electrically connected to the first fan-out line of the first connection segment, and the orthographic projection of the base of the second aperture partially overlaps with the orthographic projection of the base of one data line. The array substrate according to claim 10 or 11, comprising a third aperture, the third aperture located on the side of a first data line electrically connected to the first fan-out line away from a second fan-out line electrically connected to the first fan-out line, and the orthographic projection of the third aperture at its base at least partially overlaps with the orthographic projection at its base of one connection line.

13. The aforementioned bridge wire layer is A receiving pattern comprising multiple rows, each row comprising multiple receiving patterns spaced apart along the second direction, each of the multiple receiving patterns in one row being electrically connected to a plurality of pixel circuits in one row, and each of the multiple receiving patterns in one row being further electrically connected to a single data line, The array substrate according to any one of claims 9 to 12, further comprising: a second connection segment, one end of which is electrically connected to the first fan-out line and the other end of which is electrically connected to a target receiving pattern, wherein the target receiving pattern is located on the side of the first fan-out line closer to the fan-out region and is the receiving pattern closest to the first fan-out line.

14. The array substrate according to claim 13, wherein the plurality of receiving patterns and the plurality of transfer blocks are offset from each other along the second direction, and at least one of the transfer blocks is located between the first fan-out line and the target receiving pattern.

15. The plurality of first data lines include at least one first sub-data line, and the orthographic projection of the first sub-data line on the base does not overlap with the orthographic projection of the transfer block on the base. The array substrate according to claim 13 or 14, wherein the orthographic projection of the base of the second connection segment connected to the first subdata line is located within the range of the orthographic projection of the base of the first subdata line.

16. The plurality of first data lines include at least one second sub-data line, and the orthographic projection of the second sub-data line on the base partially overlaps with the orthographic projection of a row of transfer blocks on the base. A row of transfer blocks electrically connected to the second sub-data line includes a target transfer block, the target transfer block is located on the side of the first fan-out line closer to the fan-out region and is closest to the first fan-out line, and the orthographic projection of the base of the target transfer block does not overlap with the orthographic projection of the base of the second sub-data line. The array substrate according to claim 13 or 14, wherein the second connection segment electrically connected to the second subdata line is a target connection segment, the orthographic projection of the target connection segment on the base is located within the range of the orthographic projection of the second subdata line on the base, the target connection segment extends along the second direction and is spaced apart from the target transfer block, and / or the target connection segment is a polyline, the orthographic projection of the target connection segment on the base does not at least partially overlap with the orthographic projection of the second subdata line on the base, and the target connection segment is spaced apart from the target transfer block.

17. The two adjacent rows of pixel circuits are arranged symmetrically. The aforementioned multiple data lines are divided into multiple groups, each group containing two data lines, with a first interval between the two data lines of one group, and a second interval between the data lines of two adjacent groups, the first interval being smaller than the second interval. The array substrate according to any one of claims 1 to 16, wherein each connecting line is located between the two data lines of a group, and the two data lines of a group are arranged symmetrically with respect to the connecting line, and each second fan-out line is located between the two data lines of a group, and the two data lines of a group are arranged symmetrically with respect to the second fan-out line.

18. The array substrate according to claim 17, wherein 1 to 10 connecting lines are included between two adjacent second fan-out lines.

19. Between two adjacent second fan-out lines, there is one first connection line, one second connection line, and one third connection line. Between the two adjacent second fan-out lines, the second connecting line, the third connecting line, and the first connecting line are arranged sequentially along the first direction and in the direction from one side edge to the other side edge of the display area, or Between the two adjacent second fan-out lines, the second connecting line, the first connecting line, and the third connecting line are arranged sequentially along the first direction and in the direction from one side edge to the other side edge of the display area, or Between the two adjacent second fan-out lines, the first connecting line, the second connecting line, and the third connecting line are arranged sequentially along the first direction and in the direction from one side edge to the other side edge of the display area, or Between the two adjacent second fan-out lines, the first connecting line, the third connecting line, and the second connecting line are arranged sequentially along the first direction and in the direction from one side edge to the other side edge of the display area, or Between the two adjacent second fan-out lines, the third connecting line, the second connecting line, and the first connecting line are arranged sequentially along the first direction and in the direction from one side edge to the other side edge of the display area, or The array substrate according to claim 17 or 18, wherein the third connection line, the first connection line, and the second connection line are sequentially arranged between the two adjacent second fan-out lines, along the first direction and in a direction from one side edge to the other side edge of the display area.

20. The second wiring layer further includes a plurality of first voltage signal lines spaced apart along the first direction, each first voltage signal line extending along the second direction, and two adjacent first voltage signal lines include a group of data lines. The bridge wire layer further includes a plurality of first voltage signal transfer lines spaced apart along the second direction, each first voltage signal line extending along the first direction and electrically connected to a row of pixel circuits. The array substrate according to any one of claims 17 to 19, wherein each first voltage signal line is electrically connected to the plurality of first voltage signal transfer lines.

21. An array substrate according to any one of claims 1 to 20, A display panel comprising a plurality of light-emitting devices, each of which is arranged on a side away from the base of the array substrate and each light-emitting device is electrically connected to a single pixel circuit.

22. A display panel according to claim 21, wherein the display panel includes an array substrate, A display device comprising: a drive circuit board electrically connected to the fan-out region of the array substrate and arranged to transmit control signals to the array substrate.

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