Controller for superconducting qubits

Abstract

A superconducting controller for a superconducting qubit that executes a high-fidelity quantum gate using magnetic flux drive. The controller includes the following components: an inductance configured to form an inductive loop and inductively couple with a qubit with a small mutual inductance; and a pulse shaping circuit configured to apply a current pulse of a predetermined shape to the inductance. The pulse shaping circuit includes: a superconducting circuit that outputs a single-flux quantum (SFQ) pulse; and a digital counter circuit that generates the shape of the current (magnetic flux) pulse applied to the inductor loop by increasing or decreasing the current flowing through the inductance by 1 SFQ pulse at a time.

Description

Detailed description of the invention

[0001] [Claim of priority and related priority applications] This patent document claims priority and benefits of U.S. Patent Application No. 18 / 197,033, “Controller for Superconducting Qubits,” filed on 12 May 2023.

[0002] [Technical Field] The embodiments described herein relate to quantum computing devices, systems, and controllers for superconducting qubits ("qubits").

[0003] 〔background〕 Quantum computing offers a new paradigm for computers. Classical computers hold and manipulate information in the form of bits, which are represented by two states: 0 or 1 (e.g., low signal or high signal). In quantum computing, instead of classical bits that clearly have one of two states, information is stored in quantum bit devices ("qubits"), and such qubits can be manipulated to form quantum superpositions of different quantum states (e.g., two quantum states).

[0004] [Brief explanation of the drawing] Figure 1A is a schematic diagram showing an example of a superconducting qubit.

[0005] Figure 1B is an energy diagram showing an example of a fractionium qubit.

[0006] Figure 2 is a diagram of the Bloch sphere.

[0007] Figure 3 shows an example of a fractionium qubit coupled to a controller.

[0008] Figure 4A shows an example of a single-flux quantum circuit (SFQ).

[0009] Figure 4B shows an example of an SFQ pulse.

[0010] Figure 5 is a diagram showing an example of a pulse shape that can be generated by a pulse shaping circuit according to an embodiment.

[0011] Figures 6A to 6E are schematic diagrams showing an example of a Bloch sphere representing the precession motion of the state after the pulse shown in Figure 5 is applied.

[0012] Figure 7A is a schematic diagram showing an example of a pulse shaping circuit that generates a trapezoidal pulse and is coupled to a qubit according to an embodiment.

[0013] Figure 7B is a schematic diagram showing an example of a pulse shaping circuit that generates a triangular pulse and is connected to a qubit according to an embodiment.

[0014] Figure 8A is a schematic diagram showing an example of a pulse counter used in the circuit of Figure 7A.

[0015] Figure 8B is a schematic diagram showing an example of a counter (without pulse output) used in the circuit of Figure 7A.

[0016] Figure 8C is a detailed schematic diagram of the pulse counter of Figure 8A.

[0017] Figure 8D is a schematic diagram showing an example of an NDRO switch.

[0018] Figure 8E is a schematic diagram showing an example of a parallel programmable counter.

[0019] Figure 8F is a schematic diagram showing an example of a serial programmable counter.

[0020] Figure 9 is a diagram showing an example of a double pulse shape that can be generated by a pulse shaping circuit according to an embodiment.

[0021] Figure 10 is a schematic diagram showing an example of a pulse shaping circuit connected to a qubit according to an embodiment for generating the double pulse shown in Figure 9.

[0022] Figure 11 shows a clock period of 47.5 ps, d f This is a plot of the gate error against the Josephson energy at =0.003.

[0023] Figure 12 is a plot of gate error against inter-pulse waiting time in a dual-pulse system.

[0024] Figure 13 is a plot of gate error against clock period.

[0025] Figure 14 is a graph of gate error with respect to mutual magnetic flux coupling.

[0026] Figure 15 shows the pulse shape obtained by changing a simple trapezoidal waveform, which can be generated by a pulse shaping circuit according to the embodiment.

[0027] Figure 16 shows the pulse shape of Figure 15, with parameter E L / h=0.7GHz, parameter E C / h=0.9GHz, parameter E J This is a plot of the gate error against the pulse integral under the conditions of / h = 5.82 GHz, trapezoidal interval 3 ns, and clock period 45 ps.

[0028] Figure 17 is a schematic diagram showing the control layer of a quantum computer.

[0029] Figure 18 is a schematic diagram showing an example of a cryostat and the location where the control layer in Figure 17 is positioned within the cryostat.

[0030] Figure 19 is a schematic diagram showing an example of a pulse shaping circuit connected to multiple qubits via a demultiplexer, according to one embodiment.

[0031] Figure 20 is a schematic diagram showing an example of a demultiplexer used in Figure 19.

[0032] Figure 21 is a schematic diagram showing an example of a pulse shaping circuit used in the circuit of Figure 19.

[0033] Figure 22 is a schematic diagram showing an example of a pulse shaping circuit configured to generate a double pulse coupled to multiple qubits via a demultiplexer, according to one embodiment.

[0034] Figure 23 is a schematic diagram showing an example of a demultiplexer used in Figure 22.

[0035] Figure 24 is a schematic diagram showing an example of a pulse counter circuit used in the circuit shown in Figure 22.

[0036] [Detailed explanation] Various architectures have been proposed for forming qubits for quantum computing. One of them is the superconducting circuit. Such superconducting qubits need to operate at sub-Kelvin temperatures, below the critical temperature of the superconducting transition. Controlling and reading out these qubits is difficult, and conventionally, this has been achieved by exciting the qubits using microwave pulses. However, this control method requires supplying microwave signals to the qubits inside the cryostat via high-quality coaxial cables. The wiring required to supply control signals from outside the cryostat to the internal qubits usually requires at least one or two connections per qubit. As a result, the number of coaxial cables and associated connectors, filters, and attenuators required is proportional to the number of qubits. This makes system expansion difficult due to space and reliability constraints, as well as increased thermal load on the cryostat due to microwave power loss and heat flow through the cables.

[0037] In one embodiment of this technology, a controller for superconducting qubits is provided. This controller includes the following:

[0038] An inductance that forms an inductor loop and is configured to inductively couple with a qubit with a small mutual inductance.

[0039] A pulse shaping circuit configured to apply a current pulse having a predetermined shape to an inductance. This pulse shaping circuit includes the following:

[0040] A superconducting circuit configured to output multiple SFQ (Single Flux Quanta) pulses, and a counter circuit that controls the number of SFQ pulses applied to an inductance, thereby increasing or decreasing the current flowing through the inductance by the amount of each SFQ pulse, and generating the shape of the current pulse.

[0041] The control device described above is based on a single-flux quantum (SFQ) circuit that can be installed in a dilution refrigerator or cryostat and positioned near the qubit. The qubit and control device may be installed together in a low-temperature measurement system below the superconducting transition temperature.

[0042] In the above embodiment, the pulse shaping circuit is configured to apply a current (magnetic flux) pulse. The SFQ pulse output by the SFQ circuit is low power and can be driven at high clock frequencies of 25-30 GHz or higher. These are classic superconducting circuits.

[0043] The controller described above changes the frequency of the quantum state precession by altering the current flowing through the inductance, thereby inductively coupling with the qubit. The inductance may take the form of an inductor loop configured to inductively couple with the qubit. Precise control of the current flowing through the inductance is possible by increasing or decreasing the magnetic flux within the superconducting loop using SFQ pulses. The magnetic flux passing through the conductive loop is directly proportional to the current flowing through the loop.

[0044] In one embodiment, the counter circuit is configured to generate the shape of current pulses (or equivalent magnetic flux pulses) flowing through the superconducting loop by applying a counted number of SFQ pulses from one side (positive SFQ pulses that increase the magnetic flux in the loop) or the other side (negative SFQ pulses that decrease the magnetic flux in the loop), or by setting a set time (plateau) between increases and decreases in magnetic flux. The counter circuit can also set a delay between sequentially generated current (magnetic flux) pulses.

[0045] This allows for the application of trapezoidal-shaped pulses. Therefore, the counter circuit is configured to generate current pulses with a shape consisting of a rising edge where positive SFQ pulses are applied in stages, a plateau region where the current flowing through the inductance is fixed (no positive or negative SFQ pulses are applied), and a falling edge where negative SFQ pulses are applied in stages to reduce the current induced in the inductance. The pulse shape can be further modified, for example, by providing multiple plateau regions, rising edges, and falling edges.

[0046] In one embodiment, the superconducting circuit includes a JJ (Josephson Junction) and is configured to output an SFQ pulse, which is a voltage pulse with a quantized area due to a 2π phase slip across the JJ. The superconducting circuit may be at least one of the following types: rapid single-flux quantum "RSFQ", ERSFQ, eSFQ, RQL, xSFQ, xeSFQ, DSFQ, bSFQ, PCL and their variations, as well as circuits based on quantum flux parametron "QFP", such as AQFP, QFP, PQ and their variations.

[0047] In one embodiment, the counting circuit includes a first counter configured to count and limit the number of positive SFQ pulses and a second counter configured to count and limit the number of negative SFQ pulses. The first and second counters may each include a register. The register may include a plurality of superconducting TFFs (T Flip Flops).

[0048] Furthermore, a third counter can be provided, which is configured to control the time interval during which no pulse is applied to the coupled inductance.

[0049] Each register is configured to output a carry signal when its limit is reached, and the controller is configured so that the first, second, and third counters are ordered, and the carry signal is sent to the next counter in the sequence, and the next counter in the sequence is started.

[0050] The controller is configured to generate pulse shapes with repeating structures and further includes a fourth counter configured to control the time between structures in the repeating pulse shapes. The structures are trapezoids or their variations, such as triangles, or trapezoidal shapes including one or more additional trapezoids (e.g., multiple trapezoids overlapping each other), and the structures may or may not be symmetrical.

[0051] In another embodiment, the controller is adapted to control multiple qubits via a demultiplexer (demux). For example, multiple inductances are provided and configured such that each of the multiple inductances is coupled to the corresponding qubit.

[0052] Each inductor is provided with a positive input and a negative input. The positive input increases the magnetic flux of that inductor, and the negative input decreases it. A demultiplexer is connected to the positive and negative inputs of each inductor.

[0053] The demultiplexer receives a pulse train and a selection signal and is configured to control whether the pulse train is sent to the positive or negative input of each inductance. This configuration, in which the demultiplexer controls the output to both positive and negative inputs, allows for pulse output to both positive and negative inputs with a single pulse counter. The polarity of the pulses to the inductances controlled by the demultiplexer is determined.

[0054] A programmable counter that can be reprogrammed to different pulse counts can be used to adjust the pulse shape parameters (including durations such as rising edge, falling edge, plateau time, and waiting time) for a specific selected qubit. The demultiplexer designs shown in Figures 20 and 23 can also be programmed to select multiple qubits simultaneously. In this case, the selected qubits are controlled by pulse shapes with the same parameters.

[0055] The demultiplexer consists of a shift register, and the selection signal is supplied sequentially along the shift register. This type of configuration makes it possible to employ SFQ or QFP type superconducting logic in the demultiplexer.

[0056] A shift register may be constructed by sequentially arranging NDRO (Non-Destructive Read-Out) elements, connecting each NDRO to either a positive or negative input. When more complex pulse shapes are required, the shift register configuration of a demultiplexer may be limited because a pattern applied to one pair of NDROs may be shifted to the next pair of NDROs, potentially controlling a different qubit for which that pattern is unsuitable. Therefore, in one embodiment, the shift register further includes dummy components between the NDROs. This holds the selection signal before it is sequentially passed to the next NDRO.

[0057] In one embodiment, the controller of claim 9 further includes two counters in the counting circuit.

[0058] In one embodiment, the pulse shape is configured to allow a qubit inductively coupled to a controller to perform a qubit operation.

[0059] In one embodiment, the controller is configured to control at least one of the following parameters: Plateau size, Size of the rising edge, Size of the falling edge, Delay between sequentially generated magnetic flux pulses, Delay before the start of the first magnetic flux pulse.

[0060] During use, the controller is inductively coupled to the qubit. In one embodiment, the qubit is a flux-type qubit with inductance. For example, the qubit may be a fractional qubit.

[0061] However, it should be noted that magnetic flux bias control is also applicable to qubits where an inductor is not explicitly present. For example, charge qubits such as transmons can be magnetically connected and driven using circuits called SQUID (superconducting quantum interference device) loops or split Josephson junctions.

[0062] A quantum computer is composed of qubits. Unlike classical bits, qubits hold a quantum superposition state of a first logical state (0) and a second logical state (1). A qubit can be visualized as having two quantum energy levels, as shown in Equation 1 below.

number

[0063] Figure 1A shows a schematic diagram of a fractionium qubit. Other types of qubits are also available. However, as the first example, we will discuss the fractionium qubit. A fractionium qubit consists of a Josephson junction (JJ) 1, a capacitor 3, and an inductor 5, all arranged in parallel. E(J) represents the strength of the coupling in the Josephson junction. Ec is the energy required to increase the charge of the capacitor by e, where e is the single-electron charge. E(L) is the induced energy of the qubit.

[0064] A JJ consists of a tunnel barrier between two superconductors. A fractionium qubit is a type of so-called flux qubit, where the two energy levels forming the qubit are a superposition of two energy states corresponding to, for example, a reverse current flowing through a Josephson junction 1. In this example, inductance is shown as an inductor. However, inductance may also be provided by a JJ.

[0065] The arrangement of the fractionium qubits yields the energy diagram shown in Figure 1B. The two lowest levels in this energy diagram are selected as the two levels of the qubit.

[0066] To visualize the two states and their transitions, the Bloch sphere shown in Figure 2 is ideal. Here, the ground state is shown in Equation 2, and the excited state (pure state) is shown in Equation 3. The quantum state of a qubit is represented by the position of a vector on the Bloch sphere. If the vector is not located at either of the perpendicular poles, it represents a superposition of states. The central plane (equator) of the sphere represents a superposition where Equation 4 below is equal.

number

number

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[0067] To switch a qubit from an (intrinsic) energy state to a superposition of states, energy is supplied to the qubit to trigger a transition between the ground state and an excited state. In the schematic example shown in Figure 3, this is achieved using a control circuit 11 that inductively couples with the qubit. The control circuit 11 induces a current in its inductor 13, which in turn induces a magnetic flux in the qubit. In order to correctly excite the superposition state, the current flowing through the inductor of the control circuit must be carefully varied over time. In other words, it must have a precise value at a specific time.

[0068] To realize this control, in one embodiment, the control circuit 11 includes a single-flux quantum (SFQ) circuit. FIG. 4A is a schematic diagram of a single-flux quantum circuit (SFQ) 101. A simple form of the SFQ circuit is a loop of superconducting wire having a Josephson junction 103 capable of holding (accumulating) a single magnetic flux quantum φ0. Here, φ0 = h / 2e. h is Planck's constant and e is the elementary charge. The elementary charge refers to the charge carried by a single electron (1.6×10 -19 C). The Josephson junction enables the insertion or release of a single magnetic flux quantum (SFQ) from this loop. A pair of serially connected Josephson junctions (J2, J3) conditionally releases the SFQ accumulated in the loop upon arrival of a clock / reset SFQ. The release of SFQ from the loop generates an output SFQ pulse. The SFQ pulse generated in this way has a fixed area under its curve 、 which corresponds to the magnetic flux quantum φ0.

[0069] The use of an SFQ circuit for applying magnetic flux to a qubit has two major advantages as follows. 1) The energy supplied to the qubit can be very precisely controlled by the quantized single magnetic flux quantum pulse. 2) The SFQ circuit can be installed in a dilution refrigerator or a cryostat and placed close to the qubit, minimizing the number of connections to room-temperature electronics and reducing the delay of control signals.

[0070] The SFQ circuit can be configured to generate a magnetic flux pulse profile by accumulating an increment of magnetic flux φ0 in a superconducting induction loop with an SFQ pulse and change the state of the qubit.

[0071] FIG. 4B shows an SFQ pulse versus time. The SFQ pulse has a constant area. The SFQ pulse width is t SFQ ~2τ_ SFQ ~2φ0 / I c R. In the case of an Nb junction, the limit t SFQ →0.4 ps. In a complex RSFQ circuit, a practical fclock ~1 / (10t SFQ ) is the SFQ pulse energy ~3 / 4φ0I c ~2×10 -19 Joule (I c ~100μA (when operating at 4K) or 2×10 -20 Joule (I c (~10μA, millikelvin operation). The maximum clock frequency of integrated circuits (ICs) can reach several hundred GHz at low power.

[0072] Figure 5 shows a trapezoidal magnetic flux distribution. This shape is formed by the summation control of single magnetic flux quantities. The vertical axis Y represents the number of positive single magnetic flux quantities applied to the inductor L of the control circuit 11. The horizontal axis X is an arbitrary time unit corresponding to the internal clock period of the controller. As time progresses, the magnetic flux quantum number increases by 1 per time unit, reaching 16 in this example. This value remains constant for a while, after which the magnetic flux quantum number decreases by 1 quantum until it reaches 0.

[0073] Figures 6A to 6E show how the state transitions caused by the current profile in Figure 5 proceed relative to the Bloch sphere.

[0074] In Figure 6A, the pure form in which the state points towards the bottom of the sphere is shown by Equation 5 below. First, a single flux quantum (1 quantum) is applied to the inductor to supply energy to the qubit in order to initiate the state transition. The arrow representing the state moves away from the pure state shown by Equation 5 below and towards the equator, as shown in Figure 6B. The state continues to move even if the value of the flux quantum applied to the inductor remains constant. However, by increasing the flux quantum, the state transition accelerates toward its maximum speed. Figure 6C represents the midpoint of the entire state transition. The state transition is maintained at its maximum speed (the base of the trapezoid in Figure 5) until the state begins to approach its intended final position. At this point, the amount of flux applied to the inductor 13 decreases by one, and the state transition decelerates as shown in Figure 6D. Finally, it reaches a state aligned along the y-axis on the central plane of the sphere, as shown in Figure 6E.

number

[0075] The qubit control using the system described above provides excellent fidelity. High fidelity means that the evolutionary control of the qubit is extremely precise, resulting in low errors during quantum gate execution and high reproducibility.

[0076] Figure 7A is a schematic diagram of the controller 201 that can be used to generate the magnetic flux distribution shown in Figure 5. The controller 201 is used to control the qubit 203. The qubit 203 is inductively coupled, and is, for example, a fractionium qubit as described in Figures 1A and 1B.

[0077] The controller 201 includes an inductor 205 used to inductively couple to the inductance of the qubit 203. It should be noted that the qubit 203 shown in Figure 7A has an inductor. However, a qubit can have inductance even without a specific inductor component. In particular, the qubit may be constructed using a SQUID (also called a split junction) and inductively coupled to magnetic flux from the controller. Therefore, inductive coupling can still occur.

[0078] Some of the components of the circuit shown in Figure 7A will be explained in more detail with reference to Figure 8. However, broadly speaking, this circuit consists of a first pulse counter (nPC1) 209 and a second pulse counter (nPC2) 213. The first pulse counter (nPC1) 209 outputs a positive SFQ pulse 211. The second pulse counter (nPC2) 213 outputs a negative SFQ pulse 215. SFQ pulses are considered positive and negative. However, these terms are simply used to describe pulses that increase or decrease the magnetic flux in the inductor loop 205. The first pulse counter 209 outputs pulses to the inductor 205 to increase the magnetic flux in the loop. The pulses are increased by the first pulse counter 209, increasing one pulse at a time. In other words, by accumulating one φ0 at a time, the trapezoidal rising slope shown in Figure 5 is formed.

[0079] When the first pulse counter 209 reaches a set value, it stops outputting the positive SFQ pulse 211, and the magnetic flux in the inductor loop 205 is maintained at a constant level. This corresponds to the upper end of the trapezoid in Figure 5. Also, when the first pulse counter reaches a set value, a carry signal is output. The carry signal is sent to the second time delay circuit 219. After the second time delay circuit 219 measures a predetermined time, the carry signal is output from the second time delay circuit 219 to the second pulse counter 213, and the second pulse counter 213 is activated. After activation, the second pulse counter measures and outputs an SFQ pulse with the opposite polarity to the pulse from the first pulse counter 209. These multiple pulses of opposite polarity attenuate the magnetic flux in the inductor loop 205, causing a decrease in magnetic flux. This gradual decrease in magnetic flux corresponds to the lower slope in Figure 5. Therefore, by using the first pulse counter 209 and the second pulse counter 213, the magnetic flux profile shown in Figure 5 can be realized.

[0080] As shown in Figure 7A, there are two more components. These are the first time delay circuit 217 and the second time delay circuit 219. The first time delay circuit 217, the second time delay circuit 219, the first pulse counter 209, and the second pulse counter 213 are all counters. Each receives the clock signal 221. The first time delay circuit 217 sets the time before the start of the trapezoidal wave. The second time delay circuit 219 sets the plateau of the trapezoidal wave. All of the counters described can be implemented with a fixed number of bits, and can also be made programmable using the programmable counter designs shown in Figures 8E and 8F. The internal configurations of the first time delay circuit 217, the second time delay circuit 219, the first pulse counter 209, and the second pulse counter 213 are very similar.

[0081] Figure 7B shows a modified pulse shaping circuit for generating a triangular waveform, i.e., a pulse with zero plateau duration. Here, the second time delay 219 is unnecessary.

[0082] Figure 8A schematically shows the arrangement of the first and second pulse counters, and Figure 8B schematically shows the arrangement of the first and second time delays. The internal configurations of both are identical, but Figure 8B outputs only the carry and not the pulse.

[0083] The internal configuration details are shown in Figure 8C. The clock input is generated from an external input (e.g., a sine wave or other periodic waveform). This input is converted into an SFQ pulse using a standard DC / SFQ converter, and the input periodic waveform is converted into a sequence of clock SFQ pulses. Examples of possible DC / SFQ converters can be found in VK Kaplunenko, MI Khabipov, VP Koshelets, KK Likharev, OA Mukhanov, VK Semenov, IL Serpuchenko, and AN Vystavkin, "Experimental Study of the RSFQ Logic Elements," IEEE Trans. Magn., vol. 25, no. 2, pp. 861-864, Mar. 1989 and SV Polonsky, VK Semenov, P. Bunyk, AF Kirichenko, A. Kidiyarova-Shevchenko, OA Mukhanov, P. Shevchenko, D. Schneider, DY Zinoviev, and KK Likharev, "New RSFQ Circuits," IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 2566-2577, Mar. It is listed in 1993.

[0084] Here, a counter 251 is provided that passes the SFQ pulse clock input to the output while the non-destructive readout (NDRO) switch 253 is ON. An example of a possible NDRO switch is described in OA Mukhanov, SV Rylov, VK Semenov, and SV Vyshenskii, "RSFQ Logic Arithmetic," IEEE Trans. Magn., vol. MAG-25, no. 2, pp. 857-860, Mar. 1989.

[0085] The counter output turns off the NDRO switch 253. This generates the number of output pulses set by counter 251. The counter is fixed (2 n It can be either a count of individual clock pulses or a programmable system (counting a preset number of clock pulses).

[0086] Figure 8D shows a schematic diagram of an NDRO switch. The NDRO switch transmits a signal from the input to the output depending on whether the switch is "on" or "off". This "on" or "off" state is controlled by at least one additional input.

[0087] Two possible embodiments of the programmable counter are shown in detail in Figures 8E and 8F. In Figure 8E, T flip-flops (TFFs) (VK Kaplunenko, MI Khabipov, VP Koshelets, KK Likharev, OA Mukhanov, VK Semenov, IL Serpuchenko, and AN Vystavkin, "Experimental Study of the RSFQ Logic Elements," IEEE Trans. Magn., vol. 25, no. 2, pp. 861-864, Mar. 1989 and SV Polonsky, VK Semenov, P. Bunyk, AF Kirichenko, A. Kidiyarova-Shevchenko, OA Mukhanov, P. Shevchenko, D. Schneider, DY Zinoviev, and KK Likharev, "New RSFQ Circuits," IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 2566-2577, The TFFs (Mar. 1993) are connected in series and connected to a serial-to-parallel conversion programming interface. The TFFs are RSFQ toggle flip-flops (TFFs) used to generate an SFQ pulse that is output every second of each incoming SFQ pulse. The TFFs connected in series form a fixed counter and output a carry with a fixed time delay at the first and second delay times. This carry serves as a start input to pulse counters 209 and 213. In Figure 8F, programming is achieved by directly applying the SFQ pulse to the input of the first TFF before the start input is applied. In both embodiments, the applied data sets the offset content of the counter and limits the number of count pulses after the start SFQ signal is applied. For example, a 7-bit counter is typically 2 7= 128 clock pulses are counted. If the programming offset data is 18, the programmed counter will only count 128 - 18 = 110 clock pulses.

[0088] The above explanation discussed a simple case involving a single trapezoidal pattern. However, it is also possible to use two or more trapezoids or other shapes, which can be constructed by increasing or decreasing the magnetic flux using SFQ pulses. Further examples of magnetic flux profiles are shown in Figure 9. Here, the profile is a double trapezoid, but it is also possible to use three or more trapezoids.

[0089] Figure 10 shows a circuit that can be used to generate a double triangle / trapezoid structure. Similar to Figure 7A, this system is supplied with positive pulses from the positive output / positive input 211 to the inductor loop 205 and negative pulses from the negative output / negative input 215 to the inductor loop 205.

[0090] The circuit in Figure 10 includes a first pulse counter nPCt1401. Its output is directly connected to the positive pulse output 211. The first pulse counter 401 is of the type described in Figures 8A and 8C and can output both SFQ pulses and a carry signal. When the first pulse counter 401 reaches a set number of pulses (first threshold), it outputs a carry signal. This carry signal is sent to the second counter t2403. The second counter 403 is of the type described in Figure 8B and cannot output an SFQ pulse train, only a carry signal. The carry signal is output once when the second counter 403 reaches the second threshold. This carry signal is input to the third pulse counter nPCt3405, which applies a pulse in the opposite direction to the output pulse of the first pulse counter 401 to the inductor loop 205. Therefore, the pulse output by the third pulse counter 405 plays a role in reducing the magnetic flux applied to the inductor loop 205. The third pulse counter 405 is of the type described with reference to Figures 8A and 8C.

[0091] When the third pulse counter 405 reaches its threshold (third threshold), it outputs a carry signal, which is sent to the fourth counter t4407. The fourth counter 407 is of the same type as described in Figure 8B, and can output a carry signal but does not output pulses. The fourth counter 407 is used to separate the two trapezoids of the double trapezoid. When the fourth counter reaches its count threshold (fourth threshold), it outputs a carry signal, which passes through the first TFF 409. The first TFF 409 passes the start signal to the first counter 401.

[0092] After this, the process is repeated in the first counter. When the first threshold is reached, a carry output is generated, and the second counter 403 is started. When the second counter 403 reaches its threshold, it outputs a carry, and this output carry starts the third counter 405. The third counter 405 sets a negative ramp. At this stage, the process can be stopped or the second trapezoid group can be restarted.

[0093] The following diagram analyzes the performance of a single-qubit gate for fractionium using a triangular pulse (zero-duration trapezoid). This gate is realized by separating two identical trapezoidal pulses of the type shown in Figure 9 with a varying time delay and applying fast detuning to the magnetic flux passing through the superinductive loop (qubit).

[0094] Each pulse has a magnetic flux increase of δφ = d f It is constructed in a stepped manner with φ0. Here, d f is a parameter that models the magnetic flux coupling between the controller and the qubit, and φ0 = h / 2e is the magnetic flux quantum. The interval between the flux increments is determined by an external clock δt = dt with a period. Then n flat The clock cycle waits. After that, the pulse continues as a mirror image of the first half. Then n flat After the idle period, the magnetic flux decreases by units of δφ.

[0095] Figures 11 to 14 show a series of results for a Yπ / 2 (Y90 degree) gate using the type of double trapezoidal pulse described in Figure 9. The following fractionium parameters are used in Figures 11 to 14 (unless otherwise indicated as variables in the figures). E L / h=1.0GHz, E C / h=1.2GHz, E J / h=5.6GHz, (h is Planck's constant).

[0096] The parameters mentioned above are also used to create the fractionium energy diagram in Figure 1B.

[0097] In both cases, the triangular wave has 16 pulses vertically. The clock period of a double triangular wave pulse is 0.046 ns, and is variable for a single triangular wave pulse. The triangular wave pulse is a trapezoidal wave with a zero plateau duration.

[0098] Figure 11 shows the Josephson energy E J The plot of gate error for is shown. 10 -4 from 10 -6 It can be seen that gate errors approaching this level are achievable.

[0099] Figure 12 plots the gate error against the waiting time (in nanoseconds). The waiting time refers to the interval between the two triangular waves.

[0100] Figure 13 plots the gate error against the clock period (other parameters are the same as in Figure 11). Figure 14 plots the fidelity against the magnetic flux coupling (other parameters are the same as in Figure 11). Magnetic flux coupling refers to the magnetic flux ratio per SFQ.

[0101] Above, we discussed magnetic flux profiles with one or two trapezoidal shapes. However, other magnetic flux profile shapes are also possible. As explained in Figures 6A to 6E, the magnetic flux alters the precessional velocity of the states on the Bloch sphere. Therefore, other shapes can be employed that cause the precessional velocity of the states at various speeds. This increases the degrees of freedom for quantum gate optimization. N This is discrete optimization for the configuration.

[0102] Figure 15 is a variation of the trapezoid in Figure 5, forming a triangle with multiple plateau sections. In Figure 15, the magnetic flux profile is symmetrical, but it does not necessarily have to be symmetrical.

[0103] Figure 16 shows a plot of gate error and pulse integral at a waiting time of 3.0 and a pulse time difference of 0.045.

[0104] The above illustrates how variations in several parameters of fractionium affect gate fidelity. In one embodiment, gate fidelity is increased to 10 over a wide range of parameters that are difficult to achieve accurately due to manufacturing variations. -3 The objective is to keep the following parameters in check. Among these parameters, the Josephson energy E of fractionium is J Therefore, the flux coupling (defining δφ) between the classical loop and the flux superinductor loop is important. These plots show that these parameters do not need to be precise in order to achieve acceptable fidelity.

[0105] As mentioned above, even more diverse shapes are possible. In one embodiment, a trapezoidal pulse is used as the basic shape, with additional increases added at the vertices of the trapezoid. This allows for the exploration of a wide range of shapes, from a triangle (without trapezoidal sections) to the original trapezoid (without additional pulses). In the example in Figure 7A, a basic trapezoid is constructed using eight consecutive up and down pulses with a vertex length of 16. The 16 clock pulses are divided into eight for increasing magnetic flux and the remaining eight symmetrically for decreasing magnetic flux. 8 This results in 256 possible combinations. The combination that provides the highest fidelity is selected.

[0106] In the above, fidelity is shown as a function of the flux integral of the sequence. While this integral does not define gate fidelity, based on these plots, it can be concluded that the integral is a useful estimate in the initial selection of a good sequence.

[0107] As mentioned above, this control device is configured to inductively couple with the qubit. While the above description uses a fractionium qubit as an example, other types of qubits with inductance can also be used. The inductance may be provided by a dedicated inductor integrated into the qubit, or it may be inherent to the qubit itself.

[0108] For use in a quantum computer, multiple qubits are arranged in the qubit array 301 shown in Figure 17. Control of the qubits is performed via a digital qubit manager (DQM) 303. The DQM is configured to read out, control, and perform some data processing on the qubits. In one embodiment, the above controller is located within the DQM 303. A controller is provided for each qubit in the qubit array 301.

[0109] In one embodiment, in addition to the DQM303 and the qubit array 301, a high-speed digital SFQ controller and a quantum error correction controller 305 are provided to communicate with the DQM303. These functions to control the DQM303 and provide classical co-processing and quantum error correction.

[0110] In one embodiment, an interface 307 is provided which is a coprocessor 307 with a high-speed digital SFQ coprocessor and cryo-CMOS memory. This provides classical coprocessing, large-capacity memory, and an interface with an external computer or network.

[0111] In one embodiment, the four layers, the qubit array 301, the DQM 303, the DQM control and error correction controller 305, and the interface 307 are housed in a low-temperature environment such as a cryostat or dilution refrigerator. A schematic example of such a configuration is shown in Figure 18. Here, the cryostat has multiple chambers, which are maintained at different temperatures. The innermost chamber 351 is maintained at the lowest temperature. This innermost chamber 351 is used to house the qubit array 301 and the DQM 303. In one embodiment, the innermost chamber 351 is maintained at the lowest temperature. In current technology, this is about 20 mK. An intermediate chamber 353 can be used to house the DQM control and error correction controller 305, which does not need to be kept at as low a temperature as the qubit array 301 and the DQM 303. The intermediate chamber 353 is kept at a temperature of about 600 mK. The interface 307 is located in the outer chamber 355 and is kept at about 3 K.

[0112] Figure 19 is a schematic diagram illustrating the demultiplexer control of the fractionium qubit chip 501. In this specific example, four qubits (503a-503d) are shown. However, any number of qubits can be used. In the same manner as previously described in Figure 7A, each qubit 503a-503d is controlled by receiving SFQ pulses applied from either the first side 507a (positive input) or the second side 507b (negative input) across the inductor 511a inductively coupled to the qubit. The pulse applied from the first side (positive input) is a positive pulse that increases the magnetic flux in the loop, and the pulse applied from the second side (negative input) is a negative pulse that decreases the magnetic flux in the loop. The positive pulse generates the rising edge of the current pulse shape (e.g., trapezoidal wave), and the negative pulse generates the falling edge of the current pulse shape.

[0113] The positive input 507a and the negative input 507b are connected to the demultiplexer unit 505. The demultiplexer unit 505 is a digital unit that receives an input pulse train 513 from the generator 509, a demultiplexer load clock signal 517 or a set of signals from the generator 509, and a qubit selection signal 515.

[0114] This selection signal can be thought of as a gate signal that instructs each of the four qubits 503a-503d whether to leave the positive input 507a or the negative input 507b open (set to 1). It can be thought of as providing a gate signal for each qubit 503a-503d that indicates whether to close the positive input 507a or the negative input (set to 0). Each qubit has its own positive and negative inputs.

[0115] For example, in the diagram, the selection signal for the first clock period is set to "10 00 00 00", which indicates that the positive input of qubit 503d is open. In the second clock period shown in the diagram, the selection signal is set to "01 00 00 00", which indicates that the negative input of qubit 503d is open, and all other positive and negative inputs are closed.

[0116] Figure 20 shows an example configuration of the demultiplexer unit 505. The demultiplexer unit 505 consists of an array of NDRO switches, each connected to either the positive or negative input of a qubit. Each NDRO is also connected to the input pulse train 513, and each NDRO functions as a switch, allowing or blocking pulses from the pulse train 513 to be transmitted to the positive or negative input connected to that NDRO. The path through which the input pulses are transmitted to the positive or negative input is shown by a dotted line.

[0117] A selection signal determines whether pulses from the input pulse train 513 are forwarded to each positive or negative input. NDROs can be arranged in a shift register format, where the carry from each NDRO in the register is supplied as the "on" input to the next switch in the register. The "off" of each NDRO is connected to the clock line. Thus, the selection signal can be configured to forward a "1" from an NDRO connected to a positive input to an adjacent NDRO connected to the negative input of the same qubit. This allows control over the pulse shape of the magnetic flux applied to the qubit, as illustrated in Figure 10.

[0118] The generator 509 that generates the pulse train 513 is similar in some respects to the circuit in Figure 10. However, the generator 509 only needs to generate the increasing (sloping) portion and the plateau region of the shape of the magnetic flux pulse, and the direction of the pulses flowing through the loop is controlled by the positive and negative inputs of the qubit connected to the demultiplexer, so the generator 509 does not need to provide a pulse train that reduces the magnetic flux. Therefore, the generator 509 only needs to supply a pulse train of a single polarity.

[0119] Figure 21 shows the configuration of the generator 509. The generator includes a first pulse counter nPCt1551. This is a counter capable of outputting both pulse trains and carries, and can be of the type described in Figure 8A. The first pulse counter receives a start signal to begin pulse output, which is supplied to the demultiplexer. The resulting gradient signal is passed to the demultiplexer, which increases the magnetic flux at the qubits of the quantum chip, thus enabling the addition of SFQ pulses to the loop. The gradient signal can be supplied to one or more qubits of the quantum chip, and which qubit receives the gradient signal is determined by the demultiplexer.

[0120] When the first counter 551 counts the set number of pulses, a carry signal is output to the second counter t2553. This counter is of the type described in Figure 8B. A signal is also sent to the demultiplexer, directing future pulses to the qubit being addressed to the negative input. Therefore, for each qubit being addressed, the signal between the positive and negative inputs is changed from 10 to 01.

[0121] After a predetermined clock cycle, the carry signal is output via the toggle flip-flop TFF555. Upon receiving the carry signal, TFF555 restarts the first counter and simultaneously toggles itself. The period counted by the second counter 553 defines a plateau. Subsequently, the carry from the first counter restarts the first counter 551, and the first counter begins generating SFQ pulses again. However, because the demultiplexer directs the pulse to the negative input, there is an effect of reducing the magnetic flux applied to the inductor coupled to the qubit. Even if TFF555 receives an input signal again from the t2 counter 553, the start signal for nPCt1551 is not generated because the TFF has already toggled. As a result, only a single trapezoidal waveform is generated.

[0122] From the above, it can be seen that the circuit in Figure 19 controls four qubits using a trapezoidal magnetic flux shape as shown in Figure 5.

[0123] Figure 22 shows a modified version of the system in Figure 19. Here, the circuit in Figure 22 is configured to control the quantum chip using two trapezoids instead of a single trapezoid.

[0124] The arrangement of the qubit chip 501 is the same as that described in Figure 19 and will not be described further here. Furthermore, the positive and negative inputs applied to the inductor loop 511a coupled to each qubit are also the same as those described in Figure 19. However, the type of demultiplexer used to enable the generation of double trapezoidal waves and demultiplexing differs from that described in relation to Figure 19.

[0125] Figure 23 shows an example of a demultiplexer usable in Figure 22. In many ways, it is similar to the one shown in Figure 20. However, here the register consists of a pair of dummy switches (DFFs) placed between two NDRO switches to hold the control data for the second trapezoidal circuit. Due to the nature of the shift register that makes up the demultiplexer, the pattern input to the demultiplexer is shifted along the register, enabling channels to different qubits.

[0126] To form a double trapezoid, the demultiplexer needs to be programmed as follows: positive ramp → plateau → negative ramp → gap → second positive ramp → second plateau → second negative ramp. No special modifications are needed to program this sequence into the first two NDRO switches in the shift register. However, programming the subsequent NDRO switches in the register is more problematic. To circumvent this, dummy flip-flops (DFFs) are placed between pairs of NDRO switches. Therefore, to program a double trapezoid waveform, the following sequence can be applied to the DFF-DFF-NDRO-NDRO configuration enclosed by the dotted line. First trapezoid 1010 0101 Second trapezoid 0010 0001

[0127] Furthermore, the generator configuration differs for double trapezoidal waves. Figure 24 shows the details of the generator. The first pulse counter 601 has a similar structure to that described in Figure 8A and can output a pulse train. It receives a start signal to initiate the pulse slope. When the first pulse counter 601 reaches its count limit (first limit), it outputs a first carry signal instructing the demultiplexer to switch to a negative slope waveform, as described in Figure 19. The carry signal also passes through the first TFF 603. This first TFF is configured to first send the carry signal directly to the second counter t2605. The second counter t2605 is identical to the second counter t2553 described in Figure 21. The structure of the second counter t2605 is similar to that described in Figure 8B. While the second counter t2605 is counting, the magnetic flux flowing through the inductor loop is kept constant, thus forming a plateau. When the second counter t2605 completes its count and reaches its limit (second limit), a carry signal is output. This restarts the first counter 601, and pulse output begins. However, as mentioned above, the demultiplexer has switched to negative polarity, so this pulse output creates a negative ramp, reducing the magnetic flux applied to the inductor loop.

[0128] When the first threshold is reached, the first pulse counter 601 outputs a carry signal again, which is then sent back to the first TFF 603. In this case, the carry is directed to the third counter t4607. The third counter 607 is also structurally similar to the one described in Figure 8B and is used to keep the magnetic flux through the loop constant. In this case, the third counter 607 controls the distance between the first and second trapezoids. When the threshold of the third counter (third limit) is reached, the third counter 607 outputs a carry signal, and the demultiplexer switches from negative input to positive input. This carry signal is output via the second TFF 609, restarting the process. This causes the first pulse counter 601 to start increasing the pulse signal, which continues until the first limit is reached. When the first limit is reached, the carry signal is output to the first TFF 603, which is then directed to the second counter 605 and the demultiplexer, which switch to negative input. When the second counter 605 reaches its second limit, it outputs a carry signal, which causes the first counter 601 to restart counting and output a pulse that forms a negative slope. Thus, the second trapezoidal wave is completed.

[0129] While specific embodiments have been described, these are merely illustrative and not intended to limit the embodiments and / or scope of the disclosed technology. In fact, the novel apparatus and methods described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications are possible to the forms of apparatus, methods, and products described herein based on what is disclosed or illustrated. [Brief explanation of the drawing]

[0130] [Figure 1A] This is a schematic diagram showing an example of a superconducting qubit. [Figure 1B] This is an energy diagram showing an example of a fractionium qubit. [Figure 2] This is a diagram of the Bloch sphere. [Figure 3] This figure shows an example of a fractionium qubit coupled to a controller. [Figure 4A]This figure shows an example of a single-flux quantum circuit (SFQ). [Figure 4B] This figure shows an example of an SFQ pulse. [Figure 5] This figure shows an example of a pulse shape that can be generated by a pulse shaping circuit according to the embodiment. [Figure 6A] Figure 5 is a schematic diagram showing an example of a Bloch sphere representing the precession of a state after pulse application. [Figure 6B] Figure 5 is a schematic diagram showing an example of a Bloch sphere representing the precession of a state after pulse application. [Figure 6C] Figure 5 is a schematic diagram showing an example of a Bloch sphere representing the precession of a state after pulse application. [Figure 6D] Figure 5 is a schematic diagram showing an example of a Bloch sphere representing the precession of a state after pulse application. [Figure 6E] Figure 5 is a schematic diagram showing an example of a Bloch sphere representing the precession of a state after pulse application. [Figure 7A] This is a schematic diagram showing an example of a pulse shaping circuit that generates a trapezoidal pulse and couples it to a qubit, according to the embodiment. [Figure 7B] This is a schematic diagram showing an example of a pulse shaping circuit that generates triangular pulses and connects them to a qubit, according to the embodiment. [Figure 8A] This is a schematic diagram showing an example of a pulse counter used in the circuit of Figure 7A. [Figure 8B] This is a schematic diagram showing an example of a counter (without pulse output) used in the circuit of Figure 7A. [Figure 8C] Figure 8A is a detailed schematic diagram of the pulse counter. [Figure 8D] This is a schematic diagram showing an example of an NDRO switch. [Figure 8E] This is a schematic diagram showing an example of a parallel programmable counter. [Figure 8F] This is a schematic diagram showing an example of a serial programmable counter. [Figure 9] This figure shows an example of a double pulse shape that can be generated by a pulse shaping circuit according to one embodiment. [Figure 10] This is a schematic diagram showing an example of a pulse shaping circuit connected to a qubit, according to the embodiment for generating the dual pulse shown in Figure 9. [Figure 11] This is a plot of the gate error against the Josephson energy at a clock period of 47.5 ps and df = 0.003. [Figure 12] This is a plot of gate error against the inter-pulse waiting time in a dual-pulse system. [Figure 13] This is a plot of gate error against clock period. [Figure 14] This is a graph of gate error with respect to mutual magnetic flux coupling. [Figure 15] This is a diagram of a pulse shape obtained by changing a simple trapezoidal waveform, which can be generated by a pulse shaping circuit according to the embodiment. [Figure 16] Figure 15 shows the gate error against the pulse integral for the pulse shape under the conditions of parameters EL / h = 0.7 GHz, EC / h = 0.9 GHz, EJ / h = 5.82 GHz, a trapezoidal interval of 3 ns, and a clock period of 45 ps. [Figure 17] This is a schematic diagram showing the control layer of a quantum computer. [Figure 18] This is an example of a cryostat and a schematic diagram showing the location of the control layer in Figure 17 within the cryostat. [Figure 19] This is a schematic diagram showing an example of a pulse shaping circuit connected to multiple qubits via a demultiplexer, according to one embodiment. [Figure 20] Figure 19 is a schematic diagram showing an example of a demultiplexer used in this application. [Figure 21] This is a schematic diagram showing an example of a pulse shaping circuit used in the circuit shown in Figure 19. [Figure 22] This is a schematic diagram showing an example of a pulse shaping circuit configured to generate a double pulse coupled to multiple qubits via a demultiplexer, according to one embodiment. [Figure 23]Figure 22 is a schematic diagram showing an example of a demultiplexer used in this application. [Figure 24] This is a schematic diagram showing an example of a pulse counter circuit used in the circuit shown in Figure 22.

Claims

1. A controller for superconducting qubits, wherein the controller is An inductor configured to be inductively coupled to a qubit, The inductor includes a pulse shaping circuit configured to apply a current pulse of a predetermined shape to the inductor, The pulse shaping circuit is, A superconducting circuit configured to output an SFQ (Single Flux Quanta) pulse, A counter circuit configured to control the number of SFQ pulses applied to the inductor, thereby increasing or decreasing the current applied to the inductor by the amount of one SFQ pulse at a time, and generating the shape of the current pulse applied to the inductor. A controller for superconducting qubits, characterized by containing the following:

2. The counter circuit is configured to generate the shape of the current pulse from a positive SFQ pulse having positive polarity and a negative SFQ pulse having negative polarity. The counter circuit is configured to increase the current flowing through the inductor by applying the positive SFQ pulse to the inductor, and to decrease the current flowing through the inductor by applying the negative SFQ pulse to the inductor. A controller for superconducting qubits according to claim 1.

3. The counter circuit is configured to generate a current pulse having a shape that includes a rising edge where the positive SFQ pulse is applied in steps, a plateau region where the current flowing through the inductor is fixed, and a falling edge where the negative SFQ pulse is applied in steps and the current flowing through the inductor decreases. A controller for a superconducting qubit according to claim 2.

4. The shape of the current pulse has multiple plateaus. A controller for superconducting qubits according to claim 3.

5. The superconducting circuit includes a JJ (Josephson Junction) and is configured to output an SFQ pulse resulting from a 2π phase increment in the JJ. A controller for a superconducting qubit according to claim 2.

6. The superconducting circuit is at least one of the following: (i) RSFQ (Rapid Single Flux Quanta / Quantum), ERSFQ, eSFQ, RQL, xSFQ, xeSFQ, DSFQ, bSFQ, PCL, and variations thereof; and (ii) AQFP, QFP, PQ, and variations thereof, which are circuits based on QFP (Quantum Flux Parametrons). A controller for a superconducting qubit according to claim 5.

7. The counter circuit includes a first counter configured to count and limit the number of positive SFQ pulses, and a second counter configured to count and limit the number of negative SFQ pulses. A controller for a superconducting qubit according to claim 2.

8. The system further comprises a third counter, the third counter configured to control the duration of time during which no pulse is output via the inductor. A controller for superconducting qubits according to claim 7.

9. The first counter, the second counter, and the third counter each include a register. A controller for a superconducting qubit according to claim 8.

10. Each of the registers is configured to output a carry signal when its limit is reached, and the first counter, the second counter, and the third counter are arranged in a certain order, and the carry signal is sent from one counter to the next in this order to start the next counter after the current counter. A controller for superconducting qubits according to claim 9.

11. The system further includes a fourth counter configured to generate a pulse shape having a repeating structure and to control the time between structures included in the repeating pulse structure. A controller for a superconducting qubit according to claim 8.

12. It is configured to control multiple qubits via a demultiplexer. A controller for superconducting qubits according to claim 1.

13. It also has multiple inductors, Each inductor is configured to be coupled to the corresponding qubit. A controller for superconducting qubits according to claim 12.

14. Each inductor is provided with a positive input and a negative input, the positive input configured to increase the magnetic flux applied to the corresponding inductor, and the negative input configured to decrease the magnetic flux applied to the corresponding inductor, and the demultiplexer is connected to the positive input and the negative input of each inductor. A controller for superconducting qubits according to claim 13.

15. The demultiplexer is configured to receive a pulse stream and a selection signal that controls whether the positive or negative input of each inductor receives the pulse stream. A controller for superconducting qubits according to claim 14.

16. The pulse shaping unit includes a single pulse counter for outputting a pulse to the positive or negative input. A controller for superconducting qubits according to claim 15.

17. The demultiplexer includes a shift register, and the selection signals are sequentially supplied to the shift register. A controller for superconducting qubits according to claim 15.

18. The shift register comprises ordered NDRO (Non-Destructive Read-Out) elements, each NDRO element NDRO-coupled to a corresponding positive or negative input. A controller for superconducting qubits according to claim 17.

19. The NDRO element further comprises a dummy component between the NDRO element and another NDRO element NDRO-coupled to the corresponding positive or negative input, which holds the selection signal before it is passed to the next NDRO in order. A controller for superconducting qubits according to claim 18.

20. The aforementioned register includes a plurality of superconducting TFFs (T Flip Flops). A controller for superconducting qubits according to claim 9.

21. The shape of the current pulse is configured to transition the qubit inductively coupled to the controller into a quantum superposition state. A controller for superconducting qubits according to claim 1.

22. The system is configured to control at least one of the pulse shape parameters, namely the plateau size, the rising edge size, the falling edge size, the delay time between sequentially generated flux pulses, and the delay before the start of the first flux pulse. A controller for superconducting qubits according to claim 3.

23. A qubit device in which the controller for a superconducting qubit described in claim 1 is inductively coupled.

24. This is a flux qubit device having an inductor. The qubit device according to claim 23.

25. Fractionium-type qubit device The qubit device according to claim 24.

26. It is installed together with the controller for the superconducting qubit in a low-temperature measurement system at a temperature of less than 1 K. The qubit device according to claim 23.

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