Voltage mode filter with output impedance neutralization

Abstract

The device comprises a differential voltage-mode filter circuit having first and second voltage-mode filter circuits and a neutralization network. Each of the first and second voltage-mode filter circuits includes a unity-gain buffer having a non-zero output impedance. The neutralization network includes a first neutralization impedance circuit that couples the input of the first voltage-mode filter circuit to the output of the second voltage-mode filter circuit, and a second neutralization impedance circuit that couples the input of the second voltage-mode filter circuit to the output of the first voltage-mode filter circuit. The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by at least one of canceling and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

Description

[Background technology]

[0001] This disclosure relates, in general, to voltage mode filters, and more particularly to voltage mode baseband filters for radio frequency (RF) signal generators such as arbitrary waveform generator (AWG) systems. The RF signal generator may be implemented as a Cartesian architecture with orthogonal phases, in which baseband in-phase (I) and orthogonal-phase (Q) signals are filtered and upconverted to an RF signal using a single-sideband (SSB) modulation system via an I / Q channel mixer. Such RF signal generators are used for applications such as radio transmitters and the generation of control pulses for qubits in quantum computing systems. In particular, in quantum computing applications, AWG systems capable of generating RF control pulses with variable amplitude and low distortion are desirable for controlling qubits in quantum processors. Furthermore, minimizing the power consumption of the AWG system is extremely important, especially in the context of cryogenic RF signal generation for qubit control.

[0002] An RF signal generator can have various signal processing stages implemented using current-mode circuits. For example, an RF signal generator can be implemented using a current-mode baseband filter interfaced to a current-mode RF output stage. Current-mode circuits can offer a favorable trade-off between power and performance. For instance, a current-mode circuit in an RF output stage allows for current reuse, where the bias current of one stage is shared with another to improve power efficiency. Furthermore, current-mode baseband filters can offer high performance with respect to frequency response (e.g., high out-of-band rejection). On the other hand, current-mode circuits often involve stacked transistor architectures that may require a moderate quiescent current and a high supply voltage (and therefore higher power dissipation) to provide the headroom necessary to operate the stacked transistors in saturation mode.

[0003] On the other hand, voltage-mode baseband filters can be used to filter the baseband signal applied to the RF output stage. Compared to current-mode baseband filtering, voltage-mode baseband filters may have architectures that require lower quiescent current and voltage headroom, and therefore can operate with relatively low supply voltages and low power dissipation. When using certain voltage-mode filter architectures that implement an active output buffer stage operating in a low-power implementation (e.g., using low quiescent current), the non-zero output impedance of the buffer stage can lead to poor filter response (e.g., poor out-of-band rejection), which may be unacceptable in various applications such as quantum computing applications. [Overview of the Initiative]

[0004] Exemplary embodiments of the present disclosure include voltage mode filter circuit architectures for use with RF signal generator systems, such as arbitrary waveform generator systems. The exemplary voltage mode filter circuit can be used at reduced supply voltage levels for low power consumption and provides a low-power filter architecture that implements an impedance neutralization network configured to neutralize the output impedance of the voltage mode filter circuit, thereby improving the frequency response of the voltage mode filter circuit and providing, for example, increased out-of-band rejection.

[0005] In an exemplary embodiment, the device comprises a differential voltage-mode filter circuit having a first voltage-mode filter circuit, a second voltage-mode filter circuit, and a neutralization network. The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance. The neutralization network includes a first neutralization impedance circuit that couples the input node of the first voltage-mode filter circuit to the output node of the second voltage-mode filter circuit, and a second neutralization impedance circuit that couples the input node of the second voltage-mode filter circuit to the output node of the first voltage-mode filter circuit. The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by at least one of canceling and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

[0006] Advantageously, the output impedance neutralization network compensates for the adverse effects on the frequency response of the first and second voltage-mode filter circuits as a result of the non-zero output impedance of the respective unity-gain buffers, thereby enabling the implementation of an ultra-low-power, high-bandwidth differential voltage-mode filter with an improved frequency response (e.g., higher out-of-band rejection) despite the non-zero output impedance of the unity-gain buffers of the first and second voltage-mode filter circuits of the differential voltage-mode filter circuit.

[0007] Another exemplary embodiment includes a device comprising a digital-to-analog converter circuit, a differential voltage mode filter circuit, and a current mode output circuit. The digital-to-analog converter circuit has an output interface configured to generate a differential analog voltage signal including a first voltage signal and a second voltage signal, which are complementary voltage signals. The differential voltage mode filter circuit is configured to filter the differential analog voltage signal and output a filtered differential analog voltage signal including a first filtered voltage signal and a second filtered voltage signal, which are complementary filtered voltage signals. The current mode output circuit is coupled to the differential voltage mode filter circuit and is configured to convert the first filtered voltage signal and the second filtered voltage signal into a first current signal and a second current signal, respectively, for processing by the current mode output circuit. The differential voltage mode filter circuit has a neutralization network including a first voltage mode filter circuit configured to filter the first voltage signal, a second voltage mode filter circuit configured to filter the second voltage signal, and a first neutralization impedance circuit and a second neutralization impedance circuit. The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance. The first neutralizing impedance circuit couples the input node of the first voltage-mode filter circuit to the output node of the second voltage-mode filter circuit, and the second neutralizing impedance circuit couples the input node of the second voltage-mode filter circuit to the output node of the first voltage-mode filter circuit. The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by canceling and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

[0008] Another exemplary embodiment includes a system comprising a radio frequency signal generator configured to convert a baseband signal into a radio frequency signal. The radio frequency signal generator comprises a digital-to-analog converter circuit, a differential voltage mode filter circuit, and a current mode radio frequency output circuit. The digital-to-analog converter circuit includes an output interface configured to generate a differential baseband voltage signal including a first baseband voltage signal and a second baseband voltage signal, which are complementary baseband voltage signals. The differential voltage mode filter circuit is configured to filter the differential baseband voltage signal and output a filtered differential baseband voltage signal including a first filtered baseband voltage signal and a second filtered baseband voltage signal, which are complementary filtered baseband voltage signals. The current mode radio frequency output circuit is coupled to the differential voltage mode filter circuit and is configured to convert the first filtered baseband voltage signal and the second filtered baseband voltage signal into a first baseband current signal and a second baseband current signal, respectively, for processing by the current mode radio frequency output circuit to generate the radio frequency signal. The differential voltage-mode filter circuit includes a neutralization network comprising a first voltage-mode filter circuit configured to filter the first baseband voltage signal, a second voltage-mode filter circuit configured to filter the second baseband voltage signal, and a first neutralization impedance circuit and a second neutralization impedance circuit. The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance. The first neutralization impedance circuit couples the input node of the first voltage-mode filter circuit to the output node of the second voltage-mode filter circuit, and the second neutralization impedance circuit couples the input node of the second voltage-mode filter circuit to the output node of the first voltage-mode filter circuit.The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by canceling out and compensating for at least one of the transmit zeros of the transfer function of each of the first and second voltage-mode filter circuits, which are derived from the non-zero output impedance of each of the unity-gain buffers.

[0009] Another exemplary embodiment includes a system comprising a quantum processor having at least one superconducting qubit, and an arbitrary waveform generator having at least one arbitrary waveform generator channel configured to convert a baseband signal into radio frequency control pulses that control the at least one superconducting qubit. The at least one arbitrary waveform generator channel includes a digital-to-analog converter circuit, a differential voltage mode filter circuit, and a current mode radio frequency output circuit. The digital-to-analog converter circuit includes an output interface configured to generate a differential baseband voltage signal including a first baseband voltage signal and a second baseband voltage signal, which are complementary baseband voltage signals. The differential voltage mode filter circuit is configured to filter the differential baseband voltage signal and output a filtered differential baseband voltage signal including a first filtered baseband voltage signal and a second filtered baseband voltage signal, which are complementary filtered baseband voltage signals. The current-mode radio frequency output circuit is coupled to the differential voltage-mode filter circuit and is configured to convert the first filtered baseband voltage signal and the second filtered baseband voltage signal into a first baseband current signal and a second baseband current signal, respectively, for processing by the current-mode radio frequency output circuit, thereby generating the radio frequency control pulse. The differential voltage-mode filter circuit includes a first voltage-mode filter circuit configured to filter the first baseband voltage signal, a second voltage-mode filter circuit configured to filter the second baseband voltage signal, and a neutralization network including a first neutralization impedance circuit and a second neutralization impedance circuit. The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance.The first neutralizing impedance circuit couples the input node of the first voltage-mode filter circuit to the output node of the second voltage-mode filter circuit, and the second neutralizing impedance circuit couples the input node of the second voltage-mode filter circuit to the output node of the first voltage-mode filter circuit. The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by canceling out and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

[0010] Another exemplary embodiment includes a method comprising the steps of: applying a differential voltage signal to first and second input nodes of a differential voltage mode filter circuit to generate filtered differential signals on first and second output nodes of the differential voltage mode filter circuit, wherein the differential voltage mode filter circuit has a neutralization network including a first voltage mode filter circuit and a second voltage mode filter circuit, each including a unity-gain buffer having a non-zero output impedance; a first neutralization impedance circuit coupling the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit; and configuring the neutralization network to correct the frequency response of each of the first voltage mode filter circuit and the second voltage mode filter circuit by canceling out and compensating for at least one of the transmit zeros of the transfer function of each of the first voltage mode filter circuit and the second voltage mode filter circuit, which are derived from the non-zero output impedance of the respective unity-gain buffers.

[0011] In another exemplary embodiment, as can be combined with the preceding paragraph, the first neutralizing impedance circuit and the second neutralizing impedance circuit each include a passive impedance element. Advantageously, the use of passive impedance elements to implement the neutralization network enables an improved frequency response of the voltage mode filter circuit using additional components that do not require a DC bias and therefore do not introduce any additional static power dissipation.

[0012] In another exemplary embodiment, as can be combined with the preceding paragraph, the first neutralizing impedance circuit includes at least a first resistor and a first capacitor connected in series between the input node of the first voltage-mode filter circuit and the output node of the second voltage-mode filter circuit, and the second neutralizing impedance circuit includes at least a second resistor and a second capacitor connected in series between the input node of the second voltage-mode filter circuit and the output node of the first voltage-mode filter circuit. Advantageously, the use of resistors and capacitors to implement the first and second neutralizing impedance circuits allows for an improved frequency response of the voltage-mode filter circuit using additional components that do not require a DC bias and therefore do not introduce any additional static power dissipation. In addition, the capacitors of the first and second neutralizing impedance circuits allow the neutralization network to be completely uncoupled from the DC bias of the first and second voltage-mode filter circuits. Thus, the neutralization network does not affect the differential voltage-mode filter circuit in terms of DC current bias, DC power consumption, and common-mode voltage levels, and the DC bias conditions remain unchanged.

[0013] In another exemplary embodiment, as can be combined with the preceding paragraph, the first and second capacitors of the neutralization network are variable capacitors. Advantageously, the use of variable capacitors allows the capacitance of the neutralization network to be digitally controlled to tune the frequency response of the differential voltage mode low-pass filter, enabling compensation for process and temperature variations.

[0014] Other embodiments will be described in the following detailed description of exemplary embodiments, which should be read in conjunction with the attached figures. [Brief explanation of the drawing]

[0015] [Figure 1] This figure schematically illustrates a radio frequency signal generator system according to an exemplary embodiment of the present disclosure.

[0016] [Figure 2] This figure schematically illustrates a radio frequency signal generator system that implements a voltage mode filter circuit, according to another exemplary embodiment of the present disclosure.

[0017] [Figure 3] This figure schematically shows a voltage mode filter circuit according to an exemplary embodiment of the present disclosure.

[0018] [Figure 4A] This figure schematically shows a differential voltage mode filter circuit with an output impedance neutralization network, according to an exemplary embodiment of the present disclosure.

[0019] [Figure 4B] This figure schematically illustrates a differential voltage mode filter circuit comprising an output impedance neutralization network, according to another exemplary embodiment of the present disclosure.

[0020] [Figure 5] This figure shows the simulated response of a voltage-mode low-pass filter with and without output impedance neutralization, according to an exemplary embodiment of the present disclosure.

[0021] [Figure 6A] This figure schematically illustrates a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. [Figure 6B]This figure schematically illustrates a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. [Figure 6C] This figure schematically illustrates a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. [Figure 6D] This figure schematically illustrates a radio frequency signal generator system according to another exemplary embodiment of the present disclosure.

[0022] [Figure 7] This figure schematically illustrates a gain control system implemented at the interface between a digital-to-analog converter circuit and a voltage mode filter circuit in an RF signal generator system, according to an exemplary embodiment of the present disclosure.

[0023] [Figure 8] This figure schematically illustrates a quantum computing system that implements an arbitrary waveform generator system with a voltage mode filter circuit, according to an exemplary embodiment of the present disclosure.

[0024] [Figure 9] This figure schematically illustrates a quantum computing system according to another exemplary embodiment of the present disclosure.

[0025] [Figure 10] This figure schematically illustrates an exemplary computing environment configured to execute a quantum computing operation of a calibration system and program instructions for performing the calibration operation, according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0026] Herein, exemplary embodiments of the present disclosure will be described in more detail with respect to voltage mode filter circuit architectures for use with RF signal generator systems such as arbitrary waveform generator systems. The exemplary voltage mode filter circuits disclosed herein provide a low-power filter architecture that can be used with reduced supply voltage levels for the low power consumption of RF signal generators such as AWG systems. In addition, exemplary voltage mode filter circuits such as those disclosed herein implement a passive neutralization network configured to neutralize the non-zero output impedance of the output buffer stage of the voltage mode filter, thereby improving the filter frequency response and providing, for example, improved out-of-band rejection. Note that the expressions “neutralizing output impedance,” “output impedance neutralization,” or “neutralization network” are intended to broadly refer to circuits or techniques for offsetting or mitigating the adverse effects on the frequency response of the voltage mode filter circuit as a result of the voltage mode filter implementing a unity-gain buffer output stage with non-zero output impedance. For illustrative purposes, the exemplary embodiments of this disclosure will be discussed in the context of output impedance neutralization techniques for Sallen-Key filters based on a unity-gain buffer, where the non-zero output impedance of the unity-gain buffer (e.g., an active source follower buffer) can adversely affect the frequency response of such a filter. However, it should be understood that exemplary techniques such as those discussed herein can be implemented with other types of voltage-mode filters that implement a unity-gain output buffer as a critical gain stage where the non-zero output impedance of the unity-gain buffer adversely affects the frequency response of the voltage-mode filter.

[0027] It should be understood that the various features shown in the attached drawings are schematic illustrations and not drawn to scale. Furthermore, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, a detailed description of such same or similar features, elements, or structures is not repeated in each of the drawings. In addition, the term “exemplary,” as used herein, means “serving as an example, case, or illustration.” Any embodiment or design described “exemplary” herein should not be construed as being preferable or advantageous to other embodiments or designs.

[0028] Furthermore, when the expression "configured to" is used in conjunction with a circuit, structure, element, component, or similar that performs one or more functions or provides any functionality in a different way, it should be understood that it is intended to encompass embodiments in which such circuit, structure, element, component, or similar is implemented in hardware, software, and / or combinations thereof, and in implementations including hardware, such hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), superconducting elements such as superconducting qubits, programmable elements (e.g., application-specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPU), graphics processing units (GPUs), etc.), one or more integrated circuits, and / or combinations thereof. Therefore, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular functionality, it is intended to include, but is not limited to, embodiments comprising elements, processing devices, and / or integrated circuits that enable the circuit, structure, element, component, etc. to perform that particular functionality when it is in operation (e.g., connected or otherwise deployed in a system, powered on, receiving input, and / or generating output), and also to include embodiments when the circuit, structure, element, component, etc. is in non-operational state (e.g., not connected or otherwise deployed in a system, not powered on, not receiving input, and / or generating output) or in a partially operational state.

[0029] Figure 1 schematically illustrates a radio frequency signal generator system according to an exemplary embodiment of the present disclosure. In particular, Figure 1 schematically illustrates an RF signal generator system 100 comprising a baseband I / Q signal generator 110, a digital-to-analog converter stage 120 (or DAC stage 120), a baseband filter stage 130, a mixer stage 140, an amplifier stage 150, an impedance matching network 160, a local oscillator (LO) signal generator circuit 170, and an LO signal driver circuit 180, the functions of which will be described in more detail below. A calibration control system 190 is configured to calibrate the various stages of the RF signal generator system 100 using digital control signals. The calibration control system 190 is implemented using a combination of software (e.g., program execution) and hardware (e.g., control logic and circuitry) to implement various control functions as described herein.

[0030] As schematically shown in Figure 1, the DAC stage 120 has an input coupled to the output of the baseband I / Q signal generator 110. The baseband filter stage 130 has an input coupled to the output of the DAC stage 120. The mixer stage 140 has an input coupled to the output of the baseband filter stage 130. The amplifier stage 150 has an input coupled to the output of the mixer stage 140 and an output coupled to the input of the impedance matching network 160, the output of which is coupled to the output node (RF_OUT) of the RF signal generator system 100. The LO signal generator circuit 170 is configured to generate an LO signal (e.g., a quadrature LO signal) that is used by the mixer stage 140 to perform upconversion of the baseband signal. The LO signal driver circuit 180 is configured to control the input of the LO signal to the mixer stage 140 for different operating modes of the RF signal generator system 100 (e.g., real-time operation mode and calibration mode), as will be discussed in more detail below.

[0031] It should be understood that the RF signal generator system 100 can be implemented for a variety of applications. For example, in some embodiments, the RF signal generator system 100 comprises an RF transmitter for wireless applications, and the output of the RF signal generator system 100 is coupled to an antenna system configured to transmit the RF output signal generated by the RF signal generator system 100. In other embodiments, the RF signal generator system 100 comprises a waveform generator (e.g., an AWG, or a function generator) whose output is coupled to the input of a sensor device, and the RF output signal generated by the RF signal generator system 100 is configured to excite the sensor device. In other embodiments, for quantum computing applications, the RF signal generator system 100 comprises an AWG system configured to generate RF control pulses to control the operation of, for example, a superconducting qubit, an active superconducting coupler circuit coupling two superconducting qubits, or other superconducting quantum devices.

[0032] In the context of the exemplary embodiments discussed herein, the RF signal includes, for example, a signal having a frequency in the range of about 20 kHz to about 300 GHz. In some embodiments, the RF signal generator system 100 comprises an analog quadrature system configured to generate quadrature (I / Q) signals (e.g., a baseband I / Q signal and an LO I / Q signal) and perform quadrature modulation (or I / Q signal modulation) to generate an RF signal for a given application. As is known in the art, a quadrature signal includes an in-phase (I) signal component and a quadrature-phase (Q) signal component. A pair of orthogonal signals have the same frequency but are in phase by 90 degrees. For example, by conversion, the I signal is a cosine waveform and the Q signal is a sine waveform. For illustrative purposes, the exemplary embodiments of this disclosure will be described in the context of quadrature RF signal generator systems, but exemplary signal processing circuits and methods as discussed herein can be implemented together with other types of RF signal generator systems and modulation techniques.

[0033] In the exemplary embodiment shown in Figure 1, the baseband I / Q signal generator 110 is configured to generate digital quadrature signals I and Q representing input baseband data for a given application. For example, in a quantum computing application, the baseband I / Q signal generator 110 is configured to implement pulse shaping techniques to generate RF-controlled pulses having a desired envelope shape (e.g., Gaussian pulses, cosine pulses (e.g., sum of half cosines), hyperbolic secant pulses, etc.) which are applied to a superconducting qubit or active qubit coupler circuit to perform single qubit gate operations, entanglement gate operations, etc. In some embodiments, the baseband I / Q signal generator 110 implements digital signal processing techniques based on a combination of hardware and software to generate digital quadrature baseband signals I and Q.

[0034] The DAC stage 120 is configured to convert digital quadrature signals I and Q into analog baseband signals I'(t) and Q'(t) having a target baseband frequency. In particular, the DAC stage 120 includes a multibit DAC circuit comprising a first DAC circuit 121 and a second DAC circuit 122. The first DAC circuit 121 is configured to convert the digital baseband component I into an analog baseband component I'(t) having a baseband frequency, and the second DAC circuit 122 is configured to convert the digital baseband component Q into an analog baseband component Q'(t) having the same baseband frequency but shifted by 90 degrees relative to I'(t). The DAC stage 120 takes a given sampling rate (f S) Alternatively, analog baseband signals I'(t) and Q'(t) at baseband frequencies in the range of approximately 100 kHz to approximately 1 GHz are generated and output, depending on the sampling frequency, for example, for a given application. In some embodiments, the first and second DAC circuits 121 and 122 implement a configurable hardware framework that can adjust various operating parameters of the DAC stage 120 by digital control signals input to the DAC stage 120. For example, in some embodiments, the digital control can be used to adjust DAC operating parameters including, but not limited to, the sampling rate, analog full-scale output, etc.

[0035] Based on the Nyquist sampling theory, the highest fundamental output frequency f that the DAC can generate at a sampling frequency f s is O equal to half of the sampling rate, i.e., f s / 2 (referred to as the first Nyquist zone). In the frequency domain, when generating a sine wave of frequency f O , the fundamental baseband frequency f O will appear as a spectral component at f O , and there will be additional higher-order frequency components generated at the output of the DAC stage 120, which are referred to as "images" and are functions of f S and f O . For example, the higher-order frequency components are determined as |(n × f S ) ± f O |, where n = 1, 2, 3,.... The images have the same information content as the fundamental spectral components, except that the frequency is higher and the amplitude is smaller. Unwanted images are suppressed / removed, for example, using the baseband filter stage 130.

[0036] The baseband filter stage 130 is configured to filter the analog baseband signals I'(t) and Q'(t) output from the DAC stage 120, thereby generating filtered analog baseband signals I(t) and Q(t). The baseband filter stage 130 comprises a first filter circuit 131 and a second filter circuit 132. The first filter circuit 131 is configured to filter the common-mode analog signal I'(t) output from the first DAC circuit 121, and the second filter circuit 132 is configured to filter the quadrature-phase analog signal Q'(t) output from the second DAC circuit 122. In some embodiments, the first and second filter circuits 131 and 132 include low-pass filters configured to allow the fundamental spectral components of the analog signals I'(t) and Q'(t) to pass through while suppressing the image components of the respective analog signals I'(t) and Q'(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as bandpass filters that allow a desired bandwidth of higher-order frequency image components of the analog signals I'(t) and Q'(t) to pass through while suppressing the fundamental spectral components and other image components of the analog signals I'(t) and Q'(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as high-pass filters as desired for a given application.

[0037] In some embodiments, the baseband filter stage 130 includes a configurable filter circuit that allows, for example, adjustment of the cutoff frequencies of the first and second filter circuits 131 and 132, or the first and second filter circuits 131 and 132 to be configured to have different filter types (e.g., low-pass, band-pass, etc.) as desired for a given application. For example, in some embodiments, a band-pass filter can be configured using two low-pass filters employing known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by a digital control signal input to the baseband filter stage 130.

[0038] For example, a higher DAC sampling frequency can be used as needed to transmit baseband data and / or to mitigate the filter response of the downstream filter of the baseband filter stage 130. In practice, increasing the DAC sampling frequency allows for the possibility of accommodating higher baseband transmission frequencies (i.e., analog signals I'(t) and Q'(t) with higher baseband frequencies). In addition, increasing the DAC sampling frequency allows for the center frequency f of the baseband component to be adjusted. O And the center frequency of higher frequency images n × f S ±f O This results in increased separation between the two frequencies, thereby mitigating the required sharpness of the filter cutoff at the filter's corner frequencies. However, higher DAC sampling rates lead to increased power consumption. Therefore, the trade-off between power consumption and DAC sampling frequency, as well as the sharpness of the filter cutoff at the filter's corner frequencies, are factors that should be considered.

[0039] In some embodiments, the mixer stage 140 is configured to perform analog I / Q signal modulation, such as single-sideband (SSB) modulation, by mixing the filtered analog signals I(t) and Q(t) output from the baseband filter stage 130 with quadrature LO signals (e.g., in-phase LO signal (LO_I) and quadrature-phase LO signal (LO_Q)) to generate and output an analog RF signal (e.g., a single-sideband modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, except that the LO_Q signal is shifted in phase by 90 degrees relative to the LO_I signal. In the case of amplitude modulation, the filtered analog signals I(t) and Q(t) amplitude modulate the LO_I and LO_Q signals.

[0040] More specifically, the mixer stage 140 comprises a first mixer circuit 141 (e.g., an I mixer circuit), a second mixer circuit 142 (e.g., a Q mixer circuit), and a signal combiner circuit 143. The first mixer circuit 141 is configured to mix a filtered analog signal I(t) with the LO_I signal to generate a first RF signal output. The second mixer circuit 142 is configured to mix a filtered analog signal Q(t) with the LO_Q signal to generate a second RF signal output. The first and second RF signals output from the first and second mixer circuits 141 and 142 are input to the signal combiner circuit 143 and combined (e.g., added) to generate a single-sideband RF signal output.

[0041] In some embodiments, quadrature phase-shifter circuits are implemented to generate quadrature LO signals LO_I and LO_Q. For example, a quadrature phase-shifter circuit is configured to receive an LO signal as input and output quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal contains the same frequency and phase as the input LO signal, and the LO_Q signal contains the same frequency as the input LO signal, but with a 90-degree phase shift. The quadrature phase-shifter circuit can be implemented using one of various quadrature phase-shifting techniques known to those skilled in the art.

[0042] The mixer stage 140 performs an upconversion mixing process configured to generate an RF analog signal having a center frequency higher than the baseband frequency of the baseband signal output from the DAC stage 120. In some embodiments, the LO frequency of the mixer stage 140 is in the range of 100 MHz to about 10 GHz, depending on the application. More specifically, as will be understood by those skilled in the art, the first and second RF signals output from the first and second mixer circuits 141 and 142, respectively, as a result of the mixing operation of the first and second mixer circuits 141 and 142, each include a double-sided RF signal. The double-sided signal includes an upper sideband (USB) and a lower sideband (LSB) positioned at equal distances above and below the LO frequency. The upper sideband includes a spectral band with frequencies higher than the LO frequency, and the lower sideband includes a spectral band with frequencies lower than the LO frequency. The upper and lower sidebands each carry the same information content of the I / Q signal. For example, if the filtered analog signals I(t) and Q(t) (i.e., the modulated signals) have a center frequency f M (Having an intermediate frequency), and the LO signal having frequency f LO Assume that the first and second RF signals output from the first and second mixer circuits 141 and 142 are, respectively, (i)(f LO +f M (ii)(f LO -f M This results in a lower sideband of the spectral component, which is a frequency band centered around the frequency of ).

[0043] In some embodiments, the signal combiner circuit 143 is configured to add the first and second RF signals output from the first and second mixer circuits 141 and 142, in which case the signal combiner circuit 143 combines the frequencies f of the modulated signals I(t) and Q(t). M From the center frequency of the lower sideband (f LO -f MThe signal combiner circuit 143 outputs an "effective" lower sideband signal as a single-sideband modulated RF signal (with a suppressed carrier frequency) having a center frequency upconverted to ). In other embodiments, the signal combiner circuit 143 is configured to subtract the first and second RF signals output from the first and second mixer circuits 141 and 142, in which case the signal combiner circuit 143 subtracts the frequency f of the modulated signals I(t) and Q(t). M From the center frequency of the upper sideband (f LO +f M The "effective" upper sideband signal will output as a single-sideband modulated RF signal (with a suppressed carrier) having a center frequency upconverted to ). In other embodiments, the mixer stage 140 is configured as a double-sideband modulator (with a suppressed carrier frequency). More specifically, the mixer stage 140 can be configured to provide double-sideband modulation by maintaining the LO_Q input to the second mixer 142 at a constant zero voltage level (i.e., LO_Q=0). In this case, the second mixer circuit 142 will have a zero output (i.e., no RF signal is output from the second mixer circuit 142), and the output of the signal combiner circuit 143 will be the double-sideband RF signal output from the first mixer circuit 141.

[0044] The amplifier stage 150 is configured to receive the modulated RF signal output from the mixer stage 140, amplify or attenuate the modulated RF signal to a desired power level, and drive the output of the RF signal generator system 100 (for example, to drive an antenna, sensor device, cubit, etc., coupled to the output of the RF signal generator system 100). In some embodiments, the amplifier stage 150 includes a programmable gain, which can be expressed as the difference between the input power level (at the input of the amplifier stage 150) and the output power level (at the output of the amplifier stage 150), or more specifically, as the ratio of the output to the input power. In some embodiments, the amplifier stage 150 is used to increase the power level of the RF output signal to a level sufficient to transmit the modulated RF signal (wirelessly or via a wire) at a given power level and over a required transmission distance. In other embodiments, the amplifier stage 150 includes a programmable gain attenuation stage. The programmable gain attenuation stage includes a programmable amplifier (or attenuator) configured to amplify the modulated RF signal with a gain coefficient of 1 or less than 1. In this way, the programmable gain attenuation stage can, as desired for a given application, attenuate the power level of the modulated RF signal output from the mixer stage 140.

[0045] The impedance matching network 160 is configured to match the source impedance or load impedance of the output of the amplifier stage 150 to the characteristic impedance of the output load of the RF signal generator system 100 (e.g., antenna input, diplexer, etc.). In some embodiments, the impedance matching network 160 includes a balun that converts the differential / balanced output of the amplifier stage 150 to a single-ended / unbalanced output. In some embodiments, the parameters of the impedance matching network 160 (e.g., impedance and bandwidth at resonance) remain substantially constant, and the impedance matching network 160 is designed at a center frequency corresponding to a desired operating frequency of the load. In other embodiments, the impedance matching network 160 is configured with multiple injection points to provide different impedance matching and filtering characteristics. Different injection points can be selected by a digital control signal applied to the impedance matching network 160. The impedance matching network 160 can have high-pass and low-pass characteristics, and different injection points can be selected to provide different impedance matching and response characteristics. In some embodiments, the impedance matching network 160 is designed with a high Q factor, and the center frequency of the impedance matching network 160 can be adjusted, depending on a given application, to provide the desired impedance conversion for different transmission frequencies that occur, for example, by changing the sampling frequency of the DAC stage 120 and / or changing the LO frequency of the mixer stage 140.

[0046] In some embodiments, the LO signal generator circuit 170 is configured to generate quadrature LO signals LO_I and LO_Q at a target center frequency, which are used by the mixer stage 140 to perform I / Q modulation and upconversion. In some embodiments, in the case of a differential signal framework, the LO signal generator circuit 170 generates complementary in-phase LO signals LO_I and

number

number

number

[0047] The LO signal generator circuit 170 can be implemented using known circuit architectures and LO signal generation techniques. For example, in some embodiments, the LO signal generator circuit 170 comprises a phase-locked loop (PLL) system configured to generate an LO signal at a target center frequency, and a phase shifter circuit that converts the LO signal generated by the PLL system into quadrature LO signals LO_I and LO_Q. In the case of differential quadrature LO signals, in some embodiments, the LO signal generator circuit 170 takes the complementary pair of LO signals and as inputs.

number

number

[0048] As shown in Figure 1, the various signal processing stages 110, 120, 130, 140, 150, 160, 170, and 180 of the RF signal generator system 100 are provided with control signal input ports that receive digital control signals from either the calibration control system 190 or some processor or microcontroller configured to control the operation of the RF signal generator system 100. The calibration control system 190 is configured to generate digital control signals to configure the RF signal generator system 100 or its signal processing stages to operate in different modes. Furthermore, in some embodiments, some or all of the stages 110, 120, 130, 140, 150, 160, 170, and 180 have a configurable hardware framework in which various operating parameters and / or components of the stage can be tuned by digital control signals for different operating modes of the RF signal generator system 100.

[0049] Figure 2 schematically illustrates an RF signal generator system according to another exemplary embodiment of the present disclosure. More specifically, Figure 2 schematically illustrates a radio frequency signal generator system 200 implementing a voltage mode filter circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 2, the RF signal generator system 200 comprises a voltage mode filter stage 210 and a current mode RF output stage 220 of the RF signal generator system 200 according to an exemplary embodiment of the present disclosure. The current mode RF output stage 220 comprises a baseband signal stage 230, a current rectifier mixer stage 240, a signal attenuation stage 250, and an output transformer stage 260. In some embodiments, the RF signal generator system 200 generates a complementary in-phase baseband signal I(t) and

number

number

number

number

[0050] The voltage mode filter stage 210 comprises a first differential voltage mode filter 212 and a second differential voltage mode filter 214. The first differential voltage mode filter 212 comprises a neutralization network 213 comprising a first voltage mode filter circuit 212-1, a second voltage mode filter circuit 212-2, and a first neutralization impedance circuit 213-1 and a second neutralization impedance circuit 213-2. The second differential voltage mode filter 214 comprises a neutralization network 215 comprising a first voltage mode filter circuit 214-1, a second voltage mode filter circuit 214-2, and a first neutralization impedance circuit 215-1 and a second neutralization impedance circuit 215-2. In some embodiments, the neutralization impedance circuits 213-1, 213-2, 215-1, and 215-2 comprise passive impedance components such as resistors and capacitors, which can be fixed or variable.

[0051] In some embodiments, the first differential voltage mode filter 212 includes a differential analog low-pass filter, and the first voltage mode filter circuit 212-1 and the second voltage mode filter circuit 212-2 each take their respective complementary in-phase baseband signals I'(t) and

number

number

number

number

[0052] In some embodiments, the voltage-mode filter circuits 212-1, 212-2, 214-1, and 214-2 each comprise an analog dual-order low-pass filter circuit utilizing a unity-gain source follower circuit. For example, in some embodiments, the voltage-mode filter circuits 212-1, 212-2, 214-1, and 214-2 each employ a single-transistor Sallen-Key filter architecture (exemplary embodiments thereof are described in further detail below in conjunction with Figure 3). Such implementations of the analog dual-order low-pass filter circuit have a transfer function with zeros resulting from the non-zero output impedance of the low-pass filter circuit (whose output impedance is limited by the output impedance of the unity-gain source follower circuit). Neutralization networks 213 and 215 comprise output impedance neutralization networks configured to neutralize the non-zero output impedance of the voltage-mode filter circuits 212-1, 212-2, 214-1, and 214-2, thereby improving the out-of-band rejection response of such filters. The neutralization networks 213 and 215 are configured to effectively cancel out the transfer function zeros (or transmit zeros) resulting from the non-zero output impedances of the voltage-mode filter circuits 212-1, 212-2, 214-1, and 214-2.

[0053] More specifically, the neutralization network 213 is configured to cancel out the transfer function zeros (or transmit zeros) of the first and second voltage-mode filter circuits 212-1 and 212-2 of the first differential voltage-mode filter 212, which result from the non-zero output impedances of the first and second voltage-mode filter circuits 212-1 and 212-2. In some embodiments, as schematically shown in Figure 2, such neutralization is achieved by (i) coupling the input of the first voltage-mode filter circuit 212-1 to the output of the second voltage-mode filter circuit 212-2 through a first neutralization impedance circuit 213-1, and (ii) coupling the input of the second voltage-mode filter circuit 212-2 to the output of the first voltage-mode filter circuit 212-1 through a second neutralization impedance circuit 213-2. In this exemplary configuration, the neutralization network 213 comprises mutually coupled neutralization impedance circuits 213-1 and 213-2.

[0054] Similarly, the neutralization network 215 is configured to cancel out the transfer function zeros (or transmit zeros) of the first and second voltage-mode filter circuits 214-1 and 214-2 of the second differential voltage-mode filter 214, which result from the non-zero output impedances of the first and second voltage-mode filter circuits 214-1 and 214-2. In some embodiments, as schematically shown in Figure 2, such neutralization is achieved by (i) coupling the input of the first voltage-mode filter circuit 214-1 to the output of the second voltage-mode filter circuit 214-2 through a first neutralization impedance circuit 215-1, and (ii) coupling the input of the second voltage-mode filter circuit 214-2 to the output of the first voltage-mode filter circuit 214-1 through a second neutralization impedance circuit 215-2. In this exemplary configuration, the neutralization network 215 comprises mutually coupled neutralization impedance circuits 215-1 and 215-2. Exemplary embodiments of the voltage mode filter stage 210 and associated first and second differential voltage mode filters 212 and 214 will be discussed in more detail below, in conjunction with the exemplary voltage mode filter circuit architectures shown, for example, in Figures 3, 4A, and 4B.

[0055] In some embodiments, the current-mode RF output stage 220 has an I / Q signal path (I) where signal processing is performed by the baseband signal stage 230 and I / Q modulation and upconversion are performed. + , I - Q + and Q - The baseband signal stage 230 has a current mode architecture that is performed using a time-varying current signal injected into ). The baseband signal stage 230 has a current mode architecture that is performed using a time-varying current signal injected into ).

number

number

number

[0056] Similarly, baseband transistors 233 and 234 are provided with a second differential transistor pair 220-2, which has a common connection source terminal coupled to the regulated voltage rail (denoted as VDD_RF_Reg), and complementary quadrature phase baseband voltage signals Q(t) and output from the first and second voltage mode filter circuits 214-1 and 214-2 of the second differential voltage mode filter 214, respectively.

number

[0057] The current rectifier mixer stage 240 is configured to perform analog I / Q modulation and baseband to RF frequency upconversion. As shown in Figure 2, the current rectifier mixer stage 240 is configured to perform complementary in-phase LO signal LO_I and

number

number

number

number

[0058] The signal attenuation stage 250 controls the differential multi-bit attenuated control signal V ATTN and

number

[0059] In some embodiments, the RF signal generator system 200 generates a complementary in-phase baseband signal I(t) and

number

number

number

number

[0060] Figure 3 schematically shows a voltage-mode filter circuit according to an exemplary embodiment of the present disclosure. In particular, Figure 3 schematically shows a voltage-mode filter circuit 300, which in some embodiments is used to implement each of the voltage-mode filter circuits 212-1, 212-2, 214-1, and 214-2 in Figure 2. In addition, Figure 3 schematically shows a DAC circuit 302 (e.g., a current-steering DAC circuit) interfaced with the voltage-mode filter circuit 300. The voltage-mode filter circuit 300 includes an input node N1, which takes as input an analog baseband input voltage signal V generated by the DAC circuit 302. IN Receive.

[0061] The DAC circuit 302 has a DAC current I DAC A current source 305 generates the current, and a load resistor R is connected between node N1 and the ground node VSS. L It should be understood that Figure 3 provides a high-level schematic illustration of a current steering DAC circuit having a current source architecture represented by a current source 305, which comprises a current source array (e.g., an array of transistors) controlled by an n-bit digital signal (e.g., b1, b2, ..., bn) where each bit causes the current source 305 to switch to output a fixed amount of current to node N1. Current output from current source 305 (I OUT ) is related

number

[0062] The voltage-mode filter circuit 300 comprises an analog dual-order low-pass filter framework comprising a first transistor M1 (e.g., a PMOS transistor), a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The voltage-mode filter circuit 300 further comprises a second transistor M2 that functions as a bias transistor (i.e., a current source). The first resistor R1 is coupled to the input node N1 and to the second node N2 (alternatively, the feedback node N2). The second resistor R2 is coupled to the second node N2 and to the third node N3. The first capacitor C1 is coupled to the second node N2 and to the fourth node N4, thereby providing a feedback path (from node N4 to node N2) for the voltage-mode filter circuit 300. The second capacitor C2 is coupled to the third node N3 and the negative power supply voltage node VSS. The first transistor M1 has a gate terminal connected to the third node N3, a source terminal connected to the fourth node N4 (i.e., connected to the feedback path of the voltage mode filter circuit 300), and a drain terminal connected to the negative power supply voltage node VSS.

[0063] As described above, the second transistor M2 (e.g., a Miller transistor) provides a bias current I to operate the voltage mode filter circuit 300 at a given operating point. BIAS The system includes a bias element configured to generate a bias voltage V. The second transistor M2 has a bias voltage V BP This is a PMOS transistor having a gate terminal that receives a bias voltage V, a source terminal coupled to a positive power supply node VDD_BBF, and a drain terminal coupled to a fourth node N4. In some embodiments, the bias voltage V BP This comprises a DC voltage generated by the reference circuit of the current mirror circuit and applied to the gate terminal of the second transistor M2. In some embodiments, the second transistor M2 is a reference current I generated by the reference circuit of the current mirror circuit, as understood by those skilled in the art. REF The bias current I is proportional to (for example, in a ratio of 1:1 or a larger ratio). BIAS This is a mirror transistor in a current mirror circuit that generates (an exemplary embodiment of this is shown in Figures 4A and 4B).

[0064] The voltage-mode filter circuit 300 features an analog bi-order low-pass filter framework, which is a variation of a second-order (two-complex pole) low-pass Sallen-Key filter (or positive feedback filter). The Sallen-Key filter configuration in Figure 3 is implemented using a single transistor, namely the first transistor M1, in a source follower configuration (providing a unity-gain source follower buffer), instead of the operational amplifier typically implemented in conventional Sallen-Key and bi-order low-pass filter designs. In the voltage-mode filter circuit 300, the filter feedback loop is implemented by coupling the source terminal of the first transistor M1 to the feedback node N2 through the first capacitor C1.

[0065] Compared to conventional dual-order low-pass filter circuits, the implementation of a Sallen-Key filter circuit architecture based on a single-transistor (source follower) active stage (as shown in Figure 3) offers lower power consumption, lower distortion, and a smaller footprint (less area occupied). In addition, by using the voltage-mode filter circuit 300, the analog signal path can be implemented in an RF signal generator system along with a baseband filter stage that operates at relatively low supply voltages VDD_BBF (e.g., 500mV to approximately 700mV) for low power consumption.

[0066] In the exemplary embodiment shown in Figure 3, the voltage output (V) of the voltage mode filter circuit 300 OUT The signal is obtained at the fourth node N4, which is the source terminal of the first transistor M1. In other words, the fourth node N4 is the output node of the active source follower stage of the voltage mode filter circuit 300. Ignoring the load of the next stage and assuming that the active source follower stage has a zero (0) output impedance (in the ideal case), the frequency response H(s) (i.e., the s-domain transfer function) of the voltage mode filter circuit 300 is expressed as follows:

number

number

number

number

number

[0067] On the other hand, the active source follower stage has a non-zero output impedance at node N4, which introduces an additional "zero" in the transfer function of the voltage mode filter circuit 300, and consequently degrades the low-pass response of the voltage mode filter circuit 300. To reduce the output impedance, a larger sized device can be used for transistor M1, and the bias current I BIAS This can be increased. In practical use, as the bias current increases, it may be required to increase the device width of transistor M2 as well. In any case, an increase in static bias current will increase the power dissipation of the voltage mode filter circuit 300, which is undesirable. In addition, a larger transistor device for M1 will result in an increase in parasitic capacitance, which will limit the bandwidth of the voltage mode filter circuit 300.

[0068] Therefore, in the non-ideal case, in order to achieve low-power operation, the active source follower stage will have a non-zero output impedance that introduces an additional "zero" in the transfer function of the voltage-mode filter circuit 300, as described above, resulting in a degraded filter response. In particular, if the active source follower stage is R OUT Assuming that it has an output impedance expressed as , the voltage-mode filter circuit 300 will have a frequency response H(s) expressed as follows:

number

[0069] In some embodiments, the voltage mode filter circuit 300 connects an additional PMOS source follower buffer circuit to the gate terminal (node ​​N3) of the first transistor M1, and outputs a voltage (V) from the source node of the additional PMOS source follower buffer circuit. OUT By obtaining ), it can be modified to provide a better filter response. In this configuration, the common-mode voltage at input node N1 of the voltage-mode filter circuit 300 is the same as the common-mode voltage at node N3, which will serve as the input node to an additional PMOS source follower buffer circuit. The additional buffer circuit will function to buffer the output of the voltage-mode filter circuit 300, thereby isolating the output node from the load of the feedback capacitor C1 and the rest of the feedback path. This further isolation will improve the frequency response of the filter and enhance out-of-band rejection. However, for low-power applications, the additional PMOS buffer circuit will result in increased power dissipation due to the static bias current of the additional PMOS buffer circuit, which is undesirable. Furthermore, the additional PMOS buffer circuit will increase the footprint of the voltage-mode filter circuit 300, which may be undesirable.

[0070] As described above, output impedance neutralization techniques are implemented to neutralize the non-zero output impedance of the voltage-mode filter circuit 300, thereby improving the low-pass filter frequency response and, in particular, out-of-band rejection of the voltage-mode filter circuit 300. In some embodiments, differential neutralization schemes using feedforward passive impedance splits are implemented to inject current from the input nodes of the differential voltage-mode filter circuit to the output nodes of the differential voltage-mode filter circuit from the opposite polarities of the input signals at the input nodes of the differential voltage-mode filter circuit to compensate (e.g., cancel out) the transmit zeros. For example, Figure 4A schematically shows a differential voltage-mode filter circuit with an output impedance neutralization network that improves the out-of-band rejection filter response, according to an exemplary embodiment of the present disclosure.

[0071] More specifically, Figure 4A schematically shows a differential voltage-mode filter circuit 400 comprising a first voltage-mode filter circuit 400-1, a second voltage-mode filter circuit 400-2, a current reference circuit 410, and a neutralization network 420. The neutralization network 420 comprises a first neutralization impedance circuit 420-1 and a second neutralization impedance circuit 420-2 in an interconnected configuration. In some embodiments, the first voltage-mode filter circuit 400-1 and the second voltage-mode filter circuit 400-2 each have the same circuit architecture as the voltage-mode filter circuit 300 in Figure 3, the details of which are not repeated. The current reference circuit 410 comprises a transistor M3 and a reference current I REF The current reference circuit 410 includes a constant current source 412 that generates a static bias voltage V applied in common to the gate terminals of the second transistor M2 of the first and second voltage mode filter circuits 400-1 and 400-2. BP It is configured to generate a current reference circuit 410 and a second transistor M2, which form a current mirror circuit, with transistor M3 including a reference transistor and the second transistor M2 including a mirror transistor of the current mirror circuit, and each of the second transistor M2s being the reference current I of the current reference circuit 410. REFThe bias current I is proportional to (for example, in a ratio of 1:1 or a larger ratio). BIAS This will cause it to happen.

[0072] Figure 4A shows that the differential voltage mode filter circuit 400 (i) the complementary input signal V IN and

number

number

number

number

number

[0073] Furthermore, as schematically shown in Figure 4A, the input node N1 of the first voltage-mode filter circuit 400-1 is coupled to the output node N4 of the second voltage-mode filter circuit 400-2 through the first neutralizing impedance circuit 420-1. Similarly, the input node N1 of the second voltage-mode filter circuit 400-2 is coupled to the output node N4 of the first voltage-mode filter circuit 400-1 through the second neutralizing impedance circuit 420-2. In some embodiments, the first and second neutralizing impedance circuits 420-1 and 420-2 are each connected by a resistor R N and capacitor C N The circuit includes passive impedance elements. The first and second neutralizing impedance circuits 420-1 and 420-2 are each configured to inject current into the output node from the opposite polarity of the input signal, using passive impedance components to effectively counteract the effects of the non-zero output impedances of the first and second voltage-mode filter circuits 400-1 and 400-2. In this regard, the exemplary output impedance neutralization technique utilizes a differential signal architecture to neutralize the adverse effects of the non-zero output impedances of the first and second voltage-mode filter circuits 400-1 and 400-2 on the low-pass filter response of the first and second voltage-mode filter circuits 400-1 and 400-2.

[0074] In the exemplary embodiment shown in Figure 4A, the neutralization network 420 can be configured to provide an improved low-pass filter frequency response by, for example, using high out-of-band attenuation / rejection to provide a higher bandwidth and a sharper frequency response. For example, assuming that the first voltage-mode filter circuit 400-1 and the second voltage-mode filter circuit 400-2 are essentially identical in circuit architecture and component values, and that transistor M1 each has an output impedance R out Assuming that the following is true, the frequency response H(s) of the first voltage-mode filter circuit 400-1 and the second voltage-mode filter circuit 400-2 can be expressed as follows:

number

number

number

[0075] The molecular number is R N Set =R1 and

number

number

[0076] This is in contrast to the frequency response H(s) of the voltage-mode filter circuit 300 (FIG. 3) having two "zeros" and two "poles" as discussed above in the absence of an output impedance neutralization network. In this regard, the output impedance neutralization network 420 reduces the effect of the non-zero output impedance R OUT (i.e., the output impedance at the source node N4 of the source follower transistor M1), and improves the filter frequency response.

[0077] FIG. 4B schematically shows a differential voltage-mode filter circuit including an output impedance neutralization network, according to another exemplary embodiment of the present disclosure. In particular, FIG. 4B shows the capacitors C1 and C2 of the first and second voltage-mode filter circuits 400-1 and 400-2, and the capacitor C of the neutralization network 420 N and schematically shows a differential voltage-mode filter circuit 401 that is similar to the differential voltage-mode filter circuit 400 of FIG. 4A, except that the capacitors C1, C2, and C N are implemented as digitally controllable variable capacitors. In this regard, the capacitance values of the variable capacitors C1, C2, and C

[0078] The exemplary output impedance neutralization networks and techniques discussed herein can be configured to compensate for the adverse effects of the non-zero output impedance of the unity-gain buffer stage of a voltage-mode filter circuit (e.g., the unity-gain source-follower buffer stage of a Sallen-Key filter circuit) by adding one or more transmitting poles to the filter transfer function, and it should be noted that such transmitting poles do not strictly "cancel out" the transmit zeros, but rather are close enough to effectively compensate for the transmit zeros in a manner that corrects or otherwise improves the frequency response of the voltage-mode filter circuit as discussed herein. While Figures 4A and 4B show exemplary filter embodiments implementing one stage of differential voltage-mode filter circuits 400 and 401, respectively, it should be further noted that in other embodiments, multiple instances of the differential voltage-mode filter circuit 400 or the differential voltage-mode filter circuit 401 can be cascaded to form higher-order filters.

[0079] Figure 5 graphically shows the simulated responses of voltage-mode low-pass filters with and without output impedance neutralization according to exemplary embodiments of the present disclosure. In particular, Figure 5 is a graph 500 of voltage gain (dB) (y-axis) as a function of frequency (x-axis), which shows a first filter response curve 501 and a second filter response curve 502 of a voltage-mode low-pass filter with a single gain. Specifically, the first filter response curve 501 shows the simulated response of a voltage-mode low-pass filter without implementing output impedance neutralization, while the second filter response curve 502 shows the simulated response of a voltage-mode low-pass filter with implementing output impedance neutralization.

[0080] In the exemplary simulated filter response curves of Figure 5, the first filter response curve 501 has a cutoff frequency FC1 of approximately 197.1 MHz (at the -3 dB point), and the second filter response curve 502 has a cutoff frequency FC2 of approximately 226.4 MHz. In addition, the first filter response curve 501 is shown to exhibit poor out-of-band rejection due to the non-zero output impedance of the single transistor M1 (active source follower stage) of the voltage-mode low-pass filter. For example, portion 501-1 of the first filter response curve 501 includes a flat out-of-band response, which is undesirable. In contrast to the first filter response curve 501, Figure 5 shows that the second filter response curve 502 has a sharper frequency response over a wider frequency range and exhibits higher out-of-band rejection due to output impedance neutralization, which is highly desirable.

[0081] It should be understood that exemplary differential voltage-mode filter circuits with output impedance neutralization networks, such as those shown in Figures 4A and 4B, offer various advantages over other filter circuit configurations discussed herein. For example, differential voltage-mode filter circuits with output impedance neutralization networks enable ultra-low power, low supply voltage, and high bandwidth voltage-mode filters with improved frequency response (e.g., higher out-of-band rejection) as a result of neutralizing the adverse effects on the filter frequency response caused by the non-zero output impedance of the unity-gain buffer of the voltage-mode filter circuit. For example, the first and second voltage-mode filter circuits 400-1 and 400-2 of exemplary differential voltage-mode filter circuits 400 and 401 with output impedance neutralizing networks, such as those shown in Figures 4A and 4B, operate with low bias currents (e.g., 60 microamperes) and low supply voltages (e.g., 675 mV) to provide low power dissipation (e.g., about 40 microwatts), while simultaneously effectively neutralizing the non-zero output impedance of the active source follower stage, which is not negligible in such low-power operation.

[0082] Furthermore, the output impedance neutralization network 420 of the differential voltage mode filter circuit 400 (or 401) does not affect the DC bias and common mode compatibility of the DAC circuit coupled to the input of the differential voltage mode filter circuit 400 and the RF output stage coupled to the output of the differential voltage mode filter circuit 400. In particular, the output impedance neutralization network 420 comprises passive elements (e.g., resistors and capacitors) that do not require a DC bias. Additionally, the output impedance neutralization network 420 is completely decoupled from the DC bias of the first and second voltage mode filter circuits 400-1 and 400-2 due to the neutralization capacitors C N of the first and second neutralization impedance circuits 420-1 and 420-2. In this regard, the output impedance neutralization network 420 does not affect the differential voltage mode filter circuit 400 in terms of DC current bias, DC power consumption, and common mode voltage level, and the DC bias condition remains unchanged.

[0083] For example, in the exemplary embodiment of FIG. 3, the common mode voltage (V IN_CM ) at the input node N1 is set by the load resistor R L and the average current output from the current source 305. The common mode voltage (V OUT_CM ) at the output node N4 is higher than V SG by an amount equal to the source / gate voltage (V IN_CM ) of the PMOS source follower transistor M1 of the voltage mode filter circuit 300 (thus, V OUT_CM =V IN_CM +V SG ). With the addition of the output impedance neutralization network 420 such as that shown in FIG. 4A, V IN_CM or V OUT_CM of the first and second voltage mode filter circuits 400-1 and 400-2 does not change. Moreover, in the exemplary embodiment of FIG. 4B with the variable filter capacitors C1 and C2 and the variable neutralization capacitor C N , the neutralization capacitor C NThis allows the filter capacitors C1 and C2 to be tuned to track each other without affecting the DC bias or common-mode voltage at the input and output of the differential voltage-mode filter circuit 401.

[0084] Another advantage is that the output impedance neutralization network 420 of the differential voltage-mode filter circuit 400 (or 401) eliminates the need to connect an additional buffer stage to the output node N4 of the first and second voltage-mode filter circuits 400-1 and 400-2 to improve the frequency response of the filters. As described above, the output impedance neutralization network 420 functions to cancel out the transmit zeros and add an additional pole to the frequency response of the first and second voltage-mode filter circuits 400-1 and 400-2 without requiring an additional buffer stage which would undesirably increase the power dissipation and footprint of the filter circuits. The DC current is neutralized by the neutralizing capacitor C N Since power does not flow through it, the addition of the impedance neutralizing network 420 has zero cost in static power dissipation.

[0085] Figures 6A, 6B, 6C, and 6D schematically illustrate a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. More specifically, Figures 6A, 6B, 6C, and 6D schematically illustrate an RF signal generator system 600 having a system architecture based on the RF signal generator system 200 of Figure 2. Figures 6A and 6B collectively show a voltage mode filter stage comprising a first differential voltage mode filter 612 (Figure 6A) and a second differential voltage mode filter 614 (Figure 6B). The first differential voltage mode filter 612 comprises a first voltage mode filter circuit 612-1, a second voltage mode filter circuit 612-2, a current reference circuit 616-1 with a reference current source 618, and a neutralization network 613 comprising a first neutralization impedance circuit 613-1 and a second neutralization impedance circuit 613-2. The second differential voltage-mode filter 614 comprises a neutralization network 615 including a first voltage-mode filter circuit 614-1, a second voltage-mode filter circuit 614-2, a current reference circuit 616-2, and a first neutralization impedance circuit 615-1 and a second neutralization impedance circuit 615-2. The first and second differential voltage-mode filters 612 and 614 have the same circuit architecture, which is based on the exemplary architecture of the differential voltage-mode filter circuit 400 in Figure 4A, the details of which are not repeated.

[0086] Referring to Figure 6A, the first differential voltage mode filter 612 receives the respective complementary common-mode baseband voltage signals I'(t) and

number

number

number

number

number

[0087] Furthermore, referring to Figure 6B, the second differential voltage mode filter 614 processes the respective complementary quadrature phase baseband voltage signals Q'(t) and

number

number

number

number

number

[0088] Figure 6C schematically illustrates an exemplary embodiment of a current-mode RF output stage that can be directly interfaced with the voltage-mode outputs of the first and second differential voltage-mode filters 612 and 614. More specifically, Figure 6C schematically illustrates an exemplary embodiment of a current-mode RF output stage 620 having an architecture based on the current-mode RF output stage 220 of Figure 2. The current-mode RF output stage 620 comprises a baseband signal stage 630, a current rectifier mixer stage 640, a signal attenuation stage 650, a differential / single-ended output circuit 660 (alternatively, an output transformer stage 660), a first DC offset compensation DAC 670, and a second DC offset compensation DAC 672. The RF signal generator system 600 further comprises a regulating system 680, which comprises a voltage regulator circuit 682 and a replica bias circuit 684, the functions of which will be described in more detail below.

[0089] The baseband signal stage 630 comprises a plurality of baseband input transistors 631, 632, 633, and 634 (e.g., PMOS transistors). Baseband input transistors 631 and 632 comprise a first differential transistor pair 630-1, and the baseband input transistors 631 and 632 have source terminals that are commonly connected to the output terminals of the voltage regulator circuit 682, and complementary baseband voltage signals I(t) and output from the first and second voltage mode filter circuits 612-1 and 612-2 of the first differential voltage mode filter 612 (Figure 6A), respectively.

number

number

[0090] In some embodiments, the baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 are connected to the I / Q signal path I + , I - Q + , and Q -The system includes a variable gain element (circularly shown by a diagonal arrow across the transistor) that can be configured to adjust the baseband signal gain. For example, in some embodiments, each baseband input transistor 631, 632, 633, and 634 varies the effective gate width of the transistor structure and therefore the static DC drain current I that flows through each baseband input transistor 631, 632, 633, and 634 when operating in saturation mode. D_1 , I D_2 , I D_3 , and I D_4 The system includes a variable-width transistor structurally configured and controlled using known techniques to adjust the maximum amount of (e.g., quiescent current). In this regard, the baseband input transistors 631, 632, 633, and 634 in the baseband signal stage 630 have transconductance (g m )tuning

number

[0091] For example, in some embodiments, each baseband input transistor 631, 632, 633, and 634 can be structurally configured to include multiple transistor segments coupled in parallel, and the number of segments that are enabled / disabled at a given time (via a digital switching control system) can be adjusted to change the effective gate width of a given baseband input transistor. In this regard, the effective width of the baseband input transistors 631, 632, 633, and 634 in the baseband signal stage 630 is set across the I / Q signal path I over a target gain range (e.g., a gain range of 20 dB) having multiple gain step settings within the gain range. + , I - Q + , and Q - It can be configured to adjust the baseband signal gain in the I / Q signal path I + , I - Q+ , and Q - The static DC baseband current in this system can be adjusted to one of several target current levels within a given range, with the highest baseband current level being approximately 10X higher than the lowest baseband current level (for example, in the range of approximately 35μA to 350μA).

[0092] The current rectifier mixer stage 640 comprises a differential I mixer 640-1 and a differential Q mixer 640-2. The differential I mixer 640-1 comprises a plurality of mixing transistors 641, 642, 643, and 644 (alternatively, I mixer switching transistors 641, 642, 643, and 644). The differential Q mixer 640-2 comprises mixing transistors 645, 646, 647, and 648 (alternatively, Q mixer switching transistors 645, 646, 647, and 648). In some embodiments, as shown in Figure 6C, the mixing transistors 641, 642, 643, 644, 645, 646, 647, and 648 are PMOS transistors. In some embodiments, mixed transistors 641, 642, 643, 644, 645, 646, 647, and 648 are biased to operate in triode mode.

[0093] In the differential I mixer 640-1, the mixing transistors 641 and 642 have a source terminal that is commonly connected to the drain terminal of the baseband input transistor 631 in the baseband signal stage 630, and a complementary in-phase LO signal LO_I and LO_I as inputs, respectively.

number

number

[0094] In differential Q mixer 640-2, mixing transistors 645 and 646 have source terminals commonly connected to the drain terminal of baseband input transistor 633 in baseband signal stage 630, and respective gate terminals for receiving complementary quadrature LO signals LO_Q and

Number

Number

[0095] Current rectifying mixer stage 640 includes two output nodes denoted as N OUT1 and N OUT2 As schematically shown in FIG. 6C, mixing transistors 641, 643, 645, and 647 have drain terminals commonly coupled to output node N of current rectifying mixer stage 640 OUT1 and mixing transistors 642, 644, 646, and 648 have drain terminals commonly coupled to output node N of current rectifying mixer stage 640 OUT2It has drain terminals commonly connected thereto. The differential I mixer 640-1 and the differential Q mixer 640-2 are configured to provide analog I / Q modulation and upconversion, where the connection of the mixing transistors of the differential I and Q mixers 640-1 and 640-2 (operating in triode mode) enables the summation / subtraction of the output currents of the mixing transistors 641, 642, 643, 644, 645, 646, 647, and 648 to achieve SSB I / Q modulation, as understood by those skilled in the art.

[0096] The signal attenuation stage 650 is configured to adjust the signal strength of the RF output signal RF_OUT. More specifically, in the exemplary embodiment of FIG. 6C, the signal attenuation stage 650 is configured to adjust the amount of differential current flowing from the output nodes N OUT1 and N OUT2 to the output transformer stage 660. In this regard, the signal attenuation stage 650 is configured to adjust the signal level of the signal output from the current rectifying mixer stage 640. The signal attenuation stage 650 includes a plurality of attenuation segments 650-1,..., 650-s that are digitally controlled by respective pairs

Number

[0097] In the first attenuation segment 650-1, the first differential pair of transistors 651 and 652 is connected to the mixer output node NOUT1 The source terminals are connected in common to each other, and differential control signals are used as inputs for each.

number

number

[0098] Similarly, in the attenuation segment 650-s, the first differential pair of transistors 655 and 656 is connected to the mixer output node N. OUT1 The source terminals are connected in common to each other, and differential control signals are used as inputs for each.

number

number

[0099] During operation, output node N OUT1 and N OUT2 The amount of differential current flowing from the output transformer stage 660 can be adjusted based on the number of activated attenuation segments 650-1, ..., 650-s. A given attenuation segment corresponds to the differential control signal V ATTN and

number

number

number

number

number

[0100] In this configuration, output nodes N OUT1 and N OUT2 The amount of differential current flowing from the output nodes N

[0101] In the exemplary I / Q modulation architecture of the RF signal generator system 600 shown in FIGS. 6A-6D, it is desirable to remove or otherwise substantially minimize the imbalance between the baseband I and Q signals for the purpose of image rejection. In practice, I / Q imbalance can result in an undesirable spectrum at the image frequency. As described above, the SSB mixer is configured to up-convert the intermediate frequency (IF) of the baseband signal to only one of the sideband signal center frequencies of LO + IF or LO - IF without creating an image of the other sideband signal, which is particularly useful when using a low IF frequency because frequency selective filtering is difficult in that case. For example, if the desired RF signal is to be generated at a frequency f RF = f LO - f IF In the case where it will occur at, f IF + f LOThe sideband signals (image signals) in this case will be suppressed by the sideband suppression provided by the SSB mixer. However, the amplitude imbalance of the baseband I and Q signals can result in the presence of relatively high spectral power for undesirable spectra at the image frequency.

[0102] Furthermore, differential analog I signal

number

number

number

number

number

number

[0103] In some embodiments, the first DC offset compensated DAC670 and the second DC offset compensated DAC672 are controlled by a calibration control system (e.g., the calibration control system 190 in Figure 1) to operate on the I / Q signal path I + , I - Q + , and Q - Static current I flowing through D_1 , I D_2 , I D_3 , and I D_4 It is used to correct the imbalance between them. As schematically shown in Figure 6C, the first DC offset compensation DAC 670 has a first output terminal coupled to the drain terminal of the baseband input transistor 631 and a second output terminal coupled to the drain terminal of the baseband input transistor 632. The second DC offset compensation DAC 672 has a first output terminal coupled to the drain terminal of the baseband input transistor 633 and a second output terminal coupled to the drain terminal of the baseband input transistor 634.

[0104] In this exemplary configuration, in response to a control signal received from the calibration control system (e.g., an n-bit digital control signal [n-1:0]), the first DC offset compensation DAC670 adjusts the static bias current I D_1 and I D_2 To compensate for any offset between them, an additional current I may be added as needed. C_1 and I C_2 to I + and I - It is configured to inject into the signal path. In particular, an additional current I C_1 and I C_2 This is the static bias current I generated by the respective baseband input transistors 631 and 632. D_1 and I D_2 It is added to, and as a result, static I + and I - The baseband current is equalized, and therefore the static I applied to the input of I mixer 640-1 + and I -Any DC offset during the baseband current is significantly reduced or eliminated. Similarly, in response to a control signal received from the calibration control system (e.g., an n-bit digital control signal [n-1:0]), the second DC offset compensation DAC672 adjusts the static bias current I D_3 and I D_4 To compensate for any offset between them, an additional current I may be added as needed. C_3 and I C_4 Q + and Q - It is configured to be injected into the baseband signal path. In particular, the additional current I C_3 and I C_4 This is the static bias current I generated by the baseband input transistors 633 and 634, respectively. D_3 and I D_4 It is added to, and as a result, static Q + and Q - The baseband current is equalized, and therefore the static Q applied to the input of Q mixer 640-2 + and Q - Any DC offset during baseband current is significantly reduced or eliminated.

[0105] In the baseband signal stage 630, matching between the first differential pair of baseband input transistors 631 and 632, and between the second differential pair of baseband input transistors 633 and 634 is important. In addition, matching between the first differential transistor pair 630-1 and the second differential transistor pair 630-2 is important. Mismatch between transistors in the baseband signal stage 630 can cause imbalance in the I / Q baseband current signal, which can lead to LO leakage and insufficient image rejection. In some embodiments, a calibration control system (e.g., calibration control system 190 in Figure 1) implements a control circuit and calibration method for configuring the RF signal generator system 600 to operate in calibration mode, and the calibration control system controls the I / Q signal path I + , I - Q + , and Q - Static current I flowing through D_1 , ID_2 , I D_3 , and I D_4 It measures the same relative {I} and provides indication of the DC offset leading to LO leakage. + ,I -} and {Q + ,Q - Determine the difference between them and the measured I + and Q + The difference (imbalance) between baseband currents can be determined, + and Q + An imbalance in baseband currents can degrade image rejection, leading to the presence of undesirable sideband spars.

[0106] It should be noted that imbalances between static baseband currents can be adjusted via the first and second DC offset compensating DACs 670 and 672, and / or I-DAC circuits 602-1 and 602-2 (Figure 6A) and Q-DAC circuits 604-1 and 604-2 (Figure 6B). For example, by utilizing the first and second DC offset compensating DACs 670 and 672 in the current-mode RF output stage 620, two static baseband currents corresponding to a given phase, e.g., {I + and I -} and {Q + and Q - Any imbalance (offset) between} is guaranteed to be minimized. On the other hand, in some embodiments, the DC offset compensated DAC uses a baseband current I + and Q + To correct the imbalance between them, compensation current can be injected into the voltage-mode output interfaces of the I-DAC circuits 602-1 and 602-2 (Figure 6A) and the Q-DAC circuits 604-1 and 604-2 (Figure 6B). Therefore, the ability to correct the imbalance is provided by utilizing the first and second DC offset compensation DACs 670 and 672 in the current-mode RF output stage 620, along with the DC offset compensation implemented with the I-DAC and Q-DAC circuits 602 and 604, and all static baseband currents I + , I - Q +, and Q - It is guaranteed that they are essentially equal in size.

[0107] Using the exemplary architecture of the RF signal generator system 600 as shown in Figures 6A to 6D, the output nodes N4 of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 are directly connected (DC coupled) to the gate terminals of the respective baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 of the current-mode RF output stage 620. However, it should be noted that interfacing the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 with the baseband signal stage 630 is not obvious, as directly connecting the voltage-mode outputs of the baseband filter transistors to the transistors in the baseband signal stage 630 typically does not provide a suitable bias for the transistors in the current-mode RF output stage 620 (unlike the current-mode connection provided between the current-mode baseband filter and the current-mode output stage based on a current mirror).

[0108] In particular, the quiescent current (e.g., I) generated by the baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 of the current-mode RF output stage 620. D1 , I D2 , I D3 , and I D4 ) is particularly sensitive to power supply voltage fluctuations in cases where the output common-mode voltages of each of the voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 are ground-referenced (e.g., VSS), while the bias of the baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 is referenced to the positive power supply (e.g., VDD). More specifically, the DC bias of the baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 is VSS.SG It is based on the bias voltage, V SG The bias is referenced to the positive power supply VDD. On the other hand, the output common-mode voltages of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 are essentially ground-referenced (referenced to VSS) and therefore do not depend on the positive power supply. In this regard, since the output common-mode voltages of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 are applied directly to the gate terminals of the respective baseband input transistors 631, 632, 633, and 634, fluctuations in the positive power supply voltage VDD affect the V of the baseband input transistors 631, 632, 633, and 634. SG This causes voltage fluctuations, and consequently, fluctuations in the quiescent current (or bias current) flowing in the analog I / Q signal path of the current-mode RF output stage 620. In other words, it affects the V of the baseband input transistors 631, 632, 633, and 634. SG Since the bias is based on the difference between the output common-mode voltage and the supply voltage VDD of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2, the quiescent current I generated by the baseband input transistors 631, 632, 633, and 634 is D1 , I D2 , I D3 , and I D4 It is highly sensitive to fluctuations in the power supply voltage VDD, which can lead to an unstable bias point for the current-mode RF output stage 620.

[0109] In this regard, the quiescent current (for example, I) generated by the baseband input transistors 631, 632, 633, and 634 in the baseband signal stage 630 D1 , I D2 , I D3 , and I D4Various techniques can be implemented to interface the voltage-mode baseband filter circuit to the current-mode RF output stage 620 while ensuring that the quiescent current (e.g., I) remains constant at the target current level. Generally, such techniques provide a mechanism for adjusting the voltage at the source nodes of the first differential transistor pair 630-1 and the second differential transistor pair 630-2, thereby allowing the baseband input transistors 631, 632, 633, and 634 to bias the current-mode RF output stage 620 at the desired quiescent current level (e.g., I D1 , I D2 , I D3 , and I D4 To achieve this, an appropriate gate / source voltage (V) in saturation mode is required. SG ) is biased.

[0110] Figure 6C shows that the adjustment system 680 has the source nodes of the baseband input transistors 631, 632, 633, and 634 connected in common, N Reg The regulated voltage node is denoted as (alternatively, the regulated node N Reg This illustrates an exemplary embodiment configured to generate a regulated positive power supply voltage, denoted as VDD_RF_Reg, which is applied to the regulated node N. Reg The replica bias circuit 684 is configured to operate in conjunction with generating the regulated positive power supply voltage VDD_RF_Reg applied to the current-mode RF output stage 620, thereby enabling the first and second differential voltage-mode filters 612 and 614 to interface with the current-mode RF output stage 620 while providing a well-controlled bias point for the current-mode RF output stage 620. The replica bias circuit 684 is configured to generate a reference voltage VDD_Replica, which is input to the voltage regulator circuit 682 and controls the output common-mode voltage level on the output nodes of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2 to control node N RegThe regulated voltage VDD_RF_Reg is generated above, thereby a constant V for the baseband input transistors 631, 632, 633, and 634. SG This is used to maintain a well-controlled quiescent current in the I / Q signal path of the current-mode RF output stage 620, thereby achieving a stable bias point for the current-mode RF output stage 620.

[0111] In some embodiments, the voltage regulator circuit 682 includes a low-dropout (LDO) voltage regulator circuit configured to receive (i) an unadjusted positive supply voltage VDD_RF_Unreg and (ii) a reference voltage VDD_Replica output from a replica bias circuit 684 as inputs, and to generate an adjusted supply voltage VDD_RF_Reg corresponding to VDD_Replica. The LDO voltage regulator circuit is a DC linear voltage regulator configured to adjust the LDO output voltage (VDD_RF_Reg) even when the unadjusted positive supply voltage VDD_RF_Unreg is close to the LDO output voltage. In some embodiments, VDD_RF_Unreg is a supply voltage of about 900mV or lower applied from a positive supply node. The voltage regulator circuit 682 is configured to adjust the node N Reg The above voltage is monitored, and the regulated power supply voltage VDD_RF_Reg is actively adjusted to ensure that VDD_RF_Reg corresponds to VDD_Replica. In this regard, the regulating system 680 controls the regulated node N Reg The above voltage is configured to actively adjust to correspond to VDD_Replica, which is set by the replica bias circuit 684.

[0112] In some embodiments, the replica bias circuit 684 comprises replicas of the circuit components of the voltage-mode baseband filter and RF output stack. In this regard, the replica bias circuit 684 will vary depending on the circuit architecture of the voltage-mode baseband filter and RF output stack. For example, Figure 6D schematically shows an exemplary embodiment of the replica bias circuit 684, which comprises replica elements corresponding to the components of the voltage-mode baseband filter and current-mode RF output stage 620. In particular, in the exemplary embodiment of Figure 6D, the replica bias circuit 684 comprises a first replica current source 690, a second replica current source 691, and a replica resistor R S , and replica transistors 692, 693, 694, 695, and 696. First replica current source 900 and replica resistor R S These are the DAC current source and load resistor R, respectively, of one instance of the voltage-mode interface between the DAC circuit and the voltage-mode baseband filter circuit. L The replica transistors 692 and 693 correspond to transistors M1 and M2 of one instance of the voltage-mode baseband filter circuit (e.g., 612-1, 612-2, 614-1, and 614-2), respectively. Replica transistor 694 corresponds to one instance of the baseband input transistor in the baseband signal stage 630. Replica transistor 695 corresponds to one instance of the LO switching transistor in the current rectifier mixer stage 640. Replica transistor 696 corresponds to one instance of the transistor in the signal attenuation stage 650. Note that the DC voltage drop across the output transformer stage 660 is negligible, so the wiring resistance of the output transformer stage 660 does not need to be included in the replica bias circuit 684.

[0113] To match the common-mode voltage on node N5 with the common-mode voltage on node N1, the first replica current source 690 is,

number

[0114] The second replica current source 691 is configured to generate a bias current of magnitude α*I2 that flows through the current path of replica transistors 694, 695, and 696, where I2 is the desired bias current for the current-mode RF output stage 620, and α is the scalar multiplier, where α << 1. In the replica bias circuit 684, replica transistors 694 and 696 are configured to operate in saturation mode (similar to the transistors in the baseband signal stage 630 and signal attenuation stage 650), while replica transistor 695 is configured to operate in triode mode (similar to the mixing transistor in the current rectifier mixer stage 640). In some embodiments, the second replica current source 691 is a variable current source that allows adjustment of the bias current of magnitude α*I2 in response to adjustment of the desired bias current I2 for the current-mode RF output stage 620, for example, when the gain of the baseband signal stage 630 is scaled (increased or decreased) to change the output amplitude of the RF output signal.

[0115] Replica transistors 692, 693, 694, 695, and 696 have a width / length (W / L) dimension ratio designed based on the W / L dimension ratio of the corresponding transistors in the voltage-mode filter circuit and current-mode RF output stage. For example, the W / L dimension ratio of the replica transistors is designed accordingly based on the following:

number

number

[0116] The dimensions of replica transistors 692 and 693 are such that the replica bias circuit 684 generates a voltage at node N6 corresponding to the output common-mode voltage generated at node N4 of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2, which are applied to the gate terminals of the respective baseband input transistors 631, 632, 633, and 634. In addition, the dimensions of replica transistors 694, 695, and 696 are such that the replica bias circuit 684 generates a voltage at node N7 corresponding to the output common-mode voltage of the single-ended voltage-mode baseband filter circuits 612-1, 612-2, 614-1, and 614-2, corresponding to the regulated node N Reg A reference voltage VDD_Replica is generated corresponding to the voltage that needs to be applied to the baseband input transistors 631, 632, 633, and 634, and the appropriate voltage is generated for them. SG The system is configured to establish a bias voltage, thereby obtaining a constant and stable bias current I2 generated by the baseband signal stage 630, and properly biasing the current-mode RF output stage 620.

[0117] As described above, in some embodiments, the baseband input transistors 631, 632, 633, and 634 of the baseband signal stage 630 (Figure 6C) include variable gain elements that can be configured (via digital control signals) to adjust the baseband signal gain in the I / Q signal paths I+, I-, Q+, and Q-. In other embodiments, the gain control system can be implemented at a voltage interface between the DAC circuit and the voltage mode filter circuit to provide fine gain control, for example (via a variable load resistor), while utilizing the baseband signal stage 630 to provide coarse gain control by, for example, enabling a variable number of segments of the baseband input transistors 631, 632, 633, and 634. For example, Figure 7 schematically shows a gain control system implemented at the interface between the DAC circuit and the voltage mode filter circuit of an RF signal generator system according to an exemplary embodiment of the present disclosure. More specifically, Figure 7 schematically shows an exemplary embodiment of a DAC circuit 702 (e.g., an I-DAC circuit) coupled to a differential voltage mode filter (e.g., a first differential voltage mode filter 612, Figure 6A) according to an exemplary embodiment of the present disclosure, the DAC circuit 702 comprising a variable load resistor that can be programmed to tune to enable fine gain control in the baseband signal path (e.g., the I signal path).

[0118] As schematically shown in Figure 7, the DAC circuit 702 comprises a first DAC circuit 702-1 and a second DAC circuit 702-2. The first DAC circuit 702-1 controls the DAC current I P A current source 703-1 generates a common-mode voltage, and a variable resistor R is configured to set the common-mode voltage at the input node N1 of the first single-ended voltage-mode baseband filter circuit 612-1. CM1 It is equipped with a voltage mode output interface. The second DAC circuit 702-2 has a DAC current I N (DAC current I PA current source 703-2 that generates (complementary to) and a variable resistor R configured to set the common-mode voltage at the input node N1 of the second single-ended voltage-mode baseband filter circuit 612-2 CM2 It is equipped with a voltage mode output interface. In addition, the voltage mode output interface of the DAC circuit 702 is connected between the input nodes N1 of the first and second voltage mode filter circuits 612-1 and 612-2, and a variable resistor R DM It is equipped with.

[0119] In the example circuit configuration shown in Figure 7, the variable resistor R CM1 and R CM2 The resistance value of the variable resistor R can be tuned using a calibration control signal to adjust the magnitude of the common-mode voltage at input node N1 of the first and second voltage-mode filter circuits 612-1 and 612-2, or otherwise calibrated. More specifically, the variable resistor R CM1 and R CM2 The resistance value of can be increased or decreased to increase or decrease the common-mode voltage at input node N1 of the first and second voltage-mode filter circuits 612-1 and 612-2. In addition, the variable resistor R DM The resistance value can be tuned using a calibration control signal to adjust the magnitude of the differential voltage (e.g., differential voltage swing) between the input nodes N1 of the first and second voltage-mode filter circuits 612-1 and 612-2, or otherwise calibrated.

[0120] Variable resistor R DM In the absence of the load resistor R, the magnitude of the differential voltage swing between the input nodes N1 of the first and second voltage-mode filter circuits 612-1 and 612-2 will increase / decrease when the common-mode voltage at input node N1 increases / decreases. In fact, in this case, the amplitude of the output voltage on node N1 is related to the load resistor R by the V=IR relationship. CM1 and R CM2 This will depend on the resistance value of the load resistor R. CM1 and R CM2An increase in the resistance value will result in a larger amplitude voltage being generated on node N1, which will lead to a larger differential voltage swing between the input nodes N1 of the first and second voltage-mode filter circuits 612-1 and 612-2 (which may be undesirable).

[0121] Variable resistor R DM This is a variable load resistor R CM1 and R CM2 Independent of common-mode voltage adjustment achieved by tuning the variable resistor R, a mechanism is provided for adjusting the magnitude of the differential voltage between the input nodes N1 of the first and second voltage-mode filter circuits 612-1 and 612-2. In practice, with respect to differential voltage tuning, a variable resistor R DM This is a variable resistor R CM1 and R CM2 Each of them is in parallel, and therefore the variable resistor R DM This functions to reduce the differential voltage swing between input nodes N1. In effect, it acts as a variable resistor R. DM The implementation breaks the link between the common-mode voltage and differential voltage swing (for DC biasing purposes), and therefore provides a second degree of freedom for adjusting the differential voltage swing at the input node N1 of the first and second voltage-mode filter circuits 612-1 and 612-2.

[0122] Figure 7 shows an exemplary embodiment for providing fine tuning of the baseband voltage signal gain in the I signal path, but the same technique will be applied to enable fine tuning of the baseband voltage signal gain in the Q signal path. For example, a Q DAC circuit similar to the I DAC circuit 702 will be implemented in (Figure 6B) with a variable resistor to allow adjustment of (i) the common-mode voltage at input node N1 of the first and second voltage-mode filter circuits 614-1 and 614-2, and (ii) the magnitude of the differential voltage swing between input node N1 of the first and second voltage-mode filter circuits 614-1 and 614-2. The exemplary gain control technique shown in Figure 7 is applied to the complementary in-phase baseband voltage signals I(t) and that are output from the first and second differential voltage-mode filters 612 and 614 and applied to the input of the baseband signal stage 630.

number

number

number

[0123] The exemplary radio frequency signal generation systems described herein are configured to operate at relatively low supply voltages and low power consumption (e.g., in the milliwatt range), so it should be understood that these radio frequency signal generation systems can be implemented together with cryoelectronics used in quantum computing applications and other applications or systems operating at cryogenic temperatures. For example, in the context of a quantum computing system implementing superconducting qubits and other components, the exemplary radio frequency signal generation system discussed herein can be implemented as an AWG system configured to generate RF control pulses to control superconducting qubits to perform high-fidelity qubit gate operations (e.g., single qubit gate operations, entangled gate operations, etc.).

[0124] For example, Figure 8 schematically shows a quantum computing system 800 that implements an arbitrary waveform generator system and a calibration circuit according to an exemplary embodiment of the present disclosure. The quantum computing system 800 comprises an arbitrary waveform generator system 802 (or AWG system 802) and a quantum processor 804. The quantum processor 804 comprises a plurality (n) of superconducting qubits 806-1, ..., 806-n. The superconducting qubits 806-1, ..., 806-n may include superconducting transmon qubits, superconducting fraxonium qubits, superconducting multimode qubits, and other types or combinations of different types of superconducting qubits suitable for a given application. Furthermore, in some embodiments, the quantum processor 804 includes a coupler circuit (e.g., a passive coupler circuit and / or an active coupler circuit) which is configured to couple pairs of superconducting qubits to implement entangled gate operations (e.g., 2-qubit gate operations).

[0125] The quantum processor 804 further comprises several control lines (e.g., transmit line resonators), including, but not limited to, qubit drive lines, flux bias lines, state readout lines, and active coupler drive lines. In some embodiments, the qubit drive lines are coupled (e.g., capacitively coupled) to each of the superconducting qubits 806-1, ..., 806-n. The qubit drive lines are configured to apply control pulses (generated by the AWG system 802) to each of the superconducting qubits 806-1, ..., 806-n to independently change the state of each superconducting qubit (e.g., a single qubit gate operation), for example, to change the state of a given superconducting qubit to, for example, a grounded state |0>, an excited state |1>, or a superposition state. As is known in the art, the state of a superconducting qubit is determined by the transition frequency (f) of the qubit. 01 It can be changed by applying a microwave control pulse at a center frequency equal to (denoted as), and the transition frequency f 01 This corresponds to the energy difference between the grounded state |0> and the excited state |1> of the qubit. In some embodiments, the superconducting qubits 806-1, ..., 806-n are configured to have different operating frequencies (transition frequencies) such that the transition frequencies of neighboring qubits are detuned.

[0126] State readout lines are coupled to each of the superconducting qubits 806-1, ..., 806-n to read out the state of the superconducting qubit using known techniques (e.g., distributed readout). In embodiments in which the superconducting qubits include frequency-tunable qubits (e.g., flux-tunable transmon qubits or fluxonium qubits, etc.), flux-bias control lines are coupled to each superconducting qubit (e.g., inductively) to apply a flux-bias control signal to the tuning structure of the superconducting qubit to tune the operating frequency of the tunable qubit, as required for a given application. In addition, in the case of active coupler circuits, coupler drive lines are coupled to each coupler circuit (e.g., capacitively), and each coupler circuit has an operating frequency or transition frequency. A given coupler circuit is driven by control pulses generated by the AWG system 802 or some other pulse signal generator to enable exchange coupling between superconducting qubits coupled through the given coupler circuit and to implement two-qubit gate operations.

[0127] As shown in Figure 8, the AWG system 802 comprises a multi-channel AWG framework with multiple AWG channels 802-1, ..., 802-c. The AWG channels 802-1, ..., 802-c are configured to generate control pulses that are applied to the qubit drive lines to control each of the superconducting qubits 806-1, ..., 806-n. Although not specifically shown in Figure 8, in some embodiments, the AWG system 802 will include AWG channels for generating control signals that are applied to the coupler drive lines to control the active coupler device of the quantum processor 804.

[0128] Each AWG channel 802-1, ..., 802-c comprises a control pulse envelope generator 810, a DAC stage 820, a filter stage 830, an I / Q mixer stage 840, an amplifier / attenuator stage 850, a matching network 860, an LO signal generator circuit 870, and an LO signal driver circuit 880. The control pulse envelope generator 810 is configured to implement pulse shaping techniques that generate RF control pulses with a desired control pulse envelope shape (e.g., Gaussian pulse, cosine pulse (e.g., sum of half-cosine waves), hyperbolic secant pulse, etc.) applied to a superconducting qubit or active qubit coupler circuit to perform single qubit gate operations, entanglement gate operations, etc. The shaped control pulse is the f of the qubit. 01 It drives the transition, while f 12 and are calibrated to suppress higher transitions. Essentially, such pulse shaping techniques suppress / reduce transients associated with turning control pulses on and off. In addition, pulse shaping techniques include DRAG (derivative removal by adiabatic gate) corrected pulses, which can be used in conjunction with the shaped pulse (Gaussian pulse, cosine pulse, or hyperbolic secant pulse, etc.) to further suppress undesirable state transitions while maintaining the same pulse envelope area (or integral of the pulse envelope).

[0129] In each AWG channel of the AWG system 802, the digital control pulse envelope signal (digital I and Q components) is converted to an analog control pulse envelope signal (analog baseband I / Q signal), and the I / Q mixer stage 840 modulates the quadrature LO signal using the baseband I / Q signal by performing SSB modulation, for example, as discussed above, to generate a modulated signal in the form of RF control pulses applied on the qubit drive line to control a given qubit, for example. The functions of the various stages 820, 830, 850, 860, 870, and 880 are the same as or similar to the corresponding stages in Figures 1, 2, etc., and these details are not repeated.

[0130] As further shown in Figure 8, in some embodiments, each AWG channel 802-1, ..., 802-c of the AWG system 802 is provided with a dedicated calibration circuit 890-1, ..., 890-c that is implemented on-chip with the AWG system 802. The calibration circuits 890-1, ..., 890-c are configured to calibrate each AWG channel 802-1, ..., 802-c of the AWG system 802 for different operating modes, as discussed above. The calibration circuits 890-1, ..., 890-c include hardware controls and logic circuits (e.g., DC offset compensated DAC, control logic circuits that generate control signals, etc.) as discussed above. In some embodiments, the calibration circuits 890-1, ..., 890-c are controlled by software running on a computing platform that controls the quantum computing system 800.

[0131] For example, Figure 9 schematically illustrates a quantum computing system according to another exemplary embodiment of the present disclosure. In particular, Figure 9 schematically illustrates a quantum computing system 900 comprising a quantum computing platform 910, a control system 920, and a quantum processor 930. In some embodiments, the quantum computing platform 910 implements software programs such as a quantum computing algorithm 912 that performs quantum computing or quantum information processes, and a calibration control process 914 that performs functions such as configuring an AWG system and controlling the execution of high-level functions of a calibration process.

[0132] Furthermore, the quantum computing platform 910 performs calibration procedures that are periodically executed on quantum systems such as quantum processors to enable high-fidelity gate operations (e.g., single-qubit gate operations and entangled gate operations) by calibrating various quantum elements such as readout resonators, data qubits, and coupler circuits. For example, various types of in-situ calibration procedures are periodically executed to determine the resonant frequency of a readout resonator, the transition frequency of a qubit, the coherence time (T1) of a qubit (where the coherence time T1 of a given qubit represents the time required for the qubit state to decay from an excited state to a ground state), the transverse relaxation time (T2) (or phase relaxation time) of a qubit, calibrate the control pulses applied to a qubit to perform a single-qubit gate operation, and calibrate the control pulses applied to an active coupler circuit to perform an entangled gate operation. As a result of the calibration procedure, various control parameters are determined that are maintained in the calibration database and, depending on the type of quantum element, the operating characteristics of the quantum computing system, and other factors that can be understood by those skilled in the art, are periodically updated on the order of seconds, minutes, hours, days, etc., as needed.

[0133] In some embodiments, the control system 920 comprises a multi-channel arbitrary waveform generator 922 and a qubit readout control system 924, and Figure 8 schematically shows an exemplary AWG system 802 that can be implemented in the control system 920. The quantum processor 930 comprises one or more quantum processor chips comprising a superconducting qubit array 932 and a network 934 of qubit drive lines, coupler drive lines and qubit state readout lines, and other circuit QED components that may be required for a given application or quantum system configuration.

[0134] In some embodiments, the control system 920 and the quantum processor 930 are housed in a dilution refrigeration system 940 capable of generating cryogenic temperatures sufficient to operate the components of the control system 920 for quantum computing applications. For example, the quantum processor 930 may need to be cooled to near absolute zero, for example, 10–15 millikelvin (mK), to allow the superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution refrigeration system 940 includes a multi-stage dilution refrigerator capable of maintaining the components of the control system 920 at different cryogenic temperatures as needed. For example, the quantum processor 930 may need to be cooled to, for example, 10–15 mK, while the circuit components of the control system 920 may operate at cryogenic temperatures higher than 10–15 mK (e.g., cryogenic temperatures in the range of 3K–4K), depending on the configuration of the quantum computing system.

[0135] In some embodiments, the superconducting qubit array 932 includes a plurality of superconducting transmon qubits and superconducting tunable coupler qubits, where each pair of superconducting qubits is connected by a superconducting qubit coupler using a technique as described herein. A network 934, including qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, is configured to apply microwave control signals to the superconducting qubits and coupler circuits in the superconducting qubit array 932 to perform various types of gate operations, such as single-gate operations and entangled-gate operations, and to read the quantum states of the superconducting qubits. The network 934, including qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, is coupled to the control system 920 via a suitable hardware input / output (I / O) interface that couples I / O signals between the control system 920 and the quantum processor 930. For example, a hardware I / O interface may include various types of hardware and components such as RF cables, wiring, RF elements, optical fibers, heat exchangers, filters, amplifiers, isolators, etc.

[0136] The quantum computing platform 910 includes a software and hardware platform including various software layers configured to perform various functions, including, but not limited to, generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into quantum assembly language, implementing and utilizing a suitable quantum instruction set architecture (ISA), and performing calibration operations to calibrate quantum circuit elements and gate operations. In addition, the quantum computing platform 910 includes a hardware architecture such as a processor and memory configured to control the execution of the quantum application and interface with the control system 920, in order to (i) generate digital control signals that are converted into analog microwave control signals by the control system 920 to control the operation of the quantum processor 930 when executing a given quantum application, and to acquire and process digital signals received from the control system 920 that represent the processing results generated by the quantum processor 930 when executing various gate operations for a given quantum application. In some exemplary embodiments, the quantum computing platform 910 of the quantum computing system 900 may be implemented using any suitable computing system architecture (for example, as shown in Figure 10) configured to implement a method of supporting quantum computing operations by executing computer-readable program instructions embodied on a computer program product, the computer program product including a computer-readable storage medium (or more mediums) having such computer-readable program instructions causing a processor to perform control methods as discussed herein.

[0137] Various aspects of this disclosure are described by explanatory text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated stage, simultaneously, or with at least partial time overlap.

[0138] Computer program product embodiments ("CPP embodiments" or "CPP") are terms used in this disclosure to describe any set of one or more storage media ("mediums") that collectively comprise a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A "storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may be, but are not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination thereof. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (e.g., punch cards or pits / lands formed on the main surface of a disk), or any suitable combination of those mentioned above. When the term "computer-readable storage medium" is used in this disclosure, it shall not be interpreted as storage in the form of a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, electrical signals communicated through wires, and / or other transmission media.As will be understood by those skilled in the art, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection; however, data is not transient while it is stored, and therefore the storage device is not transient.

[0139] The computing environment 1000 includes an example of an environment for executing at least a portion of the computer code 1026 associated with performing the method of the present invention, such as quantum computing algorithm code for performing quantum computing or quantum information processing, and hardware calibration process control code for controlling functions such as the calibration control system 190 in Figure 1 and calibration circuits 890-1, ..., 890-c in Figure 8. In addition to block 1026, the computing environment 1000 includes, for example, a computer 1001, a wide area network (WAN) 1002, an end user device (EUD) 1003, a remote server 1004, a public cloud 1005, and a private cloud 1006. In this embodiment, the computer 1001 includes a processor set 1010 (including processing circuits 1020 and a cache 1021), a communication fabric 1011, volatile memory 1012, persistent storage 1013 (including an operating system 1022 and blocks 1026 as identified above), a peripheral device set 1014 (including a user interface (UI), a device set 1023, storage 1024, and an Internet of Things (IoT) sensor set 1025), and a network module 1015. The remote server 1004 includes a remote database 1030. The public cloud 1005 includes a gateway 1040, a cloud orchestration module 1041, a host physical machine set 1042, a virtual machine set 1043, and a container set 1044.

[0140] Computer 1001 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device currently known or to be developed in the future that is capable of executing programs, accessing networks, or querying databases such as remote database 1030. As is well understood in the field of computer technology, and depending on the technology, the execution of a computer implementation method may be distributed among multiple computers and / or across multiple locations. On the other hand, in this presentation concerning the computing environment 1000, in order to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 1001. Computer 1001 may be located in the cloud, although it is not shown in the cloud in Figure 10. On the other hand, computer 1001 is not required to be located in the cloud, except to any extent that can be definitively shown.

[0141] The processor set 1010 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuitry 1020 may be distributed across multiple packages, e.g., multiple coordinated integrated circuit chips. The processing circuitry 1020 may implement multiple processor threads and / or multiple processor cores. The cache 1021 is memory located within the processor chip package and is typically used for data or code that should be available for high-speed access by threads or cores running on the processor set 1010. The cache memory is typically organized into multiple levels, depending on its relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 1010 may operate using qubits and be designed to perform quantum computing.

[0142] Computer-readable program instructions typically cause the processor set 1010 of computer 1001 to execute a series of operational steps, thereby loading them onto computer 1001 to implement a computer implementation method, and the instructions thus executed instantiate the methods specified in the flowcharts and / or descriptions of the computer implementation methods contained herein (collectively referred to as the "Methods of the Invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as the cache 1021 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 1010 to control and direct the execution of the Methods of the Invention. In computing environment 1000, at least some of the instructions for executing the Methods of the Invention may be stored in block 1026 in persistent storage 1013.

[0143] The communication fabric 1011 is a signal conduction path that enables various components of the computer 1001 to communicate with one another. Typically, this fabric is made up of switches and conductive paths, such as buses, bridges, and physical input / output ports. Other types of signal communication paths, such as optical fiber communication paths and / or wireless communication paths, may be used.

[0144] Volatile memory 1012 is any type of volatile memory currently known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory is characterized by random access, but this is not required unless explicitly stated. In computer 1001, volatile memory 1012 is located in a single package and resides inside computer 1001, but alternatively or in addition, volatile memory may be distributed across multiple packages and / or located externally to computer 1001.

[0145] The persistent storage 1013 is any form of non-volatile storage for a computer, currently known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained whether or not power is directly supplied to the computer 1001 and / or the persistent storage 1013. The persistent storage 1013 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 1022 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface (POSHU) type operating systems employing a kernel. The code contained in block 1026 typically includes at least a portion of computer code involved in performing the method of the present invention.

[0146] The peripheral device set 1014 includes a set of peripheral devices for the computer 1001. Data communication connections between the peripheral devices and other components of the computer 1001 may be implemented in various ways, such as Bluetooth connections, near-field communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insert-type connections (e.g., secure digital (SD) cards), connections made via local area communication networks, and even connections made via wide area networks such as the internet. In various embodiments, the UI device set 1023 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic device. Storage 1024 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 1024 may be persistent and / or volatile. In some embodiments, storage 1024 may take the form of a quantum computing memory device for storing data in the form of qubits. In embodiments where computer 1001 is required to have a large amount of storage (for example, computer 1001 locally stores and manages a large database), this storage may be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 1025 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0147] The network module 1015 is a collection of computer software, hardware, and firmware that enables computer 1001 to communicate with other computers via the WAN 1002. The network module 1015 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for transmission over a communication network, and / or web browser software for communicating data over the internet. In some embodiments, the network control and network forwarding functions of the network module 1015 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 1015 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 1001 through a network adapter card or network interface included in the network module 1015.

[0148] WAN1002 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any currently known or future-developed technology for transmitting computer data. In some embodiments, the WAN may be replaced and / or supplemented by a local area network (LAN), such as a Wi-Fi network, designed to transmit data between devices located in a local area. The WAN and / or LAN typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0149] The end-user device (EUD) 1003 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 1001), and may take any of the forms discussed above in relation to computer 1001. Typically, EUD 1003 receives useful and valuable data from the operation of computer 1001. For example, in a hypothetical case where computer 1001 is designed to provide recommendations to the end-user, these recommendations would typically be communicated from the network module 1015 of computer 1001 to EUD 1003 via WAN 1002. In this way, EUD 1003 can display or otherwise present the recommendations to the end-user. In some embodiments, EUD 1003 may be a client device such as a thin client, heavy client, mainframe computer, or desktop computer.

[0150] The remote server 1004 is any computer system that provides at least some data and / or functionality to computer 1001. The remote server 1004 may be controlled and used by the same entity that operates computer 1001. The remote server 1004 represents a machine that collects and stores useful and valuable data for use by other computers, such as computer 1001. For example, in the hypothetical case where computer 1001 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 1001 from the remote database 1030 of the remote server 1004.

[0151] Public Cloud 1005 is any computer system available for use by multiple entities, providing on-demand availability of computer system resources and / or other computer functions, particularly data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of the computing resources of Public Cloud 1005 is performed by the computer hardware and / or software of the Cloud Orchestration Module 1041. The computing resources provided by Public Cloud 1005 are typically implemented by virtual computing environments running on various computers that make up the host physical machine set 1042, which is the universe of physical computers available in and / or to Public Cloud 1005. The virtual computing environment (VCE) typically takes the form of virtual machines from the virtual machine set 1043 and / or containers from the container set 1044. These VCEs may be stored as images and are understood to be transferable as images or after VCE instantiation, among and between various physical machine hosts. The cloud orchestration module 1041 manages the transfer and storage of images, deploys new VCE instantiations, and manages active instantiations of VCE deployments. The gateway 1040 is a collection of computer software, hardware, and firmware that enables the public cloud 1005 to communicate over the WAN 1002.

[0152] Herein, some further explanation of virtualized computing environments (VCEs) will be provided. A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature in which the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave as actual computers from the perspective of the programs running within them. Computer programs running on a normal operating system can utilize all of that computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container; this feature is known as containerization.

[0153] Private Cloud 1006 is similar to Public Cloud 1005, except that its computing resources are available only for use by a single enterprise. While Private Cloud 1006 is shown as communicating with WAN 1002, in other embodiments, the private cloud may be completely isolated from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple configured clouds. In this embodiment, both Public Cloud 1005 and Private Cloud 1006 are part of a larger hybrid cloud.

[0154] While descriptions of various embodiments of this disclosure have been presented for illustrative purposes, they are not intended to be exhaustive or to limit oneself to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the technology available on the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. It comprises a first voltage mode filter circuit, a second voltage mode filter circuit, and a differential voltage mode filter circuit having a neutralization network. The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance; The neutralization network includes a first neutralization impedance circuit that couples the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit, and a second neutralization impedance circuit that couples the input node of the second voltage mode filter circuit to the output node of the first voltage mode filter circuit; The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by at least one of canceling out and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

2. The device according to claim 1, wherein the neutralization network is configured to correct the frequency response of each of the first and second voltage mode filter circuits by adding at least one transmitting pole to the transfer function of each of the first and second voltage mode filter circuits.

3. The device according to claim 1, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include a low-pass filter circuit with at least a biquadratic transfer function.

4. The device according to claim 1, wherein the first neutralizing impedance circuit and the second neutralizing impedance circuit each include a passive impedance element.

5. The first neutralizing impedance circuit includes at least a first resistor and a first capacitor connected in series between the input node of the first voltage mode filter circuit and the output node of the second voltage mode filter circuit; The device according to claim 1, wherein the second neutralizing impedance circuit includes at least a second resistor and a second capacitor connected in series between the input node of the second voltage-mode filter circuit and the output node of the first voltage-mode filter circuit.

6. The device according to claim 5, wherein the first capacitor and the second capacitor are variable capacitors.

7. The device according to claim 1, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include an analog Sallen-Key filter circuit including a unity-gain source follower.

8. A digital-to-analog converter circuit having an output interface configured to generate a differential analog voltage signal including a first voltage signal and a second voltage signal, which are complementary voltage signals; A differential voltage mode filter circuit configured to filter the differential analog voltage signal and output a filtered differential analog voltage signal including a first filtered voltage signal and a second filtered voltage signal, which are complementary filtered voltage signals; and The current mode output circuit is coupled to the differential voltage mode filter circuit and is configured to convert the first filtered voltage signal and the second filtered voltage signal into a first current signal and a second current signal, respectively, for processing by the current mode output circuit. Equipped with; The differential voltage mode filter circuit has a neutralization network including a first voltage mode filter circuit configured to filter the first voltage signal, a second voltage mode filter circuit configured to filter the second voltage signal, and a first neutralization impedance circuit and a second neutralization impedance circuit; The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance; The first neutralizing impedance circuit connects the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit, and the second neutralizing impedance circuit connects the input node of the second voltage mode filter circuit to the output node of the first voltage mode filter circuit; The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by at least one of canceling out and compensating for at least one transmit zero of the transfer function of each of the first and second voltage-mode filter circuits, which is derived from the non-zero output impedance of each of the unity-gain buffers.

9. The current mode output circuit is, A first input transistor comprising a gate terminal coupled to the output node of the first voltage mode filter circuit and a source terminal coupled to the voltage node being regulated; A second input transistor comprising a gate terminal coupled to the output node of the second voltage-mode filter circuit and a source terminal coupled to the voltage under regulation node; A regulating circuit configured to generate a current for biasing the current-mode output circuit by adjusting the voltage level on the regulated voltage node to maintain a constant gate / source bias voltage for the first and second input transistors. The device according to claim 8, having the following features.

10. The device according to claim 8, wherein the neutralization network is configured to correct the frequency response of each of the first and second voltage mode filter circuits by adding at least one transmitting pole to the transfer function of each of the first and second voltage mode filter circuits.

11. The device according to claim 8, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include a low-pass filter circuit with at least a biquadratic transfer function.

12. The device according to claim 8, wherein the first neutralizing impedance circuit and the second neutralizing impedance circuit each include a passive impedance element.

13. The first neutralizing impedance circuit includes at least a first resistor and a first capacitor connected in series between the input node of the first voltage mode filter circuit and the output node of the second voltage mode filter circuit; The second neutralizing impedance circuit includes at least a second resistor and a second capacitor connected in series between the input node of the second voltage mode filter circuit and the output node of the first voltage mode filter circuit; The device according to claim 8, wherein the first capacitor and the second capacitor are one of a fixed capacitor and a variable capacitor.

14. The device according to claim 8, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include an analog Sallen-Key filter circuit including a unity-gain source follower.

15. A radio frequency signal generator configured to convert a baseband signal into a radio frequency signal. The radio frequency signal generator is equipped with, A digital-to-analog converter circuit including an output interface configured to generate a differential baseband voltage signal, which includes a first baseband voltage signal and a second baseband voltage signal, which are complementary baseband voltage signals; A differential voltage mode filter circuit configured to filter the differential baseband voltage signal and output a filtered differential baseband voltage signal including a first filtered baseband voltage signal and a second filtered baseband voltage signal, which are complementary filtered baseband voltage signals; and The current-mode radio frequency output circuit is coupled to the differential voltage mode filter circuit and is configured to convert the first filtered baseband voltage signal and the second filtered baseband voltage signal into a first baseband current signal and a second baseband current signal, respectively, for processing by the current-mode radio frequency output circuit, thereby generating the radio frequency signal. Having; The differential voltage mode filter circuit includes a first voltage mode filter circuit configured to filter the first baseband voltage signal, a second voltage mode filter circuit configured to filter the second baseband voltage signal, and a neutralization network including a first neutralization impedance circuit and a second neutralization impedance circuit; The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance; The first neutralizing impedance circuit connects the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit, and the second neutralizing impedance circuit connects the input node of the second voltage mode filter circuit to the output node of the first voltage mode filter circuit; The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by canceling out and compensating for at least one of the transmit zeros of the transfer function of each of the first and second voltage-mode filter circuits, which are derived from the non-zero output impedance of each of the unity-gain buffers, in a system.

16. The system according to claim 15, wherein the neutralization network is configured to correct the frequency response of each of the first and second voltage mode filter circuits by adding at least one transmitting pole to the transfer function of each of the first and second voltage mode filter circuits.

17. The system according to claim 15, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include a low-pass filter circuit with at least a double-quadrature transfer function.

18. The first neutralizing impedance circuit includes at least a first resistor and a first capacitor connected in series between the input node of the first voltage mode filter circuit and the output node of the second voltage mode filter circuit; The second neutralizing impedance circuit includes at least a second resistor and a second capacitor connected in series between the input node of the second voltage mode filter circuit and the output node of the first voltage mode filter circuit; The system according to claim 15, wherein the first capacitor and the second capacitor are one of a fixed capacitor and a variable capacitor.

19. The system according to claim 15, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include an analog Sallen-Key filter circuit including a unity-gain source follower.

20. A quantum processor having at least one superconducting qubit; An arbitrary waveform generator having at least one arbitrary waveform generator channel configured to convert a baseband signal into radio frequency control pulses that control the at least one superconducting qubit. The at least one arbitrary waveform generator channel is A digital-to-analog converter circuit including an output interface configured to generate a differential baseband voltage signal, which includes a first baseband voltage signal and a second baseband voltage signal, which are complementary baseband voltage signals; A differential voltage mode filter circuit configured to filter the differential baseband voltage signal and output a filtered differential baseband voltage signal including a first filtered baseband voltage signal and a second filtered baseband voltage signal, which are complementary filtered baseband voltage signals; and The current-mode radio frequency output circuit is coupled to the differential voltage mode filter circuit and is configured to convert the first filtered baseband voltage signal and the second filtered baseband voltage signal into a first baseband current signal and a second baseband current signal, respectively, for processing by the current-mode radio frequency output circuit, thereby generating the radio frequency control pulse. Having; The differential voltage mode filter circuit includes a first voltage mode filter circuit configured to filter the first baseband voltage signal, a second voltage mode filter circuit configured to filter the second baseband voltage signal, and a neutralization network including a first neutralization impedance circuit and a second neutralization impedance circuit; The first voltage-mode filter circuit and the second voltage-mode filter circuit each include a unity-gain buffer having a non-zero output impedance; The first neutralizing impedance circuit connects the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit, and the second neutralizing impedance circuit connects the input node of the second voltage mode filter circuit to the output node of the first voltage mode filter circuit; The neutralization network is configured to correct the frequency response of each of the first and second voltage-mode filter circuits by canceling out and compensating for at least one of the transmit zeros of the transfer function of each of the first and second voltage-mode filter circuits, which are derived from the non-zero output impedance of each of the unity-gain buffers, in a system.

21. The system according to claim 20, wherein the neutralization network is configured to correct the frequency response of each of the first and second voltage mode filter circuits by adding at least one transmitting pole to the transfer function of each of the first and second voltage mode filter circuits.

22. The system according to claim 20, wherein each of the first voltage-mode filter circuit and the second voltage-mode filter circuit includes at least a low-pass filter circuit with a double-quadrature transfer function.

23. The first neutralizing impedance circuit includes at least a first resistor and a first capacitor connected in series between the input node of the first voltage mode filter circuit and the output node of the second voltage mode filter circuit; The second neutralizing impedance circuit includes at least a second resistor and a second capacitor connected in series between the input node of the second voltage mode filter circuit and the output node of the first voltage mode filter circuit; The system according to claim 20, wherein the first capacitor and the second capacitor are one of a fixed capacitor and a variable capacitor.

24. The system according to claim 20, wherein the first voltage-mode filter circuit and the second voltage-mode filter circuit each include an analog Sallen-Key filter circuit including a unity-gain source follower.

25. Steps include applying a differential voltage signal to the first and second input nodes of a differential voltage mode filter circuit to generate filtered differential signals on the first and second output nodes of the differential voltage mode filter circuit, wherein the differential voltage mode filter circuit includes a neutralization network comprising a first voltage mode filter circuit and a second voltage mode filter circuit, each containing a unity-gain buffer having a non-zero output impedance, a first neutralization impedance circuit coupling the input node of the first voltage mode filter circuit to the output node of the second voltage mode filter circuit, and a second neutralization impedance circuit coupling the input node of the second voltage mode filter circuit to the output node of the first voltage mode filter circuit; and The step of configuring the neutralization network to correct the frequency response of the first voltage-mode filter circuit and the second voltage-mode filter circuit by at least one of canceling out and compensating for at least one transmit zero of the transfer function of the first voltage-mode filter circuit and the second voltage-mode filter circuit, which is derived from the non-zero output impedance of the respective unity-gain buffers. A method that includes [a certain feature].

Images