Method and system for improving forward error correction in serial coding during data transmission

Abstract

This invention relates to a method for improving forward error correction of serial coding in data transmission within a vehicle, and compared to the prior art, it offers the advantage of always being able to deterministically control the physical behavior on the transmission channel while reducing resource requirements. Accordingly, according to the proposed method, bit errors are minimized, and transmission errors can be corrected efficiently, i.e., with minimal technical effort. Furthermore, the encoder used is designed with a minimum number of gates, and interleaving is implicitly provided in the proposed method, which is based on the fact that so-called burst errors can be corrected particularly favorably. This implicit interleaving makes it possible to eliminate the buffer memory that was conventionally required for explicit interleaving. In addition, the invention ensures that user data can be encoded favorably with respect to transmission along with correction metadata. According to the invention, it can be guaranteed that not only user data but also correction data can be line-coded or line-encoded. The invention also relates to a system device similarly designed to perform this method, and a computer program product having control commands for performing this method.

Description

Technical Field

[0001] The present invention is directed to a method for improving the forward error correction of serial coding in data transmission within a vehicle, which, compared to the prior art, brings the advantage of being able to always deterministically control the physical behavior on the transmission channel while reducing resource requirements. Thus, according to the proposed method, bit errors are minimized and transmission errors can be corrected efficiently, i.e., with minimal technical effort. Furthermore, the encoder used is designed with a minimum number of gates, and interleaving is implicitly provided in the proposed method, which is based on the fact that it can particularly advantageously correct so-called burst errors. This implicit interleaving makes it possible to eliminate the buffer memory that was previously required for explicit interleaving. In addition, the present invention ensures that user data can be advantageously encoded for transmission together with correction metadata. According to the present invention, it can be guaranteed that not only user data but also correction data is line-coded or line-encoded. The present invention also relates to a system device designed similarly for executing this method and a computer program product having control commands for executing this method.

Background Art

[0002] Patent Document 1 discloses a system and method for transmitting packets over a data link. A packet may contain a stream of data symbols separated by one or more frame symbols. Damage to a frame symbol that results in a valid data symbol may be associated with an invalid symbol.

[0003] Patent Document 2 describes a method for integrating and executing two types of encoding schemes rather than executing them individually. The two encoding schemes can be integrated by interleaving one or more steps of one encoding scheme (e.g., data encoding) between two or more steps of the other encoding scheme (e.g., line encoding).

[0004] From prior art, various versions of the Ethernet® protocol are known. Ethernet uses various techniques to detect and correct errors during data transmission. Error correction mechanisms are part of the Ethernet protocol and ensure that received data is accurate and complete. Cyclic Redundancy Check (CRC) is one of the most important error detection techniques in Ethernet. In CRC, a checksum is calculated for the transmitted data and attached to the packet. At the receiver, the checksum is calculated again and compared to the received checksum. If the checksums do not match, an error is detected and the packet is discarded.

[0005] A known conventional technique is forward error correction (FEC). Forward error correction is an error correction method in which additional redundant information is added to the data. This redundancy allows the receiver to detect and correct errors without having to retransmit the packet. FEC is often used in high-speed Ethernet connections such as 10 Gigabit Ethernet (10GbE) to ensure data integrity.

[0006] Furthermore, link-level error correction is also known from conventional technology. Ethernet can also perform error correction at the physical level. Here, techniques such as signal amplification, noise suppression, and error correction codes are used to improve the stability of data transmission. These error correction mechanisms are implemented in Ethernet transceivers that perform the conversion between digital data and physical signals.

[0007] Error correction mechanisms play a crucial role in ensuring reliable data transmission across networks. They help detect, isolate, and correct transmission errors to ensure data integrity is maintained. Error correction mechanisms are especially essential for maintaining connection quality in mission-critical environments where large volumes of data are transmitted.

[0008] Furthermore, the DisplayPort standard is also well-known. DisplayPort uses various error detection and correction methods to ensure that transmitted data is reproduced accurately and without loss. These mechanisms are part of the DisplayPort protocol and contribute to the stability and quality of data transmission. Forward Error Correction (FEC) is an important error correction method in DisplayPort. Additional redundant information is inserted into the transmitted data. This redundancy allows the receiver to recognize and correct erroneous data bits. In this way, errors that occur during transmission can be effectively corrected without retransmitting the data.

[0009] Furthermore, prior art generally recognizes that data transmission over serial data channels typically contains errors. To address this problem, prior art has recognized various coding methods, such as line coding, also known as line coding (Leitungskodierung).

[0010] Conventional technologies recognize the problem of erroneous data transmission over serial communication links and stipulate that line-coded data should be provided with forward error correction. Therefore, conventional technologies address the error correction problem by providing additional information that is not line-coded, i.e., unline-coded forward error correction, to the line-coded data. Consequently, conventional technologies have the problem that even when line coding is provided, the benefits of line coding cannot be used for all transmitted data because individual metadata is not transmitted in coded form. This can lead to errors. Conventional technologies may address this by separately encoding the forward error correction data and then transmitting it. This creates an additional load, as new forward error correction must be calculated to protect the line-coded forward error correction data. This creates yet another additional load, and also creates unline-coded forward error correction.

[0011] Furthermore, conventional technologies have the problem that forward error correction is always calculated over the entire data word, resulting in enormous technical effort required to maintain and operate a number of gates that increases exponentially with increasing word length. Consequently, conventional encoders that calculate forward error correction are very expensive to manufacture and are vulnerable to errors. In addition, they consume a large amount of energy, which is undesirable in vehicles. Moreover, errors that affect the entire word propagate more widely than when error correction is performed using only a portion of the word, resulting in increased vulnerability to errors. This is also undesirable in vehicles because data transmission is critical to safety, especially in vehicles. Therefore, vulnerability to errors is particularly important in automobiles or vehicles in general, where safety-critical functions must be provided.

[0012] While various encoding and data transmission methods are known from prior art, all of them relate to application scenarios that are only disadvantageous in automobiles. Prior art often assumes that high computing power is available and that high real-time requirements are not imposed. Furthermore, prior art often assumes that the weight or reliability of the components used plays only a secondary role. In many cases, prior art refers to conventional computer networks where reliability and low technical complexity are not particularly important.

[0013] Based on this prior art, there is a need to create a method or system that enables data to be processed as quickly as possible for automotive safety requirements, requires minimal technical effort, and minimizes the error rate during transmission by making retransmission impossible if an error is detected. Low technical effort should mean incorporating components that are as simple, lightweight, and mass-producible as possible. Known methods and system devices from computer network technology are typically unsuitable here because weight reduction and real-time operation are not critical factors in standalone PCs or servers. While heat dissipation is generally a challenge for computer configurations, energy efficiency in automobiles is even more important in electromobility, for example, because power consumption affects the range of the vehicle.

[0014] Further prior art concerns the transmission of data in serial data streams. For example, prior art provides extensive descriptive data to be transmitted along with user data, indicating where the user data is located and how it should be interpreted. Furthermore, prior art is known to discard individual data packets if they are not transmitted correctly. It is also known that prior art retransmits data packets if they do not arrive at the sender on time or if they arrive at the sender in an unexpected format.

[0015] In serial data transmission, it is necessary to have as many equal numbers of 1s and 0s as possible within the serial data stream. This is called disparity. To avoid baseline drift during transmission, it is desirable to have zero disparity on average and over short periods. Baseline drift (DC voltage fluctuations) in serial signals can lead to bit errors. In extreme cases, transmission may become impossible.

[0016] To ensure that the serial bits in the serial data stream can be reliably recovered at the receiving end without the need to transmit a clock, a minimum number of transitions from 0 to 1 or 1 to 0 are required. This means that the clock for recovering the serial data is locally generated at the receiver from the serial data stream. The so-called run-length specifies the number of consecutive occurrences of the same bit (1 or 0) without change. A short run-length is always desirable because a long run-length no longer reliably recovers the clock from the serial data stream.

[0017] The task of line code (in this case, block code or line code) is to generate symbols with guaranteed disparity and guaranteed run-length from any data word with arbitrary disparity and infinite run-length. This leads to transmission overhead. This means that more bits (in the form of symbols) must be transmitted than would occur in the net data word to be transmitted. This means that the required transmission speed (bandwidth) must be greater than the data rate of the data being transmitted. This means that the system requires a higher error rate or more load, power, etc., than would be required to transmit the raw data. [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] U.S. Patent Application Publication No. 2003 / 237041 [Patent Document 2] U.S. Patent No. 7103830 [Overview of the project] [Problems that the invention aims to solve]

[0019] Therefore, an object of the present invention is to propose a method for improving forward error correction in serial coding during data transmission in vehicles. The proposed method should be efficient, require little technical effort, and be as error-resistant as possible. Furthermore, an object of the present invention is to provide a system device appropriately configured for carrying out this method. Furthermore, an object of the present invention is to propose a computer program product that provides control commands for carrying out the method or operating the system device. Furthermore, an object of the present invention is to propose a storage medium having control commands. [Means for solving the problem]

[0020] This problem is solved by the features of claim 1. Further advantageous embodiments are described in the dependent claims. Accordingly, a method is proposed to improve forward error correction in serial coding for data transmission within a vehicle, the method comprising the steps of: providing user data to be transmitted; dividing the provided user data into multiple bit sequences of the same length; reading out subdivision rules that subdivide the bit sequences into sequences of segments of a predetermined length at predetermined bit positions; applying the read subdivision rules to all bit sequences of the multiple bit sequences; iteratively creating individual partial forward error corrections for all segments at the same bit position across all bit sequences; iteratively applying individual segment encoders across all segments at the same bit position to generate segment routing codes for all segments for each bit position and bit sequence; applying individual segment encoders, which were also applied to the segments in which the individual partial forward error corrections were created, to individual partial forward error corrections to generate individual partial forward error correction routing codes for each partial forward error correction; and transmitting all segment routing codes and all partial forward error correction routing codes.

[0021] According to the present invention, forward error correction is improved in that it is calculated with respect to user data and for this purpose the user data is first segmented. Next, a separate forward error correction is calculated for each segment, so that the forward error correction is performed with respect to different sub-words rather than with respect to the entire data word. This keeps the number of gates of the FEC coder to be used low and avoids an exponential increase. Further, according to the present invention, since line coding is performed through the user data together with forward error correction, an improvement is obtained from the fact that the drawback of the prior art in which forward error correction is transmitted in an uncoded form is overcome. Furthermore, error correction refers only to partial words and thus, since the location where an error has occurred can be recognized with fine granularity, error correction can function more efficiently. Conventional error correction is inefficient because it always refers to the entire data word or there is a possibility that an error that cannot be corrected in the prior art may occur. This is avoided by the segmentation according to the present invention.

[0022] A further improvement is that all transmitted data is line-coded, whereby the entire data can benefit from line coding. Thus, the transmission link can be deterministically controlled and bit errors can be minimized. In addition, an implicit interleaving occurs from the fact that smaller packets are transmitted and not all data words are transmitted. This is achieved by using a plurality of forward error correction encoders, each forward error correction encoder referring only to partial words. Thus, according to the present invention, the drawback of the prior art, namely that an explicit interleaving has to be created at great expense and additional buffer memory is also required, is overcome.

[0023] Optimized disparity (line coding) of the bit sequence to be transmitted makes it possible to avoid errors when interpreting on a serial channel. Thus, efficiency also refers to the fact that the bit sequence should be particularly error-resistant and transmitted only once with high reliability. Redundant transmission is avoided by high detection capabilities and also by optimized disparity.

[0024] In the serial transmission of data, it is advantageous to keep the number of 1s and 0s in the serial data stream as equal as possible. This is generally referred to as disparity. A run-length limit can be imposed on the generated channel sequence for reliable clock recovery at the receiver. This limits the maximum number of consecutive 1s and 0s. Thus, the proposed method can also be described as a method for efficient coding of a bit sequence. According to the invention, the disparity is optimized by skillfully setting partial disparities. This can be particularly advantageously used when the run length of the bit sequence is limited. The limited disparity and the limited run length can also be associated with any bit sequence provided. This means that it is not necessary for the bit sequence to be efficiently transmissible. Overall, any bit sequence provided can be efficiently transmitted, and a bit sequence to be transmitted from the bit sequence is generated or created, and then this bit sequence can be efficiently transmitted.

[0025] The proposed method can be used particularly in vehicles or is specially adapted to the requirements in vehicles. This is because safety-critical functions that must be appropriately protected are provided in vehicles. According to the invention, this is done in a plurality of aspects. On the one hand, it is done through forward error correction and via line coding. In addition, the reduction in the number of gates required is particularly advantageous in electromobility.

[0026] According to the present invention, user data to be transmitted is provided in a preparation process step. This is typically a fixed-length bit sequence. This may also be called a data word.

[0027] The provided user data is then divided into multiple bit sequences of the same length. In a preferred embodiment, these bit sequences may have a length of 112 bits. While the user data can be a continuous data stream, the bit sequences are always of a constant length and provide a subdivision of the user data in a sense. Hereafter, bit sequences will also be referred to as data words. Furthermore, hereafter, particularly in the drawings, it will be assumed that bit sequences are, figuratively speaking, arranged one below the other. This means that each individual bit sequence extends horizontally, and each individual bit sequence is arranged vertically, one above the other.

[0028] Since the bit sequence is segmented, a subdivision rule is read out that divides the bit sequence into a sequence of segments of a predetermined length at a given location. . pieces Each segment does not need to be the same length; they may differ in length. However, the subdivision rules stipulate that each individual bit sequence has the same format, thus, figuratively speaking, resulting in identical subdivisions vertically. For example, the first segment of each bit sequence may have 11 bits. For example, the first four segments may each have 11 bits, followed by a 7-bit segment. Then, another 11-bit segment may follow, followed by a 6-bit segment. This data format is adhered to for all bit sequences. This means that segments at the same position can always be the same length, but figuratively speaking, segments can differ vertically. Each line of segments forms a bit sequence. The bit sequence as a whole, in its vertical arrangement, forms user data.

[0029] This means that the read subdivision rule is applied to all bit sequences of multiple bit sequences, so that the entire user data is broken down into bit sequences horizontally and segments are formed vertically. This means that all bit sequences are subdivided according to the same subdivision rule. The subdivision rule is , Yu This applies to all bit sequences obtained from the data.

[0030] Here, partial forward error correction is iteratively created for all segments at the same bit position, across the entire bit sequence. Figuratively speaking, the forward error correction is calculated for all segments for all vertical segments at the same bit position or in the same sequence. Since this is performed for all segments, partial forward error correction is created for all bit sequences, and therefore for the complete user data. Thus, the sum of all partial forward error corrections creates a total forward error correction that refers to the complete user data or the entire bit sequence.

[0031] Generally, user data may be divided into only one bit sequence, or it may already be available as a single bit sequence of its length. In that case, partial forward error correction is generated for each segment.

[0032] Here, the segment encoder is repeatedly applied across all segments at the same bit position, generating segment line codes across all segments for each bit position and bit sequence. In other words, line coding is performed, figuratively speaking, across all vertical segments. This is advantageous because the line encoder is specifically provided for a given length. This ensures that each vertical segment can be coded by a single line encoder. Thus, the repeated application of the segment encoder, figuratively speaking, ensures that segments are line coded column by column, and this is done across all segments until all bit sequences are line coded with respect to those segments.

[0033] A particular advantage is that the number of partial forward error corrections is the same as the number of segments. This means that the partial forward error corrections can be encoded using the same line encoder as the corresponding segments.

[0034] In either case, for each partial forward error correction, the segment encoder used for the segment in which the partial forward error correction was created is applied to generate one partial forward error correction line code for each partial forward error correction. This means that a segment encoder is used that line-codes the individual segment and then line-codes the corresponding partial forward error correction. This means that the segments are line-coded column by column using the same segment encoder as the partial forward error correction associated with the individual column.

[0035] Subsequently, all segment line codes and all partial forward error correction line codes are transmitted. According to one aspect of the present invention, the subdivision rule is ,This is read from the hardware architecture. This has the advantage that the subdivision rules can be statically predefined or modified within data memory. Furthermore, the subdivision rules can take into account the corresponding hardware architecture. For example, if different encoders are prepared for different bit lengths, the bit sequence is subdivided so that the corresponding segments correspond to the individual encoders. Thus, the segments have exactly the lengths provided by the individual encoders.

[0036] According to a further aspect of the present invention, all bit sequences have the same structure in their data format, the same segment length and / or the same bit position. This has the advantage that individual segments can be fed to separate encoders. For example, each first segment of each bit sequence is fed to the same encoder. Thus, figuratively speaking, segments are encoded column by column, and there is a dedicated encoder for each column.

[0037] According to a further aspect of the present invention, partial forward error correction includes correction information describing the target content of the segment on which the partial forward error correction is made. This has the advantage that transmitted data can be corrected by this correction data, thereby ensuring that individual partial forward error corrections are made for individual segments rather than the entire correction being made for each bit sequence. All partial forward error corrections, as a whole, describe all segments of all bit sequences, and therefore all user data. However, the difference from the prior art is that the forward error correction is not made for each bit sequence, but for all segments across all bit sequences. Therefore, it is possible to use the same line encoder for each partial forward error correction as the one used for the corresponding segment.

[0038] According to a further aspect of the present invention, the partial forward error correction has the same bit length as the segment in which the partial forward error correction is generated. This has the advantage of providing maximum efficiency in that a dedicated line encoder can be provided, and thus the corresponding column-direction line encoder is precisely dedicated to the bit length that needs to be encoded. Thus, an efficient method with minimal technical complexity is provided.

[0039] According to a further aspect of the present invention, the entire partial forward error correction describes all user data to be transmitted in a correctable manner. This has the advantage that all user data transmitted can be corrected for their errors, but because it is based on individual segments, the proposed method has a finer granularity than that offered by the prior art.

[0040] According to a further aspect of the present invention, each segment encoder generates at least a portion of a line code. This has the advantage that the outputs of the segment encoders can be combined to provide a line code to be transmitted.

[0041] According to a further aspect of the present invention, a set of segment encoders encodes a 112-bit bit sequence into a 128-bit word. This has the advantage of producing particularly efficient line codes.

[0042] According to a further aspect of the present invention, during transmission, a partial forward error correction line code is added to the segment line code. This has the advantage that all data to be transmitted is line-coded, and therefore the lines are processed deterministically, or the advantages of line coding can be applied not only to the payload data itself but to all data.

[0043] According to a further aspect of the present invention, the bit position is specified as an offset or bit index within a bit sequence. This has the advantage that different types of addressing schemes can be used and that the index can be advantageously specified using known methods, since it is based on a sequence of individual segments.

[0044] According to a further aspect of the present invention, user data is available as a serial data stream. This has the advantage that, theoretically, any amount of user data can be transmitted, and that the user data is divided into bit sequences of the same length.

[0045] According to a further aspect of the present invention, the method steps are performed in the order described and / or repeatedly. This has the advantage of reversing the order of the codes. According to the present invention, forward error correction is created first, followed by line coding. This does not preclude the need to perform individual process steps multiple times. This is the case, for example, when there are multiple bit sequences that must be segmented.

[0046] According to one aspect of the present invention, line code segments are generated for each data subword block and / or for forward error correction of each data subword block. This has the advantage that forward error correction, in particular, does not need to be transmitted in an uncoded form, but is instead line-coded. Thus, the advantages of line coding can be used not only for user data but also for forward error correction.

[0047] According to a further aspect of the present invention, forward error correction for a data block consists of multiple partial forward error corrections of data subword blocks. This has the advantage that instead of generating an overall forward error correction first, a number of individual partial forward error corrections are generated, which together form the overall forward error correction. In this way, the number of gates required for the FEC encoder is minimized. Nevertheless, all data is protected by forward error correction, and it is still possible to transmit the data in line-coded format along with the forward error-corrected FEC.

[0048] According to another aspect of the present invention, a data structure is read, and a forward error-correcting subencoder is selected according to the individual bit length of the data subword. This has the advantage that the FEC encoder is precisely fitted to the segment length or the bit length of the subword. In this way, the number of gates can be minimized, and the encoder only needs to encode small subwords, rather than the entire data word. As a result, each FEC encoder is precisely fitted to the bit length of the data subword to be encoded.

[0049] According to a further aspect of the present invention, the number of gates in the FEC partial encoder is selected according to the bit length of the data subword. This has the advantage of reducing the number of gates required in the FEC coder compared to the prior art, and as a result, providing an efficient system or method, which is particularly advantageous in automobiles or vehicles. In this way, there is no need to prepare unnecessary gates. This makes the number of gates deterministic and minimized.

[0050] According to a further aspect of the present invention, the number of gates for all encoders is selected such that, in iterative execution of the method, the number of gates increases linearly with increasing data word length. This has the advantage that the data format can be selected such that a minimum number of gates is provided considering the data format, or only a linear increase in the number of gates is required. For example, in one embodiment, the maximum bit length can be 10, 11, or 12 bits, which means that the required gates or circuitry of the FEC encoder increase only linearly. Since an exponential increase in gates is required for larger values, the present invention produces the technical effect of minimizing power consumption or energy consumption and leading to less heat dissipation. Furthermore, the proposed method is particularly robust, which is particularly advantageous in automobiles where safety-critical functions are provided.

[0051] According to a further aspect of the present invention, each data word has 112 bits. This has the advantage that a 128-bit word can be generated using line coding, which corresponds to a common format. According to the present invention, it has been demonstrated that 112 bits can be robustly encoded to 128 bits. This takes into account that transmission may be affected by data channels that are lossy or error-prone.

[0052] According to a further aspect of the present invention, the bit length of the forward error correction of the data subword block is selected to correspond to the bit length of the data subword. This has the advantage that both the forward error correction and the data subword or segment can be encoded using the same encoder, which is a line encoder rather than an FEC encoder. Thus, the present invention makes a technical contribution by not only preparing a minimum number of gates but also minimizing the total number of encoders. Consequently, the forward error correction can be line-coded with the same encoder as the actual segment of the user data.

[0053] According to a further aspect of the present invention, the forward error correction of a data subword block and the data subword block on which the forward error correction is calculated are line-coded using the same line encoder. This has the advantage that only a minimum number of line codings need to be prepared. Figuratively speaking, substantially every column, i.e., every subword block, is line-coded using the same segment encoder, along with its corresponding partial forward error correction.

[0054] According to a further aspect of the present invention, the data structure is selected according to the bit length of the data word. This has the advantage that it can dynamically accommodate different bit lengths at runtime and therefore the same data format as the initially provided data word can also be selected for subsequent data words. If the initial data word is available, the corresponding data structure can be used for subsequent serial data streams, and the subsequent data words are structured to correspond to the data structure of the initially received data word.

[0055] According to a further aspect of the present invention, serial line coding is performed after the forward error correction of the data subword block has been calculated. This has the advantage of reversing the order as provided in the prior art, with the forward error correction being calculated first, which means that the forward error correction also does not need to be line coded and transmitted unencrypted or unencoded.

[0056] According to a further aspect of the present invention, the method steps are performed in a virtualized manner, and information regarding the underlying encoders and / or gates is generated. This has the advantage that the implementation status can be evaluated in the preparation process steps, and in this regard, it is possible to determine how many gates or how many FEC encoders and / or line encoders need to be prepared. Furthermore, the entire process can be simulated. Hardware components can be provided virtually.

[0057] The problem of the present invention is also solved by a system device for improving forward error correction in serial coding for data transmission within a vehicle, the system device comprising: an interface unit configured to provide user data to be transmitted; a division unit configured to divide the provided user data into a plurality of bit sequences of the same length; another interface unit configured to read a subdivision rule for subdividing a bit sequence into a sequence of segments of a predetermined length at predetermined bit positions; a subdivision unit configured to apply the read subdivision rule to all bit sequences of the plurality of bit sequences; a correction unit configured to iteratively create individual partial forward error corrections for all segments at the same bit position across all bit sequences; a coding unit configured to iteratively apply an individual segment coder across all segments at the same bit position to generate segment line codes for each bit position and bit sequence across all segments; another coding unit configured to apply an individual segment encoder, also applied to the segment in which the individual partial forward error correction was created, to each individual partial forward error correction to generate an individual partial forward error correction line code for each partial forward error correction; and a transmission unit configured to transmit all segment line codes and all partial forward error correction line codes. The present invention also relates to a system or method for receiving data, then decoding it, and reading out both forward error correction and useful data.

[0058] The problems of the present invention can also be solved by carrying out the proposed method or by a computer program product having control instructions for operating the proposed device. A particular advantage of the present invention is that the proposed apparatus and units can be operated using this method. Furthermore, the proposed apparatus and units are suitable for carrying out the method according to the present invention. Accordingly, in each case, the apparatus implements structural features suitable for carrying out the corresponding method. However, the structural features may also be designed as process steps. The proposed method comprises steps for carrying out the function of the structural features. In addition, physical components may be provided or virtualized virtually.

[0059] Further advantages, features, and details of the present invention are provided in the following description, in which aspects of the invention are described in detail with reference to the drawings. The features described in the claims and specification may be essential to the invention individually or in any combination. Similarly, the features described above and those further described herein may be used individually or in any combination. Functionally similar or identical parts or components may be given the same reference numerals. The terms “left,” “right,” “top,” and “bottom” used in the description of embodiments are based on the designation of the drawings in a normally legible orientation or the drawing in an orientation having normally legible reference numerals. The illustrated and described embodiments should not be understood as definitive, but are essentially illustrative for the purpose of illustrating the invention. The detailed description is for the informational purposes of those skilled in the art, and therefore known circuits, structures, and methods are not shown or described in detail in this description so as not to make it more difficult to understand this description. [Brief explanation of the drawing]

[0060] [Figure 1] This figure shows several examples of process flows, including serial coding and calculation for forward error correction, using conventional technology. [Figure 2] This figure shows an optimized process flow using forward error correction and serial coding according to one aspect of the present invention. [Figure 3] This figure shows the encoding of user data and calculation of forward error correction using conventional technology. [Figure 4] This figure shows a method for improving forward error correction in serial coding for in-vehicle data transmission, according to the present invention. [Figure 5] This figure shows a comparison between conventional coding and a method for improving forward error correction according to one aspect of the present invention. [Figure 6] This figure shows the number of gates required per bit length for forward error correction. [Figure 7A] This figure shows the encoding of user data into line codes according to one aspect of the present invention. [Figure 7B] This figure shows a proposed system device for improving forward error correction in serial coding in in-vehicle data transmission, according to one aspect of the present invention. [Figure 8A] This figure shows one embodiment of a method for improving forward error correction on the transmitter side, according to one aspect of the present invention. [Figure 8B] This figure shows a method for improving forward error correction on the receiver side, according to one aspect of the present invention. [Figure 9] This is a flowchart of a method for improving forward error correction in serial coding for in-vehicle data transmission, according to one aspect of the present invention. [Modes for carrying out the invention]

[0061] This figure partially shows parameters that are well known to those skilled in the art in English and are used as parameters, and therefore do not need to be translated. Figure 1 shows three examples of how forward error correction is performed according to conventional methods. On the left, an example is shown in which serial coding of user data is performed first, and then a forward error correction code (FEC) is generated. The serially encoded data is transmitted, and then the forward error correction is encoded and appended to the encoded user data. Thus, according to this example from the prior art, the forward error correction is generated over the entire data word, which must then be encoded again and appended. Therefore, the forward error correction is encoded over the entire bit sequence, rather than over individual segments.

[0062] The center shows another example of prior art, where the line coding step for forward error correction is omitted and unencoded parity information is added. The drawback here is that the final data portion, i.e., the parity information, is not line-coded, making it highly prone to errors.

[0063] The example on the right, in contrast to the central example, shows an example where parity information is not looped back into serial coding. This has the same drawback as the central example. Data transmission solutions constantly impose increasingly stringent requirements for error-free operation / error tolerance, which necessitates fine-tuning between serial coding and forward error correction (FEC) as data rates continue to increase.

[0064] Current conventional technologies (Ethernet® / DisplayPort) process data streams in the following order: 1. Input data is encoded in the first step using serial coding (8b10b, 64b66b, 128b132b, etc.). For larger codings than 64b66b, this is achieved primarily by scrambling using LFSR.

[0065] 2. The serialized stream is then further protected against bit errors by FEC (Forward Error Correction) coding. A complete FEC coding (FEC coding word) includes both the symbol-based input data and the so-called parity symbol. In these applications, the input data passes through FEC as is. This means that the input data always corresponds to the original serial code. Herein lies another procedure:

[0066] a. The parity symbol is then coded serially (e.g., 8b10b) to meet the requirements for serial transmission (run-length encoding, DC balance, etc.). This additional subsequent coding of the parity symbol requires an additional encoder in hardware.

[0067] b. Another solution involves using feedback of the parity symbol to step 1) instead of the subsequent serial coding of the parity symbol described above. A serial encoder allows for control of DC balance based on the selection of a positive or negative symbol. However, this is associated with a corresponding dead time (depending on the serial coding and FEC encoder values). This can lead to large deviations in the amount of temporal DC balance, for example.

[0068] c. The parity symbol is sent directly to the serial link (e.g., DisplayPort 2.0) unprocessed. However, this is highly inaccurate because the parity symbol is generated dependent on the input data. Here, we rely on the fact that the parity symbol is DC balanced on average.

[0069] All of the methods described in (a) to (c) above have the drawback of requiring a large amount of resources (e.g., two serial encoders) or resulting in inaccurate serial coding (e.g., DC balancing, run-length encoding, spectral encoding). In particular, improper control of serial coding in combination with the transmission channel can lead to the data stream not being accurately reconstructed at the receiver (the CDR sampling inaccurately). While these effects are mitigated by using FfEC (to correct bit / symbol errors), this unnecessarily deprives FfEC coding of correction margin for signal integrity or additional necessary error correction for errors caused by external influences, etc., with each error caused by inadequate serial coding. Reed-Solomon FEC can only correct t symbol errors based on the size of the overhead in the symbol (2t, see Figure 3).

[0070] On the other hand, Figure 2 shows the method according to the present invention, in which forward error correction is generated across the user data and is also encoded together with the user data. The advantage of the present invention is that both the user data and the forward error correction are line-coded, and therefore the method is robust against errors. This figure also shows that a difference from the prior art is that the forward error correction is generated directly against the user data, rather than against the line-coded user data. This makes it possible to transmit all data in a line-coded form, resulting in improved robustness against errors.

[0071] The method proposed below to address the aforementioned challenges applies to all conceivable ECC / FEC coding and is not limited to Reed-Solomon coding. The proposed procedure changes the order of serial coding and FEC.

[0072] 1. In the first step, the input data is protected by FEC or multiple individual FEC units with a smaller symbol width (6-12 bits). This also incurs an overall overhead of 2t.

[0073] The use of multiple FEC subcodings is particularly preferred here because it has additional positive characteristics (described below). 2. Subsequently, individual current FEC output symbols (multiple) (which should not be confused with the entire FEC coded word n) are coded using block codes, while preserving all desired characteristics such as DC balance, run-length encoding, and frequency spectrum.

[0074] In the case of multiple FEC codings in step 1), exactly the same number of block coders are used here. This means that on the receiving end, even if a bit error on the link corrupts one complete data symbol of the serial code, it will result in only a single FEC symbol error.

[0075] Figure 3 shows a flowchart of a conventional technique where input data is line-coded, and then forward error correction is generated. This forward error correction is added to the right, as shown at the bottom. This means that the data word is line-coded first at the top, and then the unline-coded forward error correction is added. This presents a problem because the forward error correction does not have the desired characteristics necessary for robust data transmission. This results in the disadvantage that the data is not DC (digital current) balanced, i.e., a favorable parity is not set. Furthermore, in transmissions that are not line-coded, errors can occur during clock regeneration. In general, line coding is advantageous in that the average value of the analog signal can be measured, and then it can be checked which actual signals are above this average value and which actual signals are below this average value. Here, it is desirable that the number of analog signals above the average value, i.e., the number of digital "1s", is the same as the number of analog signals below the average value, i.e., the number of digital "0s". This means that optimized signal modeling can be performed. This is not possible in Figure 3 because the forward error correction code is not line-coded.

[0076] Figure 4 illustrates the procedure and transmission over a lossy channel according to the present invention. Here, each channel is potentially susceptible to loss, and it is particularly advantageous that forward error coding is performed first at the data input, followed by overall serial coding. On the receiver side, the procedure is performed in reverse, with serial decoding performed first, thereby restoring forward error correction in addition to the user data.

[0077] Figure 5 illustrates the prior art method in the upper example, where in the first method step, the output data word or bit sequence is line-coded from the first line to the second line. This results in a code longer than the output bit sequence, which is also called overhead. In the subsequent processing step, a forward error correction code is generated from the second line to the third line and added to the line coding. As can be seen, the first portion on the left side of the data to be transmitted is line-coded, while the second portion, i.e., the forward error correction, is not line-coded. This causes problems because the advantages of line coding cannot be utilized in the added portion on the right side. This is a disadvantage.

[0078] In the central example of Figure 5, the source word ABC is again shown in the upper row. Thus, the bit sequence consists of segments A, B, and C, which are 11-bit, 6-bit, and 7-bit in length, respectively. According to the present invention, instead of the entire data word, i.e., the entire bit sequence, being protected, and instead of a forward error correction code being provided, individual segments are protected. This is indicated by the fact that in the second line, the corresponding forward error correction codes are shown after each segment A, B, and C. In a subsequent process step, line coding is applied in the third line, i.e., the data from the second line is completely line coded, and a line code is generated in the third line. Here, it can be seen that this line code is transmittable, and the entire data is line coded, and the forward error correction code is also line coded. Thus, the advantages of line coding apply to all data to be transmitted.

[0079] In the lower part of Figure 5, an example of the embodiment illustrates the steps of the method according to the present invention, and further substeps are possible. Here, different bit sequences are shown, and the user data is divided into bit sequences of the same length. In this way, the entire user data is divided into four bit sequences, all of the same length. These four bit sequences are divided into segments of the same length. Figuratively speaking, the individual bit sequences are arranged horizontally, and these bit sequences are arranged vertically, with each line reflecting a bit sequence. Also, as can be seen from the figure, each bit sequence is divided into three segments of the same length. This gives the user data a matrix-like arrangement where each row is a bit sequence and each column is a segment.

[0080] Here, line coding as provided in prior art is not performed, and partial forward error correction is calculated for each column, i.e., for all segments at the same bit position, according to a subdivision rule specified in a higher processing step. Partial forward error correction is shown at the top, as seen in the first row of the second rectangle, and in this figure, the entire partial forward error correction is called the FEC overhead. Here, the segmented bit sequences become available according to the subdivision rule, and partial forward error correction becomes available for all segments at the same bit position across all bit sequences.

[0081] Subsequently, a segment encoder is applied to all segments at the same bit position to generate segment line codes for all segments, bit by bit and bit by bit sequence. Further in another process step, or in the same process step, the segment encoder used for the segments is applied to individual partial forward error corrections to obtain a single line code containing the segment line code and the partial forward error correction line code. As shown at the bottom of Figure 5, all data is line-coded, and in particular, the forward error correction FEC is also line-coded. This means that this data can be transmitted advantageously.

[0082] Figure 6 shows the number of gates required to create a forward error correction code on the y-axis, depending on the bit length to be encoded on the x-axis. As can be seen, this is an exponential increase, and from bit lengths of 10 to 12 bits, the number of gates, i.e., the number of gates required for forward error correction, increases above average. Therefore, according to the present invention, it is particularly advantageous to perform forward error correction segment by segment, as it is no longer necessary to consider the entire data word, i.e., the entire bit length. If the entire bit length must be considered in forward error correction, the bit length will typically exceed the critical 12 bits. The number of gates required in the forward error correction encoder will increase unfavorably. Therefore, this demonstrates the advantageous technical effect of the present invention, which involves first forming multiple segments across a bit sequence and then calculating forward error correction for each segment.

[0083] At this point, we refer again to the subdivision rules shown in Figure 5, which specify that a segment can have 11 bits, 6 bits, or 7 bits. By using multiple FEC encoders / decoders with smaller FEC symbol sizes, the number of gates required is reduced, and given process node F max The maximum operating frequency for this increases (due to shorter carry chains and improved parallelism).

[0084] Figure 6 shows the relationship between the FEC symbol size (in bits) and the required implementation. This refers to the hardware implementation of the Reed-Solomon FEC. The number of gates is normalized (to a 12-bit symbol size) and can therefore be directly compared. The graph can be seen to show an exponentially significant relationship between the symbol size (in bits) and the implementation per gate.

[0085] Note that the symbol widths of individual small FEC subencoders do not necessarily have to be the same. Larger serial encodings can consist of multiple different subencoders (the simplest example being 8b10b, which can be constructed from 3b4b and 5b6b), similar to the proposed use of FEC. In the case of this invention or ADXpress®, this is achieved by a total of 11 encoders, namely 6b8b, 7b8b, 11b12b, and 11b13b. The FEC symbol width used for individual subcodings is determined by the data word width of the individual serial encoder. For example, 6b8b uses an FEC with a symbol width of 6 bits.

[0086] The complete structure of the transmitter data path of the present invention or ADXpress is shown according to one aspect of Figure 8A. The data path in the receiver has a corresponding inverse structure (see also Figure 8B).

[0087] Figure 7A shows a line coding or line coding device having multiple line coding units, for example, that map 11 bits to 12 bits, 11 bits to 13 bits, or 11 bits to 12 bits. This corresponds to the right-to-left order in Figure 7 and shows that the input data word, which is the bit sequence described above, is divided into individual segments, and then each individual segment is line coded. Since the calculation of forward error correction is not yet considered in Figure 7A, the system device according to Figure 7A can function as the output system device of the present invention.

[0088] Figure 7A shows an arbitrary 112-bit bit sequence at the top, which is segmented into 11-bit, 6-bit, or 7-bit segments. The coding units are then addressed in parallel, and these coding units convert the bits into sub-symbols so that the bits are optimized with respect to disparity. For example, 11 bits are coded into 12 bits, or 11 bits are coded into 13 bits.

[0089] In Figure 7A, the coding unit format of the second subset is shown at the leftmost center, labeled 11B12B. This coding unit provides subsymbols with arbitrary codes, i.e., arbitrary disparity. To compensate for this disparity, coding unit 11B13B is connected downstream in parallel to the bit sequence. This means that a data stream is formed in which the most significant bits of 11 times twice as many are converted into two subsymbols; that is, an 11-bit data segment is converted by 11B12B into a 12-bit subsymbol with arbitrary codes, i.e., disparity, and the data segment is encoded from 11 bits to 13 bits by coding unit 11B13B. As shown below the coding units in the figure, the second coding unit from the left, 11B13B, is the coding unit of the first subset. The coding unit of the first subset has an inverter and a multiplexer. Thus, the first 13 bits are available as a data stream, which is branched so that it is inverted once with respect to the code, i.e., disparity, and remains unchanged once. As shown further below, a positive or negative value, i.e., the original data stream or the inverted data stream, is used under disparity feedback to compensate for the code from the leftmost coding unit. Thus, the first multiplexer on the left receives two data streams, each representing a subsymbol with the normal code as the output from the 11-bit 13-bit coding unit and a subsymbol with the inverted code or inverted disparity.

[0090] Therefore, based on feedback from the top unit, it is determined what kind of disparity will arise from the leftmost encoder 11B12B, and the lower left multiplexer compensates for or minimizes the disparity for the subsymbols of the leftmost encoder 11B12B. This is performed in parallel, with coding units from the first subset that minimize or eliminate disparity following coding units from the second subset. Finally, the entire symbol is output from the lower right. This entire symbol has 128 bits and consists of subsymbols that are inserted using diagonal arrows in the thick line below. Therefore, on this output line there are subsymbols that have been optimized or minimized with respect to disparity, and these subsymbols then form the entire symbol that can be output and transmitted.

[0091] According to one aspect of the present invention, the present invention encodes a 112-bit wide data word having an arbitrary disparity (maximum disparity: 112) and an arbitrary run length (maximum run length: 112) into a 128-bit wide symbol. This means that the overhead caused by the encoding is 14.2%.

[0092] The maximum run-length encoding that occurs within a symbol is eight identical bits, just as with any sequencing of any symbol. The maximum disparity in the long-term average is 0, and the disparity in the symbol is less than 9.

[0093] The logic complexity is minimal, comparable to 10 8B / 10B encoders (though it has the known drawback of high overhead). This is achieved by using or using in parallel multiple "small" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0094] Encoders 11B12B, 7B8B, and 6B8B generate all symbols that guarantee a maximum run-length of 6, regardless of the order in which the (partial) symbols are ordered. According to one aspect of the present invention, the encoder (11B13B) generates a symbol with a guaranteed maximum run length of 7, or a symbol whose first or last run length is 5. Due to the ordering of (11B13B) with other encoders (Figure 2), a maximum run length of 8 can be generated within a symbol.

[0095] The characteristics of the encoder are shown below. 11B13B: 11 bits of data are mapped to 2048 symbols, each having 13 bits. These symbols can be transmitted in inverted or non-inverted form.

[0096] Disparity: +3...+9 or controllable -3...-9 Run length within word: 7 Run length at the edge: 5.

[0097] 11B13B: 11 bits of data are mapped to 2048 symbols, each having 13 bits. These symbols can be transmitted in inverted or non-inverted form. Disparity: +3...+9 or controllable -3...-9 Run length within word: 7 Run length at the edge: 5.

[0098] 11B12B: 11 bits of data are mapped to 2048 symbols, each having 12 bits. The symbols are transmitted only in their non-inverted form. Disparity: -2, -1, 0, 1, 2 Run length within word: 6 Run length at the edge: 3.

[0099] 7B8B: 7 bits of data are mapped to 128 symbols, each having 8 bits. The symbols are transmitted only in their non-inverted form. Disparity: -2, -1, 0, 1, 2 Run length within word: 6 Run length at the edge: 3.

[0100] 6B8B: 6 bits of data are mapped to 64 symbols, each having 8 bits. The symbols are transmitted only in their non-inverted form. Disparity: 0 Run length within word: 6 Run length at the edge: 3 Using four 11B13B encoders, a controllable disparity of at least ±12 can be generated, thereby compensating for the uncontrollable disparity of up to ±12 (6x±2) of 11B12B and 7B8B encoders. As a result, balanced disparity can be reliably achieved regardless of the data to be transmitted.

[0101] To further reduce hardware complexity, according to one aspect of the present invention, four miniature encoders (11B13B) are used, and their disparity can be controlled with respect to sign (+ / -).

[0102] According to one aspect of the present invention, symbol disparity is controlled so that each encoder calculates the parity of "each" subsymbol. This can be done with minimal overhead because subsymbols have only a few bits.

[0103] By using four of the eleven encoders to invert the generated subsymbols, the sign of the disparity of the subsymbols can be actively controlled. For this purpose, the encoders (11B13B) are characterized in that they generate symbols that have positive disparity (+3...+9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3...-9) can be obtained.

[0104] In this way, the disparities (-2,-1,0,1,2) of the partial symbols of the other encoders (11B12B and 7B8B) can be compensated. Encoder 6B8B generates symbols with a disparity of always 0. Then, all (partial) parities of the encoders (11B12B and 7B8B) are added together, and the result controls the decision of how many inverted and non-inverted symbols of encoder (11B13B) to use.

[0105] The minimum disparity of encoders 11B and 13B is ±3. Therefore, a total disparity of ±12 (4 * ±3) per symbol can be reliably compensated using these four encoders.

[0106] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in extreme cases, these six encoders would generate exactly ±12 (2*±6) disparity. This can be reliably compensated for by the 11B13B encoder.

[0107] According to one aspect of the present invention, this method achieves the same quality as 8B10B code despite having half the overhead (encoding loss). By using multiple small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires minimal resources (logic).

[0108] Encoding can typically be completed entirely in a single cycle of a parallel data path (pipeline processing is not required). Controlling the disparity of 128-bit symbols can be achieved with (very) little logic and can be done entirely within a single clock cycle (slow) of the data path, rather than calculating disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0109] Due to deterministic disparity and run-length encoding, additional scrambling is not required, and therefore, high-speed synchronization to the data stream is possible at the receiver side (scrambler synchronization is not necessary).

[0110] In particular, this is extremely useful for a power-saving mode that allows the link to be turned off to conserve energy and turned back on when needed. For this to work, high-speed synchronization between the transmitter and receiver is essential.

[0111] According to one aspect of the present invention, the present invention encodes a 112-bit wide data word having an arbitrary disparity (maximum disparity: 112) and an arbitrary run length (maximum run length: 112) into a 128-bit wide symbol. Therefore, the overhead caused by the encoding is 14.2%.

[0112] The maximum run-length encoding that occurs within a symbol is eight identical bits, just as with any sequencing of any symbol. The maximum disparity in the long-term average is 0, and the disparity in the symbol is less than 9.

[0113] The logic complexity is minimal, comparable to 10 8B / 10B encoders (though it has the known drawback of high overhead). This is achieved by using or using in parallel multiple "small" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0114] Encoders 11B12B, 7B8B, and 6B8B generate all symbols that guarantee a maximum run-length of 6, regardless of the order in which the (partial) symbols are ordered. According to one aspect of the present invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7, or symbols with a run length of 5 at the beginning or end. Due to the ordering of (11B13B) with other encoders (Figure 2), a maximum run length of 8 can be generated within a symbol.

[0115] The characteristics of the encoder are shown below. To further reduce hardware complexity, four small encoders (11B13B) are used, and their disparity can be controlled with respect to the sign (+ / -).

[0116] According to one aspect of the present invention, symbol disparity is controlled so that each encoder calculates the parity of "each" subsymbol. This can be done with minimal overhead because subsymbols have only a few bits.

[0117] By using four of the eleven encoders to invert the generated subsymbols, the sign of the disparity of the subsymbols can be actively controlled. For this purpose, the encoders (11B13B) are characterized in that they generate symbols that have positive disparity (+3...+9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3...-9) can be obtained.

[0118] In this way, the disparities (-2,-1,0,1,2) of the partial symbols of the other encoders (11B12B and 7B8B) can be compensated. Encoder 6B8B generates symbols with a disparity of always 0. Then, all (partial) parities of the encoders (11B12B and 7B8B) are added together, and the result controls the decision of how many inverted and non-inverted symbols of encoder (11B13B) to use, respectively.

[0119] The minimum disparity of encoders 11B and 13B is ±3. Therefore, a total disparity of ±12 (4 * ±3) per symbol can be reliably compensated using these four encoders.

[0120] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in extreme cases, these six encoders would generate exactly ±12 (2*±6) disparity. This can be reliably compensated for by the 11B13B encoder.

[0121] This process achieves the same quality as 8B10B code, despite having half the overhead (coding loss). By using multiple small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires minimal resources (logic). Encoding can typically be completed entirely in a single cycle of a parallel data path (pipeline processing is not required).

[0122] Controlling the disparity of 128-bit symbols can be achieved with (very) little logic and can be done entirely within a single clock cycle (slow) of the data path, rather than calculating disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0123] Due to deterministic disparity and run-length encoding, further scrambling is unnecessary, and therefore, high-speed synchronization to the data stream is possible at the receiver (scrambler synchronization is not required).

[0124] In particular, this is extremely useful for a power-saving mode that allows the link to be turned off to conserve energy and turned back on when needed. For this to work, high-speed synchronization between the transmitter and receiver is essential.

[0125] Figure 7B shows the adapted system assembly from Figure 7A, where a newly corresponding partial forward error correction encoder is shown. These are referred to herein as FEC blocks. Thus, Figure 7B shows that the segment is first formed from a bit sequence, which corresponds to the upper arrow pointing downward from the user data. This is the case when the partial forward error correction is generated and then fed to the coding unit, as already shown in Figure 7A. The line coding unit, referred to herein as the line coder, encodes both the segment of the bit sequence and the partial forward error correction. Parity can be adjusted at any process step. The line-coded data is then output at the bottom and transmitted to a receiver (not shown) via a rightward potentially error-prone communication channel.

[0126] Figure 8A illustrates a method according to the present invention for improving forward error correction, and in particular, shows the method steps performed on the transmitter side. The downward arrow in Figure 8A corresponds to the upward arrow in the following Figure 8B. Thus, the data is input as shown in Figure 8A, and then partial forward error correction is calculated. As can be seen from the above, all segments have the same bit length. This means that the first column contains 11 bits, the second column contains 11 bits, and the last column contains 6 bits.

[0127] Here, partial forward error correction is generated for all segments at the same bit position that have the same bit length as the corresponding segment. As a result, data with parity symbols is obtained. In the final processing step, serial line coding is performed, for example, mapping 11 bits to 12 bits, or 11 bits to 13 bits, or 6 bits to 8 bits. This data can be transmitted over a potentially interference-prone channel. This results in transmission as shown in the lower part of Figure 8A or the upper part of Figure 8B.

[0128] Figure 8B shows the receiver-side procedure, which is the reverse of the procedure in Figure 8A. As also shown in Figure 8B, bit errors may exist, but it is recognized that these can be handled particularly favorably at the segment level. Thus, bit errors can be handled favorably because they occur only in individual segments and not in the entire bit sequence. This results in corrected data as shown in the lower part of Figure 8B, and thus the 112 bits used as output in Figure 8A are restored.

[0129] Figure 9 shows a method for improving forward error correction in serial coding for data transmission within a vehicle. The method includes steps 100 (providing user data to be transmitted), 101 (dividing the provided user data into multiple bit sequences of the same length), 102 (reading a subdivision rule that subdivides the bit sequences into sequences of segments of a predetermined length at predetermined bit positions), 103 (applying the read subdivision rule to all bit sequences of the multiple bit sequences), and iteratively creating individual partial forward error corrections for all segments at the same bit position across all bit sequences. The process includes step 104, step 105, which involves iteratively applying individual segment encoders across all segments at the same bit position to generate segment routing codes across all segments for each bit position and bit sequence, step 106, which involves applying individual segment encoders (105) that were also applied to the segments (104) where the individual partial forward error correction was created, to each individual partial forward error correction to generate individual partial forward error correction routing codes for each partial forward error correction, and step 107, which involves transmitting all segment routing codes and all partial forward error correction routing codes.

[0130] All segment line codes and all partial forward error correction line codes are also transmitted. In this final step, all generated segment line codes and partial forward error correction line codes are transmitted. These transmitted codes include information for error detection and correction for the corresponding segments, and information for partial forward error correction. The described method enables improved forward error correction during serial coding and data transmission in vehicles. Effective error detection and correction are achieved at the segment level by dividing user data into segments and applying specific coding procedures to these segments.

[0131] By iteratively creating partial forward error correction for all segments at the same bit position and applying a segment encoder to each segment, targeted error correction of transmitted data becomes possible. The partial forward error correction line code contains the information necessary to detect and correct errors, while the segment line code represents the structure and content of the segment, also contributing to error detection and correction.

[0132] By transmitting all generated segment line codes and partial forward error correction line codes, the receiver can properly analyze the received data, detect and correct errors, and ensure reliable and accurate transmission of user data within the vehicle.

[0133] Therefore, the described method provides improved forward error correction, which is particularly important in harsh environments such as vehicles where interference and signal loss can occur. This method helps ensure reliable and high-quality data transmission, which is crucial for various applications in the automotive sector, such as autonomous driving, vehicle safety systems, and infotainment applications.

[0134] This invention makes it possible to operate the FEC efficiently while always maintaining all the desired characteristics and requirements for serial coding. By intentionally placing the serial encoder downstream of the FEC unit, the physical behavior on the link can always be controlled deterministically (this is not the case when a scrambler is used as the serial encoder).

[0135] Furthermore, selecting FEC symbol sizes based on the data word size of individual serial subencoders always ensures that bit errors propagate to the minimum extent possible (a defective linecode symbol will generate only one defective FEC symbol).

[0136] Furthermore, by using multiple FEC subencoders, a highly efficient form of so-called interleaving is created. This is possible without time-consuming manual interleaving of symbols, which would require data to always be held (more latency and buffering). This also makes it possible to correct burst errors (e.g., 112 / 128 bit errors) all at once.

[0137] This fact can only be seen from the schematic structures in Figures 7A, 7B and 8A, 8B. In this case, a 128-bit error leads to only one single symbol error in the individual FEC subencoders. In conventional single FEC coding, a burst error of the same length (128 consecutive bits of error) will generate multiple symbol errors in succession. This can lead to a situation where, depending on the chosen encoding, the FEC word (all the symbols of the FEC cycle) becomes undecodeable (and therefore uncorrectable). This is usually achieved by interleaving the symbols of one or more other FEC cycles. However, this is only possible by using buffers on both the transmitter and receiver sides, so that the transmitter can interleave the data and the receiver can reverse-engineer it back into the original consecutive FEC symbol data stream of the individual FEC cycles. By using multiple small FEC encoders, interleaving, and therefore the need to maintain buffers required for interleaving, is eliminated (however, this is limited to a certain extent; consecutive burst errors exceeding 128 bits, as described in the example, will damage two or more symbols for each individual FEC).

[0138] The number of symbols (t) that an individual FEC subencoder can repair depends on the overhead 2t (see Figure 2). This must be selected according to the desired application. As shown in Figure 8A, if each FEC subencoder has one symbol error, this is already achieved at t=1 (i.e., the overhead of two parity symbols). It should also be noted that burst errors can occur, or may occur, without limitation in the parity symbol area.

Claims

1. A method for improving forward error correction in serial coding for data transmission within a vehicle, Step (100) of providing user data to be transmitted, The steps include (101) dividing the provided user data into multiple bit sequences of the same length, Step (102) of reading a subdivision rule that subdivides a bit sequence into a sequence of segments of a predetermined length at predetermined bit positions, Step (103) of applying the read subdivision rule to all bit sequences of the plurality of bit sequences, Step (104) involves iteratively creating individual partial forward error corrections for all segments at the same bit position across the entire bit sequence, Step (105) involves iteratively applying individual segment encoders across all segments at the same bit position to generate segment line codes across all segments for each bit position and bit sequence, Step (106) is to apply the individual segment encoder, which has also been applied to the segment (104) on which the individual partial forward error correction was created, to the individual partial forward error correction, and generate an individual partial forward error correction line code for each partial forward error correction. A method comprising the step (107) of transmitting all segment line codes and all partial forward error correction line codes.

2. The method according to claim 1, characterized in that the subdivision rules are stored in data memory and exist as coding rules and / or are read from the hardware architecture.

3. The method according to claim 1 or 2, characterized in that all bit sequences have the same structure, the same segment length and / or the same bit position in their respective data formats.

4. The method according to any one of claims 1 to 3, characterized in that the partial forward error correction has correction information describing the target content of the segment in which the partial forward error correction was created.

5. The method according to any one of claims 1 to 4, characterized in that the partial forward error correction has the same bit length as the segment on which the partial forward error correction is created.

6. The method according to any one of claims 1 to 5, characterized in that the entire partial forward error correction describes all user data to be transmitted in a correctable form.

7. The method according to any one of claims 1 to 6, characterized in that each of the segment encoders generates at least a portion of a line code.

8. The method according to any one of claims 1 to 7, characterized in that the entire segment encoder encodes a 112-bit bit sequence into a 128-bit word.

9. The method according to any one of claims 1 to 8, characterized in that the partial forward error correction line code is added to the segment line code during transmission (107).

10. The method according to any one of claims 1 to 9, characterized in that the bit position is indicated as an offset or bit index in the bit sequence.

11. The method according to any one of claims 1 to 10, characterized in that the user data exists as a serial data stream.

12. The method according to any one of claims 1 to 11, characterized in that the steps of the method are carried out in the order described and / or repeatedly.

13. A system device for improving forward error correction in serial coding for data transmission within a vehicle, An interface unit configured to provide user data to be transmitted (100), A splitting unit configured to divide the provided user data into multiple bit sequences of the same length (101), Another interface unit configured to read a subdivision rule (102) that subdivides a bit sequence into a sequence of segments of a predetermined length at predetermined bit positions, A subdivision unit configured to apply the read subdivision rule to all bit sequences of the plurality of bit sequences (103), A correction unit configured to iteratively create individual partial forward error corrections for all segments at the same bit position across the entire bit sequence (104), A coding unit configured to generate segment line codes over all segments for each bit position and bit sequence by iteratively applying individual segment coders over all segments at the same bit position (105), Another coding unit is configured to generate a separate partial forward error correction line code for each partial forward error correction (106) by applying a separate segment code (105) to the segment (104) on which the separate partial forward error correction was created, for each separate partial forward error correction, A system device comprising a transmission unit configured to transmit all segment line codes and all partial forward error correction line codes (107).

14. A computer program product comprising instructions, wherein, when the program is executed by at least one computer, the instructions cause the computer to perform a step according to any one of claims 1 to 12.

15. A computer-readable storage medium containing instructions, wherein, when executed by at least one computer, the instructions cause the computer to perform a step of the method according to any one of claims 1 to 12.

Images