Efficiently transmittable bit sequences with limited disparity and encoded forward error correction.

Abstract

The present invention relates to a method for generating an efficiently transmittable bit sequence with limited disparity and limited run-length. The proposed method enables data to be transmitted particularly efficiently over a transmission channel. One of the advantages of the present invention over the prior art is that the physical behavior on the transmission channel can always be controlled deterministically while reducing resource requirements. Thus, according to the proposed method, bit errors are minimized, and transmission errors can be corrected efficiently, i.e., with minimal technical effort. Furthermore, the encoder used is designed with a minimum number of gates, and interleaving is implicitly present in the proposed method, which ensures that so-called burst errors can be corrected particularly favorably.

Description

[Technical Field]

[0001] The present invention relates to a method for generating an efficiently transmittable bit sequence with limited disparity and limited run-length. The proposed method enables data to be transmitted particularly efficiently over a transmission channel. One advantage of the present invention over the prior art is that the physical behavior on the transmission channel can always be controlled deterministically while reducing resource requirements. Thus, according to the proposed method, bit errors are minimized, and transmission errors can be corrected efficiently, i.e., with minimal technical effort. Furthermore, the encoder used is designed with a minimum number of gates, and interleaving is implicitly present in the proposed method, based on the fact that so-called burst errors can be corrected particularly favorably. This implicit interleaving makes it possible to eliminate the buffer memory that was conventionally required for explicit interleaving. In addition, the present invention ensures that user data can be encoded favorably for transmission along with correction metadata. According to the present invention, it can be guaranteed that not only user data but also correction data can be line-coded or line-encoded. Optimized disparity is a quality feature for the transmittability of data. Undesirable disparity can mean that data is not properly transmitted through the data channel because it cannot be properly interpreted at the receiving end. Another quality characteristic is data efficiency, which relates to the ratio of user data transmitted to additional data not directly related to the content of the user data. This includes so-called header data. The proposed invention makes it possible to generate a data stream that can be read particularly efficiently and is also highly efficient with respect to overhead data. This minimizes the so-called overhead of user data, thereby creating an extremely efficient process. Unambiguity at the receiving end ensures that the data does not need to be transmitted repeatedly and can be read with high error tolerance at the receiving end.Furthermore, the proposed method can convert data segments in parallel into sub - symbols or symbols composed of sub - symbols. This parallel design is particularly efficient because only units that are technically easy to manufacture are required. Therefore, the efficiency improvement also relates to the hardware or runtime used. The present invention further relates to a correspondingly configured system device, a computer program product having control instructions for executing the method, and a memory - readable medium.

Background Art

[0002] Patent Document 1 describes a system and method for transmitting packets over a data link. A packet may contain a data stream delimited by one or more frame symbols.

[0003] Patent Document 2 shows that two coding schemes are integrated instead of each coding being performed independently of the others. The two coding schemes can be integrated by interleaving one or more operations of one coding scheme (e.g., data coding) between two or more operations of the other coding scheme (e.g., line coding). In some embodiments, the division of data blocks (e.g., bytes) for line coding (e.g., DC equalization coding) is performed before data coding (e.g., error correction coding).

[0004] Patent Document 3 describes an 8B / 10B serial transmission code that ensures a balanced distribution of 1s and 0s, has a maximum run length (code run) of 4, and achieves a transition density of 40% in the worst case. In addition, the code includes two special control characters that are unique in the encoded bitstream and can be used for synchronization.

[0005] Patent Document 4 describes a binary DC balanced code and an encoding circuit for its implementation, in which an 8-bit information byte is converted into 10 binary characters for transmission over an electromagnetic or optical transmission line with temporal and low-frequency limitations.

[0006] Patent Documents 5 show a method that enables an analog data stream to be read out via a data line, especially in an error - prevention method. In particular, the amplitude of the signal is monitored, and preferably, the signal is measured at the point where the amplitude is maximum. Thereby, the analog data stream is converted into a digital data set, and the maximum amplitude corrects whether the threshold between 0 and 1 on the line is safely exceeded or not.

[0007] From the prior art, various coding methods and data transmission methods are known, but all of them are related to application scenarios that can only be disadvantageously utilized in automobiles. For example, the prior art often assumes that high computing power is available and high real - time requirements are not imposed. Furthermore, the prior art often assumes that the weight or reliability of the components used plays only a secondary role. In many cases, the prior art refers to conventional computer networks where reliability and low technical complexity are not so important.

[0008] Furthermore, so-called forward error correction is known from prior art. Forward Error Correction (FEC) is an error correction method in which additional redundant information is added to the data. This redundancy allows the receiver to detect and correct errors without having to retransmit the packet. FEC is often used in high-speed Ethernet connections such as 10 Gigabit Ethernet (10GbE) to ensure data integrity.

[0009] Based on this prior art, there is a need to create a method or system that enables data to be processed as quickly as possible for automotive safety requirements, requires minimal technical effort, and minimizes the error rate during transmission by making retransmission impossible if an error is detected. Low technical effort should mean incorporating components that are as simple, lightweight, and mass-producible as possible. Known methods and system devices from computer network technology are typically unsuitable here because weight reduction and real-time operation are not critical factors in standalone PCs or servers. While heat dissipation is generally a challenge for computer configurations, energy efficiency in automobiles is even more important in electromobility, for example, because power consumption affects the range of the vehicle.

[0010] Further prior art concerns the transmission of data in serial data streams. For example, prior art provides extensive descriptive data to be transmitted along with user data, indicating where the user data is located and how it should be interpreted. Furthermore, prior art is known to discard individual data packets if they are not transmitted correctly. It is also known that prior art retransmits data packets if they do not arrive at the sender on time or if they arrive at the sender in an unexpected format.

[0011] In serial data transmission, it is necessary to have as many equal numbers of 1s and 0s as possible within the serial data stream. This is called disparity. To avoid baseline drift during transmission, it is desirable to have zero disparity on average and over short periods. Baseline drift (DC voltage fluctuations) in serial signals can lead to bit errors. In extreme cases, transmission may become impossible.

[0012] To ensure that the serial bits in the serial data stream can be reliably recovered at the receiving end without the need to transmit a clock, a minimum number of transitions from 0 to 1 or 1 to 0 are required. This means that the clock for recovering the serial data is locally generated at the receiver from the serial data stream. The so-called run-length specifies the number of consecutive occurrences of the same bit (1 or 0) without change. A short run-length is always desirable because a long run-length no longer reliably recovers the clock from the serial data stream.

[0013] The task of line code (in this case, block code or line code) is to generate symbols with guaranteed disparity and guaranteed run-length from any data word with arbitrary disparity and infinite run-length. This leads to transmission overhead. This means that more bits (in the form of symbols) must be transmitted than would occur in the net data word to be transmitted. This means that the required transmission speed (bandwidth) must be greater than the data rate of the data being transmitted. This means that the system requires a higher error rate or more load, power, etc., than would be required to transmit the raw data.

[0014] Conventional technologies either have high overhead (8B10B) or very poor quality in terms of disparity and run-length encoding, often requiring additional measures (complexity) such as scramblers to improve the quality in terms of disparity or run-length encoding. [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] U.S. Patent Application Publication No. 2003 / 0237041 [Patent Document 2] U.S. Patent No. 7103830 [Patent Document 3] U.S. Patent No. 5025256 [Patent Document 4] U.S. Patent No. 4486739 [Patent Document 5] European Patent Application Publication No. 3323219 [Overview of the project] [Problems that the invention aims to solve]

[0016] Accordingly, the object of the present invention is to provide a method for generating bit sequences that can be transmitted particularly efficiently and securely. In this context, efficiency can refer to hardware efficiency, efficient decoding at the receiver, the absence of redundant data transmission due to uninterpretable signals, and / or the ratio of user data to overhang data. Furthermore, according to the present invention, it should be possible to create or use particularly efficient hardware that enables runtime optimization by parallel processing. Furthermore, the object of the present invention is to provide a correspondingly equipped system device, and a computer program product and computer-readable storage medium comprising control instructions for executing the method or operating the system device. [Means for solving the problem]

[0017] This problem is solved by the features of claim 1. Further advantageous embodiments are described in the dependent claims. Accordingly, a method has been proposed for generating an efficiently transmittable bit sequence in an automobile, having limited disparity, limited run length, and line-coded forward error correction, the method comprising the steps of: providing an arbitrary bit sequence; segmenting the provided bit sequence into predetermined sequence segments according to individual predetermined bit lengths; calculating forward error correction for each segment or multiple segments of the same bit length; and encoding each segment or multiple segments of the same bit position into one or more subsymbols, together with the corresponding forward error correction, using the same coding unit from a plurality of coding units for segments of the same bit position and associated forward error correction, wherein a first subset of the plurality of coding units compensates for the disparity of a second subset of the plurality of coding units by actively controlling the coding of the disparity of the subsymbols by inverting the disparity of the generated subsymbols, and the juxtaposition of the subsymbols generates an efficiently transmittable bit sequence together with the calculated forward error correction.

[0018] In the preparation process step, it is possible to prepare a potentially infinite bit stream containing an arbitrary bit sequence. Depending on the application scenario, the data stream is already of any length and can be split into words or any bit sequence. Thereby, an output data stream having a potentially arbitrary length bit sequence is provided. However, this arbitrary length can be defined in the preparation process step and preferably can be defined as 112 bits. Once the length or bit length of an arbitrary bit sequence is defined, its length is fixed according to one aspect of the present invention. In this regard, the arbitrary length of the bit sequence in the meaning of the present invention should not be understood as arbitrary. Rather, a synonym for an arbitrary bit sequence according to the present invention is a bit sequence whose length can be freely selected in advance and / or whose content can correspond to at least a part of the data to be transmitted or the data to be sent.

[0019] Therefore, in the preparation process step, it is possible to provide an output data stream containing an arbitrary bit sequence. This arbitrary bit sequence is then read from the output data stream and provided to the first method step.

[0020] Normally, since the output data stream or output bit sequence can have a very large number of bits, the process is repeatedly executed such that several arbitrary bit sequences are generated from the output bit sequence, segmented, converted into sub-symbols, optimized with respect to disparity, and then transmitted. This means that the output bit sequence can be of any length and may ultimately be transmitted as a plurality of complete symbols.

[0021] There are multiple symbolization units, and each symbolization unit is assigned to a segment corresponding to a part of an arbitrary or freely selectable bit sequence in advance. Then, the symbolization unit converts the segment into partial symbols, and the set of concatenated partial symbols corresponds to the symbols or the entire symbols of the bit sequence to be efficiently transmitted. Therefore, according to one aspect of the present invention, the symbolization unit is arranged in the logical path of the processing chain or structural arrangement between the segment and the partial symbol.

[0022] The proposed method is particularly efficient because the bit sequence that can be transmitted has a particularly high proportion of useful data compared with the prior art. For example, it is possible to transmit 128 bits having 112 bits of user data. Therefore, the proposed method is already superior to the prior art in this aspect. In addition, the creation of the bit sequence that can be transmitted can be performed in parallel, and since a symbolization unit with a particularly simple design can be used for this purpose, it is particularly efficient. In this context, simple means, for example, that there are very few circuits that need to be installed in the symbolization unit. The symbolization unit does not need to have large-scale logic and can also be optimized according to a specific number of bits. Therefore, according to the present invention, it is possible to fix the input and output of individual symbolization units with respect to the number of bits.

[0023] The optimized disparity of the bit sequence to be transmitted makes it possible to avoid errors when interpreting on a serial channel. Therefore, efficiency also refers to the fact that the bit sequence is particularly error-resistant and only needs to be transmitted once with high reliability. Redundant transmission is avoided by high detection ability and also by optimized disparity.

[0024] In serial data transmission, it is advantageous to maintain as equal a number of 1s and 0s as possible in the serial data stream. This is commonly referred to as disparity. To ensure reliable clock recovery at the receiver, run-length limitations can be imposed on the generated channel sequence. This limits the maximum number of consecutive 1s and 0s. Thus, the proposed method can also be described as a method for efficient coding of bit sequences. According to the present invention, disparity is optimized by cleverly setting partial disparity. This can be used particularly advantageously when the run-length of the bit sequence is limited. Limited disparity and limited run-length may also apply to any bit sequence provided. This means that it does not need to be an efficiently transmittable bit sequence. Overall, any bit sequence provided is efficiently transmittable, and a bit sequence to be transmitted is generated or created from the bit sequence, and this bit sequence can then be efficiently transmitted.

[0025] In the preparation process step, an arbitrary bit sequence for encoding user data is provided. Problems may arise if this arbitrary bit sequence contains, for example, undesirable disparity. For instance, too many zeros can cause transmission problems. Such situations should be avoided, and therefore, the arbitrary bit sequence is optimized in subsequent process steps so that it can be transmitted efficiently. Thus, the provided arbitrary bit sequence represents arbitrary user data to be transmitted from the transmitter to the receiver via a serial data channel. The arbitrary bit sequence could, for example, be control data within a vehicle.

[0026] According to the present invention, a given bit sequence is segmented into predetermined sequence segments according to a predetermined bit length. This means that the input data stream, i.e., any bit sequence, is divided according to a predetermined procedure so that individual data segments are created. Thus, the segments cumulatively constitute any bit sequence. The predetermined bit length has the advantage that the encoding unit can be optimized in the same way as considering individual bit lengths. This makes it possible to construct highly specialized, and especially efficient, circuits. Defined bit lengths are described below, but these are merely examples.

[0027] Each segment is encoded into a subsymbol using one encoding unit per segment from multiple encoding units. The encoding itself takes place in a single encoding unit, which receives a segment at the input and converts it into a subsymbol. A subsymbol is also a bit sequence. Thus, as a whole, any bit sequence is divided into segments, each of which is converted into a subsymbol by an encoding unit, and the sum of the subsymbols results in the encoding of any bit sequence to be transmitted. Overall, it is advantageous that the number of segments corresponds to the number of encoding units, and therefore to the number of subsymbols. Thus, it is possible for each segment to have exactly one encoding unit, and that encoding unit generates exactly one subsymbol from the segment. The number of encoding units represents all encoding units to be used, corresponding to the number of segments. The number of segments is predefined because a given bit length is specified. Therefore, this method as a whole is deterministic.

[0028] To achieve an overall favorable disparity, there exists a coding unit of a first subset that compensates for the disparity of a second subset's coding unit by actively controlling the code of the disparity of the subsymbols by inverting the disparity of the generated subsymbols. This means that there exists a coding unit of a subset that controls the code of the disparity and a coding unit of a subset that does not. The coding unit of the first subset controls this code, while the coding unit of the second subset does not. Thus, the coding unit of the first subset is described as active, and the coding unit of the second subset is described as passive. Due to different subsets or types of coding units, it is possible to connect coding units in series such that the coding unit of the first subset favorably forms the overall disparity of the subsymbols, including subsymbols from the coding unit of the second subset.

[0029] Accordingly, according to the present invention, any coding unit is used with respect to the disparity of a subsymbol. Subsequently, coding units of the first subset are connected in parallel, thereby controlling the coding of the preceding coding unit and its own coding unit or its subsymbols in accordance with the disparity of the coding units of the second subset. Thus, a certain number of coding units of the second subset are used, and then another certain number of coding units of the first subset are used. In this way, the type or subset of coding units changes so that the next coding unit connected in parallel adjusts the disparity of the preceding subsymbol and / or its own subsymbol. In this way, it is avoided that uncontrollable coding units are connected in parallel with each other in a way that results in undesirable disparity. Thus, each coding unit of the first subset corrects the coding of the coding unit or its subsymbol that was connected in parallel immediately before it. This parallel connection of coding units will be described in more detail below with reference to Figure 4.

[0030] Therefore, in summary, it can be concluded that the coding units of the first subset optimize the coding units of the second subset with respect to disparity. Optimizing disparity means that the disparity is zero. For example, how disparity is calculated or set by changing the codes is well known to those skilled in the art.

[0031] Therefore, according to the proposed method, subsymbols are created in which the sequence is optimized with respect to disparity. Since each segment is converted into a subsymbol, the (whole) symbol to be transmitted can be generated by concatenating the subsymbols together. This symbol can be transmitted in a particularly efficient or fault-tolerant manner because its disparity or partial disparity is optimized. As a result, a bit sequence that is particularly advantageous for transmission is obtained.

[0032] According to one aspect of the present invention, any bit sequence is not limited in terms of its disparity and run-length. This has the advantage that any amount of user data can be transmitted, or converted into a bit sequence that is limited with respect to disparity and run-length. Thus, any bit sequence is encoded into a bit sequence to be transmitted that is optimized in terms of its disparity and run-length.

[0033] According to a further aspect of the present invention, the disparity of the second subset of coding units is not controllable. This has the advantage that any subsymbol can be generated using the second subset of coding units, thereby allowing the use of particularly simple coding units. These coding units can be designed particularly simply because the subsymbols generated by the coding units are not subject to any restrictions with respect to disparity or run-length encoding.

[0034] According to a further aspect of the present invention, active control of the code is performed by conditional inversion of subsymbols. This has the advantage that the corresponding subsymbols of a first subset of coding units can be controlled in a simple manner. Only the disparity of the subsymbol or inversion of individual bits is required. The code relates to the disparity of the subsymbol, which may be positive or negative.

[0035] According to a further aspect of the present invention, conditional inversion is performed according to the disparity of the entire symbol formed from all subsymbols. This has the advantage that not only are the subsymbols optimized, but the whole, i.e., the combined subsymbols, i.e., the entire symbol, is optimized with respect to disparity. This results in a particularly advantageous overall symbol.

[0036] According to a further aspect of the present invention, the dependencies are influenced such that the magnitude of the disparity is minimized. This has the advantage that the lowest possible disparity, preferably 0, is achieved. Thus, the disparities are linked to each other so that the amount of their disparity becomes as close to 0 as possible, or as small as possible.

[0037] According to a further aspect of the present invention, the total value is minimized such that, when the disparity of the total symbol is positive, it is canceled out by the negative parity of the sub-symbols. This has the advantage that the positive disparity of the total symbol is minimized or eliminated.

[0038] According to a further aspect of the present invention, the magnitude value is minimized such that the negative disparity of the whole symbol is canceled out by the positive parity of the sub-symbols. This has the advantage that the disparity of the whole symbol is minimized or eliminated overall.

[0039] According to a further aspect of the present invention, active control is performed such that the disparity of all whole symbols is minimized in accordance with the whole symbols that have already been transmitted. This has the advantage that multiple whole symbols are minimized or have their disparity removed, and therefore multiple sequences of whole symbols are also optimized with respect to their transmittability.

[0040] According to a further aspect of the present invention, the encoding unit of the first subset encodes an 11-bit segment into a 13-bit subsymbol. This has the advantage that the 11 bits are encoded particularly efficiently, requiring only an additional 2 bits for this purpose. This is particularly advantageous when a 128-bit overall symbol is to be created. In general, the specific values ​​of the proposed technical teachings referred to herein are empirically determined and their validity is supported by the fact that only an additional load of 128-112 bits, i.e., 14%, is required. Thus, the values ​​enumerated herein have been demonstrated to be advantageous in the case of 112-bit transmission.

[0041] According to a further aspect of the present invention, the first subset of encoding units has a disparity of +3 to +9, which is inverted to -3 to -9 in particular. This has the advantage that, for example, a +3 disparity is offset by a -3 disparity, and the same applies when adjusting a +9 disparity with a -9 disparity. This is particularly advantageous when encoding any 112-bit bit sequence as 128 bits.

[0042] According to another aspect of the present invention, the run-length of the subsymbol is up to 7. This is advantageous in that up to 7 identical 0s or 1s are generated, which is particularly advantageous in the proposed 112-bit or 128-bit scenarios.

[0043] According to a further aspect of the present invention, the run-length of the subsymbols of the first subset of coding units is at most 5, starting from the most significant and / or least significant bit. This has the advantage that at most 5 identical bits may be present at the end or beginning of the subsymbol. This has also been demonstrated to be particularly advantageous in the proposed scenario.

[0044] According to a further aspect of the present invention, in the second subset encoding unit, an 11-bit segment is encoded into a 12-bit subsymbol, or a 7-bit segment is encoded into an 8-bit subsymbol, or a 6-bit segment is encoded into an 8-bit subsymbol. This has the advantage that in a scenario of transmitting 112 bits in a 128-bit symbol, this encoding produces a particularly favorable value with a minimized overhead of only 14%.

[0045] According to a further aspect of the present invention, the second subset of encoding units generates disparities of -2 to +2. This again has the advantage of generating particularly favorable disparities.

[0046] According to a further aspect of the present invention, in the second subset encoding unit, the run-length of the generated subsymbols is 6. This has the advantage of generating particularly optimized subsymbols.

[0047] According to a further aspect of the present invention, the coding units of a second subset generate subsymbols having a run-length of up to 3 at the edges. This has the advantage that the subsymbols created by the second subset of coding units have a run-length of up to 3 at the beginning or end, which is a particularly favorable value.

[0048] According to a further aspect of the present invention, the coding units are addressed in parallel, and in each case, one segment is coded into one subsymbol. This has the advantage that one segment is converted into exactly one subsymbol having exactly one coding unit. Thus, since multiple segments are formed from any bit sequence and they are converted into subsymbols in parallel, multiple coding units can be addressed in parallel.

[0049] According to a further aspect of the present invention, the coding units are addressed in the order 21212221212, where "1" represents a first subset of coding units and "2" represents a second subset of coding units. This has the advantage that several coding units that are not actively controlled are always followed by a single coding unit that can be actively controlled. In this regard, it has been empirically confirmed that a particularly advantageous whole symbol can be obtained from the proposed coding units.

[0050] According to a further aspect of the present invention, when positive and negative data streams are applied, the multiplexer selects a data stream that contributes to minimizing the overall disparity of the entire symbol set. This has the advantage that it is possible to select a suitable data stream having a sign that minimizes or eliminates disparity. For example, if the disparity to be optimized is negative, a data stream with positive disparity is selected, and then the disparity of this data stream is minimized or compensated.

[0051] According to the present invention, forward error correction is improved in that it is calculated with respect to user data, and the user data is first segmented for this purpose. Then, a separate forward error correction is calculated for each segment, so that forward error correction is performed with respect to different subwords rather than the entire data word. This keeps the number of gates of the FEC coder to be used low and avoids exponential growth. Furthermore, according to the present invention, since line coding is performed via user data along with forward error correction, an improvement is obtained in that it overcomes the drawback of the prior art in which forward error correction is transmitted in an uncoded form. In addition, it is advantageous in that error correction can function more efficiently because it refers to only partial words, and therefore the location where the error occurred can be recognized at a finer granularity. Conventional error correction is inefficient because it always refers to the entire data word, or errors may occur that cannot be corrected in the prior art. This is avoided by segmentation according to the present invention.

[0052] A further improvement is that all transmitted data is line-coded, so that the entire data benefits from line coding. Thus, the transmission link can be deterministically controlled, and bit errors are minimized. In addition, implicit interleaving occurs because smaller packets are transmitted and not all data words are transmitted. This is achieved by using multiple forward error-correcting encoders, where each forward error-correcting encoder references only partial words. Thus, according to the present invention, the drawbacks of the prior art, namely the need to create explicit interleaving at great expense and the need for additional buffer memory, are overcome.

[0053] Optimized disparity (line coding) of the bit sequence to be transmitted makes it possible to avoid errors when interpreting it on a serial channel. Therefore, efficiency also refers to the fact that the bit sequence is particularly fault-tolerant and only needs to be transmitted once with high reliability. Redundant transmission is avoided by high detection capability and optimized disparity.

[0054] In serial data transmission, it is advantageous to maintain as equal a number of 1s and 0s as possible in the serial data stream. This is commonly referred to as disparity. To ensure reliable clock recovery at the receiver, run-length limitations can be imposed on the generated channel sequence. This limits the maximum number of consecutive 1s and 0s. Thus, the proposed method can also be described as a method for efficient coding of bit sequences. According to the present invention, disparity is optimized by cleverly setting partial disparity. This can be used particularly advantageously when the run-length of the bit sequence is limited. Limited disparity and limited run-length may also apply to any bit sequence provided. This means that it does not need to be an efficiently transmittable bit sequence. Overall, any bit sequence provided is efficiently transmittable, and a bit sequence to be transmitted is generated or created from the bit sequence, and this bit sequence can then be efficiently transmitted.

[0055] The proposed method is particularly usable in vehicles or specifically adapted to the requirements of vehicles. This is because safety-critical functions that must be adequately protected are provided in vehicles. According to the present invention, this can be done in several ways. On the one hand, it can be done through forward error correction and on the other hand through line coding. In addition, the reduction in the number of gates required is particularly advantageous in electromobility.

[0056] According to the present invention, user data to be transmitted is provided in a preparation process step. This is typically a fixed-length bit sequence. This may also be called a data word.

[0057] The provided user data is then divided into multiple bit sequences of the same length. In a preferred embodiment, these bit sequences may have a length of 112 bits. While the user data can be a continuous data stream, the bit sequences are always of a constant length and provide a subdivision of the user data in a sense. Hereafter, bit sequences will also be referred to as data words. Furthermore, hereafter, particularly in the drawings, it will be assumed that bit sequences are, figuratively speaking, arranged one below the other. This means that each individual bit sequence extends horizontally, and each individual bit sequence is arranged vertically, one above the other.

[0058] Because bit sequences are segmented, a subdivision rule is read out that divides the bit sequence into a sequence of segments of a predetermined length at a given location. The subdivision rule can take the form of a data format that defines the length of each segment. Individual segments do not need to be of the same length; they may differ in length. However, the subdivision rule stipulates that each bit sequence has the same format, thus, figuratively speaking, resulting in identical subdivision vertically. For example, the first segment of each bit sequence may have 11 bits. For example, the first four segments may each have 11 bits, followed by a 7-bit segment. Then, another 11-bit segment may follow, followed by a 6-bit segment. This data format is adhered to for all bit sequences. This means that segments at the same location can always be of the same length, but figuratively speaking, segments can differ vertically. Each line of segments forms a bit sequence. The bit sequence as a whole, in its vertical arrangement, forms user data.

[0059] This means that the read subdivision rule is applied to all bit sequences of multiple bit sequences, so that the entire user data is broken down into bit sequences horizontally and segments are formed vertically. This means that all bit sequences are subdivided according to the same subdivision rule. The subdivision rule can be read from data memory and applied to all bit sequences obtained from user data.

[0060] Here, partial forward error correction is iteratively created for all segments at the same bit position, across the entire bit sequence. Figuratively speaking, the forward error correction is calculated for all segments for all vertical segments at the same bit position or in the same sequence. Since this is performed for all segments, partial forward error correction is created for all bit sequences, and therefore for the complete user data. Thus, the sum of all partial forward error corrections creates a total forward error correction that refers to the complete user data or the entire bit sequence.

[0061] Generally, user data may be divided into only one bit sequence, or it may already be available as a single bit sequence of its length. In that case, partial forward error correction is generated for each segment.

[0062] Here, the segment encoder is repeatedly applied across all segments at the same bit position, generating segment line codes across all segments for each bit position and bit sequence. In other words, line coding is performed, figuratively speaking, across all vertical segments. This is advantageous because the line encoder is specifically provided for a given length. This ensures that each vertical segment can be coded by a single line encoder. Thus, the repeated application of the segment encoder, figuratively speaking, ensures that segments are line coded column by column, and this is done across all segments until all bit sequences are line coded with respect to those segments.

[0063] A particular advantage is that the number of partial forward error corrections is the same as the number of segments. This means that the partial forward error corrections can be encoded using the same line encoder as the corresponding segments.

[0064] In either case, for each partial forward error correction, the segment encoder used for the segment in which the partial forward error correction was created is applied to generate one partial forward error correction line code for each partial forward error correction. This means that a segment encoder is used that line-codes the individual segment and then line-codes the corresponding partial forward error correction. This means that the segments are line-coded column by column using the same segment encoder as the partial forward error correction associated with the individual column.

[0065] Subsequently, all segment line codes and all partial forward error correction line codes are transmitted. According to one aspect of the present invention, the subdivision rules are stored in data memory and exist as coding rules and / or are read from the hardware architecture. This has the advantage that the subdivision rules can be statically predefined or modified within data memory. Furthermore, the subdivision rules can take into account the corresponding hardware architecture. For example, if different encoders are prepared for different bit lengths, the bit sequence is subdivided so that the corresponding segments correspond to the individual encoders. Thus, the segments have exactly the lengths provided by the individual encoders.

[0066] According to a further aspect of the present invention, all bit sequences have the same structure in their data format, the same segment length and / or the same bit position. This has the advantage that individual segments can be fed to separate encoders. For example, each first segment of each bit sequence is fed to the same encoder. Thus, figuratively speaking, segments are encoded column by column, and there is a dedicated encoder for each column.

[0067] According to a further aspect of the present invention, partial forward error correction includes correction information describing the target content of the segment on which the partial forward error correction is made. This has the advantage that transmitted data can be corrected by this correction data, thereby ensuring that individual partial forward error corrections are made for individual segments rather than the entire correction being made for each bit sequence. All partial forward error corrections, as a whole, describe all segments of all bit sequences, and therefore all user data. However, the difference from the prior art is that the forward error correction is not made for each bit sequence, but for all segments across all bit sequences. Therefore, it is possible to use the same line encoder for each partial forward error correction as the one used for the corresponding segment.

[0068] According to a further aspect of the present invention, the partial forward error correction has the same bit length as the segment in which the partial forward error correction is generated. This has the advantage of providing maximum efficiency in that a dedicated line encoder can be provided, and thus the corresponding column-direction line encoder is precisely dedicated to the bit length that needs to be encoded. Thus, an efficient method with minimal technical complexity is provided.

[0069] According to a further aspect of the present invention, the entire partial forward error correction describes all user data to be transmitted in a correctable manner. This has the advantage that all user data transmitted can be corrected for their errors, but because it is based on individual segments, the proposed method has a finer granularity than that offered by the prior art.

[0070] According to a further aspect of the present invention, each segment encoder generates at least a portion of a line code. This has the advantage that the outputs of the segment encoders can be combined to provide a line code to be transmitted.

[0071] According to a further aspect of the present invention, a set of segment encoders encodes a 112-bit bit sequence into a 128-bit word. This has the advantage of producing particularly efficient line codes.

[0072] According to a further aspect of the present invention, during transmission, a partial forward error correction line code is added to the segment line code. This has the advantage that all data to be transmitted is line-coded, and therefore the lines are processed deterministically, or the advantages of line coding can be applied not only to the payload data itself but to all data.

[0073] According to a further aspect of the present invention, the bit position is specified as an offset or bit index within a bit sequence. This has the advantage that different types of addressing schemes can be used and that the index can be advantageously specified using known methods, since it is based on a sequence of individual segments.

[0074] According to a further aspect of the present invention, user data is available as a serial data stream. This has the advantage that, theoretically, any amount of user data can be transmitted, and that the user data is divided into bit sequences of the same length.

[0075] According to a further aspect of the present invention, the method steps are performed in the order described and / or repeatedly. This has the advantage of reversing the order of the codes. According to the present invention, forward error correction is created first, followed by line coding. This does not preclude the need to perform individual process steps multiple times. This is the case, for example, when there are multiple bit sequences that must be segmented.

[0076] According to one aspect of the present invention, line code segments are generated for each data subword block and / or for forward error correction of each data subword block. This has the advantage that forward error correction, in particular, does not need to be transmitted in an uncoded form, but is instead line-coded. Thus, the advantages of line coding can be used not only for user data but also for forward error correction.

[0077] According to a further aspect of the present invention, forward error correction for a data block consists of multiple partial forward error corrections of data subword blocks. This has the advantage that instead of generating an overall forward error correction first, a number of individual partial forward error corrections are generated, which together form the overall forward error correction. In this way, the number of gates required for the FEC encoder is minimized. Nevertheless, all data is protected by forward error correction, and it is still possible to transmit the data in line-coded format along with the forward error-corrected FEC.

[0078] According to another aspect of the present invention, a data structure is read, and a forward error-correcting subencoder is selected according to the individual bit length of the data subword. This has the advantage that the FEC encoder is precisely fitted to the segment length or the bit length of the subword. In this way, the number of gates can be minimized, and the encoder only needs to encode small subwords, rather than the entire data word. As a result, each FEC encoder is precisely fitted to the bit length of the data subword to be encoded.

[0079] According to a further aspect of the present invention, the number of gates in the FEC partial encoder is selected according to the bit length of the data subword. This has the advantage of reducing the number of gates required in the FEC coder compared to the prior art, and as a result, providing an efficient system or method, which is particularly advantageous in automobiles or vehicles. In this way, there is no need to prepare unnecessary gates. This makes the number of gates deterministic and minimized.

[0080] According to a further aspect of the present invention, the number of gates for all encoders is selected such that, in iterative execution of the method, the number of gates increases linearly with increasing data word length. This has the advantage that the data format can be selected such that a minimum number of gates is provided considering the data format, or only a linear increase in the number of gates is required. For example, in one embodiment, the maximum bit length can be 10, 11, or 12 bits, which means that the required gates or circuitry of the FEC encoder increase only linearly. Since an exponential increase in gates is required for larger values, the present invention produces the technical effect of minimizing power consumption or energy consumption and leading to less heat dissipation. Furthermore, the proposed method is particularly robust, which is particularly advantageous in automobiles where safety-critical functions are provided.

[0081] According to a further aspect of the present invention, each data word has 112 bits. This has the advantage that a 128-bit word can be generated using line coding, which corresponds to a common format. According to the present invention, it has been demonstrated that 112 bits can be robustly encoded to 128 bits. This takes into account that transmission may be affected by data channels that are lossy or error-prone.

[0082] According to a further aspect of the present invention, the bit length of the forward error correction of the data subword block is selected to correspond to the bit length of the data subword. This has the advantage that both the forward error correction and the data subword or segment can be encoded using the same encoder, which is a line encoder rather than an FEC encoder. Thus, the present invention makes a technical contribution by not only preparing a minimum number of gates but also minimizing the total number of encoders. Consequently, the forward error correction can be line-coded with the same encoder as the actual segment of the user data.

[0083] According to a further aspect of the present invention, the forward error correction of a data subword block and the data subword block on which the forward error correction is calculated are line-coded using the same line encoder. This has the advantage that only a minimum number of line codings need to be prepared. Figuratively speaking, substantially every column, i.e., every subword block, is line-coded using the same segment encoder, along with its corresponding partial forward error correction.

[0084] According to a further aspect of the present invention, the data structure is selected according to the bit length of the data word. This has the advantage that it can dynamically accommodate different bit lengths at runtime and therefore the same data format as the initially provided data word can also be selected for subsequent data words. If the initial data word is available, the corresponding data structure can be used for subsequent serial data streams, and the subsequent data words are structured to correspond to the data structure of the initially received data word.

[0085] According to a further aspect of the present invention, serial line coding is performed after the forward error correction of the data subword block has been calculated. This has the advantage of reversing the order as provided in the prior art, with the forward error correction being calculated first, which means that the forward error correction also does not need to be line coded and transmitted unencrypted or unencoded.

[0086] According to a further aspect of the present invention, the method steps are performed in a virtualized manner, and information regarding the underlying encoders and / or gates is generated. This has the advantage that the implementation status can be evaluated in the preparation process steps, and in this regard, it is possible to determine how many gates or how many FEC encoders and / or line encoders need to be prepared. Furthermore, the entire process can be simulated. Hardware components can be provided virtually.

[0087] One aspect of the present invention involves bundling multiple data streams (video, audio, and data) into a single transport frame and transmitting them serially. Different data formats have different bandwidth requirements, as well as different requirements regarding latency, reconstruction sublayers, and bit error rates. In particular, the transmission of today's video data formats requires not only the transmission of pure video data and its frame information, but also support for encryption schemes such as HDCP. All of this necessitates many different data channels with a wide range of requirements regarding bandwidth, latency, reconstruction sublayers, etc. In addition to this, a network architecture far more complex than that provided by a simple transmitter / receiver architecture is desired. An architecture having multiple repeaters to which data paths can start and end, and branches (Y-branchs) that can also reintegrate data paths into links, is advantageous.

[0088] According to one aspect of the present invention, the technology follows the fundamental idea of ​​bundling services in a completely consistent manner, but offers entirely new possibilities with respect to network architecture and enables new methods in the implementation of today's video interfaces. In addition, it can be used as a general-purpose data transport layer for, for example, Ethernet® or camera data or any type of sensor data transmission.

[0089] In a virtual path, all packets / cells travel along the same path, in contrast to IP, where a single packet can reach its destination via different routes than previous and subsequent packets. Therefore, latency and reconstruction sublayers on a virtual path are constant.

[0090] Virtual paths also have the advantage of being usable as a derivative form of multiplexing for different services (video, audio, Ethernet®) because different virtual paths can be configured to have different characteristics without interfering with each other.

[0091] Virtual paths consume bandwidth only when data is actually being transmitted. The concept of virtual paths makes it possible to implement complex and extensive diagnostic and network configuration functions at runtime using dedicated (virtual) data channels.

[0092] According to one aspect of the present invention, the virtual path layer is implemented between the physical layer (serializer and framer) and various application data interfaces. According to one aspect of the present invention, this virtual path layer is used to multiplex different data paths and support more complex architectures having repeaters and branches. This is primarily done in the cell layer.

[0093] According to one aspect of the present invention, another part of the virtual path layer is an application adaptation layer that performs the conversion of video (stream) or, for example, Ethernet® (packet) data into cells. This application adaptation layer also includes OAM functions for network diagnostics and management.

[0094] According to one aspect of the present invention, this technology can serve as a basis for transmitting various data formats via serial links within a vehicle (and other locations). Thus, this forms the basis for a new generation of devices.

[0095] High serial bandwidth necessitates defining architectures, cell formats, and interfaces that allow for flexible internal data bus widths to match the speed of the internal time system to the capabilities of the chip technology.

[0096] According to one aspect of the present invention, the virtual path layer is a physical layer, the physical layer comprises a transmission sublayer, a physical medium sublayer, a cell layer, and an application adaptation layer, the application adaptation layer includes a segmentation sublayer and a reconstruction sublayer, and a function for adapting the data format to the corresponding application.

[0097] Its primary role is to establish a physical connection with other physical layers. This connection is essentially bidirectional. Theoretically, this connection can be realized through a wide variety of media. In practice, two serial differential GBps connections are used. In this layer, line coding, insertion of empty cells to separate the cell rate from the connection rate, and integration of the cell stream into a serial frame are performed.

[0098] In the cell layer, segmented data (cell payload data) from the higher-level segmentation and reconstruction sublayers is constructed into complete cells with headers, VP identifiers, and CRCs, or the cells are CRC-checked and the payload is passed to the segmentation and reconstruction sublayers. Here, multiplexing of cell streams with different application adaptation functions or distribution of cell payloads to application adaptation functions according to VP identifiers also occurs (feed-in / feed-out).

[0099] According to one aspect of the present invention, the cell layer also performs multiplexing and demultiplexing (transferring) of the cell stream in the repeater and splitter. According to one feature of the present invention, the role of the application adaptation function is to adapt the data of the application interface to the format of the user data field of the cell, and to transmit control information to the other side, or to transmit control information to the other side for adaptation (time generation, frame formation) to be used.

[0100] According to one aspect of the present invention, all virtual data paths are unidirectional, i.e., they start at an initiator and end at one or more destinations. If the virtual data paths are logically related to each other (e.g., HDCP to a video channel) and thus form a bidirectional data path, these paths should have the same VP identifier.

[0101] A virtual data path begins at an initiator and ends at one or more destinations. This is achieved by a cell sublayer, which performs the following functions on the virtual path: - Add / remove multiplexing -VP conversion.

[0102] Stream data (continuous data stream) The stream data function integrates time-domain crossing and bit-width conversion processes for data input from the application interface, adapting it to the N-bit width of a cell row. The cell row payload is pre-formatted so that the selfetter and cell header fit the first and last cell rows.

[0103] The streamed data is (usually) source-synchronous. Here, the data path's clock region crossing occurs from the application clock region to the virtual path layer clock region.

[0104] A data buffer is provided in the transmission direction, and source-synchronized data is written to this data buffer along with the source clock. The segmentation layer retrieves data from this buffer as needed to perform data format conversion to N-bit wide rows of cells. Frame data (e.g., Hsync, Vsync, DE) is encoded into payload information bits, which allows the receiver to reconstruct the frame.

[0105] In the receiving direction, cell data is written to the data buffer by a reconstruction sublayer, where the cell row is bit-width (depending on the bit width of the cell row). Frame information is reconstructed based on payload information bits. The source clock is regenerated, for example, using buffer occupancy and clock synthesis.

[0106] If data encryption is required (HDCP), this function encrypts or decrypts the cell data. Because different types of streaming data exist, such as audio and video, regardless of whether or not encryption is used, this basic functionality can have different implementations (e.g., VStream In / Out, AStream In / Out, EncVStream In / Out).

[0107] The interface to the segmentation and reconstruction sublayers is the same for all functions. Burst data (discontinuous data stream) The burst data function integrates clock domain crossing and data bit width conversion processes for data input from the application interface to adapt it to the N-bit width of the cell row. The cell row payload is pre-formatted so that the selfetter and header fit the first and last cell rows.

[0108] Burst data is (usually) synchronized with external time and has different identification signals regarding direction and data type (address / data / ByteEnable). This data typically involves control lines to implement a specific protocol.

[0109] A data buffer is provided in the transmission direction, and burst data is written to the data buffer along with the interface clock. The segmentation layer retrieves data from this buffer as needed to perform data format conversion to N-bit wide rows of cells.

[0110] In the receiving direction, cell data is written to the data buffer by the reconstruction sublayer, where the cell row is the bit width. Interface control signals are reconstructed based on the payload information bits.

[0111] Payload information bits are used to generate control signals for application-specific interfaces or to synchronize protocol state machines within application-specific interfaces.

[0112] Due to the different interfaces that provide burst-type data (SPI, I2C, MII), this basic functionality can have different implementation forms (e.g., SPIBurst, I2CBurst, MIIBurst).

[0113] Therefore, although there may be stream input / output interfaces with (slightly) different structures, their structures should be the same. This problem is solved by a system device in an automobile for generating efficiently transmittable bit sequences with limited disparity and limited run-length, the system device comprising: an interface unit configured to provide an arbitrary bit sequence; a segmentation unit configured to segment the provided bit sequence into predetermined sequence segments according to individual predetermined bit lengths; a computation unit configured to compute forward error correction for each or more segments of the same bit length; and an encoding device configured to encode each segment or multiple segments of the same bit position into one or more subsymbols, each with the corresponding forward error correction, using the same encoding unit from a plurality of encoding units for segments of the same bit position and associated forward error correction, wherein a first subset of the plurality of encoding units compensates for the disparity of a second subset of the plurality of encoding units by actively controlling the encoding of the disparity of the subsymbols by inverting the disparity of the generated subsymbols, and the juxtaposition of the subsymbols generates an efficiently transmittable bit sequence with the computed forward error correction.

[0114] The problems of the present invention can also be solved by carrying out the proposed method or by a computer program product having control instructions for operating the proposed device. A particular advantage of the present invention is that the proposed apparatus and units can be operated using this method. Furthermore, the proposed apparatus and units are suitable for carrying out the method according to the present invention. Accordingly, in each case, the apparatus implements structural features suitable for carrying out the corresponding method. However, the structural features may also be designed as process steps. The proposed method comprises steps for carrying out the function of the structural features. In addition, physical components may be provided or virtualized virtually.

[0115] Further advantages, features, and details of the present invention are provided in the following description, in which aspects of the invention are described in detail with reference to the drawings. The features described in the claims and specification may be essential to the invention individually or in any combination. Similarly, the features described above and those further described herein may be used individually or in any combination. Functionally similar or identical parts or components may be given the same reference numerals. The terms “left,” “right,” “top,” and “bottom” used in the description of embodiments are based on the designation of the drawings in a normally legible orientation or the drawing in an orientation having normally legible reference numerals. The illustrated and described embodiments should not be understood as definitive, but are essentially illustrative for the purpose of illustrating the invention. The detailed description is for the informational purposes of those skilled in the art, and therefore known circuits, structures, and methods are not shown or described in detail in this description so as not to make it more difficult to understand this description. [Brief explanation of the drawing]

[0116] [Figure 1] This figure shows several examples of process flows, including serial coding and calculation for forward error correction, using conventional technology. [Figure 2] This figure shows an optimized process flow using forward error correction and serial coding according to one aspect of the present invention. [Figure 3] This figure shows the encoding of user data and calculation of forward error correction using conventional technology. [Figure 4] This figure shows a method for improving forward error correction in serial coding for in-vehicle data transmission, according to the present invention. [Figure 5] This figure shows a comparison between conventional coding and a method for improving forward error correction according to one aspect of the present invention. [Figure 6] This figure shows the number of gates required per bit length for forward error correction. [Figure 7A] This figure shows the encoding of user data into line codes according to one aspect of the present invention. [Figure 7B] This figure shows a proposed system device for improving forward error correction in serial coding in in-vehicle data transmission, according to one aspect of the present invention. [Figure 8A] This figure shows one embodiment of a method for improving forward error correction on the transmitter side, according to one aspect of the present invention. [Figure 8B] This figure shows a method for improving forward error correction on the receiver side, according to one aspect of the present invention. [Figure 9] This is a flowchart of a method for improving forward error correction in serial coding for in-vehicle data transmission, according to one aspect of the present invention. [Figure 10] This figure shows the application of a basic frame format and so-called block code according to one aspect of the present invention. [Figure 11] This is a schematic diagram of the layout and structure of a so-called block code according to another aspect of the present invention. [Figure 12] This is a schematic diagram of a frame format for which applications can be found according to the present invention. [Figure 13] This figure shows an exemplary encoding of data segments to symbols in which disparity is optimized, according to one aspect of the present invention. [Figure 14] This figure shows an exemplary encoding of data segments to symbols in which disparity is optimized, according to one aspect of the present invention. [Figure 15] This figure shows an exemplary encoding of data segments to symbols in which disparity is optimized, according to one aspect of the present invention. [Figure 16] This figure shows an exemplary encoding of data segments to symbols in which disparity is optimized, according to one aspect of the present invention. [Modes for carrying out the invention]

[0117] This figure partially shows parameters that are well known to those skilled in the art in English and are used as parameters, and therefore do not need to be translated. Figure 1 shows three examples of how forward error correction is performed according to conventional methods. On the left, an example is shown in which serial coding of user data is performed first, and then a forward error correction code (FEC) is generated. The serially encoded data is transmitted, and then the forward error correction is encoded and appended to the encoded user data. Thus, according to this example from the prior art, the forward error correction is generated over the entire data word, which must then be encoded again and appended. Therefore, the forward error correction is encoded over the entire bit sequence, rather than over individual segments.

[0118] The center shows another example of prior art, where the line coding step for forward error correction is omitted and unencoded parity information is added. The drawback here is that the final data portion, i.e., the parity information, is not line-coded, making it highly prone to errors.

[0119] The example on the right, in contrast to the central example, shows an example where parity information is not looped back into serial coding. This has the same drawback as the central example. Data transmission solutions constantly impose increasingly stringent requirements for error-free operation / error tolerance, which necessitates fine-tuning between serial coding and forward error correction (FEC) as data rates continue to increase.

[0120] Current conventional technologies (Ethernet® / DisplayPort) process data streams in the following order: 1. Input data is encoded in the first step using serial coding (8b10b, 64b66b, 128b132b, etc.). For larger codings than 64b66b, this is achieved primarily by scrambling using LFSR.

[0121] 2. The serialized stream is then further protected against bit errors by FEC (Forward Error Correction) coding. A complete FEC coding (FEC coding word) includes both the symbol-based input data and the so-called parity symbol. In these applications, the input data passes through FEC as is. This means that the input data always corresponds to the original serial code. Herein lies another procedure:

[0122] a. The parity symbol is then coded serially (e.g., 8b10b) to meet the requirements for serial transmission (run-length encoding, DC balance, etc.). This additional subsequent coding of the parity symbol requires an additional encoder in hardware.

[0123] b. Another solution involves using feedback of the parity symbol to step 1) instead of the subsequent serial coding of the parity symbol described above. A serial encoder allows for control of DC balance based on the selection of a positive or negative symbol. However, this is associated with a corresponding dead time (depending on the serial coding and FEC encoder values). This can lead to large deviations in the amount of temporal DC balance, for example.

[0124] c. The parity symbol is sent directly to the serial link (e.g., DisplayPort 2.0) unprocessed. However, this is highly inaccurate because the parity symbol is generated dependent on the input data. Here, we rely on the fact that the parity symbol is DC balanced on average.

[0125] All of the methods described in (a) to (c) above have the drawback of requiring a large amount of resources (e.g., two serial encoders) or resulting in inaccurate serial coding (e.g., DC balancing, run-length encoding, spectral encoding). In particular, improper control of serial coding in combination with the transmission channel can lead to the data stream not being accurately reconstructed at the receiver (the CDR sampling inaccurately). While these effects are mitigated by using FfEC (to correct bit / symbol errors), this unnecessarily deprives FfEC coding of correction margin for signal integrity or additional necessary error correction for errors caused by external influences, etc., with each error caused by inadequate serial coding. Reed-Solomon FEC can only correct t symbol errors based on the size of the overhead in the symbol (2t, see Figure 3).

[0126] On the other hand, Figure 2 shows the method according to the present invention, in which forward error correction is generated across the user data and is also encoded together with the user data. The advantage of the present invention is that both the user data and the forward error correction are line-coded, and therefore the method is robust against errors. This figure also shows that a difference from the prior art is that the forward error correction is generated directly against the user data, rather than against the line-coded user data. This makes it possible to transmit all data in a line-coded form, resulting in improved robustness against errors.

[0127] The method proposed below to address the aforementioned challenges applies to all conceivable ECC / FEC coding and is not limited to Reed-Solomon coding. The proposed procedure changes the order of serial coding and FEC.

[0128] 1. In the first step, the input data is protected by FEC or multiple individual FEC units with a smaller symbol width (6-12 bits). This also incurs an overall overhead of 2t.

[0129] The use of multiple FEC subcodings is particularly preferred here because it has additional positive characteristics (described below). 2. Subsequently, individual current FEC output symbols (multiple) (which should not be confused with the entire FEC coded word n) are coded using block codes, while preserving all desired characteristics such as DC balance, run-length encoding, and frequency spectrum.

[0130] In the case of multiple FEC codings in step 1), exactly the same number of block coders are used here. This means that on the receiving end, even if a bit error on the link corrupts one complete data symbol of the serial code, it will result in only a single FEC symbol error.

[0131] Figure 3 shows a flowchart of a conventional technique where input data is line-coded, and then forward error correction is generated. This forward error correction is added to the right, as shown at the bottom. This means that the data word is line-coded first at the top, and then the unline-coded forward error correction is added. This presents a problem because the forward error correction does not have the desired characteristics necessary for robust data transmission. This results in the disadvantage that the data is not DC (digital current) balanced, i.e., a favorable parity is not set. Furthermore, in transmissions that are not line-coded, errors can occur during clock regeneration. In general, line coding is advantageous in that the average value of the analog signal can be measured, and then it can be checked which actual signals are above this average value and which actual signals are below this average value. Here, it is desirable that the number of analog signals above the average value, i.e., the number of digital "1s", is the same as the number of analog signals below the average value, i.e., the number of digital "0s". This means that optimized signal modeling can be performed. This is not possible in Figure 3 because the forward error correction code is not line-coded.

[0132] Figure 4 illustrates the procedure and transmission over a lossy channel according to the present invention. Here, each channel is potentially susceptible to loss, and it is particularly advantageous that forward error coding is performed first at the data input, followed by overall serial coding. On the receiver side, the procedure is performed in reverse, with serial decoding performed first, thereby restoring forward error correction in addition to the user data.

[0133] Figure 5 illustrates the prior art method in the upper example, where in the first method step, the output data word or bit sequence is line-coded from the first line to the second line. This results in a code longer than the output bit sequence, which is also called overhead. In the subsequent processing step, a forward error correction code is generated from the second line to the third line and added to the line coding. As can be seen, the first portion on the left side of the data to be transmitted is line-coded, while the second portion, i.e., the forward error correction, is not line-coded. This causes problems because the advantages of line coding cannot be utilized in the added portion on the right side. This is a disadvantage.

[0134] In the central example of Figure 5, the source word ABC is again shown in the upper row. Thus, the bit sequence consists of segments A, B, and C, which are 11-bit, 6-bit, and 7-bit in length, respectively. According to the present invention, instead of the entire data word, i.e., the entire bit sequence, being protected, and instead of a forward error correction code being provided, individual segments are protected. This is indicated by the fact that in the second line, the corresponding forward error correction codes are shown after each segment A, B, and C. In a subsequent process step, line coding is applied in the third line, i.e., the data from the second line is completely line coded, and a line code is generated in the third line. Here, it can be seen that this line code is transmittable, and the entire data is line coded, and the forward error correction code is also line coded. Thus, the advantages of line coding apply to all data to be transmitted.

[0135] In the lower part of Figure 5, an example of the embodiment illustrates the steps of the method according to the present invention, and further substeps are possible. Here, different bit sequences are shown, and the user data is divided into bit sequences of the same length. In this way, the entire user data is divided into four bit sequences, all of the same length. These four bit sequences are divided into segments of the same length. Figuratively speaking, the individual bit sequences are arranged horizontally, and these bit sequences are arranged vertically, with each line reflecting a bit sequence. Also, as can be seen from the figure, each bit sequence is divided into three segments of the same length. This gives the user data a matrix-like arrangement where each row is a bit sequence and each column is a segment.

[0136] Here, line coding as provided in prior art is not performed, and partial forward error correction is calculated for each column, i.e., for all segments at the same bit position, according to a subdivision rule specified in a higher processing step. Partial forward error correction is shown at the top, as seen in the first row of the second rectangle, and in this figure, the entire partial forward error correction is called the FEC overhead. Here, the segmented bit sequences become available according to the subdivision rule, and partial forward error correction becomes available for all segments at the same bit position across all bit sequences.

[0137] Subsequently, a segment encoder is applied to all segments at the same bit position to generate segment line codes for all segments, bit by bit and bit by bit sequence. Further in another process step, or in the same process step, the segment encoder used for the segments is applied to individual partial forward error corrections to obtain a single line code containing the segment line code and the partial forward error correction line code. As shown at the bottom of Figure 5, all data is line-coded, and in particular, the forward error correction FEC is also line-coded. This means that this data can be transmitted advantageously.

[0138] Figure 6 shows the number of gates required to create a forward error correction code on the y-axis, depending on the bit length to be encoded on the x-axis. As can be seen, this is an exponential increase, and from bit lengths of 10 to 12 bits, the number of gates, i.e., the number of gates required for forward error correction, increases above average. Therefore, according to the present invention, it is particularly advantageous to perform forward error correction segment by segment, as it is no longer necessary to consider the entire data word, i.e., the entire bit length. If the entire bit length must be considered in forward error correction, the bit length will typically exceed the critical 12 bits. The number of gates required in the forward error correction encoder will increase unfavorably. Therefore, this demonstrates the advantageous technical effect of the present invention, which involves first forming multiple segments across a bit sequence and then calculating forward error correction for each segment.

[0139] At this point, we refer again to the subdivision rules shown in Figure 5, which specify that a segment can have 11 bits, 6 bits, or 7 bits. By using multiple FEC encoders / decoders with smaller FEC symbol sizes, the number of gates required is reduced, and given process node F max The maximum operating frequency for this increases (due to shorter carry chains and improved parallelism).

[0140] Figure 6 shows the relationship between the FEC symbol size (in bits) and the required implementation. This refers to the hardware implementation of the Reed-Solomon FEC. The number of gates is normalized (to a 12-bit symbol size) and can therefore be directly compared. The graph can be seen to show an exponentially significant relationship between the symbol size (in bits) and the implementation per gate.

[0141] Note that the symbol widths of individual small FEC subencoders do not necessarily have to be the same. Larger serial encodings can consist of multiple different subencoders (the simplest example being 8b10b, which can be constructed from 3b4b and 5b6b), similar to the proposed use of FEC. In the case of this invention or ADXpress®, this is achieved by a total of 11 encoders, namely 6b8b, 7b8b, 11b12b, and 11b13b. The FEC symbol width used for individual subcodings is determined by the data word width of the individual serial encoder. For example, 6b8b uses an FEC with a symbol width of 6 bits.

[0142] The complete structure of the transmitter data path of the present invention or ADXpress is shown according to one aspect of Figure 8A. The data path in the receiver has a corresponding inverse structure (see also Figure 8B).

[0143] Figure 7A shows a line coding or line coding device having multiple line coding units, for example, that map 11 bits to 12 bits, 11 bits to 13 bits, or 11 bits to 12 bits. This corresponds to the right-to-left order in Figure 7 and shows that the input data word, which is the bit sequence described above, is divided into individual segments, and then each individual segment is line coded. Since the calculation of forward error correction is not yet considered in Figure 7A, the system device according to Figure 7A can function as the output system device of the present invention.

[0144] Figure 7A shows an arbitrary 112-bit bit sequence at the top, which is segmented into 11-bit, 6-bit, or 7-bit segments. The coding units are then addressed in parallel, and these coding units convert the bits into sub-symbols so that the bits are optimized with respect to disparity. For example, 11 bits are coded into 12 bits, or 11 bits are coded into 13 bits.

[0145] In Figure 7A, the coding unit format of the second subset is shown at the leftmost center, labeled 11B12B. This coding unit provides subsymbols with arbitrary codes, i.e., arbitrary disparity. To compensate for this disparity, coding unit 11B13B is connected downstream in parallel to the bit sequence. This means that a data stream is formed in which the most significant bits of 11 times twice as many are converted into two subsymbols; that is, an 11-bit data segment is converted by 11B12B into a 12-bit subsymbol with arbitrary codes, i.e., disparity, and the data segment is encoded from 11 bits to 13 bits by coding unit 11B13B. As shown below the coding units in the figure, the second coding unit from the left, 11B13B, is the coding unit of the first subset. The coding unit of the first subset has an inverter and a multiplexer. Thus, the first 13 bits are available as a data stream, which is branched so that it is inverted once with respect to the code, i.e., disparity, and remains unchanged once. As shown further below, a positive or negative value, i.e., the original data stream or the inverted data stream, is used under disparity feedback to compensate for the code from the leftmost coding unit. Thus, the first multiplexer on the left receives two data streams, each representing a subsymbol with the normal code as the output from the 11-bit 13-bit coding unit and a subsymbol with the inverted code or inverted disparity.

[0146] Therefore, based on feedback from the top unit, it is determined what kind of disparity will arise from the leftmost encoder 11B12B, and the lower left multiplexer compensates for or minimizes the disparity for the partial symbols of the leftmost encoder 11B12B. This is performed in parallel, with coding units from the first subset that minimize or eliminate disparity following coding units from the second subset. Finally, the total symbol is output from the lower right. This total symbol has 128 bits and consists of subsymbols that are inserted using diagonal arrows in the thick line below. Therefore, on this output line there are subsymbols that have been optimized or minimized with respect to disparity, and these subsymbols then form the total symbol that can be output and transmitted.

[0147] According to one aspect of the present invention, the present invention encodes a 112-bit wide data word having an arbitrary disparity (maximum disparity: 112) and an arbitrary run length (maximum run length: 112) into a 128-bit wide symbol. This means that the overhead caused by the encoding is 14.2%.

[0148] The maximum run-length encoding that occurs within a symbol is eight identical bits, just as with any sequencing of any symbol. The maximum disparity in the long-term average is 0, and the disparity in the symbol is less than 9.

[0149] The logic complexity is minimal, comparable to 10 8B / 10B encoders (though it has the known drawback of high overhead). This is achieved by using or using in parallel multiple "small" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0150] Encoders 11B12B, 7B8B, and 6B8B generate all symbols that guarantee a maximum run-length of 6, regardless of the order in which the (partial) symbols are ordered. According to one aspect of the present invention, the encoder (11B13B) generates a symbol with a guaranteed maximum run length of 7, or a symbol whose first or last run length is 5. Due to the ordering of (11B13B) with other encoders (Figure 2), a maximum run length of 8 can be generated within a symbol.

[0151] The characteristics of the encoder are shown below. 11B13B: 11 bits of data are mapped to 2048 symbols, each having 13 bits. These symbols can be transmitted in inverted or non-inverted form.

[0152] Disparity: +3...+9 or controllable -3...-9 Run length within word: 7 Run length at the edge: 5.

[0153] 11B13B: 11 bits of data are mapped to 2048 symbols, each having 13 bits. These symbols can be transmitted in inverted or non-inverted form. Disparity: +3...+9 or controllable -3...-9 Run length within word: 7 Run length at the edge: 5.

[0154] 11B12B: 11 bits of data are mapped to 2048 symbols, each having 12 bits. The symbols are transmitted only in their non-inverted form. Disparity: -2, -1, 0, 1, 2 Run length within word: 6 Run length at the edge: 3.

[0155] 7B8B: 7 bits of data are mapped to 128 symbols, each having 8 bits. The symbols are transmitted only in their non-inverted form. Disparity: -2, -1, 0, 1, 2 Run length within word: 6 Run length at the edge: 3.

[0156] 6B8B: 6 bits of data are mapped to 64 symbols, each having 8 bits. Symbols are transmitted only in their non-inverted form. Disparity: 0 Run length within word: 6 Run length at the edge: 3 Using four 11B13B encoders, a controllable disparity of at least ±12 can be generated, thereby compensating for the uncontrollable disparity of up to ±12 (6x±2) of 11B12B and 7B8B encoders. As a result, balanced disparity can be reliably achieved regardless of the data to be transmitted.

[0157] To further reduce hardware complexity, according to one aspect of the present invention, four miniature encoders (11B13B) are used, and their disparity can be controlled with respect to sign (+ / -).

[0158] According to one aspect of the present invention, symbol disparity is controlled so that each encoder calculates the parity of "each" subsymbol. This can be done with minimal overhead because subsymbols have only a few bits.

[0159] By using four of the eleven encoders to invert the generated subsymbols, the sign of the disparity of the subsymbols can be actively controlled. For this purpose, the encoders (11B13B) are characterized in that they generate symbols that have positive disparity (+3...+9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3...-9) can be obtained.

[0160] In this way, the disparities (-2,-1,0,1,2) of the partial symbols of the other encoders (11B12B and 7B8B) can be compensated. Encoder 6B8B generates symbols with a disparity of always 0. Then, all (partial) parities of the encoders (11B12B and 7B8B) are added together, and the result controls the decision of how many inverted and non-inverted symbols of encoder (11B13B) to use.

[0161] The minimum disparity of encoders 11B and 13B is ±3. Therefore, a total disparity of ±12 (4 * ±3) per symbol can be reliably compensated using these four encoders.

[0162] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in extreme cases, these six encoders would generate exactly ±12 (2*±6) disparity. This can be reliably compensated for by the 11B13B encoder.

[0163] According to one aspect of the present invention, this method achieves the same quality as 8B10B code despite having half the overhead (encoding loss). By using multiple small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires minimal resources (logic).

[0164] Encoding can typically be completed entirely in a single cycle of a parallel data path (pipeline processing is not required). Controlling the disparity of 128-bit symbols can be achieved with (very) little logic and can be done entirely within a single clock cycle (slow) of the data path, rather than calculating disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0165] Due to deterministic disparity and run-length encoding, additional scrambling is not required, and therefore, high-speed synchronization to the data stream is possible at the receiver side (scrambler synchronization is not necessary).

[0166] In particular, this is extremely useful for a power-saving mode that allows the link to be turned off to conserve energy and turned back on when needed. For this to work, high-speed synchronization between the transmitter and receiver is essential.

[0167] According to one aspect of the present invention, the present invention encodes a 112-bit wide data word having an arbitrary disparity (maximum disparity: 112) and an arbitrary run length (maximum run length: 112) into a 128-bit wide symbol. Therefore, the overhead caused by the encoding is 14.2%.

[0168] The maximum run-length encoding that occurs within a symbol is eight identical bits, just as with any sequencing of any symbol. The maximum disparity in the long-term average is 0, and the disparity in the symbol is less than 9.

[0169] The logic complexity is minimal, comparable to 10 8B / 10B encoders (though it has the known drawback of high overhead). This is achieved by using or using in parallel multiple "small" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0170] Encoders 11B12B, 7B8B, and 6B8B generate all symbols that guarantee a maximum run-length of 6, regardless of the order in which the (partial) symbols are ordered. According to one aspect of the present invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7, or symbols with a run length of 5 at the beginning or end. Due to the ordering of (11B13B) with other encoders (Figure 2), a maximum run length of 8 can be generated within a symbol.

[0171] The characteristics of the encoder are shown below. To further reduce hardware complexity, four small encoders (11B13B) are used, and their disparity can be controlled with respect to the sign (+ / -).

[0172] According to one aspect of the present invention, symbol disparity is controlled so that each encoder calculates the parity of "each" subsymbol. This can be done with minimal overhead because subsymbols have only a few bits.

[0173] By using four of the eleven encoders to invert the generated subsymbols, the sign of the disparity of the subsymbols can be actively controlled. For this purpose, the encoders (11B13B) are characterized in that they generate symbols that have positive disparity (+3...+9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3...-9) can be obtained.

[0174] In this way, the disparities (-2,-1,0,1,2) of the partial symbols of the other encoders (11B12B and 7B8B) can be compensated. Encoder 6B8B generates symbols with a disparity of always 0. Then, all (partial) parities of the encoders (11B12B and 7B8B) are added together, and the result controls the decision of how many inverted and non-inverted symbols of encoder (11B13B) to use, respectively.

[0175] The minimum disparity of encoders 11B and 13B is ±3. Therefore, a total disparity of ±12 (4 * ±3) per symbol can be reliably compensated using these four encoders.

[0176] Furthermore, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in extreme cases, these six encoders would generate exactly ±12 (2*±6) disparity. This can be reliably compensated for by the 11B13B encoder.

[0177] This process achieves the same quality as 8B10B code, despite having half the overhead (coding loss). By using multiple small encoders instead of one large encoder, the implementation of the encoding and decoding hardware requires minimal resources (logic).

[0178] Encoding can typically be completed entirely in a single cycle of a parallel data path (pipeline processing is not required). Controlling the disparity of 128-bit symbols can be achieved with (very) little logic and can be done entirely within a single clock cycle (slow) of the data path, rather than calculating disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0179] Due to deterministic disparity and run-length encoding, further scrambling is unnecessary, and therefore, high-speed synchronization to the data stream is possible at the receiver (scrambler synchronization is not required).

[0180] In particular, this is extremely useful for a power-saving mode that allows the link to be turned off to conserve energy and turned back on when needed. For this to work, high-speed synchronization between the transmitter and receiver is essential.

[0181] Figure 7B shows the adapted system assembly from Figure 7A, where a newly corresponding partial forward error correction encoder is shown. These are referred to herein as FEC blocks. Thus, Figure 7B shows that the segment is first formed from a bit sequence, which corresponds to the upper arrow pointing downward from the user data. This is the case when the partial forward error correction is generated and then fed to the coding unit, as already shown in Figure 7A. The line coding unit, referred to herein as the line coder, encodes both the segment of the bit sequence and the partial forward error correction. Parity can be adjusted at any process step. The line-coded data is then output at the bottom and transmitted to a receiver (not shown) via a rightward potentially error-prone communication channel.

[0182] Figure 8A illustrates a method according to the present invention for improving forward error correction, and in particular, shows the method steps performed on the transmitter side. The downward arrow in Figure 8A corresponds to the upward arrow in the following Figure 8B. Thus, the data is input as shown in Figure 8A, and then partial forward error correction is calculated. As can be seen from the above, all segments have the same bit length. This means that the first column contains 11 bits, the second column contains 11 bits, and the last column contains 6 bits.

[0183] Here, partial forward error correction is generated for all segments at the same bit position that have the same bit length as the corresponding segment. As a result, data with parity symbols is obtained. In the final processing step, serial line coding is performed, for example, mapping 11 bits to 12 bits, or 11 bits to 13 bits, or 6 bits to 8 bits. This data can be transmitted over a potentially interference-prone channel. This results in transmission as shown in the lower part of Figure 8A or the upper part of Figure 8B.

[0184] Figure 8B shows the receiver-side procedure, which is the reverse of the procedure in Figure 8A. As also shown in Figure 8B, bit errors may exist, but it is recognized that these can be handled particularly favorably at the segment level. Thus, bit errors can be handled favorably because they occur only in individual segments and not in the entire bit sequence. This results in corrected data as shown in the lower part of Figure 8B, and thus the 112 bits used as output in Figure 8A are restored.

[0185] Figure 9 shows a flowchart of a method in an automobile for generating an efficiently transmittable bit sequence with limited disparity, limited run-length, and line-coded forward error correction, the method comprising: step 100 providing an arbitrary bit sequence; step 101 segmenting the provided bit sequence into predetermined sequence segments according to individual predetermined bit lengths; step 101A calculating forward error correction for each or more segments of the same bit length; and step 102 encoding each segment or multiple segments of the same bit position into one or more subsymbols, each with the corresponding forward error correction, using the same encoding unit from a plurality of encoding units for segments of the same bit position and associated forward error correction, wherein a first subset of the plurality of encoding units compensates for the disparity of a second subset of the plurality of encoding units by actively controlling the encoding of the disparity of the subsymbols by inverting the disparity of the generated subsymbols, and the juxtaposition of the subsymbols generates an efficiently transmittable bit sequence with the calculated forward error correction.

[0186] All segment line codes and all partial forward error correction line codes are also transmitted. In this final step, all generated segment line codes and partial forward error correction line codes are transmitted. These transmitted codes include information for error detection and correction for the corresponding segments, and information for partial forward error correction. The described method enables improved forward error correction during serial coding and data transmission in vehicles. Effective error detection and correction are achieved at the segment level by dividing user data into segments and applying specific coding procedures to these segments.

[0187] By iteratively creating partial forward error correction for all segments at the same bit position and applying a segment encoder to each segment, targeted error correction of transmitted data becomes possible. The partial forward error correction line code contains the information necessary to detect and correct errors, while the segment line code represents the structure and content of the segment, also contributing to error detection and correction.

[0188] By transmitting all generated segment line codes and partial forward error correction line codes, the receiver can properly analyze the received data, detect and correct errors, and ensure reliable and accurate transmission of user data within the vehicle.

[0189] Therefore, the described method provides improved forward error correction, which is particularly important in harsh environments such as vehicles where interference and signal loss can occur. This method helps ensure reliable and high-quality data transmission, which is crucial for various applications in the automotive sector, such as autonomous driving, vehicle safety systems, and infotainment applications.

[0190] This invention makes it possible to operate the FEC efficiently while always maintaining all the desired characteristics and requirements for serial coding. By intentionally placing the serial encoder downstream of the FEC unit, the physical behavior on the link can always be controlled deterministically (this is not the case when a scrambler is used as the serial encoder).

[0191] Furthermore, selecting FEC symbol sizes based on the data word size of individual serial subencoders always ensures that bit errors propagate to the minimum extent possible (a defective linecode symbol will generate only one defective FEC symbol).

[0192] Furthermore, by using multiple FEC subencoders, a highly efficient form of so-called interleaving is created. This is possible without time-consuming manual interleaving of symbols, which would require data to always be held (more latency and buffering). This also makes it possible to correct burst errors (e.g., 112 / 128 bit errors) all at once.

[0193] This fact can only be seen from the schematic structures in Figures 7A, 7B and 8A, 8B. In this case, a 128-bit error leads to only one single symbol error in the individual FEC subencoders. In conventional single FEC coding, a burst error of the same length (128 consecutive bits of error) will generate multiple symbol errors in succession. This can lead to a situation where, depending on the chosen encoding, the FEC word (all the symbols of the FEC cycle) becomes undecodeable (and therefore uncorrectable). This is usually achieved by interleaving the symbols of one or more other FEC cycles. However, this is only possible by using buffers on both the transmitter and receiver sides, so that the transmitter can interleave the data and the receiver can reverse-engineer it back into the original consecutive FEC symbol data stream of the individual FEC cycles. By using multiple small FEC encoders, interleaving, and therefore the need to maintain buffers required for interleaving, is eliminated (however, this is limited to a certain extent; consecutive burst errors exceeding 128 bits, as described in the example, will damage two or more symbols for each individual FEC).

[0194] The number of symbols (t) that an individual FEC subencoder can repair depends on the overhead 2t (see Figure 2). This must be selected according to the desired application. As shown in Figure 8A, if each FEC subencoder has one symbol error, this is already achieved at t=1 (i.e., the overhead of two parity symbols). It should also be noted that burst errors can occur, or may occur, without limitation in the parity symbol area.

[0195] Figure 10 shows a data format in which an arbitrary bit sequence is shown on the left and a sub-symbol is shown on the right. The data to be encoded has 112 bits, and the sub-symbol has 128 bits. In this way, any 112-bit bit sequence is encoded into a 128-bit whole symbol. The encoded 128 bits are optimized with respect to disparity. The arrow in the center indicates that the encoding unit converts the data segment on the left into the sub-symbol on the right. This figure also shows that this method can be used multiple times, and as a result, any number of bit sequences can be converted into any number of whole symbols. Furthermore, the data can be divided into different data cells or data frames.

[0196] Even if the data on the left has the same meaning as the data on the right, the data on the right is encoded in a way that optimizes its disparity. In general, this method can be applied to any data, and therefore any bit sequence, and can transmit both user data and header data.

[0197] The illustrated data fields are merely examples and represent application examples of the present invention. Figure 11 shows an encoding unit with inputs and outputs in the center. The output data consists of 112 bits with indices 0 to 111. These are decomposed into segments with 11 bits, 6 bits, 7 bits, or other bit length allocations. In this example, these segments are converted into subsymbols of 12 bits, 13 bits, 8 bits, or other data lengths. The proposed example is particularly advantageous in that it encodes 112 bits into 128 bits, thereby achieving particularly high efficiency. 128 bits have the same content as the bit sequence to be encoded, but are only 16 bits longer.

[0198] Figure 11 shows, on the left, that an arbitrary 112-bit bit sequence is segmented into 11-bit data segments, which are then encoded into 12 bits using the encoding unit 11B12B.

[0199] Figure 12 shows a data format that may be used, for example, in Figure 10 or Figure 11. In this case as well, a 128-bit whole symbol and a 112-bit arbitrary data sequence are shown. Overall, any bit sequence and whole symbol can have different header data or frame data.

[0200] The following shows several specific possibilities of how segments of any bit sequence can be converted into subsymbols such that disparity is minimized or eliminated. The first table shows a 6-bit to 8-bit conversion, the second table shows a 7-bit to 8-bit conversion, the third table shows an 11-bit to 12-bit conversion, and the fourth table shows an 11-bit to 13-bit conversion. Thus, 6-bit, 7-bit, or 11-bit segments are converted into 8-bit, 12-bit, or 13-bit subsymbols. The illustrated encodings are illustrative and illustrate the technical effects achieved in this case. The present invention has been empirically evaluated and found that, based on the proposed encoding, 112 bits can be optimized with respect to their disparity so that only 128 bits are required. This corresponds to a so-called overhead of only 14%.

[0201] In this case, "cell" is used as a synonym for "frame." These could also be packets. Cell format / Frame format According to one aspect of the present invention, the cell includes a header having a fixed bit length, a payload area having four selectable bit lengths, and a footer having a fixed bit length.

[0202] The cell structure is a sequence of bits as follows: - A 7-bit virtual path identifier (VP) representing the unique address of a virtual path. - A 3-bit sequence number (SN) used to number cells sequentially.

[0203] - A 2-bit wide cell type (CT) identifier that specifies the length of user data. - 3-bit wide payload information (PI) containing additional information about the payload. This can also be used to synchronize payload data with frame data or control data.

[0204] - A 10-bit wide CRC polynomial (HCRC) for error protection of header information. The polynomial has a Hamming distance of 5 for bit sequences up to 21 bits (P=0x2B9).

[0205] - The payload (PL) area is 187 bits, 411 bits, 635 bits, or 859 bits, depending on the CT value. The shortest payload is selected to be larger than the maximum supported (video) streaming bus width (to simplify the mapping of streaming data to the cell payload).

[0206] - Finally, a 12-bit wide CRC polynomial (PCRC) for error protection of user data. This polynomial has a Hamming distance of 4 for bit sequences up to 2035 bits (P=0x8F3).

[0207] Transmission frame format According to one aspect of the present invention, a transmission frame includes a sequence of M-bit wide words. The frame begins with an M-bit wide "comma" word from a defined sequence of comma words for frame alignment. This is followed by K cells. Each cell consists of 2, 4, 6, or 8 N-bit wide words that make up the header, payload, and footer. These N-bit wide words are encoded into M-bit wide symbols (line encoding).

[0208] This format is chosen to enable processing of cell data at an appropriate time-frequency, under the condition that the serializer / deserializer always processes M-bit blocks.

[0209] Figure 13 shows a portion of exemplary encoding of data segments into symbols, where 6 bits are encoded into 8 bits so that disparity is optimized according to one aspect of the present invention. For example, segment 000000 is encoded into subsymbol 00101011, i.e., a 6B8B encoder. Furthermore, Figure 14 shows a 7B8B encoder, Figure 15 shows an 11B12B encoder, and Figure 16 shows an 11B13B encoder.

Claims

1. A method in an automobile for generating an efficiently transmittable bit sequence with limited disparity, limited run length, and line-coded forward error correction, Step (100) of providing an arbitrary bit sequence, The steps (101) include segmenting the provided bit sequence into predetermined sequence segments according to individual predetermined bit lengths, Step (101A) of calculating forward error correction for each of the segments or for multiple segments of the same bit length, A method comprising the step (102) encoding each segment or multiple segments of the same bit position into one or more subsymbols together with the corresponding forward error correction, wherein a first subset of the multiple encoding units compensates for the disparity of a second subset of the multiple encoding units by actively controlling the code of the disparity of the subsymbols by inverting the disparity of the generated subsymbols, and the juxtaposition of the subsymbols generates a bit sequence that can be efficiently transmitted together with the calculated forward error correction.

2. The method according to claim 1, characterized in that the step (101A) of calculating forward error correction for each of the segments is performed such that segments at the same position from a plurality of segmented bit sequences are combined and forward error correction is formed across the combined segments.

3. The method according to claim 1 or 2, characterized in that the disparity of the second subset of the plurality of coding units is not controllable.

4. The method according to any one of claims 1 to 3, characterized in that the entire partial forward error correction describes a provided bit sequence in a correctable manner.

5. The method according to any one of claims 1 to 4, characterized in that the encoding unit has the minimum number of gates with respect to the predetermined bit length.

6. The method according to any one of claims 1 to 5, characterized in that a calculation unit for calculating the forward error correction is connected to the front of each coding unit.

7. The method according to any one of claims 1 to 6, characterized in that a first subset of the plurality of encoding units encodes an 11-bit segment into a 13-bit subsymbol.

8. The method according to any one of claims 1 to 7, characterized in that a first subset of the plurality of encoding units has a disparity of +3 to +9, and the disparity is inverted to -3 to -9 by bitwise inversion of the subsymbols.

9. The method according to any one of claims 1 to 8, wherein the run-length of the subsymbol is at most 7.

10. The method according to any one of claims 1 to 9, characterized in that the run length of the subsymbols in the first subset of the plurality of encoding units is at most 5, counting from the most significant bit and / or the least significant bit.

11. The method according to any one of claims 1 to 10, characterized in that in a second subset of the plurality of encoding units, an 11-bit segment is encoded into a 12-bit subsymbol, or a 7-bit segment is encoded into an 8-bit subsymbol, or a 6-bit segment is encoded into an 8-bit subsymbol.

12. The method according to any one of claims 1 to 11, characterized in that, when there are positive and negative data streams with respect to the disparity, the multiplexer selects a data stream that contributes to minimizing the overall disparity of the symbols as a whole.

13. A system device in an automobile for generating an efficiently transmittable bit sequence with limited disparity and limited run length, An interface unit configured to provide an arbitrary bit sequence (100), A segmentation unit adapted to segment the provided bit sequence into segments of a predetermined sequence according to individual predetermined bit lengths (101), A calculation unit configured to calculate forward error correction (101A) for each of the segments or for multiple segments of the same bit length, A system device comprising: an encoding device configured to encode each segment or multiple segments at the same bit position into one or more subsymbols together with the corresponding forward error correction, using the same encoding unit from a plurality of encoding units for segments at the same bit position and associated forward error correction (102), wherein a first subset of the plurality of encoding units actively controls the code of the disparity of the subsymbols by inverting the disparity of the generated subsymbols to compensate for the disparity of a second subset of the plurality of encoding units, and the juxtaposition of the subsymbols generates a bit sequence that can be efficiently transmitted together with the calculated forward error correction.

14. A computer program product comprising instructions, wherein, when the program is executed by at least one computer, the instructions cause the computer to perform a step according to any one of claims 1 to 12.

15. A computer-readable storage medium containing instructions, wherein, when executed by at least one computer, the instructions cause the computer to perform a step of the method according to any one of claims 1 to 13.

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