Low-power memory state during non-idle processor state

Abstract

The disclosed device includes a plurality of processing components and a cache. Any of the processing components may be instructed to avoid allocation to the cache, and any other processing component may be permitted to use the cache while reducing access to memory. The memory can then enter a low-power state depending on the idle state of the memory, which is achieved by the processing components avoiding access to the memory for a predetermined period of time. Various other methods, systems, and computer-readable media are also disclosed.

Description

Background Art

[0004] , , , [Figure 4] , [Figure 3] , , [Figure 2] , , [Figure 1] ,

[0001] Under certain conditions such as the idle state, the processor can enter a low-power state (e.g., by turning off some or all of its components) to reduce power consumption. Similarly, a memory such as DRAM can enter a low-power state (e.g., self-refresh where data values are read and rewritten to refresh the weakening of the charge). The low-power state of the memory often requires a period during which the processor does not access the memory, so it is often linked to the processor idle state. However, certain architectures can reduce the opportunity for the memory to enter the low-power memory state.

[0002] The accompanying drawings illustrate several exemplary embodiments and are part of this specification. Together with the following description, these drawings demonstrate and explain the various principles of the present disclosure.

Brief Description of the Drawings

[0003] [Figure 1] It is a block diagram of an exemplary system for entering a low-power memory state during a non-idle processor state. [Figure 2] It is a block diagram of another exemplary system for entering a low-power memory state during a non-idle processor state. [Figure 3] It is a flowchart of an exemplary method for entering a low-power memory state during a non-idle processor state. [Figure 4] It is a flowchart of another exemplary method for entering a low-power memory state during a non-idle processor state.

Modes for Carrying Out the Invention

[0005] This disclosure generally relates to entering a low-power memory state during a non-idle processor state. As will be described in more detail below, embodiments of this disclosure enable memory to enter a low-power state by instructing a first processing component to avoid accessing the cache and a second processing component to avoid accessing memory. The first processing component may have a stutter mode that allows its memory fabric to become temporarily idle (for example, by exhausting a previously filled buffer). By causing the first processing component to avoid the cache, the second processing component can more fully utilize the cache to avoid memory. During the stutter mode of the first processing component, memory can enter a low-power state even if the second processing component is active, advantageously providing power savings without performance degradation.

[0006] In one embodiment, a device for entering a low-power memory state during a non-idle processor state includes a first processing component, a second processing component, a cache, and a control circuit. The control circuit may be configured to instruct the first processing component to avoid allocating in the cache in response to a cache miss, to instruct the second processing component to allocate in the cache, and to instruct the memory device to enter a low-power state in response to the idle state of the memory device.

[0007] In some examples, the control circuit is further configured to instruct a first processing component to force evictions from the cache in response to cache hits. The first processing component comprises an activity buffer and is configured to fill the activity buffer up to a buffer threshold by accessing a memory device. In some examples, an idle state in the memory device corresponds to the first processing component pausing access to the memory device while the activity buffer is exhausted. In some examples, the first processing component corresponds to a display engine, and the activity buffer corresponds to a display buffer.

[0008] In some examples, the first processing component avoiding allocation to the cache allows the second processing component to allocate its workload within the cache. In some examples, the idle state of the memory device corresponds to the second processing component avoiding access to the memory device by having its workload allocated within the cache. In some examples, the idle state of the memory device coincides with the active state of the second processing component. In some examples, the low-power state of the memory device corresponds to a self-refresh. In some examples, the control circuit is further configured to instruct the memory device to enter a low-power state when it predicts that the idle state of the memory device will have a sufficient idle duration.

[0009] In one embodiment, a system for entering a low-power memory state during a non-idle processor state includes memory, a processor with a cache, a first processing component that utilizes an activity buffer, a second processing component, and a control circuit. The control circuit is configured to instruct the first processing component to use the activity buffer, avoid allocating in the cache in response to a cache miss, and force evicting from the cache in response to a cache hit, to instruct the second processing component to allocate in the cache, and to instruct the memory to enter a low-power state while the second processing component is active.

[0010] In some examples, the control circuit is further configured to instruct the memory to enter a low-power state in response to the memory entering an idle state. In some examples, the control circuit is further configured to instruct the memory device to enter a low-power state in response to the prediction that the memory device's idle state will have a sufficient idle duration. In some examples, the first processing component is configured to fill the activity buffer to a buffer threshold by accessing memory, and the memory idle state corresponds to the first processing component suspending access to memory while the activity buffer is exhausted. In some examples, the first processing component avoids allocation to the cache and forces evicting from the cache, allowing the second processing component to allocate its workload into the cache. In some examples, the memory idle state corresponds to the second processing component avoiding access to memory by causing the second processing component to allocate its workload into the cache.

[0011] In some examples, the first processing component corresponds to the display engine, and the activity buffer corresponds to the display buffer. In some examples, the low-power state of memory corresponds to a self-refresh.

[0012] In one embodiment, a method for entering a low-power memory state during a non-idle processor state includes: (i) filling the activity buffer of a first processing component with a first processing component to reduce the workload footprint of the first processing component in the cache; (ii) avoiding access to memory by the first processing component by depleting the activity buffer; (iii) accessing the cache with a second processing component having its workload in the cache; and (iv) entering a low-power memory state while the second processing component is active.

[0013] In some examples, the method further includes filling the activity buffer to a buffer threshold by accessing memory. In some examples, entering a low-power state of memory occurs in response to memory being idle, as a first processing component avoids accessing memory and a second processing component avoids accessing memory. In some examples, the low-power state of memory corresponds to a self-refresh. In some examples, entering a low-power state of memory occurs in response to the expectation that memory will be idle for a sufficient idle duration.

[0014] Features from any of the embodiments described herein can be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features and advantages will be better understood by reading the following detailed description in conjunction with the accompanying drawings and claims. [Examples]

[0015] The following provides a detailed explanation of enabling a low-power state of memory during a non-idle or non-low-power state of the processor, with reference to Figures 1 to 4. A detailed description of an exemplary system is provided in relation to Figures 1 and 2. A detailed description of the corresponding method is also provided in relation to Figures 3 and 4.

[0016] Figure 1 is a block diagram of an exemplary system 100 for enabling a low-power memory state during a non-idle processor state. System 100 corresponds to computing devices such as desktop computers, laptop computers, servers, tablet devices, mobile devices, smartphones, wearable devices, augmented reality devices, virtual reality devices, network devices, and / or electronic devices. As shown in Figure 1, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, and / or any other suitable storage memory.

[0017] As shown in Figure 1, the exemplary system 100 includes one or more physical processors, such as a processor 110. The processor 110 generally represents any type or form of hardware implementation processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, the processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, chiplets (for example, smaller, and in some cases more specialized processing units that can work together as a single chip), microprocessors, microcontrollers, Central Processing Units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), system-on-chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of these, one or more variations or combinations of these, and / or any other suitable physical processors.

[0018] As further shown in Figure 1, the processor 110 includes a control circuit 112, a cache 114, a processing component 130, and a processing component 140. The control circuit 112 corresponds to circuits and / or instructions for controlling specific functions related to power management, and in some examples includes, integrated with and / or interfaced with a cache controller (e.g., for controlling cache 114), and in some examples includes, integrated with and / or interfaced with a traffic monitor (e.g., for monitoring traffic in memory 120). The cache 114 corresponds to local storage of the processor 110 for holding data so that the processor 110 and / or components within it (e.g., processing component 130 and / or processing component 140) can access the data without incurring latency for accessing memory 120. In some examples, the cache 114 can correspond to a cache hierarchy or a part thereof. Each of the processing components 130 and 140 corresponds to any component of the processor 110 that can access data for processing, such as a chiplet client. In one embodiment, the processing component 130 corresponds to a stutter client having an activity buffer (for example, a chiplet component that can be idle or not access memory while a previously filled activity buffer is exhausted).

[0019] Figure 2 shows a simplified architecture of system 200 corresponding to system 100. System 200 includes a processor 210 corresponding to processor 110 and memory 220 corresponding to memory 120. As further shown in Figure 2, processor 210 includes a cache 214 corresponding to cache 114, processing component 230 corresponding to processing component 130, and processing component 240 corresponding to processing component 140. Processing component 230 further includes a buffer 232 corresponding to an activity buffer for storing data, which allows processing component 230 to stutter when filled to a buffer threshold.

[0020] In some examples, the processing component 230 corresponds to the display engine, such that buffer 232 corresponds to the display frame buffer. During normal operation, display data (e.g., frames) can be accessed from cache 214 (e.g., accessed from memory 220 in case of a cache miss and cached in cache 214) for buffering in buffer 232. The processing component 240 can also access the cached data in cache 214 from memory 220 (and access memory 220 as needed, for example in case of a cache miss). However, having the display frame buffer in cache 214 can be inefficient, especially for small caches, because the display frame buffer can often be large. For example, the potentially large cache footprint of the display engine can undesirably cause capacity displacement for other processing components (e.g., by occupying a significant portion of cache 214, preventing other processing components from allocating to cache 214).

[0021] To improve cache utilization, a control circuit (e.g., control circuit 112) can instruct a processing component 230 (as indicated by the dotted arrow) to avoid allocating to cache 214 in order to exclude data in buffer 232 from cache 214 (e.g., to exclude the display frame buffer). The processing component 230 can instead access memory 220 (as indicated by the solid arrow) for the buffered data and use buffer 232. For coherence reasons, the processing component 230 can still access cache 214 (e.g., to avoid reading potentially old data from memory 220 when modified data is available in cache 214), but can be further instructed to force evicting from cache 214 on hit. In some examples, this forced evicting can further evict lines already cached by the processing component 230 to prevent such lines from being promoted to Most Recently Used (MRU) position in cache 214, which can keep cache 214 occupied and prevent other processing components from making allocations. Therefore, the processing component 230 can prevent other processing components from being displaced from the cache 214 in terms of capacity. In some examples, the processing component 230 can use the cache 214 minimally, and / or not use it at all.

[0022] Therefore, the processing component 240 can access / use the cache 214 more efficiently (as indicated by the solid arrow), for example, by using a freed location in the cache 214 previously used by the processing component 230. For example, the processing component 240 can be allocated to the cache 214 to avoid a cache miss (which would result in a memory access to memory 220). In some examples, the processing component 240 can fit its entire workload into the cache 214 (e.g., for at least a certain period of time) to avoid accessing memory 220 (as indicated by the dotted arrow). Low-power memory residency can be enhanced by using the processing component 240 which has its entire workload in the cache 214. Therefore, in some examples, the processing component 240 can be selected based on having a workload footprint that is potentially suitable for the cache 214, or it can otherwise benefit from cache-as-RAM modes or cache-as-buffer modes.

[0023] This operation further allows for sufficient periods of time (e.g., sufficient idle time for memory 220) during which memory 220 is not accessed, so that memory 220 can enter a low-power state (e.g., self-refresh). For example, during the period during which processing component 240 can operate from cache 214, processing component 230 can stutter by fully filling buffer 232, thus avoiding access to memory 220 while buffer 232 is exhausted (e.g., suspending). Thus, even while processor 210 is active or otherwise non-idle or non-low-power (e.g., at least due to processing component 240 being active), memory 220 can advantageously enter a low-power state such as self-refresh.

[0024] In some embodiments, the control circuit monitors the traffic of memory 220 to predict whether the idle interval of memory 220 meets a desired or sufficient idle duration (e.g., for entering and exiting a low-power state). As a result, the control circuit (and / or power management logic) can determine whether memory 220 should enter a low-power state. In some examples, the control circuit can make the prediction based on past history. For example, the control circuit can classify the type of traffic as stutter traffic (e.g., from processing component 230 and / or other processing components that can stutter) or other traffic (e.g., from processing component 240 and / or other processing components other than those that can stutter). The control circuit can analyze other traffic (e.g., based on past history) to predict whether the idle state has a sufficient idle duration. Additionally, based on the analysis of other traffic, workload, software, and / or driver configuration, etc., the control circuit can determine the effective time to achieve a sufficient idle duration for memory 220 and instruct processing component 230 and / or processing component 240 to actively enter the low-power state for memory 220.

[0025] The examples herein illustrate avoiding access to memory 220 and / or cache 214 (e.g., allocating to and / or evicting from cache 214), however, in certain scenarios, components may access memory 220 and / or cache 214 as needed. For example, if buffer 232 is nearly exhausted (e.g., below a lower buffer threshold to avoid blackouts where display frames are unavailable for display, it may account for the latency of memory 220 exiting its low-power state), processing component 230 may access memory 220 as needed. Processing component 230 may also access cache 214 as needed. Furthermore, processing component 240 may access memory 220 as needed, for example, due to a cache miss with cache 214. Thus, memory 220 and various processing components may enter / exit a low-power state as needed, including, for example, processor 210 exiting a low-power state to lead to a self-refresh of memory 220, or processor 210 transitioning from an active state to a low-power state during a self-refresh of memory 220. As described herein, instructions for bypassing memory 220 and / or cache 214 allow sufficient coinciding periods of idle state for some components (e.g., for processing component 230 and memory 220) to allow the active state for other components (e.g., processing component 240) to enable memory 220 to enter a low-power state even when processor 210 is active or otherwise not in a low-power state.

[0026] FIG. 3 is a flow diagram of an exemplary method 300 for entering a low-power memory state during a non-idle processor state. The steps shown in FIG. 3 can be performed by any suitable circuit, device, and / or system, including the system shown in FIG. 1 and / or FIG. 2. In one example, each of the steps shown in FIG. 3 represents an algorithm whose structure includes a plurality of sub-steps and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0027] As shown in FIG. 3, in step 302, one or more of the systems described herein instruct a first processing component to avoid cache allocation in response to a cache miss. For example, control circuit 112 can instruct processing component 130 to avoid allocation to cache 114 upon a cache miss.

[0028] The systems described herein can perform step 302 in various ways. In one example, control circuit 112 can further instruct processing component 130 to force eviction from cache 114 in response to a cache hit. In some examples, the first processing component (e.g., processing component 130 and / or processing component 230) includes an activity buffer (e.g., buffer 232) and is configured to fill the activity buffer up to a buffer threshold by accessing a memory device (e.g., memory 120 and / or memory 220). In some examples, the first processing component corresponds to a display engine and the activity buffer corresponds to a display buffer, but in other examples, the first processing component can correspond to other components capable of stuttering (e.g., an image signal processor (ISP), an input / output device capable of periodic isochronous traffic, etc.). In some examples, processing component 130 can further confirm that the stuttering conditions are met.

[0029] In step 304, one or more of the systems described herein instruct a second processing component to allocate within a cache. For example, control circuit 112 may instruct processing component 140 to allocate to cache 114 and reduce access to memory 120 (for example, by reducing misses). In some examples, processing component 140 can allocate its workload to cache 114 by preventing processing component 130 from allocating to cache 114. In some examples, control circuit 112 may instruct processing component 140 to flush pending writes to memory 120.

[0030] As shown in Figure 3, in step 306, one or more of the systems described herein instruct the memory device to enter a low-power state depending on the idle state of the memory device. For example, the control circuit 112 and / or memory 120 may detect the idle state of memory 120 and instruct memory 120 to enter a low-power state accordingly.

[0031] The systems described herein can perform step 306 in various ways. In one example, a low-power state of the memory device corresponds to a self-refresh. In some examples, an idle state in the memory device corresponds to the first processing component suspending access to the memory device while the activity buffer is exhausted. Furthermore, in some examples, an idle state of the memory device corresponds to the second processing component avoiding access to the memory device by allocating its workload to a cache. Furthermore, in some examples, an idle state of the memory device coincides with an active state of the second processing component.

[0032] Figure 4 is a flowchart of an exemplary method 400 for entering a low-power memory state during a non-idle processor state. The steps shown in Figure 4 can be performed by any suitable circuit, device and / or system, including the system shown in Figure 1 and / or Figure 2. In one example, each of the steps shown in Figure 4 has a structure that includes and / or represents an algorithm represented by multiple sub-steps, examples of which are provided in more detail below.

[0033] As shown in Figure 4, in step 402, one or more of the systems described herein fill the activity buffer of the first processing component with the first processing component, thereby reducing the workload footprint of the first processing component in the cache. For example, processing component 130 (or processing component 230) can fill its activity buffer (e.g., buffer 232) and avoid accessing cache 114 (or cache 214).

[0034] The systems described herein can perform step 404 in various ways. For example, filling the activity buffer includes filling the activity buffer up to a buffer threshold by accessing memory, as described herein.

[0035] In step 404, one or more of the systems described herein avoid access to memory by the first processing component by depleting (using up) the activity buffer. For example, processing component 130 (or processing component 230) can avoid accessing memory 120 (or memory 220).

[0036] In step 406, one or more of the systems described herein access the cache by a second processing component that has its workload in the cache. For example, processing component 140 accesses the cache 114 and avoids accessing memory 120.

[0037] In step 408, one or more of the systems described herein enter a low-power state of memory while the second processing component is active. For example, memory 120 may enter a low-power state (e.g., self-refresh) while processing component 140 is active.

[0038] The systems described herein can perform step 408 in various ways. In one example, entering a low-power state of memory occurs in response to the memory being idle, as a first processing component avoids accessing the memory and a second processing component avoids accessing the memory. For example, memory 120 may be idle, in part, due to processing component 130 avoiding accessing memory 120 and processing component 140 avoiding accessing memory 120. In some examples, the control circuit 112 can also predict that memory 120 will be idle for a sufficient idle duration to enter and exit a low-power state. Depending on whether memory 120 is idle, memory 120 can enter a low-power state.

[0039] As mentioned above, in SoCs with large caches, certain workloads, such as battery-sensitive workloads with a sufficiently small footprint, can fit entirely into the cache without DRAM misses, or certain software or driver optimizations that leverage cache-as-RAM (CAR) mode or cache-as-buffer (CAB) mode can intentionally avoid DRAM access so that the DRAM can remain in a lower power state or self-refresh. For example, if the DRAM interface is determined to be idle by the traffic monitor in the cache controller, the data fabric can either proactively enter a DRAM self-refresh while not in a low-power processor state, or exit low power to restore cache access without removing the DRAM from self-refresh.

[0040] For example, a DRAM request generated by the cache controller in response to a miss or an uncached request may terminate the self-refresh in response to the request, or a low-power processor state ready achieved during a non-idle processor state self-refresh may lead to a conversion to a low-power state while the DRAM remains in self-refresh mode. For example, an operating system (OS) that wakes up for scheduler checks, audio workloads that use the cache as RAM, and video conferencing can operate without cache misses, but when mixed with other workloads such as graphics / displays that have cache misses, the cache will access DRAM. When graphics become active (and DRAM is in self-refresh mode), the cache miss causes the DRAM to terminate self-refresh, and stutter mode is reserved when the system is idle.

[0041] Therefore, some clients can operate out of the cache, while other clients, such as stutter clients, are less able to operate out of the cache. Stutter clients, such as displays, can be configured to operate from DRAM without using the cache. A display client can then be forced into stuttering, which, along with other clients operating from the cache, allows the DRAM to self-refresh even when the system is active.

[0042] Therefore, the systems and methods described herein enable SoCs with small caches to often exclude large display framebuffers from caching, and as a result, the cache can be reserved for other components that require more cache usage, such as hardware-stored states, audio, scenario-based cache-as-RAM usage by the inference engine or video decoding engine (e.g., for I-frame caching). By eliminating display caching, framebuffer access always goes to DRAM, which is facilitated, as described herein, by negotiating the display stutter during non-idle or non-low-power states to create gaps in the DRAM traffic so that cached components can continue to hit in the cache along with DRAM during self-refresh.

[0043] In other words, the systems and methods described herein allow display stutter to occur even when the system is active, because the cache does not necessarily access the DRAM, and the DRAM is sufficiently able to enter self-refresh mode. By forcing the display to the DRAM and not using the cache, the cache can be utilized more efficiently. Since self-refresh is a low-power mode for the DRAM, power efficiency is improved.

[0044] As described above, the circuits and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions. In their most basic configurations, each of these computing devices includes at least one memory device and at least one physical processor.

[0045] In some instances, the term “memory device” generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more modules and / or circuits described herein. Examples of memory devices include, but are not limited to, random-access memory (RAM), read-only memory (ROM), flash memory, hard disk drives (HDDs), solid-state drives (SSDs), optical disk drives, caches, one or more variations or combinations thereof, or any other suitable storage memory.

[0046] In some cases, the term “physical processor” generally refers to any type or form of hardware implementation processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor accesses and / or modifies one or more modules stored in the memory devices described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems-on-a-chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of these, one or more variations or combinations of these, or any other suitable physical processor.

[0047] In some embodiments, the term “computer-readable medium” generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable mediums include, but are not limited to, transmission media such as carrier waves, magnetic storage media (e.g., hard disk drives, tape drives, and floppy disks), optical storage media (e.g., Compact Disks (CDs), Digital Video Disks (DVDs), and Blu-ray® discs), electronic storage media (e.g., solid-state drives and flash media), and non-transient media such as other distribution systems.

[0048] The process parameters and steps described and / or illustrated herein are given only as examples and may be changed as desired. For example, the steps illustrated and / or described herein are illustrated or discussed in a particular order, but these steps do not necessarily have to be performed in the illustrated or discussed order. Various exemplary methods described and / or shown herein may omit one or more of the steps described or shown herein, or may include additional steps in addition to those disclosed.

[0049] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit to any specific form disclosed. Many modifications and variations are possible without departing from the spirit and scope of this disclosure. The embodiments disclosed herein should be considered in all respects to be exemplary and not restrictive. In determining the scope of this disclosure, the appended claims and their equivalents should be referenced.

[0050] Unless otherwise stated, the terms “connected” and “joined” (and their derivatives) as used herein and in the claims should be interpreted to allow both direct and indirect connections (i.e., through other elements or components). In addition, the terms “a” or “an” as used herein and in the claims should be interpreted to mean “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives) as used herein and in the claims are interchangeable with the term “comprising” and have the same meaning.

Claims

1. It is a device, The first processing component and The second processing component, Cache and, Equipped with a control circuit, The aforementioned control circuit is In response to a cache miss, the first processing component is instructed to avoid allocation within the cache, The second processing component is instructed to perform the allocation within the cache, The memory device is instructed to enter a low-power state depending on its idle state, It is configured to do, device.

2. The control circuit is configured to instruct the first processing component to force an evicting from the cache in response to a cache hit. The device according to claim 1.

3. The first processing component is configured to include an activity buffer and to fill the activity buffer up to a buffer threshold by accessing the memory device. The device according to claim 1.

4. The idle state of the memory device corresponds to the first processing component temporarily suspending access to the memory device while the activity buffer is exhausted. The device according to claim 3.

5. The first processing component corresponds to the display engine, and the activity buffer corresponds to the display buffer. The device according to claim 3.

6. The first processing component avoiding allocation within the cache enables the second processing component to allocate its workload within the cache. The device according to claim 1.

7. The idle state of the memory device corresponds to the second processing component avoiding access to the memory device because its workload is allocated within the cache. The device according to claim 6.

8. The idle state of the memory device coincides with the active state of the second processing component. The device according to claim 1.

9. The control circuit is configured to instruct the memory device to enter the low-power state when it predicts that the idle state of the memory device will have a sufficient idle duration. The device according to claim 1.

10. It is a system, Memory and Processor and Equipped with a control circuit, The aforementioned processor, Cache and, A first processing component that utilizes the activity buffer, A second processing component is provided, The aforementioned control circuit is The first processing component is instructed to use the activity buffer, to avoid allocation within the cache in response to a cache miss, and to force evicting from the cache in response to a cache hit. The second processing component is instructed to perform the allocation within the cache, While the second processing component is active, an instruction is given to the memory to enter a low-power state, It is configured to do, system.

11. The control circuit is configured to instruct the memory to enter the low-power state when the memory enters an idle state. The system according to claim 10.

12. The control circuit is configured to instruct the memory to enter the low-power state when it predicts that the idle state of the memory will have a sufficient idle duration. The system according to claim 11.

13. The first processing component is configured to fill the activity buffer up to a buffer threshold by accessing the memory, and the idle state of the memory corresponds to the first processing component temporarily suspending access to the memory while the activity buffer is exhausted. The system according to claim 11.

14. The first processing component avoids allocation within the cache and forces evicting from the cache, thereby enabling the second processing component to allocate its workload to the cache. The system according to claim 11.

15. The idle state of the memory corresponds to the second processing component avoiding access to the memory because its workload is allocated within the cache. The system according to claim 14.

16. The first processing component corresponds to the display engine, and the activity buffer corresponds to the display buffer. The system according to claim 10.

17. It is a method, The first processing component fills the activity buffer of the first processing component and reduces the workload footprint of the first processing component in the cache, By depleting the activity buffer, access to memory by the first processing component is avoided, A second processing component having a workload within the cache accesses the cache, This includes transitioning the memory to a low-power state while the second processing component is active. method.

18. Accessing the memory includes filling the activity buffer up to the buffer threshold. The method according to claim 17.

19. Transitioning the memory to a low-power state is performed when the memory becomes idle, as a result of the first processing component avoiding access to the memory and the second processing component avoiding access to the memory. The method according to claim 17.

20. The transition of the memory to a low-power state is performed in accordance with the prediction that the memory will remain idle for a sufficient idle duration. The method according to claim 17.

Images