Processor with virtualizable signal monitor

Abstract

A processing unit (e.g., a CPU)[102] runs multiple processes, such as multiple virtual machines[103, 104], each process employing virtual signals[106, 108] and virtual signal monitors[107, 109] to support signaling between the process and one or more accelerators. A hardware signal manager (HSM)[110] assigns each virtual signal to a system physical signal[115, 118] and each virtual signal monitor to a physical signal monitor[114, 117]. Based on the process's interaction with the virtual signal monitor (e.g., signal operation), the HSM performs the corresponding interaction on the assigned physical signal monitor. In this way, the HSM virtualizes the physical signal monitors for the running processes.

Description

Background Art

[0001] To improve processing efficiency and save power, some processing systems employ one or more accelerators to perform designated operations instead of a central processing unit (CPU). For example, some processing systems employ a graphics processing unit (GPU) for performing graphics operations, an AI accelerator for performing artificial intelligence (AI) operations, a digital signal processor (DSP) for performing signal processing operations, and the like. To facilitate communication between the accelerator and the CPU, some processing systems use signals, each of which is a shared memory object that can be accessed by the CPU and one or more accelerators to share information. Examples of signals include doorbell signals that notify an agent (e.g., one or more accelerators) that work is available, and completion signals that notify an agent (e.g., the CPU or an accelerator) when the assigned work is available. However, existing signal implementations are not very suitable for efficient signal processing, including systems that execute a relatively large number of processes, and as a result, the number of signals to be managed increases.

[0002] The present disclosure may be better understood by reference to the accompanying drawings, and its various features and advantages may become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items.

Brief Description of the Drawings

[0003] [Figure 1] FIG. 1 is a block diagram of a system that monitors signals and employs a virtualizable physical signal monitor to perform signal operations according to some embodiments. [Figure 2] FIG. 2 is a block diagram of a hardware signal manager (HSM) of FIG. 1 according to some embodiments. [Figure 3]Figure 2 shows an example of an HSM that, according to several embodiments, assigns different subsets of virtual signal monitors to a set of physical signal monitors at different points in time. [Figure 4] This is a flowchart illustrating a method for virtualizing a physical signal monitor in a system, according to several embodiments. [Modes for carrying out the invention]

[0004] Figures 1-4 illustrate the circuitry and techniques for virtualizing a set of physical signal monitors in a system. A processing unit (e.g., CPU) runs multiple processes, such as multiple virtual machines, and each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. A hardware signal manager (HSM) assigns each virtual signal to a physical signal in the system and assigns each virtual signal monitor to a physical signal monitor. Based on the process's interactions with the virtual signal monitor (e.g., signal operation), the HSM performs the corresponding interactions with the assigned physical signal monitor. Thus, by virtualizing the physical signal monitors for running processes, the HSM provides a relatively simple method for different processes to employ physical signal monitors, thereby increasing processing efficiency. Furthermore, the HSM enables the system to manage a relatively large number of signals for different running processes while using a relatively small set of physical signal monitors.

[0005] For example, in some embodiments, the system includes at least one CPU and several agents, including accelerators. To communicate, the agents use a set of signals, each signal being a shared memory-assisted object with a corresponding memory address assigned to it. Each signal includes both a signal value and a signal condition. A signal is typically listened to by one or more agents, each agent taking action when the signal condition is met by the corresponding signal value (for example, the signal condition is met when the signal value is less than 1). An agent sends a signal when it performs a write to the corresponding address using atomic memory operations. An example of a signal is a doorbell signal, which is used by one agent (e.g., a CPU) to indicate to another agent (e.g., an accelerator) that work (e.g., one or more commands) is ready to be executed. Another example of a signal is a completion signal, which is used by one agent to indicate to another agent that the assigned work is complete.

[0006] To reduce the overhead associated with software-based signal management, the system employs multiple physical monitors (PMs), each being a circuit configured to monitor a corresponding physical signal and perform actions related to that signal. Furthermore, the system employs a High-Speed ​​Microsystem (HSM) to virtualize the PMs, enabling software processes to run and interact with the PMs via a set of virtual signals. For example, in some embodiments, the system runs multiple virtual machines. Each virtual machine is configured to employ one or more virtual signals and virtual signal monitors (VSMs) for signaling, using a corresponding virtual address space known to each virtual machine. The HSM maps physical signals and corresponding PMs to each VSM. The system is configured to forward all virtual machine interactions with the VSMs to the HSM (e.g., via a runtime application programming interface (API)), and the HSM causes the mapped PMs to perform corresponding interactions about the mapped physical signals. For example, in response to a virtual machine issuing a signaling action to a VSM, the HSM issues a corresponding action to the mapped PM. Therefore, the HSM manages all mapped signals and monitors via virtual signals and monitors, allowing any mixture of mapped signals and monitors to occupy the system at any time, regardless of which process (e.g., virtual machine or address space) each belongs to. Furthermore, by mapping physical signals and PMs to different virtual signals and VSMs at different points in time, the HSM enables the system to support a relatively large number of virtual signals with a relatively small number of physical signals and PMs.

[0007] Figure 1 shows System 100 in several embodiments. System 100 is generally configured to execute an instruction set (e.g., a computer program) to perform actions as specified by the set of instructions, instead of an electronic device. Thus, in different embodiments, System 100 is any part of many electronic devices, such as a desktop or laptop computer, a server, a smartphone, a tablet, or a game console.

[0008] To facilitate instruction execution, system 100 includes a CPU 102 and a set of accelerators (e.g., accelerator 120). The number of accelerators shown in Figure 1 is only an example; in other embodiments, system 100 may include more accelerators. Furthermore, in some embodiments, system 100 includes additional circuitry not shown in Figure 1 that supports instruction execution, such as one or more memory controllers, one or more input / output controllers, one or more memory modules, etc., or any combination thereof. In some embodiments, the CPU 102 and accelerator 120 are part of a single integrated circuit, while in other embodiments, accelerator 120 is external to system 100. In other embodiments, the CPU 102 and accelerator 120 are part of the same integrated circuit package but are mounted on separate integrated circuit dies.

[0009] The CPU 102 is generally configured to execute a set of instructions for the system 100. In some embodiments, the CPU 102 includes one or more processor cores, each processor core including one or more instruction pipelines. Each instruction pipeline includes circuitry configured to fetch instructions from a set of instructions assigned to the pipeline, decode each fetched instruction into one or more operations, execute the decoded operations, and retire each instruction when the corresponding operations have completed execution. In the process of executing at least some of these operations, the CPU 102 generates operations that are executed by one of the accelerators 120.

[0010] The accelerator 120 is a circuit configured to perform a specified operation on behalf of the CPU 102. For example, in different embodiments, the accelerator may be a GPU, a vector processor, a general-purpose GPU (GPGPU), a non-scalar processor, a highly parallel processor, an artificial intelligence (AI) processor, an inference engine, a machine learning processor, a DSP, a network controller, etc.

[0011] To support further communication between the CPU 102 and the accelerator 120, the system 100 is configured to support a signal architecture such as a heterogeneous system architecture (HSA). In particular, the CPU 102 and the accelerator 120 are configured to communicate specified information, such as status information, via a set of signals, each of which is a shared memory object accessible by the CPU 102 and the accelerator 120. To support the signals, the system 100 includes a signal memory 111 containing multiple addressable entries, each corresponding to a different signal. To change the state of a signal, the accelerator 120 or the CPU 102 performs a write operation to the memory address corresponding to the signal. The value written by the write operation sets the value of the signal corresponding to the memory address. The different signal values ​​are represented as signal data 116 and signal data 119 in Figure 1. In some embodiments, the signal memory 111 is a standalone memory. In other embodiments, the signal memory 111 is a region of system memory allocated by the operating system.

[0012] To illustrate with an example, in some embodiments, an operating system (not shown) or other software running on the CPU 102 assigns a memory address as a signal for the accelerator 120, and the value of the signal indicates whether the accelerator 120 is available to process additional work items from the CPU 102. Therefore, if the accelerator 120 determines that it can process more work items, the accelerator 120 writes the specified value to the memory address in the signal memory 111 that was assigned to the signal. In response, the CPU 102 provides one or more additional work items to the accelerator 120. In different embodiments, it will be understood that the signal memory 111 stores the values ​​of any number of signals, such as a signal indicating the completion of one or more work items by the accelerator, a signal indicating that a specified action is performed by the CPU 102, etc., and indicates any of several statuses or other information.

[0013] As described above, one method for the CPU 102 and accelerator 120 to determine the status of a given signal is to poll the signal by performing read operations at the memory address specified by the signal. However, this requires the CPU 102 to repeatedly perform the polling loop for the signal, which consumes CPU resources and hinders asynchronous communication of the signal status. Therefore, to facilitate more efficient signal communication and more advanced signal processing, the system 100 includes a hardware signal manager (HSM) 110. The HSM 110 is a circuit that includes several physical signal monitors (PMs), such as PMs 114 and 117. The HSM 110 is further configured to assign each PM to a physical signal (PS). For example, in the illustrated embodiment, the HSM 110 assigns PM 114 to PS 115 and PM 117 to PS 118. Each PS is supported by corresponding signal data in the signal memory 111, where the signal data indicates the value of the corresponding PS. Therefore, in the illustrated example, the value of PS115 is indicated by signal data 116, and the value of PS118 is indicated by signal data 119.

[0014] In some embodiments, as will be further described below, PMs are assigned to physical signals by the HSM110 via a mapping table (not shown in Figure 1). Thus, at different points in time, the HSM110 assigns a given PM to a different physical signal. Each PM is a circuit configured to perform basic signal operations (load, store, and atomic memory operations in the signal memory 111) and signal waiting semantics. For example, in some embodiments, a PM circuit is configured to monitor a signal (and corresponding signal data) for a specified value and, depending on whether the signal is in the PM circuit, take a specified action, such as issuing a notification. Each PS represents a circuit that performs the functions of signal memory access (i.e., access to signal data corresponding to a signal in the signal memory 111), including load, store, and atomic memory operations (also called atomic read-modify-write operations). The PM and PS circuits thus perform signals and signal operations together in hardware, thereby reducing or eliminating the need for software polling of signals and software execution of other signal operations, and thus improving the processing efficiency in system 100.

[0015] Since PMs and their corresponding physical signals are executed in hardware, each PM and PS consumes circuit area in system 100. Therefore, in at least some embodiments, it is not feasible to implement different PMs and PSs for each signal used by the software running in system 100. For example, in the illustrated embodiment, CPU 102 implements two different virtual machines (VMs) designated VM103 and VM104, respectively. In some embodiments, VMs 103 and 104 are configured to execute more signals together than the PMs and physical signals in HSM 110. In other embodiments, each of VMs 103 and 104 individually executes more signals than the PMs and physical signals in HSM 110. Therefore, in order to support a relatively large number of signals for running software while using fewer PMs and physical signals, system 100 is configured to virtualize PMs and their corresponding physical signals.

[0016] To support virtualization, CPU 102 executes API 105, which communicates with HSM 110 based on commands generated by VMs 103 and 104. API 105 and HSM 110 provide a layer of abstraction between VMs 104 and PM, as well as physical signals in HSM 110. For example, in some embodiments, a VM instantiates a signal by sending a specified command to API 105. In response to the specified command, API 105 generates virtual signals (VS) such as VS106 and VS108, and for each virtual signal, generates virtual signal monitors (VSMs) such as VSM107 for VS106 and VSM109 for VS108. In response to a request from a VM instantiating a signal, API 105 sends a signal assignment request (not shown) to HSM 110. In response, HSM 110 assigns PSs to the VSs generated by API 105, assigns PMs to the PSs, and assigns VSMs corresponding to the signals. The HSM110 maintains a data structure called map 121 that stores information indicating the assigned PS and PM for each VS and VSM.

[0017] Next, VMs 103 and 104 each interact with their corresponding virtual signals and VSMs by providing signal commands to API 105. In at least some embodiments, these signal commands are commands configured for signal operation and signal monitoring. That is, each VS and VSM appears to the corresponding VM as if it were a local resource, and each VM interacts with its corresponding virtual signals and VMs through commands configured to interact with local signals or local signal monitors specific to that VM. API 105 and HSM 110 execute these commands together in system 100, thereby virtualizing the physical resources of HSM 110 (e.g., PM and the corresponding physical signals) as local resources for each of VMs 103 and 104.

[0018] For example, the VM interacts with the virtual signal or VSM by issuing signal operations to the virtual signal or VSM. The VM issues signal operations by sending commands corresponding to the signal operations to API 105. Examples of these signal operations include identifying signal values, changing signal values, identifying signal conditions, etc. Upon receiving a signal operation for the VS, API 105 forwards the signal operations (e.g., signal operations 112 and 113) to HSM 110. Upon receiving the forwarded signal operations, HSM 110 identifies the PS and PM assigned to the signal indicated by the forwarded signal operations. HSM 110 then causes the identified PS and PM to perform the signal operations.

[0019] For example, VM103 issues a signal operation command targeting VSM107. For illustrative purposes, assume the signal operation command is a request to change the value of VS106. In response to the signal operation command from VM103, the API forwards signal operation 112 to HSM110. HSM110 determines, based on map 121, that VS106 and VSM107 are assigned to PS115 and PM114, respectively. HSM110 then causes PM114 and PS115 to execute the forwarded operation. In this example, PM114 and PS115 jointly perform a write operation on signal memory 111 to set the value of signal data 116 to the value indicated by signal operation 112. Thus, the specific hardware used to execute the signal command is abstracted away from VM103. This allows VM103 to manage signals by employing existing signal interface software, including signal interface software that has not been reconfigured to use hardware physical signal monitors.

[0020] In some cases, a given signal is not mapped to a corresponding physical signal. For example, in some cases, signals that are not critical to system performance, or signals that are only checked periodically in a non-polling manner, may not require a physical signal and physical monitor, and instead are executed as virtual memory objects by a virtual machine. Thus, in some embodiments, the HSM110 is configured to identify, based on map 121, when a signal operation targets a VS to which a corresponding PS has not been assigned. In response to identifying such a virtual signal, the HSM110 is configured to transfer the operation directly to a cache or device memory for execution. In some embodiments, bits in the signal object are used to indicate whether there is a monitor associated with the signal. For example, a bit value of 1 indicates that there is one or more monitors associated with the signal, and a value of 0 indicates that there are no monitors associated with the signal.

[0021] In some cases, the consequences of a particular signal operation may not affect the operation of the VM that issued the signal operation. Such operations are referred to herein as non-impact operations. The HSM110 is configured to conserve system resources by identifying non-impact operations based on the information provided when a signal is generated, and by refraining from performing the operation in accordance with the identification of non-impact operations.

[0022] Figure 2 is a block diagram showing embodiments of the HSM110 according to several embodiments. In the illustrated examples, the HSM110 includes a physical signal monitor (PSM) 222 and a PSM memory 224. The PSM memory 224 is a memory structure, such as one or more caches, higher memory, or a combination thereof, configured to store data on behalf of the PSM 222. For example, in the illustrated embodiment, the PSM memory 224 stores a set of physical signal (PS) pages 232 and a set of physical monitor (PM) pages 234.

[0023] PSM222 is a circuit configured to manage and execute signal operations for physical signals in response to signal operations received from VMs 103 and 104 via API 105. Thus, in the exemplary embodiments, PSM222 includes a physical signal assignable device interface (ADI) 225 (referred to as PS ADI225), a physical monitor ADI (PM ADI) 226, physical signals (PS) 227 (including PS115 and PS118), physical monitors 228 (including PM114 and 117), a PS-PM map 230, and a manager 235. PS ADI225 is a set of circuitry, software, firmware, or a combination thereof configured to allocate PS resources based on commands received from API 105. For example, in some embodiments, PS ADI225 is configured to assign any of the PS227 to virtual signals in response to requests from API 105, such as requests triggered when a VM requests signal assignment. Similarly, PM ADI226 is a set of circuitry, software, firmware, or a combination thereof configured to allocate PM resources based on commands received from API105. For example, in some embodiments, PM ADI226 is configured to allocate any PM227 to a virtual signal in response to a request from API105, such as a request triggered when a VM requests the allocation of a signal monitor.

[0024] The PS-PM map 230 is a data structure, such as a table, that stores the mapping of PSs to PMs. In some embodiments, the PS-PM map 230 associates all PMs with one corresponding PS, and the PS is indicated by the state of the PM monitor. In some embodiments, the PS-PM map 230 is indexed by PS, and the output of the PS-PM map 230 is a bitmask indicating which physical monitor is associated with each PS. In other embodiments, the PS-PM map 230 operates as a content-addressable memory (CAM), where each entry represents a mapping from one PS to a PM, and there may be multiple valid entries for a given PS, each entry pointing to a different PM.

[0025] The manager 235 is a circuit configured to manage the mapping of virtual signals to physical signals and thus to set the data stored in the map 121. For example, in response to a request from the API 105 to assign a PS to a VS, the manager 235 is configured to identify the PS to be assigned and store in the map 121 data indicating that the identified PS is assigned to the VS indicated by the request. In some embodiments, the number of VSs instantiated by the API 105 exceeds the number of PSs and PMs available in the HSM 110 over time. Thus, in some embodiments, the manager 235 uses a specified policy to determine which virtual signals should be mapped at any given time. In some embodiments, the manager 235 is configured to prefetch signals from the device memory to the PSM memory 224 to reduce physical signal errors. In some embodiments, the manager 235 is configured to manage the signal pages mapped to the physical device. This includes allocating new pages when the API 105 requests more signals. In some embodiments, signal page translation is tagged with special page table attributes or bits to keep the page pinned in system memory (when the page is migrated from the device to system memory) or to indicate properties regarding the signals located on the page. For example, in some embodiments, page table bits are employed to indicate that none of the signals on the page have an associated monitor.

[0026] In some embodiments, the manager 235 is configured to map a PM to a VSM in response to a request from the API 105. Similar to physical and virtual signals, in at least some cases, the number of PMs in the HSM 110 becomes less than the number of VSMs over time. Thus, in some embodiments, the manager 235 uses a specified policy to determine which VSM is mapped to a PM at a given point in time. For example, in some embodiments, the manager 235 is configured to identify when a VSM or VS is no longer being used or has not been accessed within a threshold time period. In response, the manager 235 reassigns the corresponding PM, PS, or any combination thereof to different VSMs or VSs, respectively. In some embodiments, the manager 235 is configured to limit the number of physical monitors assigned to VSMs associated with the same physical signal to prevent too many physical monitors from being assigned to one signal.

[0027] As described above, the HSM 110 is generally configured to assign PSs and PMs to VSs and VSMs, respectively. Further, in some embodiments, the number of VSs and VSMs executed over time in the CPU 102 exceeds the number of PSs and PMs in the HSM 110. Thus, the HSM 110 is configured to assign a given PS to different virtual signals at different times based on specified selection and assignment policies. Similarly, the HSM 110 is configured to assign a given PM to different virtual signal monitors at different times based on specified selection and assignment policies. Thereby, the system 100 can implement a relatively large number of virtual signals and virtual signal monitors using a relatively small number of physical signals and physical signal monitors, and thus provides scalability to the hardware signal monitors.

[0028] Figure 3 shows an example of an HSM110 that assigns physical signals to different virtual signals according to several embodiments. In the illustrated example, it is assumed that API105 executes a set of virtual signals 330 over time. For illustrative purposes, it is assumed that the set of virtual signals 330 includes two subsets of virtual signals, namely subset 331 and subset 332. Different subsets 331 and 332 represent virtual signals executed by API105 and CPU102 at different points in time. Subsets 331 and 332 are shown as partially overlapping to indicate that subsets 331 and 332 contain some of the same virtual signals, and that each contains at least one virtual signal not included in the other subset.

[0029] Figure 3 also shows a set of physical signals 333 representing all the physical signals supported by the HSM110. In the illustrated example, at a first point in time, the HSM110 assigns a subset of virtual signals 331 to the set of physical signals 333. Subsequently, based on the specified selection and assignment policy, the HSM110 assigns a subset of virtual signals 332 to the set of physical signals 333. Thus, in the illustrated example, at different points in time, the HSM110 assigns the same set of physical signals to different subsets of virtual signals executed in the CPU 102.

[0030] Figure 4 shows a flowchart of Method 400 for a system that virtualizes a set of physical signals and a physical signal monitor, according to several embodiments. Although Method 400 is described with respect to an exemplary embodiment in System 100 of Figure 1, it should be understood that in other embodiments, Method 400 is performed in a processing system having a different configuration.

[0031] In block 402, the VM (e.g., VM104) issues (sends) a signal operation for a virtual monitor associated with a virtual signal (e.g., virtual monitor virtual signal 108) by sending a command to API105. In response, API105 sends the signal operation (e.g., signal operation 113) to HSM110. In block 404, HSM110 determines whether the signal operation is for a signal that has a monitorable signal type. In some embodiments, HSM110 maintains a table of signals and signal attributes for each physical signal. The signal attributes indicate whether the corresponding signal is monitorable or not, i.e., whether the signal is of a monitorable type or a non-monitor type. If the signal operation is identified as being associated with a non-monitor signal, the method flow proceeds to block 406, where HSM110 transfers the operation to signal memory 111 for execution. For example, in some embodiments, the signal operation is a write operation to write a signal value, and the HSM110 transfers the write operation to the signal memory 111 in order to write the signal value to the memory location corresponding to the signal.

[0032] In block 404, if the signal operation is for a monitorable signal, the method flow proceeds to block 408, where the HSM110 determines whether the signal associated with the signal operation is assigned to a physical signal. Otherwise, the method flow proceeds to block 412, as described below. If the signal operation is for a signal that is not assigned a physical signal, the method flow proceeds to block 410, where the HSM110 assigns a physical signal to the virtual signal and assigns a physical monitor to the physical signal.

[0033] In block 412, the HSM110 determines whether the signal operation is a non-impact operation. If so, the method flow proceeds to block 414, where the HSM110 refrains from performing the operation, thereby saving system resources. If the signal operation is an impact operation, the method flow proceeds to block 416, where the physical monitor assigned to the physical signal performs the signal operation.

[0034] As disclosed herein, in some embodiments, the method includes, in a system, receiving a first virtual signal monitor request from a first virtual signal monitor associated with a first virtual signal, and, in response to the first virtual signal monitor request, performing a first signal operation in the system's hardware signal monitor circuit (HSM). In one embodiment, the first signal operation includes any of a load operation, a storage operation, an atomic memory operation, and a signal wait operation. In another embodiment, the method includes, in the HSM, mapping a first physical signal of the system to a first virtual signal. In yet another embodiment, the method includes, in response to receiving a second virtual signal monitor request associated with a second virtual signal, transferring the second virtual signal monitor request to memory for execution in the HSM.

[0035] In one embodiment, the forwarding includes forwarding a second virtual signal monitor request in response to the HSM determining that the second virtual signal is a non-monitored signal. In another embodiment, the method includes, in response to receiving a second virtual signal monitor request associated with the second virtual signal, postponing the execution of the second virtual signal monitor request based on the identified impact of the execution. In yet another embodiment, the HSM includes a plurality of physical signal monitors, and the method further includes assigning a first physical signal monitor from among the plurality of physical signal monitors to a first virtual signal monitor in the HSM. In yet another embodiment, the method includes reassigning the first physical signal monitor to a second virtual signal monitor in the HSM.

[0036] In some embodiments, the system includes a processor that performs a first virtual signal monitor associated with a first virtual signal, and a hardware signal monitor circuit (HSM) that performs a first signal operation in response to a first virtual signal monitor request from the first virtual signal monitor. In one embodiment, the first signal operation includes any of a load operation, a storage operation, an atomic memory operation, and a signal waiting operation. In another embodiment, the HSM maps a first physical signal of the system to a first virtual signal. In yet another embodiment, the HSM, upon receiving a second virtual signal monitor request associated with a second virtual signal, transfers the second virtual signal monitor request to memory for execution.

[0037] In one embodiment, the HSM forwards a second virtual signal monitor request in response to determining that the second virtual signal is a non-monitor signal. In another embodiment, the HSM, upon receiving a second virtual signal monitor request associated with the second virtual signal, refrains from executing the second virtual signal monitor request based on the identified impact of the execution. In yet another embodiment, the HSM includes multiple physical signal monitors, and the HSM assigns a first physical signal monitor to a first virtual signal monitor. In yet another embodiment, the HSM reassigns the first physical signal monitor to a second virtual signal monitor.

[0038] In some embodiments, the method includes instantiating a plurality of virtual signals in a system, and at a first time point, assigning a plurality of physical signals to a first subset of the plurality of virtual signals in the system's hardware signal monitor circuit (HSM). In one embodiment, the method includes, at a second time point, assigning a plurality of physical signals to a second subset of the plurality of virtual signals, the second subset being different from the first subset. In another embodiment, the method includes monitoring the plurality of physical signals in the HSM. In yet another embodiment, the method includes, in the HSM, performing signal operations on the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals.

[0039] In some embodiments, certain aspects of the technology described above are implemented by one or more processors of a processing system that executes the software. The software includes one or more sets of executable instructions, which are stored in a non-temporary computer-readable storage medium or otherwise clearly embodied. The software may also include instructions and specific data, which, when executed by one or more processors, operate the one or more processors to execute one or more aspects of the technology described above. Non-temporary computer-readable storage mediums may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, caches, random-access memory (RAM), or other non-volatile memory devices (one or more). Executable instructions stored in a non-temporary computer-readable storage medium can be implemented as source code, assembly language code, object code, or other instruction forms that can be interpreted or otherwise executed by one or more processors.

[0040] In addition to the foregoing, it should be noted that not all activities or elements described in the summary are required, and certain activities or parts of devices may not be required, and one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed does not necessarily indicate the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and variations can be made without departing from the scope of the invention as described in the claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all of these variations are intended to fall within the scope of the invention.

[0041] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and features that may give rise to or manifest any benefits, advantages, or solutions are not to be construed as essential, necessary, or indispensable features to any or all of the claims. Furthermore, the disclosed invention can be modified and implemented in different but similar ways, in ways that are obvious to those skilled in the art who are interested in the teachings of this specification; therefore, the specific embodiments described above are merely illustrative. There are no limitations to the details of the configuration or design shown herein beyond those described in the appended claims. Accordingly, the specific embodiments described above may be modified or altered, and it is clear that all such modifications are within the scope of the disclosed invention. Accordingly, the protection sought herein is described in the appended claims.

Claims

1. It is a method, In the system, receiving a first virtual signal monitor request from a first virtual signal monitor associated with a first virtual signal, This includes performing a first signal operation in the system's hardware signal monitor circuit (HSM) in response to the first virtual signal monitor request, method.

2. The first signal operation includes any of the following: load operation, memory operation, atomic memory operation, and signal waiting operation. The method according to claim 1.

3. The HSM includes mapping the first physical signal of the system to the first virtual signal, The method according to claim 1.

4. In response to receiving a second virtual signal monitor request associated with a second virtual signal, the HSM includes transferring the second virtual signal monitor request to memory for execution. The method according to claim 1.

5. The transfer includes transferring the second virtual signal monitoring request in response to the HSM determining that the second virtual signal is a non-monitoring signal. The method according to claim 4.

6. In response to receiving a second virtual signal monitor request associated with a second virtual signal, the execution of the second virtual signal monitor request is postponed based on the identified impact of the execution, The method according to claim 1.

7. The HSM includes multiple physical signal monitors, The HSM includes assigning a first physical signal monitor from among the plurality of physical signal monitors to the first virtual signal monitor. The method according to claim 1.

8. The HSM includes reassigning the first physical signal monitor to the second virtual signal monitor. The method according to claim 7.

9. It is a system, A processor that runs a first virtual signal monitor associated with a first virtual signal, The system includes a hardware signal monitor circuit (HSM) that performs a first signal operation in response to a first virtual signal monitor request from the first virtual signal monitor, system.

10. The first signal operation includes any of the following: load operation, memory operation, atomic memory operation, and signal waiting operation. The system according to claim 9.

11. The HSM maps the first physical signal of the system to the first virtual signal. The system according to claim 9.

12. Upon receiving a second virtual signal monitor request associated with a second virtual signal, the HSM transfers the second virtual signal monitor request to memory for execution. The system according to claim 9.

13. The HSM, upon determining that the second virtual signal is a non-monitoring signal, forwards a request to monitor the second virtual signal. The system according to claim 12.

14. Upon receiving a second virtual signal monitor request associated with the second virtual signal, the HSM decides to forgo the execution of the second virtual signal monitor request based on the identified impact of the execution. The system according to claim 9.

15. The HSM includes multiple physical signal monitors, The HSM is configured to assign a first physical signal monitor from among the plurality of physical signal monitors to the first virtual signal monitor. The system according to claim 9.

16. The HSM reassigns the first physical signal monitor to the second virtual signal monitor. The system according to claim 15.

17. It is a method, In the system, instantiation of multiple virtual signals, The first step includes assigning a plurality of physical signals to a first subset of the plurality of virtual signals in the hardware signal monitor circuit (HSM) of the system, method.

18. The second step involves assigning the plurality of physical signals to a second subset of the plurality of virtual signals, The second subset is different from the first subset. The method according to claim 17.

19. The HSM includes monitoring the plurality of physical signals, The method according to claim 17.

20. The HSM includes performing signal operations on the plurality of physical signals in response to signal operation requests associated with the plurality of virtual signals, The method according to claim 17.

Images