Exfoliation layer for IR laser lift-off process

Abstract

A method for processing a substrate, comprising: forming an infrared (IR) absorption separation layer on a first substrate; forming one or more layers on the IR absorption separation layer; forming a wafer stack by joining the first substrate and the second substrate at the bonding interface between one or more layers and the second substrate using a direct bonding technique; and separating the first substrate from one or more layers by irradiating the wafer stack with infrared (IR) light.

Description

Technical Field

[0001] Cross - reference to related applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 531,840, filed Aug. 10, 2023, which is hereby incorporated by reference in its entirety.

[0002] The present invention generally relates to a method of processing a substrate, and in certain embodiments, to a release layer for an infrared (IR) laser lift - off (LLO) process.

Background Art

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning layers of dielectric materials, conductive materials, and semiconductor materials on a substrate to form a network of electronic and interconnect components (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated into a monolithic structure. Efforts in scaling have significantly increased the number of transistors and other electrical components per unit area, leading to the development of three - dimensional (3D) semiconductor devices where various components are stacked on top of each other. As technology nodes continue to advance, the number of stack levels has increased. One method of 3D integration for creating such stacks for 3D semiconductor devices is wafer - to - wafer bonding, where electrical components are manufactured separately on two or more wafers, and the wafers are bonded to form a permanent bonding structure for these electrical components.

[0004] In certain manufacturing methods, after a device structure is manufactured by joining electrical components, one of the wafers used in the joining process can be delaminated from the device structure. One common technique for such delamination is mechanical back grinding, in which the carrier wafer (e.g., the top silicon wafer) is mechanically ground and removed. However, this method is costly because it consumes carrier wafers and therefore requires replacement for every delamination process. Furthermore, the mechanical back grinding method faces various problems, including, among others, environmental impacts (e.g., high water usage and sludge formation), high costs for technology insertion (e.g., carrier wafer consumption), and consumable materials for the process (e.g., grinding wheels and slurry). Importantly, mechanical grinding also inherently carries the risk of damaging the underlying semiconductor device structure. Alternative techniques for delamination include, for example, thermal dissipation, chemical dissolution, and laser ablation. [Overview of the project] [Means for solving the problem]

[0005] According to embodiments of the present invention, a method for processing a substrate includes forming an infrared (IR) absorption separation layer on a first substrate, forming one or more layers on the IR absorption separation layer, forming a wafer stack by bonding the first substrate and the second substrate at the bonding interface between one or more layers and the second substrate using a direct bonding technique, and separating the first substrate from one or more layers by irradiating the wafer stack with infrared (IR) light.

[0006] According to embodiments of the present invention, a method for processing a wafer includes forming a delamination layer stack on a first silicon (Si) wafer, the delamination layer stack comprising a conductive layer and a dielectric layer beneath the conductive layer; forming a semiconductor device structure on the delamination layer; joining a first Si wafer and a second Si wafer to form a bonded structure, the semiconductor device structure being positioned between the delamination layer stack and the second Si wafer; and scanning an infrared (IR) laser across the bonded structure to separate the first Si wafer from the bonded structure in the delamination layer stack, the IR laser being irradiated from the first Si wafer side of the bonded structure.

[0007] According to embodiments of the present invention, a method for processing a wafer includes forming a delamination layer stack on a first wafer by forming a first dielectric layer on the first wafer and forming a first conductive layer on the first dielectric layer; forming a first device array on the delamination layer stack; forming a second device array on a second wafer; and forming a bonded structure by joining the first device array and the second device array, wherein the first device array and the second device array are arranged between the delamination layer stack and the second wafer in the bonded structure; and separating the first and second wafers in the delamination layer stack by scanning an infrared (IR) laser across the bonded structure such that the separated second wafer includes the stack of the first device array and the second device array, wherein the IR laser is irradiated from the first wafer side of the bonded structure.

[0008] For a more detailed understanding of the present invention and its advantages, refer hereto to the following description, which will be interpreted in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1]This is a cross-sectional view of an exemplary carrier wafer, including a delamination layer stack and a semiconductor device stack before bonding, according to various embodiments. [Figure 2] These are cross-sectional views of exemplary device wafers before bonding, according to various embodiments. [Figure 3] This is a cross-sectional view of an exemplary bond structure after bonding a carrier wafer and a device wafer according to various embodiments. [Figure 4A] Figure 4A is a cross-sectional view of an exemplary bond structure during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bond structure according to various embodiments, showing the bond structure entering under IR laser irradiation. [Figure 4B] Figure 4B is a cross-sectional view of an exemplary bond structure during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bond structure according to various embodiments, showing the separated wafer after the IR LLO process. [Figure 5] This is a cross-sectional view of an exemplary separated wafer after an IR laser lift-off (LLO) process according to an embodiment. [Figure 6A] Figure 6A is a cross-sectional view of another exemplary bond structure during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bond structure according to a particular embodiment, showing the bond structure entering under IR laser irradiation. [Figure 6B] Figure 6B is a cross-sectional view of another exemplary bonded structure during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bonded structure according to a particular embodiment, showing the separated wafer after the IR LLO process. [Figure 7A] Figure 7A is a cross-sectional view of an exemplary carrier wafer after the IR LLO process, showing a carrier wafer with a damaged surface. [Figure 7B] Figure 7B is a cross-sectional view of an exemplary carrier wafer after the IR LLO process, showing the carrier wafer after planarization using gas cluster ion beam (GCIB) treatment. [Figure 8A] Figure 8A is a process flow diagram of an IR laser lift-off (LLO) process method according to various embodiments, showing one embodiment. [Figure 8B] Figure 8B is a process flow diagram of an IR laser lift-off (LLO) process method according to various embodiments, illustrating another embodiment. [Figure 8C] Figure 8C is a process flow diagram of an IR laser lift-off (LLO) process method according to various embodiments, and further illustrates another embodiment. [Modes for carrying out the invention]

[0010] This application relates to a method for processing substrates, and more specifically, to an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer, die, or other substrate from a bonded device structure formed by a bonding process. In semiconductor device manufacturing processes, wafer bonding / delamination can be useful for 3D integration of semiconductor devices. Typically, a carrier wafer carrying a first set of electrical components may be bonded to a device wafer carrying a second set of electrical components to form a bonded device structure, and after bonding, the carrier wafer may be separated from the bonded device structure. One promising technique for delaminating carrier wafers is the laser lift-off (LLO) process. Unlike conventional mechanical back grinding, the LLO process can be a non-contact method, thereby reducing the risk of damaging the semiconductor device structure. In a typical LLO process, laser irradiation is used to supply energy and induce physical, thermal, or chemical modification of layers within the bonded structure, causing delamination. However, layer separation at incorrect interfaces (e.g., within the device structure) in LLO remains a significant challenge. This is particularly problematic for advanced semiconductor device applications such as NAND devices, which may have numerous layers (e.g., more than 200 layers) forming thick stacks (e.g., more than 10 μm). In addition, common LLO techniques often use glass wafers as carrier wafers and employ ultraviolet (UV) laser irradiation, which also presents other problems, among others, such as electrostatic chuck damage, non-uniformity of the surface after separation, incompatibility with silicon manufacturing equipment, and impurity contamination on tools. Therefore, an improved method of LLO process that is more reliable and specifically tailored for layer separation at the target interface may be desired.

[0011] Embodiments of this application disclose a method for an infrared (IR) laser lift-off (LLO) process involving an improved delamination layer design interposed between a carrier wafer and a semiconductor device structure. In various embodiments, the IR LLO process may use a delamination layer stack comprising at least one IR reflective layer (e.g., a metal-containing layer) and at least one IR absorbing layer (e.g., a silicon-containing dielectric layer). In one exemplary embodiment, the delamination layer stack may consist of one IR reflective layer stacked below or on one IR absorbing layer. In another exemplary embodiment, the delamination layer stack may consist of multiple IR reflective layers stacked below and / or on one or more IR absorbing layers. This design of the delamination layer stack is particularly beneficial in preventing IR irradiation from reaching the underlying semiconductor device structure and thus limiting delamination to a target layer within the delamination layer stack. As a result, delamination at false interfaces can be avoided. The IR LLO process may offer various advantages over conventional methods such as mechanical back grinding. For example, it is a non-contact method that does not consume the carrier wafer and may allow the same carrier wafer to be reused across many cycles of the delamination process. The method can also be more environmentally friendly, as it involves virtually no water usage and no sludge formation, unlike mechanical or chemical mechanical planarization (CMP) processes. IR LLO processes can further eliminate costly additional steps and consumable materials. Furthermore, because IR can penetrate silicon wafers, and therefore silicon wafers can be used as carrier wafers, IR LLO processes may be superior to UV LLO processes that use glass wafers. The ability to use silicon wafers makes IR LLO processes compatible with most silicon manufacturing facilities. In addition, IR wavelengths are compatible with the properties of various thin-film materials useful in NAND applications, such as silicon dioxide and TEOS.

[0012] In various embodiments, the IR LLO process may be particularly useful in delaminating permanent bond structures formed by permanent bonding processes, which are bond structures having stable chemical bonds without the use of an adhesive layer. For example, such permanent bonds may be formed by direct (fusion) bonding or hybrid bonding processes that utilize covalent bonds to adhere opposing surfaces of a target substrate without any intermediate layer. In contrast, conventional UV LLO process methods are generally used to delaminate bond structures having a thick adhesive layer (formed by a temporary bonding process). In one example, the adhesive layer may be a polymer matrix that is reversible in adhesion or chemically degradable in response to UV irradiation. Therefore, UV LLO process methods may not be applicable to delaminating permanent bond structures, but IR LLO may be advantageously used instead. This disclosure primarily describes embodiments for delaminating such permanent bond structures. However, in other embodiments, the IR LLO method may be applicable to a variety of other bond structures, with or without the intermediate layer used in bonding.

[0013] The following describes various embodiments of a bonding / delamination process, including an IR laser lift-off (LLO) process. First, carrier wafers supporting a semiconductor device structure and device wafers receiving the semiconductor device structure from the carrier wafer are described with reference to Figures 1 and 2, according to various embodiments. Next, the bonded structure formed by the permanent bonding process is described with reference to Figure 3. For the delamination step, the IR LLO process for separating the carrier wafer from the bonded structure is described with reference to Figures 4A and 4B, 5 and 6A to 6B. An optional post-separation planarization step is described with reference to Figures 7A to 7B. Exemplary process flow diagrams are shown in Figures 8A to 8C. All figures in this disclosure are for illustrative purposes only and are not to scale, including the aspect ratio of feature parts. While this disclosure primarily describes embodiments of a bonding / delamination method using two wafers, this method can also be applied to bonded structures of any two substrates (e.g., wafers, dies, or other manufacturing / reconstruction structures).

[0014] Figure 1 shows a cross-sectional view of an exemplary carrier wafer 110, including a delamination layer stack 120 and a semiconductor device stack 130 before bonding, according to various embodiments.

[0015] In various embodiments, the carrier wafer 110 may be a silicon wafer or a silicon-on-insulator (SOI) wafer that is sufficiently transparent to infrared (IR) light of wavelengths used in the IR LLO process. In certain embodiments, the carrier wafer 110 may include silicon-germanium wafers, silicon carbide wafers, gallium arsenide wafers, gallium nitride wafers, and other compound semiconductors. In other embodiments, the carrier wafer 110 may include heterogeneous layers such as silicon-germanium-on-silicon, gallium nitride-on-silicon, and silicon-carbon-on-silicon, as well as silicon-on-silicon layers or SOI substrates. In certain embodiments, the carrier wafer 110 has a thickness of about 750 μm. In one or more embodiments, the carrier wafer 110 may have a diameter of 200 mm or 300 mm. However, the techniques described herein may be applied to support components having other dimensions, including panels, dies, and other suitable substrates of various sizes.

[0016] In various embodiments, the carrier wafer 110 can be transparent to infrared (IR) light. As will be further described below with reference to FIGS. 4A-4B, the IR light used in the IR LLO process needs to efficiently reach the release layer stack 120. In various embodiments, the IR light can be irradiated from the side of the back surface 100b of the carrier wafer 110 opposite to the side of the front surface 100a of the carrier wafer 110. Thus, the material and thickness of the carrier wafer 110 can be selected such that the IR light can substantially pass through the carrier wafer 110. For example, in one embodiment, at least 50% of the IR light can pass through the carrier wafer 110 during the IR LLO process and reach the underlying layer (e.g., the release layer stack 120), but in other embodiments, the amount of IR passing through the carrier wafer 110 may be less. Accordingly, the conditions (e.g., intensity) of the IR irradiation can be adjusted.

[0017] As shown in FIG. 1, the release layer stack 120 can be formed on the carrier wafer 110. The release layer stack 120 is designed to include a layer or stack of layers that are separated by the IR LLO process. In various embodiments, the release layer stack 120 can include at least one absorption layer 122 and at least one reflective layer 124, as shown in FIG. 1. The reflective layer 124 can be disposed on top of the absorption layer 122 of FIG. 1, with the absorption layer 122 interposed between the carrier wafer 110 and the reflective layer 124. In certain embodiments, the release layer stack 120 can include two or more absorption layers or two or more reflective layers, as will be further described below with reference to FIG. 6A.

[0018] In various embodiments, the absorption layer 122 may include a dielectric material capable of efficiently absorbing IR light. In one or more embodiments, a silicon-containing dielectric material may be used for the absorption layer 122. For example, the absorption layer 122 may include silicon oxide prepared by plasma-enhanced CVD or fluidized CVD using tetraethyl orthosilicate (TEOS) as a precursor. In one embodiment, the absorption layer 122 may be a metal-free layer. In certain embodiments, the absorption layer 122 may include SiN, SiCN, SiON, TiO, HfO, AlO, or ZrO. The absorption layer 122 may be deposited using suitable techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD), and other plasma processes and other processes. In one embodiment, the absorption layer 122 has a thickness of 5 nm to 200 nm, and in another embodiment, 50 nm to 150 nm.

[0019] In a simplified method of IR laser lift-off (LLO), only the absorption layer may be used for the release layer to induce separation of the stack structure. However, the inventors of the present application have found that such an absorption layer may need to be thick enough (e.g., more than 1 μm) to avoid unwanted IR transmission to the underlying layer. Forming a thick release layer (e.g., more than 1 μm) structure may interfere with subsequent processes or processing tools for subsequent processes, and thus may not be compatible with advanced device manufacturing processes for, for example, NAND devices. The inventors of the present application have demonstrated that various embodiments can overcome this problem by introducing at least one reflective layer, enabling a thinner absorption layer and also a thinner release layer stack that can be employed in advanced device manufacturing processes. Thus, in various embodiments, the overall thickness of the release layer stack 120 may be 500 nm or less. In one or more embodiments, the overall thickness may be 300 nm or less. Further, in certain embodiments, the release layer stack has a thickness less than half of the thickness of the semiconductor device stack 130.

[0020] Continuing to refer to Figure 1, the reflective layer 124 of the delamination layer stack 120 may include a material that substantially reflects IR light. In one or more embodiments, the materials of the reflective layer 124 and the absorbing layer 122 are selected to cause total internal reflection at the interface between these layers. In various embodiments, the reflective layer 124 may include a conductive material containing a metal. For example, the reflective layer 124 may include a pure metal, a metal alloy, a metal nitride, or a metal silicide. Examples of metallic elements used in the reflective layer 124 include, but are not limited to, W, Ti, Mo, TA, and Ru. The material of the reflective layer 124 may be selected considering IR reflectivity, cost, thermal stability, and compatibility with the manufacturing process. In certain embodiments, a conductive material that can be used in a front-end-of-line (FEOL) process may be used for the reflective layer 124. The reflective layer 124 can be deposited using appropriate techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma-enhanced CVD (PECVD), as well as other processes. In one embodiment, the reflective layer 124 has a thickness of 5 nm to 50 nm. In certain embodiments, the thickness of the reflective layer 124 may be less than the thickness of the absorption layer 122, as long as it substantially reflects incoming IR light.

[0021] In various embodiments, the entire release layer stack 120, including the absorption layer 122, the reflective layer 124, and the resulting release layer stack 120, may have high thermal stability (e.g., up to 1000°C), and the materials of these layers may be selected accordingly. The thermal stability of the release layer stack 120 is particularly advantageous in applications such as NAND device manufacturing, which require high-temperature processes (e.g., annealing at temperatures above 350°C). In one embodiment, the release layer stack 120 may be thermally stable up to 1000°C.

[0022] The delamination layer stack 120 may be designed to maximize IR absorption by one or more absorption layers and IR reflection by one or more reflection layers. Therefore, the thickness and material of each layer may be selected to maximize IR absorption / reflection performance in terms of the wavelength of IR light used in the IR LLO process.

[0023] Using a conductive material for the reflective layer 124 may be advantageous because it can mitigate charge accumulation problems during subsequent plasma etching processes, such as high aspect ratio contact (HARC) etching for NAND device manufacturing or 3D integration of devices.

[0024] In various embodiments, the carrier wafer 110 may include semiconductor devices and may have undergone several processing steps following a conventional process, for example. Thus, the carrier wafer 110 may include layers of semiconductors useful in various microelectronics. For example, as shown in Figure 1, the carrier wafer 110 may include a semiconductor device stack 130.

[0025] In various embodiments, the semiconductor device stack 130 may include a memory device structure (e.g., NAND flash memory) and is a stack of various dielectric layers, semiconductor layers, and conductive layers. The dotted lines in Figure 1 are used to show exemplary layer interfaces within the semiconductor device stack 130. Although not specifically illustrated, in one embodiment, the semiconductor device stack 130 may be patterned for a memory device. For example, the semiconductor device stack 130 may include a channel structure and a stack of alternating layers of word lines having dielectric layers separating the word lines (e.g., made of a conductive material such as tungsten).

[0026] The semiconductor device stack 130 in Figure 1 is a simplified example for illustrative purposes only. In various embodiments, the semiconductor device stack 130 may include any number of layers (e.g., more than 200 layers) to form a memory cell stack and may have any total thickness. In one embodiment, the total thickness may be 10 μm or more. The semiconductor device stack 130 may be formed directly on the carrier wafer 110 or transferred to the carrier wafer 110 from another substrate.

[0027] Figure 2 shows cross-sectional views of exemplary device wafers 210 before bonding, according to various embodiments.

[0028] In various embodiments, the device wafer 210 is a wafer from which the semiconductor device stack 130 can be transferred from a carrier wafer (e.g., carrier wafer 110 in Figure 1). The device wafer 210 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the device wafer 210 may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the device wafer 210 includes heterogeneous layers such as silicon-germanium-on-silicon, gallium nitride-on-silicon, and silicon-carbon-on-silicon, as well as a silicon-on-silicon layer or SOI substrate.

[0029] In various embodiments, the device wafer 210 may include semiconductor devices formed on or within it, and may have undergone several processing steps following, for example, a conventional process. Thus, the device wafer 210 may include layers of semiconductors useful in various microelectronics. For example, in exemplary embodiments, though not specifically shown, the device wafer 210 may include logic device structures that can be mechanically and electrically connected to the memory device structure of the carrier wafer 110 in Figure 1. In various embodiments, the carrier wafer 110 and the device wafer 210 may include different types of electrical components, which may require different types of processing with different parameters, including, among other things, different thermal budgets and material requirements. Thus, these different processes may be carried out on separate workpieces and then combined after such processing is completed. Furthermore, the carrier wafer 110 and the device wafer 210 may be obtained from different manufacturers or different facilities, enabling greater flexibility in terms of circuit design and device source.

[0030] As further shown in Figure 2, the device wafer 200 may include a dielectric layer 220. In one or more embodiments, the device wafer 210 may include a reconfigured wafer with redistribution lines, and the dielectric layer 220 may include a redistribution layer. In certain embodiments, the dielectric layer 220 may include a passivation layer to protect the underlying devices and circuits. In various embodiments, the dielectric layer 220 on the outermost surface may include the front surface 220a of the device wafer 210, and the device wafer 210 may include the back surface 220b opposite to the front surface 220a. The front surface 220a may be a bonding interface for the bonding process. In various embodiments, the dielectric layer 220 may include silicon oxide thermally grown from the silicon of the device wafer 210. In one embodiment, the dielectric layer 220 may have a thickness of 50 nm to 300 nm. In certain embodiments, conductive interconnects may be additionally provided on the front surface 220a to electrically couple a device on the device wafer 201 to a device on the carrier wafer 110 through hybrid bonding structures and techniques.

[0031] Figure 3 shows cross-sectional views of exemplary bonded structures 300 after bonding a carrier wafer and a device wafer according to various embodiments.

[0032] In various embodiments, the bonded structure 300 may be formed by bonding a carrier wafer carrying a set of electrical components to a device wafer receiving a set of electrical components. For example, a NAND flash memory cell stack may be carried by a carrier wafer and mechanically and electrically connected to logic cells on a device wafer by a bonding process. The bonding process may include various types of wafer bonding processes, such as the direct bonding or hybrid bonding described above. In particular embodiments where high-temperature annealing (e.g., above 350°C) is required, the bonding process may be based on any permanent bonding process that does not involve adhesives.

[0033] In Figure 3, the bonded structure 300 includes the carrier wafer 110 of Figure 1 bonded to the device wafer 210 of Figure 2, with the front surface 110a of the carrier wafer 110 in contact with the front surface 200a of the device wafer 210 as the bonded interface. The surfaces are bonded according to a known and otherwise documented direct bonding or hybrid bonding process. After the bonding process, the semiconductor device stack 130 is interposed between the delamination layer stack 120 and the dielectric layer 220 on the device wafer 210. In Figure 3, for illustrative purposes, the carrier wafer 110 is shown upside down compared to Figure 1.

[0034] As described above, in various embodiments, the bond between the semiconductor device stack 130 and the device wafer 210 can be permanent. Furthermore, the device wafer 210 may include a second set of electrical components (e.g., logic devices), and the bond can directly form an electrical connection between the semiconductor device stack 130 and the second set of electrical components. In other embodiments, the electrical connection can be achieved by a further manufacturing process.

[0035] Figures 4A and 4B show cross-sectional views of exemplary bonded structures 400 during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bonded structure, according to various embodiments. Figure 4A shows the bonded structure 400 entering under IR laser irradiation, and Figure 4B shows the separated wafer after the IR LLO process. The bonded structure 400 may be identical to the bonded structure 300 shown in Figure 3 and described above, so its details will not be repeated.

[0036] The IR LLO process can be carried out by exposing the junction structure 400 to IR light. In various embodiments, as shown in Figure 4A, this IR exposure can be carried out by scanning the junction structure 400 with an IR laser 410. The IR light can be in the near-infrared, mid-infrared, or far-infrared range. Various light sources can be used to generate the IR light. For example, in one embodiment, an Nd:YAG laser can be used for near-IR (wavelength of about 1060 nm). In various embodiments, the IR can have wavelengths from 2 μm to 10 μm. Generally, the absorption coefficient of silicon decreases significantly at wavelengths above 1000 nm. Therefore, it is advantageous to use longer IR wavelengths to avoid absorption by the silicon substrate (e.g., carrier wafer 110). On the other hand, the material used for the absorption layer 122, such as silicon dioxide, may have a higher absorption coefficient at the IR wavelength so that most of the irradiation is absorbed and does not pass through the absorption layer 122.

[0037] The absorbed IR can be converted into heat, which can rapidly move downward through the potentially thermally conductive reflective layer 124 and damage the sensing device region. The amount of heat absorbed within the absorption layer 122 may depend on the thickness of the absorption layer 122, the absorption coefficient of the absorption layer 122 for the specific IR wavelength being irradiated, and the irradiation parameters (e.g., intensity, scanning speed, spot size, angle, etc.). Therefore, in various embodiments, the absorption layer 122 and processing parameters are selected to avoid overheating that could damage the sensing region, such as the semiconductor device stack 130.

[0038] IR can substantially pass through the carrier wafer 110 and enter the absorption layer 122 of the delamination layer stack 120, causing delamination (separation) of the bonding structure 400. Although we do not wish to be limited by any theory, delamination can be induced by the energy of the IR absorbed by the absorption layer 122. In various embodiments, the absorbed IR may lead to thermal expansion of the absorption layer 122, thereby creating an initial delamination point within the delamination layer stack 120.

[0039] In various embodiments, the IR LLO process is a heat release-based process that can proceed without ablation of the absorption layer 122, and IR does not cause any decomposition or vaporization of the absorption layer 122.

[0040] In various embodiments, the IR laser 410 may be oriented perpendicular to the back surface 100b of the carrier wafer 110, as shown in Figure 4A. In other embodiments, the IR laser 410 may be oblique to a perpendicular line perpendicular to the back surface 100b. The incident angle of the IR laser 410 may be selected to minimize reflection at the back surface 100b and maximize reflection at the reflective layer 124.

[0041] As shown in Figure 4B, in certain embodiments, delamination may occur at the interface between the absorption layer 122 and the reflection layer 124, resulting in a delaminated carrier wafer 400a and a delaminated device wafer 400b. In other embodiments, delamination may occur at different interfaces within the delamination layer stack 120.

[0042] Figure 5 shows an exemplary cross-sectional view of a separated wafer after the IR laser lift-off (LLO) process according to an alternative embodiment.

[0043] In certain embodiments, delamination may occur on the upper surface of the delamination layer stack 120, i.e., at the interface between the carrier wafer 110 and the absorption layer 122 in Figure 5. The location of delamination may depend on the material and design used for the delamination layer stack 120 and the IR exposure conditions. In both cases shown in Figures 4B and 5, delamination occurs within or at the interface of the delamination layer stack 120 due to improved IR absorption / reflection. The design of the absorption / reflection layer stack can favorably eliminate or minimize the transmission of IR to the layers below the delamination layer stack 120 (e.g., the semiconductor device stack 130). As a result, various embodiments of the method can prevent delamination at undesirable locations, such as within the semiconductor device stack 130 (e.g., any interface indicated by the dotted line in the semiconductor device stack 130 in Figure 6B).

[0044] Figures 6A and 6B show cross-sectional views of another exemplary bond structure 600 during an infrared (IR) laser lift-off (LLO) process for separating a carrier wafer from the bond structure, according to another embodiment. Figure 6A shows the bond structure 600 entering under IR laser irradiation, and Figure 6B shows the separated wafer after the IR LLO process.

[0045] In Figure 6A, the elements of the bond structure 600 may be the same as the bond structure 300 or 400 shown in Figure 3 or Figure 4A of the previous embodiment, except that the delamination layer stack 620 includes two absorption layers (first absorption layer 622 and second absorption layer 626) and two reflection layers (first reflection layer 624 and second reflection layer 628). By having alternating layers for IR absorption and reflection, a thinner layer stack structure may be advantageously able to achieve the same IR LLO performance compared to using only a single layer for each of IR absorption and reflection.

[0046] In various embodiments, the upper part of the layer stack (e.g., the first absorption layer 622 and the first reflection layer 624 in Figure 6A) may be thinner than the lower part of the layer stack (e.g., the second absorption layer 626 and the second reflection layer 628 in Figure 6A), allowing a portion of the IR to reach the bottom of the layer stack. In certain embodiments, the first reflection layer 624 or the second reflection layer 628 may have a thickness of 5 nm to 250 nm, and the first absorption layer 622 or the second absorption layer 626 may have a thickness of 10 nm to 500 nm. In certain embodiments, pairs of absorption and reflection layers may be formed such that the reflection layer (e.g., the first or second reflection layer) is thinner than the corresponding absorption layer (e.g., the first or second absorption layer). Each of the absorption layers or each of the reflection layers may be made of the same or different materials.

[0047] The layer stack structures shown in Figures 4A and 6A (release layer stacks 120 and 620) are merely examples, and in other embodiments, other suitable layer stack designs having any number of layers may be used for the release layer stack. In one embodiment, three or more layers may be used for IR absorption and reflection, respectively. In another embodiment, two reflective layers and one absorbing layer interposed between them may be used.

[0048] Although this disclosure uses the term “exfoliation layer stack,” it is not limited to a stack of individual layers having distinct interfaces, as shown in Figures 1, 4A, and 6A. In one or more embodiments, interfaces within the exfoliation layer stack 120 may not be clearly distinguished by a particular gradient of chemical composition.

[0049] As shown in Figure 6B, in certain embodiments, delamination may occur at the interface between the carrier wafer 110 and the first absorption layer 622, resulting in a delaminated carrier wafer 600a and a delaminated device wafer 600b. In other embodiments, delamination may occur at different interfaces within the delamination layer stack 620, for example, at any of the interfaces indicated by the arrows in Figure 6B.

[0050] As described above with reference to Figures 4B, 5, and 6B, the delaminated carrier wafer may be a carrier wafer 110 with or without a residual portion of the delamination layer stack 120 (for example, the delaminated carrier wafer 400a has the absorbent layer 122 attached in Figure 4B). In any of these embodiments, the IR LLO process unimpededly separates the carrier wafer from the bonding structure and prevents delamination at any interface or layer outside the delamination layer stack 120 (e.g., within the semiconductor device stack 130). Since the IR LLO process can be advantageously carried out without consuming or damaging the carrier wafer 110, this substrate can be reused in another IR LLO process. In certain embodiments, a removal step may be performed to remove any residual layers that may be present on the carrier wafer 110 after delamination (e.g., the absorbent layer 122 in Figure 4B). Alternatively, such residual layers on the carrier wafer 110 may be more useful as part of a new delamination layer stack, thereby omitting the removal step. In one or more embodiments, the removal step may be carried out using a dry or wet etching process.

[0051] After delamination is complete, the device wafer (e.g., the delaminated device wafer 600b in Figure 6B) may be further processed by subsequent manufacturing steps. For example, in one embodiment, the device wafer may be cut into individual dies. In another embodiment, a process may be carried out to provide electrical connections between semiconductor device components.

[0052] Figures 7A and 7B show cross-sectional views of an exemplary carrier wafer 110 after the IR LLO process.

[0053] In various embodiments, after the IR LLO process is performed, the carrier wafer 110 can be recovered and reused in another cycle of the IR LLO process. In certain embodiments, as shown in Figure 7A, the IR LLO process may result in a damaged surface 100c of the carrier wafer 110, which has considerable roughness. To planarize the damaged surface 100c, an optional post-separation planarization process may be performed. In one or more embodiments, a gas cluster ion beam (GCIB) process may be used for planarization. For example, the carrier wafer 110 is scanned under a beam containing ionized gas clusters 700 (Figure 7A) to obtain a recovered flat surface 110d (Figure 7B). With the recovered flat surface 110d, the carrier wafer 110 after the optional post-separation planarization process may be available for another IR LLO process. Generally, GCIB processes use electrically accelerated clustered ions of gas atoms or molecules directed to strike a substrate as a beam, and the impact of these ions removes, modifies, or smooths the surface layer of the substrate. Due to the low energy per atom / molecule, GCIB can offer unique features in surface treatment, such as low damage, low thermal load, and lateral sputtering that allows for shallow impact and surface smoothing. In various embodiments, the gas used for GCIB treatment may include inert gases such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and nitrogen (N2), reactive gases such as O2, CO2, NH3, NF3, SF6, CF4, CHF3, or mixtures thereof. In other embodiments, other planarization techniques may be used to treat damaged surfaces.

[0054] In various embodiments, for an IR LLO process, a substrate including a bonding structure 700 may be scanned using IR, for example, by moving the substrate relative to a fixed IR laser beam. In this disclosure, “scanning” is used broadly to mean processing the substrate with a beam and is not limited to any scanning mode (e.g., moving the substrate across a fixed beam or moving the beam across a fixed substrate). The method may dynamically adjust the scanning direction and IR laser parameters (e.g., scanning speed and IR laser power) while processing the substrate.

[0055] Figures 8A to 8C show process flow diagrams of IR laser lift-off (LLO) process methods according to various embodiments. The process flow can follow the diagrams discussed above (Figures 1 to 5) and will not be described again.

[0056] In Figure 8A, process flow 80 begins by forming an IR absorption isolation layer on a first substrate (block 810, Figure 1), followed by forming one or more layers on top of the IR absorption isolation layer (block 820, Figure 1). Subsequently, the first and second substrates can be bonded at the bonding interface between one or more layers and the second substrate using direct bonding techniques to form a wafer stack (block 830, Figure 3). The wafer stack can then be exposed to IR light irradiation to separate the first substrate from one or more layers (block 840, Figures 4A-5).

[0057] In Figure 8B, process flow 82 begins by forming a delamination layer stack on a first wafer before the IR LLO process, the delamination layer stack comprising a conductive layer and a dielectric layer beneath the conductive layer (block 812, Figure 1), followed by forming a semiconductor device structure on the delamination layer (block 822, Figure 1). Next, the first and second wafers can be bonded together to form a bonded structure so that the semiconductor device structure can be positioned between the delamination layer stack and the second wafer (block 832, Figure 3). The IR LLO process can then be carried out by scanning an IR laser across the bonded structure to separate the carrier wafer from the bonded structure in the delamination layer stack, the IR laser being irradiated from the first wafer side of the bonded structure (block 842, Figures 4A-5).

[0058] In Figure 8C, process flow 84 begins by forming a delamination layer stack on a first wafer by forming a first dielectric layer on the first wafer and a first conductive layer on the first dielectric layer before the IR LLO process (block 814, Figure 1), followed by forming an array of first devices on the delamination layer stack (block 824, Figure 1). Separately, an array of second devices may be formed on a second wafer (block 816, Figure 2). The arrays of first and second devices can then be bonded together to form a bonded structure such that the arrays are positioned between the delamination layer stack and the second wafer (block 834, Figure 3). The IR LLO process may be carried out by scanning an IR laser across the bonded structure to separate the first and second wafers in the delamination layer stack so that the delaminated second wafer contains the arrays of first and second devices, with the IR laser irradiated from the first wafer side of the bonded structure (block 844, Figures 4A-4B).

[0059] As described above, by using a novel delamination layer stack design, various embodiments of the IR LLO process method can offer advantages in wafer delamination during permanent bonding / delamination processes, particularly for their effective IR absorption / reflection, non-consumption of wafers during processing (i.e., carriers can be reused), adaptable layer thickness of the delamination layer stack, and reduced environmental footprint. Thus, the method can improve the entire process of 3D integration of semiconductor devices (e.g., NAND flash memory devices) where delamination of silicon carrier wafers from permanent bonding device structures is required as an alternative to mechanical back grinding.

[0060] Herein, exemplary embodiments of the present invention are summarized. Other embodiments may also be understood from the entirety of this specification and the claims filed herein.

[0061] Example 1. A method for processing a substrate, comprising: forming an infrared (IR) absorption separation layer on a first substrate; forming one or more layers on the IR absorption separation layer; forming a wafer stack by bonding the first substrate and the second substrate at the bonding interface between one or more layers and the second substrate using a direct bonding technique; and separating the first substrate from one or more layers by irradiating the wafer stack with infrared (IR) light.

[0062] Example 2. The method according to Example 1, wherein exposure involves scanning a first substrate with an IR laser from opposite sides of one or more layers.

[0063] Example 3. The method according to Example 1 or 2, further comprising forming an IR reflective layer on top of an IR absorption separation layer before forming one or more layers.

[0064] Example 4. The method according to any one of Examples 1 to 3, wherein the IR reflective layer is conductive and contains a metal, metal silicide, or metal nitride, and the IR absorption separation layer contains silicon oxide.

[0065] Example 5. The method according to any one of Examples 1 to 4, further comprising forming a further IR reflective layer, wherein the IR absorption separation layer is disposed between the IR reflective layer and the further IR reflective layer.

[0066] Example 6. The IR reflective layer is thermally stable up to 1000°C, according to any one of Examples 1 to 5.

[0067] Example 7. A method for processing a wafer, comprising: forming a delamination layer stack on a first silicon (Si) wafer, the delamination layer stack comprising a conductive layer and a dielectric layer beneath the conductive layer; forming a semiconductor device structure on the delamination layer; forming a bond structure by bonding a first Si wafer and a second Si wafer, the semiconductor device structure being positioned between the delamination layer stack and the second Si wafer; and separating the first Si wafer from the bond structure in the delamination layer stack by scanning an infrared (IR) laser across the bond structure, the IR laser being irradiated from the side of the bond structure toward the first Si wafer.

[0068] Example 8. The method according to Example 7, wherein forming a delamination layer stack comprises carrying out a chemical vapor deposition (CVD) process to deposit silicon oxide as a dielectric layer and depositing a conductive layer on top of the dielectric layer, the conductive layer comprising a metal, a metal silicide or a metal nitride.

[0069] Example 9. The method according to Example 7 or 8, further comprising depositing another dielectric layer on top of a conductive layer to form a delamination layer stack.

[0070] Example 10. The method according to any one of Examples 7 to 9, further comprising depositing another conductive layer on top of another dielectric layer to form a delamination layer stack.

[0071] Example 11. The method according to any one of Examples 7 to 10, wherein the semiconductor device structure includes a plurality of patterned and electrically interconnected electrical components.

[0072] Example 12. The method according to any one of Examples 7 to 11, wherein the first Si wafer is separated at the interface between the conductive layer and the dielectric layer, or the first Si wafer is separated at the interface between the dielectric layer and the first Si wafer.

[0073] Example 13. A method for processing a wafer, comprising: forming a delamination layer stack on a first wafer by forming a first dielectric layer on a first wafer and forming a first conductive layer on the first dielectric layer; forming a first device array on the delamination layer stack; forming a second device array on a second wafer; and forming a bonded structure by joining the first device array and the second device array, wherein the first device array and the second device array are positioned between the delamination layer stack and the second wafer in the bonded structure; and separating the first and second wafers in the delamination layer stack by scanning an infrared (IR) laser across the bonded structure such that the separated second wafer includes the stack of the first device array and the second device array, wherein the IR laser is irradiated from the first wafer side of the bonded structure.

[0074] Example 14. The IR laser has a wavelength of 2 μm to 10 μm, as described in Example 13.

[0075] Example 15. The method according to Example 13 or 14, wherein the first conductive layer comprises a metal, a metal silicide, or a metal nitride, and the method further comprises selecting the thickness of the first conductive layer so as to prevent an IR laser from being transmitted through the first conductive layer from the first dielectric layer to the array of the first device.

[0076] Example 16. The method according to any one of Examples 13 to 15, wherein the first dielectric layer contains silicon and the thickness of the first dielectric layer is 5 nm to 200 nm.

[0077] Example 17. The method according to any one of Examples 13 to 16, wherein the release layer stack has a thickness of less than half the thickness of the array of the first device.

[0078] Example 18. The method according to any one of Examples 13 to 17, wherein the array of the first device is electrically connected to the circuit elements of the array of the second device after bonding.

[0079] Example 19. The method according to any one of Examples 13 to 18, wherein the first device array includes memory device components and the second device array includes logic device components, and the bonding includes a hybrid bonding process for forming an electrical connection between the memory device components and the logic device components.

[0080] Example 20. The method according to any one of Examples 13 to 19, further comprising performing another bonding process using the first wafer after separation.

[0081] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. By reference to this specification, various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art. For example, the embodiments shown in Figures 1 to 7C may be combined with each other in further embodiments. Therefore, the appended claims are intended to encompass any such modifications or embodiments.

Claims

1. A method for processing a substrate, Forming an infrared (IR) absorption separation layer on the first substrate, Forming an IR reflective layer on the aforementioned IR absorption separation layer, Forming one or more layers on the aforementioned IR absorption separation layer, A wafer stack is formed by joining the first substrate and the second substrate at the bonding interface between one or more layers and the second substrate using direct bonding technology. The wafer stack is exposed to infrared (IR) light irradiation having a wavelength greater than 2 μm to separate the first substrate from one or more layers. A method comprising, wherein the IR absorption separation layer includes a metal-free layer.

2. The method according to claim 1, wherein the exposure includes scanning the first substrate with an IR laser from opposite sides of the one or more layers.

3. The method according to claim 1, wherein the IR absorption separation layer comprises at least one of silicon dioxide or SiCN.

4. The method according to claim 1, wherein the IR reflective layer is conductive and comprises at least one of a metal silicide, a metal nitride, or a metal oxide.

5. The method according to claim 3, further comprising forming a further IR reflective layer, wherein the IR absorption separation layer is disposed between the IR reflective layer and the further IR reflective layer.

6. The method according to claim 3, wherein the IR reflective layer is thermally stable up to 1000°C.

7. A method for processing wafers, The method involves forming a release layer stack on a first silicon (Si) wafer, wherein the release layer stack comprises a conductive layer and a metal-free dielectric layer located beneath the conductive layer, and the conductive layer comprises at least one of a metal silicide, a metal nitride, or a metal oxide. Forming the structure of a semiconductor device on the aforementioned delamination layer, The first Si wafer and the second Si wafer are joined together to form a bonded structure, wherein the semiconductor device structure is formed to be placed between the delamination layer stack and the second Si wafer. The separation of the first Si wafer in the delamination layer stack is achieved by scanning the bonding structure with an infrared (IR) laser having a wavelength greater than 2 μm, wherein the IR laser is irradiated from the side of the bonding structure where the first Si wafer is located. A method that includes this.

8. A method for processing wafers, A first dielectric layer containing a metal-free oxide is formed on a first wafer, and a first conductive layer is formed on the first dielectric layer, thereby forming a release layer stack on the first wafer, wherein the release layer stack includes a SiCN layer. The first wafer is bonded to the second wafer to form a bonded structure, The separation of the first and second wafers in the delamination layer stack is achieved by scanning the bonding structure with an infrared (IR) laser having a wavelength greater than 2 μm, wherein the IR laser is irradiated from the side of the bonding structure toward the first wafer. A method comprising the IR creating an initial delamination point within the delamination layer stack.

9. The method according to claim 8, wherein the IR laser has a wavelength of 2.5 μm to 10 μm.

10. The method according to claim 8, wherein the first conductive layer comprises a metal, a metal silicide, or a metal nitride, and the method further comprises selecting the thickness of the first conductive layer such that the IR laser is prevented from passing through the first conductive layer to the array of the first device through the first conductive layer.

11. The method according to claim 8, wherein the first dielectric layer comprises silicon, and forming the first dielectric layer involves carrying out a chemical vapor deposition (CVD) process using tetraethyl orthosilicate (TEOS) as a precursor.

12. The method according to claim 8, wherein the delamination layer stack has a thickness of less than half the thickness of the array of the first device.

13. The method according to claim 8, wherein the array of the first device is electrically connected to the circuit elements of the array of the second device after the joining.

14. The method according to claim 8, wherein the array of first devices includes memory device components, and the array of second devices includes logic device components, and the bonding includes a hybrid bonding process for forming an electrical connection between the memory device components and the logic device components.

15. The method according to claim 8, further comprising performing another bonding process using the first wafer after the separation.

16. The first substrate and The second circuit board, One or more layers between the first substrate and the second substrate and A bonding structure comprising, the one or more layers, The first absorption layer on the first substrate, The second absorption layer between the first absorption layer and the second substrate A junction structure comprising, wherein the first absorption layer is a layer of silicon carbon nitride, and the second absorption layer is a layer of silicon dioxide deposited using tetraethyl orthosilicate (TEOS) as a precursor in a gas-phase deposition process.

17. The bonding structure according to claim 16, wherein the one or more layers include a first reflective layer between the first absorbing layer and the second absorbing layer, and the first reflective layer is conductive.

18. The bonding structure according to claim 17, wherein the one or more layers include a second reflective layer between the second absorption layer and the second substrate, and the first reflective layer and the second reflective layer each include at least one of a metal silicide, a metal nitride, or a metal oxide.

19. The bonding structure according to claim 18, wherein the first reflective layer and the second reflective layer are made of the same material.

20. The bonding structure according to claim 16, wherein both the first substrate and the second substrate are silicon substrates, and the vapor deposition process includes chemical vapor deposition.

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