Scanning drive circuit, scanning drive method, and display device

Abstract

In the scanning drive circuit, scanning drive method, and display device, the pull-up unit (102) is provided with a first switch unit (T1) and a second switch unit (T2). The control terminal of the first switch unit (T1) is connected to the second output terminal (P) of the logic control unit (101), the first terminal is connected to a voltage signal source, and the second terminal is connected to a first node (N1). The first switch unit (T1) is turned on when the second output terminal (P) of the logic control unit (101) is at a high level. The control terminal of the second switch unit (T2) is connected to a third node (N3), the first terminal is connected to a second node (N2), and the second terminal is connected to the second output terminal (P) of the logic control unit (101). The second switch unit (T2) is turned on when the clock signal is at a high level. A preset level signal, which is less than the high level of the clock signal and greater than the low level of the clock signal, is provided to the first terminal of the first switch unit (T1) via a voltage signal source. The preset level signal (VM) is used to pre-raise the level of the first node (N1), thereby improving the problem of insufficient effective charging time for the scanning transistor (S-TFT) due to level switching delay, and at the same time reducing the effects of potential coupling due to parasitic capacitance.

Description

Technical Field

[0001] The disclosure of the present application claims the priority of the Chinese patent application with the application number 2023111346695 and the title "Scanning Drive Circuit, Scanning Drive Method and Display Device" filed on September 5, 2023, and all the contents of this Chinese patent application are incorporated into the text by reference.

[0002] The present application relates to the field of display technology, and particularly to a scanning drive circuit, a scanning drive method and a display device.

Background Art

[0003] The scanning signal is used as an input signal of the pixel unit to control the on / off state of the scanning transistor corresponding to each pixel unit. When the scanning transistor of a certain row is turned on, a data voltage acts on the pixel units of that row, and the display of a specific screen can be realized. However, when the scanning signal switches from the low level VSS to the high level VDD, there is a switching delay, so the effective charging time of the scanning transistor is insufficient, which affects the screen display effect.

Summary of the Invention

[0004] The present application provides a scanning drive circuit, a scanning drive method and a display device.

[0005] According to an aspect of an embodiment of the present application, a scanning drive circuit including a plurality of scanning drive modules is disclosed. The scanning drive module includes a logic control unit, a pull-up unit, and a pull-down unit. The pull-down unit is connected to the first output end of the logic control unit and a first node.

[0006] The pull-up unit includes a pull-up switch unit, a bootstrap capacitor, a first switch unit, and a second switch unit, wherein the control terminal of the pull-up switch unit is connected to a second node, the first terminal of the pull-up switch unit is connected to a third node, the third node is configured to receive a clock signal, and the second terminal of the pull-up switch unit is connected to the first node. One end of the bootstrap capacitor is connected to the first node, and the other end is connected to the second node. The control terminal of the first switch unit is connected to a second output terminal of the logic control unit, the first terminal of the first switch unit is connected to a voltage signal source, the voltage signal source is used to provide a preset level signal, the preset level signal is less than the high level of the clock signal and greater than the low level of the clock signal, and the second terminal of the first switch unit is connected to the first node. The control terminal of the second switch unit is connected to a third node, the first terminal of the second switch unit is connected to a second node, and the second terminal of the second switch unit is connected to a second output terminal of the logic control unit.

[0007] The first switch unit is configured to turn on when the second output terminal of the logic control unit is at a high level and to raise the potential of the first node to the preset level signal, and the second switch unit is configured to turn on when the clock signal is at a high level and to raise the potential of the first node to the high level of the clock signal.

[0008] In the scan drive circuit disclosed herein, the pull-up unit includes a first switch unit and a second switch unit. The control terminal of the first switch unit is connected to the second output terminal of a logic control unit, the first terminal is connected to a voltage signal source, and the second terminal is connected to a first node. The first switch unit is turned on when the second output terminal of the logic control unit is at a high level. The control terminal of the second switch unit is connected to a third node, the first terminal is connected to a second node, and the second terminal is connected to the second output terminal of the logic control unit. The second switch unit is turned on when the clock signal is at a high level. A preset level signal, smaller than the high level of the clock signal and larger than the low level of the clock signal, is provided to the first terminal of the first switch unit via a voltage signal source. By using the preset level signal to pre-raise the level of the first node, the voltage difference between the level of the first node and the high level of the clock signal can be reduced. This improves the problem of insufficient effective charging time for the scanning transistor due to level switching delay when the scanning signal of the first node needs to be switched to the high level of the clock signal. At the same time, it reduces the effect of potential coupling to other nodes due to parasitic capacitance and improves the screen display effect.

[0009] According to one embodiment of the present invention, a scanning drive method used in the aforementioned scanning drive circuit is disclosed, the scanning drive method including the step of causing the voltage signal source to output a preset level signal to the first terminal of the first switch unit when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level.

[0010] The technical solutions provided by the embodiments of this application include at least the following beneficial effects:

[0011] In the scanning drive method disclosed in this application, when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source causes the first terminal of the first switch unit to output a preset level signal, thereby reducing the voltage difference between the level of the first node and the high level of the clock signal before the high level of the clock signal arrives. This improves the problem of insufficient effective charging time for the scanning transistor due to level switching delay, and at the same time reduces the influence of potential coupling to other nodes due to parasitic capacitance, thereby improving the screen display effect.

[0012] Please understand that the general explanation above and the detailed explanation below are illustrative only and do not limit the scope of this application. [Brief explanation of the drawing]

[0013] Herein, the attached drawings are incorporated into the specification and constitute part of this specification, illustrating embodiments consistent with the present application and are used together with the specification to interpret the principles of the present application. [Figure 1] A schematic diagram of the OLED display configuration is shown. [Figure 2] The circuit diagram of a conventional scanning drive circuit is shown. [Figure 3] The waveform diagram of a conventional scanning drive circuit is shown. [Figure 4] A schematic diagram of the pixel unit's circuitry is shown. [Figure 5] A schematic diagram of a scanning drive circuit provided according to one embodiment of the present invention is shown. [Figure 6] A schematic diagram of the drive waveform of a scanning drive circuit according to one embodiment of the present invention is shown. [Figure 7] A schematic comparison of voltage fluctuations during level switching using the present invention and the prior art is shown. [Figure 8] A schematic diagram of the configuration structure of a display device provided according to one embodiment of the present invention is shown. [Modes for carrying out the invention]

[0014] Next, exemplary embodiments will be described in full with reference to the drawings. However, exemplary embodiments can be carried out in various forms and should not be understood as being limited to the examples described herein. Rather, these exemplary embodiments are provided to make the description of the present application more comprehensive and complete and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0015] In the description of this application, "multiple" means two or more unless otherwise specified.

[0016] Furthermore, the terms “first,” “second,” and “third” are used solely for descriptive purposes and should not be understood as indicating or implying relative importance or the quantity of the technical features being described. Therefore, features limited to “first,” “second,” and “third” may explicitly or implicitly include one or more features.

[0017] OLED (Organic Light-Emitting Diode) displays have a fast response speed, a wide viewing angle, and can generate brightness with high luminous efficiency. An OLED includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode and cathode electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a driving voltage is applied to the anode and cathode electrodes, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the emissive layer (EML), generating excitons, and visible light is generated in the emissive layer (EML).

[0018] As shown in Figure 1, the structure of an OLED display generally includes a display panel and a driving circuit. The display panel is provided with pixel units (R, G, B) and necessary wiring. The driving circuit includes a timing controller 20 (i.e., TCON), a scanning driving circuit, a data driving circuit 30, and a power supply circuit 40. The scanning driving circuit is used to output a scanning signal, which is used as an input signal to the pixel units to control the on / off state of the scanning transistors corresponding to each pixel unit. When the scanning transistors of a row are turned on, a data voltage is applied to the pixel units of that row, enabling screen display.

[0019] The structure of a typical scan drive circuit, as shown in Figure 2, includes a logic control section and an output section. The logic control section receives a trigger signal IN (i.e., the scan signal) and uses it to output a corresponding high-level or low-level signal to the output section based on the received trigger signal. The output section includes a pull-up circuit and a pull-down circuit. The pull-up circuit consists of a pull-up transistor M1 and a bootstrap capacitor C. The output terminal of the pull-up transistor M1 acts as a scan signal output node, and its output state can be switched between the low-level VSS of the clock signal CK and the high-level VDD of the clock signal CK. The pull-down circuit consists of a pull-down transistor M2.

[0020] However, when the scanning signal switches from low-level VSS to high-level VDD, a switching delay exists, resulting in insufficient effective charging time for the scanning transistor S-TFT (shown in Figure 4). This leads to insufficient conduction of the scanning transistor S-TFT, preventing the data voltage VData from being fully written, which can affect display brightness. Simultaneously, it can also affect the potential of other nodes via parasitic capacitance C'. For example, it can affect the gate-drain potential of the scanning transistor S-TFT and the drain-source potential of the driving transistor D-TFT. This negatively impacts the display screen effect.

[0021] To solve the above problems, an embodiment of the present application provides a scanning drive circuit. The scanning drive circuit includes a plurality of scanning drive modules 10, and each scanning drive module 10 is used to drive a row of pixel units. As shown in FIG. 5, the scanning drive module 10 includes a logic control unit 101 and an output unit.

[0022] The logic control unit 101 is used to receive a scanning signal and output a corresponding high-level signal or low-level signal based on the received scanning signal. The logic control unit 101 has a first output terminal Q and a second output terminal P, and the output levels of the first output terminal Q and the second output terminal P are opposite. When the output of the first output terminal Q is at a low level, the output of the second output terminal P is at a high level, so that the output node of the scanning signal of the output unit becomes a high level, and the scanning transistor of the corresponding row is turned on. When the output of the first output terminal Q is at a high level, the output of the second output terminal P is at a low level, so that the output node of the scanning signal of the output unit becomes a low level, and the scanning transistor of the corresponding row is turned off.

[0023] A plurality of scanning drive modules 10 are connected in cascade, and the logic control unit 101 of at least some of the scanning drive modules 10 outputs a low-level signal or a high-level signal corresponding to the second output terminal P based on the scanning signal of the previous-stage scanning drive module 10, and outputs a low-level signal or a high-level signal corresponding to the first output terminal Q based on the scanning signal of the next-stage scanning drive module 10. Exemplarily, before the scanning signal of the previous-stage scanning drive module 10 (here, it refers to a high-level scanning signal) arrives, the output of the second output terminal P of the logic control unit 101 is at a low level, and the output of the first output terminal Q is at a high level. At this time, the scanning transistors of the row corresponding to the current scanning drive module 10 are turned off. When the scanning signal of the previous-stage scanning drive module 10 (here, it refers to a high-level scanning signal) arrives, the potentials of the second output terminal P and the first output terminal Q of the logic control unit 101 are inverted, the output of the second output terminal P of the logic control unit 101 is at a high level, and the output of the first output terminal Q is at a low level. At this time, the scanning transistors of the row corresponding to the current scanning drive module 10 are turned on. When the scanning signal of the next-stage scanning drive module 10 (here, it refers to a high-level scanning signal) arrives, the potentials of the second output terminal P and the first output terminal Q of the logic control unit 101 are inverted again, the output of the second output terminal P of the logic control unit 101 is at a low level, and the output of the first output terminal Q is at a high level. At this time, the scanning transistors of the row corresponding to the current scanning drive module 10 are turned off.

[0024] The logic control unit 101 may also include a first input terminal (not shown) and a second input terminal (not shown). The first input terminal may be an output node of a scanning signal connected to the next-stage scanning drive module 10, and the second input terminal may be an output node of a scanning signal connected to the preceding-stage scanning drive module 10. When the second input terminal receives a high-level scanning signal from the preceding-stage scanning drive module 10, the output of the second output terminal P of the logic control unit 101 is high level, and the output of the first output terminal Q is low level. When the first input terminal receives a high-level scanning signal from the next-stage scanning drive module 10, the output of the first output terminal Q of the logic control unit 101 is high level, and the output of the second output terminal P is low level.

[0025] In the first stage, the scanning drive module 10 may have a second input terminal connected to a timing controller. The second input terminal receives a trigger signal output from the timing controller and outputs a high-level scanning signal to turn on the scanning transistor of the corresponding row. In the last stage, the scanning drive module 10 may be connected to a redundant scanning drive module to turn off the scanning transistor of the last row.

[0026] Here, the logic control unit 101 may adopt any conventional logic control unit structure as long as it can realize the present invention, and the specific configuration structure of the logic control unit 101 will not be described in further detail here.

[0027] In the above-described embodiment, a plurality of scanning drive modules 10 are cascaded, and the logic control unit 101 outputs a corresponding low-level signal or high-level signal based on the scanning signals of the preceding scanning drive module 10 and the subsequent scanning drive module 10. This is merely an exemplary embodiment of the present invention and is not limited to this in actual implementation.

[0028] Referring to Figure 5, the output unit includes a pull-up unit 102 and a pull-down unit 103.

[0029] Here, the pull-up unit 102 includes a pull-up switch unit M1, a bootstrap capacitor C, a first switch unit T1 and a second switch unit T2, and includes a first node N1, a second node N2 and a third node N3. Here, the first node N1 outputs a scan signal Scan as a scan signal output node of the scan drive module 10. The third node N3 is configured to receive a clock signal CK as a clock signal input node.

[0030] The pull-up switch unit M1 has a control terminal, a first terminal, and a second terminal, where the control terminal of the pull-up switch unit M1 is connected to the second node N2, the first terminal of the pull-up switch unit M1 is connected to the third node N3, and the second terminal of the pull-up switch unit M1 is connected to the first node N1. When the pull-up switch unit M1 is sufficiently turned on, the potential of the first node N1 becomes equal to the potential of the third node N3, that is, the potential of the first node N1 becomes equal to the high potential of the clock signal, and at this time the scanning drive module 10 outputs a high-potential scanning signal VDD.

[0031] In this embodiment, the pull-up switch unit M1 is a pull-up transistor, the control terminal corresponds to the gate of the pull-up transistor, and the first and second terminals correspond to the source and drain of the pull-up transistor, respectively. The pull-up transistor is preferably a MOS transistor, which has strong interference immunity, low power consumption, and a simple control method.

[0032] In one embodiment, the pull-up switch unit M1 is a thin-film transistor, which has a fast response time, low power consumption, and helps to achieve a good image display effect.

[0033] Selectively, the pull-up switch unit M1 may be another form of switch unit.

[0034] The first switch unit T1 comprises a control terminal, a first terminal, and a second terminal, where the control terminal of the first switch unit T1 is connected to the second output terminal P of the logic control unit 101, the first terminal of the first switch unit T1 is connected to a voltage signal source, and the second terminal of the first switch unit T1 is connected to the first node N1. Here, the voltage signal source is used to provide a preset level signal VM, which is less than the high level VDD of the clock signal CK and greater than the low level VSS of the clock signal CK. The first switch unit T1 turns on when the second output terminal P of the logic control unit 101 is high, raising the potential of the first node N1 to the preset level signal VM, and turns off when the second output terminal P of the logic control unit 101 is low, so that the preset level signal VM cannot be output to the first node N1 via the first switch unit T1.

[0035] In this embodiment, the first switch unit T1 is a transistor, the control terminal corresponds to the gate of the transistor, and the first and second terminals correspond to the source and drain of the transistor, respectively. The transistor is preferably a MOS transistor, which has strong interference immunity, low power consumption, and a simple control method.

[0036] In one embodiment, the first switch unit T1 is a thin-film transistor, which has a fast response time, low power consumption, and helps to achieve a good screen display effect.

[0037] Selectively, the first switch unit T1 may be another form of switch unit.

[0038] In this embodiment, the preset level signal VM is smaller than the on-voltage of the scanning transistor in the pixel unit, and the control terminal of the scanning transistor is connected to the first node N1. By setting the preset level signal VM to be smaller than the on-voltage of the scanning transistor in the pixel unit, the preset level signal VM pre-turns on the scanning transistor in the pixel unit, thus preventing abnormal screen display.

[0039] In some embodiments, other mechanisms may be provided to prevent the scanning transistor in the pixel unit from being pre-turned on, in which case the preset level signal VM can be greater than or equal to the on-voltage of the scanning transistor in the pixel unit.

[0040] Selectively, the preset level signal VM may be a fixed level signal, and when the first switch unit T1 is turned on, the potential of the first node N1 is raised to that fixed level.

[0041] Selectively, the preset level signal VM may be a level signal containing multiple different amplitudes. For example, the preset level signal VM may include a first level signal and a second level signal greater than the first level signal, and correspondingly, the period during which the second output terminal P of the logic control unit 101 is high level and the clock signal CK is low level includes a first period and a second period later than the first period, and the voltage signal source is configured to provide the first level signal during the first period and the second level signal during the second period. As another example, the preset level signal VM includes a first level signal, a second level signal, and a third level signal, where the amplitudes of the first, second, and third level signals increase in sequence, and correspondingly, the period during which the second output terminal P of the logic control unit 101 is high level and the clock signal CK is low level includes a first period, a second period, and a third period, where the times corresponding to the first, second, and third periods are sequentially located, and the voltage signal source is configured to provide the first level signal in the first period, the second level signal in the second period, and the third level signal in the third period. This installation method allows the potential of the first node N1 to be raised in steps.

[0042] In one embodiment, the voltage signal source is a timing controller, which outputs a preset level signal VM via the idle output channel of the timing controller, eliminating the need to add any additional electronic devices. Of course, the voltage signal source may be a separately provided voltage source.

[0043] The second switch unit T2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second switch unit T2 is connected to the third node N3, the first terminal of the second switch unit T2 is connected to the second node N2, and the second terminal of the second switch unit T2 is connected to the second output terminal P of the logic control unit 101. When the clock signal CK is at a high level, the second switch unit T2 turns on, the pull-up switch unit M1 turns on, and the potential of the first node N1 is raised to the high level VDD of the clock signal CK. When the clock signal CK is at a low level, the second switch unit T2 turns off, the pull-up switch unit M1 turns off, and the high level VDD of the clock signal CK cannot be output to the first node N1 via the pull-up switch unit M1.

[0044] In this embodiment, the second switch unit T2 is a transistor, with the control terminal corresponding to the gate of the transistor and the first and second terminals corresponding to the source and drain of the transistor, respectively. The transistor is preferably a MOS transistor, which has strong interference immunity, low power consumption, and a simple control method.

[0045] In one embodiment, the second switch unit T2 is a thin-film transistor, which has a fast response time, low power consumption, and helps to achieve a good screen display effect.

[0046] Selectively, the second switch unit T2 may be another form of switch unit. One end of the bootstrap capacitor C is connected to the first node N1, and the other end is connected to the second node N2.

[0047] Referring to Figure 5, the pull-down unit 103 is connected to the first output terminal Q of the logic control unit 101 and the first node N1, and is used to lower the potential of the first node N1.

[0048] In this embodiment, the pull-down unit 103 includes a pull-down switch unit M2, which has a control terminal, a first terminal, and a second terminal. The control terminal of the pull-down switch unit M2 is connected to the first output terminal Q of the logic control unit 101, the first terminal of the pull-down switch unit M2 is connected to the first node N1, and the second terminal of the pull-down switch unit M2 is connected to the common ground terminal, i.e., VSS. When the output of the first output terminal Q of the logic control unit 101 is at a high level, the pull-down switch unit M2 turns on, pulling down the level of the first node N1 to the level of the common ground terminal, i.e., lowering the level of the first node N1 to the low level VSS of the clock signal.

[0049] In this embodiment, the pull-down switch unit M2 is a pull-down transistor, the control terminal corresponds to the gate of the pull-down transistor, and the first and second terminals correspond to the source and drain of the pull-down transistor, respectively. The pull-down transistor is preferably a MOS transistor, which has strong interference immunity, low power consumption, and a simple control method.

[0050] In one embodiment, the pull-down switch unit M2 is a thin-film transistor, which has a fast response time, low power consumption, and helps to achieve a good screen display effect.

[0051] Selectively, the pull-down switch unit M2 may be another form of switch unit.

[0052] Next, the operating principle of the pull-up unit 102 will be explained with reference to Figures 5 and 6:

[0053] At time t0, the second output terminal P is at a low level VSS, the first switch unit T1 is off, the preset level signal VM is not output to the first node N1 via the first switch unit T1, and the first node N1 is at a low level; therefore, the scan signal Scan is at a low level VSS. At time t1, the second output terminal P is at a high level V1, the clock signal CK is at a low level VSS, the first switch unit T1 is on, the second switch unit T2 is off, and the preset level signal VM is output to the first node N1 via the first switch unit T1; therefore, the scan signal Scan is at a preset level VM. At time t2, the second output terminal P is still at a high level, and the clock signal CK is also at a high level. The first switch unit T1, the second switch unit T2, and the pull-up switch unit M1 are all turned on, and due to the action of the bootstrap capacitor C, the second output terminal P is pulled up to an even higher level V2. At this time, the pull-up switch unit M1 can be sufficiently turned on, and the first and second terminals of the pull-up switch unit M1 can reach the same potential. Therefore, the first node N1 is the high level VDD of the clock signal CK, and the scan signal Scan is the high level VDD of the clock signal CK. At time t3, the second output terminal P is at a low level VSS, and the clock signal CK is at a low level VSS. The potential of the first node N1 is lowered to a low level VSS by the pull-down unit 103.

[0054] In actual implementation, if it is necessary to raise the potential of the first node N1 to the preset level signal VM, it is preferable to place the clock signal CK at a low level VSS so that the second switch unit T2 does not turn on beforehand. That is, when the clock signal CK is at a low level VSS and the second output terminal P is at a high level, the first switch unit T1 turns on, and the preset level signal VM is output to the first node N1 via the first switch unit T1. When the clock signal CK is at a high level VSS and the second output terminal P is at a high level, the first switch unit T1 and the second switch unit T2 are set to ON, and the pull-up switch unit M1 is turned on so that the high level VDD of the clock signal CK is output to the first node N1, and the scan signal Scan is the high level VDD of the clock signal CK.

[0055] In summary, the scanning drive circuit disclosed herein includes a pull-up unit 102 with a first switch unit T1 and a second switch unit T2. The control terminal of the first switch unit T1 is connected to the second output terminal P of the logic control unit 101, the first terminal is connected to a voltage signal source, and the second terminal is connected to the first node N1. When the second output terminal P of the logic control unit 101 is at a high level, the first switch unit T1 is turned on. The control terminal of the second switch unit T2 is connected to the third node N3, the first terminal is connected to the second node N2, and the second terminal is connected to the second output terminal P of the logic control unit 101. When the clock signal CK is at a high level VDD, the second switch unit T2 is turned on. Before the rising edge of the clock signal CK arrives, a preset level signal VM, smaller than the high level VDD of the clock signal CK and larger than the low level VSS of the clock signal CK, is first provided to the first terminal of the first switch unit T1 via a voltage signal source. The preset level signal VM is used to pre-raise the level of the first node N1, reducing the voltage difference between the level of the first node N1 and the high level VDD of the clock signal CK. As shown in Figure 7, the voltage difference ΔV between the level of the first node N1 and the high level VDD of the clock signal CK in this application is smaller than the voltage difference ΔV' corresponding to the scanning drive circuit shown in Figure 2. When the rising edge of the clock signal CK arrives, the level of the first node N1 only needs to be pulled up from the preset level signal VM to the high level VDD of the clock signal CK. Because the level change range of the first node N1 is small, the effect of potential coupling to other nodes due to parasitic capacitance can be reduced. At the same time, the problem of insufficient effective charging time of the scanning transistor due to level switching delay is also improved, improving the image display effect.

[0056] The present invention further provides a scanning drive method that can be applied to any of the scanning drive circuits of the above-described embodiments. The scanning drive method includes the step of causing a voltage signal source to output a preset level signal to the first terminal of a first switch unit when the second output terminal of a logic control unit is at a high level and the clock signal is at a low level.

[0057] In one embodiment, the preset level signal is a fixed level signal, and when the second output terminal of the logic control unit is high level and the clock signal is low level, the voltage signal source outputs one preset level signal to the first terminal of the first switch unit.

[0058] In one embodiment, the preset level signal is a level signal containing two different amplitudes, and correspondingly, the period during which the second output terminal of the logic control unit is high and the clock signal is low includes a first period and a second period that is slower than the first period. When the second output terminal of the logic control unit is high and the clock signal is low, during the first period, the voltage signal source outputs a first level signal to the first terminal of the first switch unit, and during the second period, the voltage signal source outputs a second level signal to the first terminal of the first switch unit.

[0059] In one embodiment, the preset level signal is a level signal containing three different amplitudes, and correspondingly, the period during which the second output terminal of the logic control unit is high and the clock signal is low includes a first period, a second period later than the first period, and a third period later than the second period. When the second output terminal of the logic control unit is high and the clock signal is low, in the first period, the voltage signal source is caused to output a first level signal to the first terminal of the first switch unit; in the second period, the voltage signal source is caused to output a second level signal to the first terminal of the first switch unit; and in the third period, the voltage signal source is caused to output a third level signal to the first terminal of the first switch unit.

[0060] By using a preset level signal to raise the level of the first node in advance, the voltage difference between the level of the first node and the high level of the clock signal is reduced. When the rising edge of the clock signal arrives, the level of the first node only needs to be pulled up from the preset level signal to the high level of the clock signal. Because the level change of the first node is small, the influence of potential coupling to other nodes due to parasitic capacitance can be reduced. At the same time, the problem of insufficient effective charging time for the scanning transistor due to level switching delay is improved, resulting in improved screen display performance.

[0061] Next, referring to Figure 8, the present invention further provides a display device including a drive circuit 100 and a display panel 200. The drive circuit 100 is connected to the display panel 200 and drives the display panel 200 to display a screen.

[0062] The display panel 200 includes a plurality of pixel units, which are arranged in an array to form a pixel unit array. Here, each pixel unit includes a scanning transistor S-TFT, a driving transistor D-TFT, a first capacitor Cst, and a sub-pixel OLED.

[0063] The control terminal of the scanning transistor S-TFT is connected to the row line, i.e., to the first node N1 mentioned above, the first terminal of the scanning transistor S-TFT is connected to the column line and used to receive the data voltage VData, and the second terminal of the scanning transistor S-TFT is connected to the control terminal of the driving transistor D-TFT. The first terminal of the driving transistor D-TFT is connected to the power supply ELVDD, and the second terminal of the driving transistor D-TFT is connected to the power supply ELVSS. When the scanning transistor S-TFT is turned on, the control terminal of the driving transistor D-TFT is high level, and the driving transistor D-TFT is turned on. One terminal of the first capacitor Cst is connected to the control terminal of the driving transistor D-TFT, i.e., to the second terminal of the scanning transistor S-TFT, and one terminal of the first capacitor Cst is connected to the second terminal of the driving transistor D-TFT.

[0064] The control terminal of the scanning transistor S-TFT corresponds to the gate of the scanning transistor S-TFT, and the first and second terminals correspond to the source and drain of the scanning transistor S-TFT, respectively. Similarly, the control terminal of the driving transistor D-TFT corresponds to the gate of the driving transistor D-TFT, and the first and second terminals correspond to the source and drain of the driving transistor D-TFT, respectively.

[0065] The subpixels are OLEDs, with the anode of the OLED connected to the second end of the driving transistor D-TFT, and the cathode of the OLED connected to the power supply ELVSS. When the driving transistor D-TFT is turned on, the OLED turns on and emits light, realizing the screen display.

[0066] The drive circuit 100 includes a scanning drive circuit as described in any of the above technical solutions. The scanning drive circuit is formed in the edge region of the display panel 200 using a Gate In Panel (GIP or GOA) method, for example, the display panel 200 includes a display area and a non-display area located at the edge, and the scanning drive circuit can be formed in the non-display area of ​​the display panel 200.

[0067] The drive circuit 100 further includes a timing controller 20, a data drive circuit 30, and a power supply circuit 40, which can be specifically referred to in Figure 1. Here, the data drive circuit 30 is connected to the timing controller 20 and is used to output a data voltage VData corresponding to each column data line based on the signal controlled by the timing controller 20, driving the currently on row pixel unit to realize screen display. The power supply circuit 40 is used to provide power supplies ELVDD and ELVSS.

[0068] Those skilled in the art will readily understand other embodiments of this application by examining this specification and practicing the invention disclosed herein. This application is intended to encompass all modifications, uses, or adaptations of this application, including common or customary art in the art not disclosed herein, in accordance with the general principles of this application. This specification and examples are for illustrative purposes only, and the true scope and spirit of this application are indicated by the appended claims. [Explanation of Symbols]

[0069] 10 Scanning drive module 101 Logic Control Unit Q First output terminal P Second output terminal 102 Pull-up Unit M1 pull-up switch unit, C Bootstrap capacitor T1 First Switch Unit T2 Second Switch Unit N1 First node N2, the second node N3, the third node 103 Pull-down unit M2 Pull-Down Switch Unit 100 drive circuit 20 Timing Controller 30 Data-driven circuits 40 Power circuit 200 Display Panels S-TFT Scanning Transistor D-TFT driving transistor Cst First Capacitor OLED subpixels C' parasitic capacitance

Claims

1. A scanning drive circuit comprising a plurality of scanning drive modules, each scanning drive module comprising a logic control unit, a pull-up unit, and a pull-down unit, wherein the pull-down unit is connected to a first output terminal and a first node of the logic control unit, The aforementioned pull-up unit is A pull-up switch unit wherein the control terminal of the pull-up switch unit is connected to a second node, the first terminal of the pull-up switch unit is connected to a third node, the third node is configured to receive a clock signal, and the second terminal of the pull-up switch unit is connected to the first node, A bootstrap capacitor, one end of which is connected to the first node and the other end of which is connected to the second node, A first switch unit, wherein the control terminal of the first switch unit is connected to the second output terminal of the logic control unit, the first terminal of the first switch unit is connected to a voltage signal source, the voltage signal source is used to provide a preset level signal, the preset level signal is less than the high level of the clock signal and greater than the low level of the clock signal, and the second terminal of the first switch unit is connected to the first switch unit connected to the first node, A second switch unit comprising: a second switch unit whose control terminal is connected to the third node, whose first terminal is connected to the second node, and whose second terminal is connected to the second output terminal of the logic control unit, The first switch unit is configured to turn on when the second output terminal of the logic control unit is at a high level and to raise the potential of the first node to the preset level signal, and the second switch unit is configured to turn on when the clock signal is at a high level and to raise the potential of the first node to the high level of the clock signal. A scanning drive circuit characterized by the following features.

2. The preset level signal is smaller than the on-voltage of the scanning transistor in the pixel unit, and the control terminal of the scanning transistor is connected to the first node. The scanning drive circuit according to claim 1.

3. The preset level signal includes a first level signal and a second level signal that is greater than the first level signal, and the period during which the second output terminal of the logic control unit is high level and the clock signal is low level includes a first period and a second period that is later than the first period, and the voltage signal source is configured to provide the first level signal during the first period and the second level signal during the second period. The scanning drive circuit according to claim 1.

4. The scanning drive circuit according to claim 3, characterized in that the voltage signal source is a timing controller.

5. The scanning drive circuit according to claim 1, characterized in that the first switch unit and the second switch unit are thin-film transistors.

6. The pull-down unit includes a pull-down switch unit, the control terminal of the pull-down switch unit is connected to the first output terminal of the logic control unit, the first terminal of the pull-down switch unit is connected to the first node, and the second terminal of the pull-down switch unit is connected to the common ground terminal. The scanning drive circuit according to claim 1.

7. The plurality of scanning drive modules are cascaded, and the logic control units of at least some of the scanning drive modules are configured to output a corresponding low-level or high-level signal to the second output terminal based on the scanning signal of the preceding scanning drive module, and to output a corresponding low-level or high-level signal to the first output terminal based on the scanning signal of the next scanning drive module. The scanning drive circuit according to claim 1.

8. The pull-up switch unit is a pull-up transistor, the control terminal of the pull-up switch unit corresponds to the gate of the pull-up transistor, and the first terminal and the second terminal of the pull-up switch unit correspond to the source and drain of the pull-up transistor, respectively. The scanning drive circuit according to claim 1.

9. The scanning drive circuit according to claim 8, characterized in that the pull-up transistor is a MOS transistor.

10. The scanning drive circuit according to claim 8, characterized in that the pull-up switch unit is a thin-film transistor.

11. The preset level signal is a fixed level signal, and when the first switch unit is turned on, it raises the potential of the first node to the fixed level signal. The scanning drive circuit according to claim 1.

12. The scanning drive circuit according to claim 1, characterized in that the preset level signal is a level signal containing a plurality of different amplitudes.

13. The preset level signal includes a first level signal, a second level signal, and a third level signal, wherein the amplitudes of the first level signal, the second level signal, and the third level signal increase in order. The period during which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period, a second period, and a third period, and the times corresponding to the first period, the second period, and the third period are arranged in order. The voltage signal source is configured to provide the first level signal during the first period, the second level signal during the second period, and the third level signal during the third period. The scanning drive circuit according to claim 12, characterized in that it is a scanning drive circuit.

14. The pull-down switch unit is a pull-down transistor, the control terminal of the pull-down switch unit corresponds to the gate of the pull-down transistor, and the first terminal and the second terminal of the pull-down switch unit correspond to the source and drain of the pull-down transistor, respectively. The scanning drive circuit according to feature 6.

15. The scanning drive circuit according to claim 14, characterized in that the pull-down transistor is a MOS transistor.

16. A scanning drive method applied to a scanning drive circuit according to any one of claims 1 to 15, The step includes causing the voltage signal source to output a preset level signal to the first terminal of the first switch unit when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level. A scanning drive method characterized by the following:

17. A display panel including an array of pixel units, A drive circuit used to drive the pixel unit, comprising a scanning drive circuit according to any one of claims 1 to 15. A display device characterized by the following features.

18. The display device according to claim 17, characterized in that the pixel unit is a self-illuminating pixel unit.

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