Array substrate and display panel

Abstract

Embodiments of the present application disclose an array substrate and a display panel, the array substrate comprising a substrate, a light shielding layer, an active layer, an interlayer insulating layer, a source-drain electrode layer, a first electrode layer, a passivation layer and a second electrode layer arranged in sequence above the substrate, the light shielding layer comprising a data line, the second electrode layer comprising an insulatively arranged common electrode and a connecting electrode, one end of the connecting electrode being electrically connected to the source-drain electrode layer through a first via, and the other end of the connecting electrode being connected to the data line through a second via; by arranging the data line and the light shielding layer in the same layer, the distance between the data line and the common electrode is increased, thereby reducing the parasitic capacitance between the data line and the common electrode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel with the same. BACKGROUND

[0002] In the prior art, since the data line of the array substrate is usually arranged in the same layer as the source-drain layer, the distance between the source-drain layer and the common electrode is small, and the parasitic capacitance generated between the source-drain layer and the common electrode is large. Therefore, there is an urgent need to provide a new array substrate architecture to reduce the parasitic capacitance between the data line and the common electrode.

[0003] Therefore, the prior art array substrate has the technical problem of large parasitic capacitance between the data line and the common electrode. SUMMARY

[0004] Embodiments of the present application provide an array substrate and a display panel, which can alleviate the technical problem of large parasitic capacitance between the data line and the common electrode in the prior art array substrate.

[0005] Embodiments of the present application provide an array substrate, comprising:

[0006] a substrate;

[0007] a light shielding layer arranged above the substrate;

[0008] an active layer arranged on a side of the light shielding layer away from the substrate;

[0009] an interlayer insulating layer arranged on a side of the active layer away from the substrate;

[0010] a source-drain layer arranged on a side of the interlayer insulating layer away from the substrate;

[0011] a first electrode layer arranged on a side of the source-drain layer away from the substrate;

[0012] a passivation layer arranged on a side of the first electrode layer away from the substrate;

[0013] a second electrode layer arranged on a side of the passivation layer away from the substrate;

[0014] wherein the light shielding layer comprises a data line, the second electrode layer comprises a common electrode arranged in insulation and a connection electrode, the first electrode layer is in direct contact with the source-drain layer, one end of the connection electrode is connected to the first electrode layer through a first via and is electrically connected to the source-drain layer, and the other end of the connection electrode is connected to the data line through a second via.

[0015] Optionally, in some embodiments of the present application, the array substrate further comprises a touch unit, the touch unit comprises a touch trace and a touch electrode, the touch trace is arranged in the same layer as the data line and is insulated, the touch electrode is arranged in the same layer as the common electrode and is insulated, and the touch trace is connected to the touch electrode through a third via hole.

[0016] Optionally, in some embodiments of the present application, the display panel further comprises a buffer layer, a gate, and a gate insulating layer, the buffer layer is arranged above the substrate, the active layer is arranged on a side of the buffer layer away from the substrate, the gate insulating layer is arranged on a side of the active layer away from the substrate, and the gate is arranged on a side of the gate insulating layer away from the substrate, the active layer further comprises a semiconductor pattern and a blocking pattern arranged in an insulating manner, the semiconductor pattern is connected to the source-drain electrode layer, and the blocking pattern is arranged in alignment with the second via hole and the third via hole, respectively, the first via hole penetrates the passivation layer, and the second via hole and the third via hole both penetrate the passivation layer, the interlayer insulating layer, the gate insulating layer, the blocking pattern, and the buffer layer.

[0017] Optionally, in some embodiments of the present application, the light shielding layer further comprises a light shielding pattern arranged in a disconnected manner with the data line, in a film thickness direction, a projection of the active layer falls within the light shielding pattern, and a preparation material of the light shielding layer is the same as a preparation material of the source-drain electrode layer.

[0018] Optionally, in some embodiments of the present application, in a film thickness direction, a thickness of the light shielding layer is greater than or equal to 1000 angstroms.

[0019] Optionally, in some embodiments of the present application, the blocking pattern comprises a first blocking piece arranged in alignment with the touch trace and a second blocking piece arranged in alignment with the data line, in a film thickness direction, a front projection of the first blocking piece is arranged at least partially in coincidence with a front projection of the touch trace, the second blocking piece is arranged in coincidence with the data line, and the active layer is arranged in coincidence with the light shielding pattern.

[0020] Optionally, in some embodiments of the present application, the source-drain electrode layer comprises a source electrode and a drain electrode, the first electrode layer comprises a lap joint and a pixel electrode arranged in an insulating manner with each other, the pixel electrode is arranged to cover a top surface of at least one of the source electrode or the drain electrode, the lap joint is arranged to cover a top surface of the other of the source electrode or the drain electrode, and one end of the connection electrode is connected to the lap joint through the first via hole.

[0021] Optionally, in some embodiments of the present application, the pixel electrode is arranged to cover a top surface and at least one side surface of one of the source electrode and the drain electrode, and the lap joint is arranged to cover a top surface and at least one side surface of the other of the source electrode and the drain electrode.

[0022] Optionally, in some embodiments of the present application, the second via hole comprises a first part and a second part arranged in a nested manner, the second part is located inside the first part, the first part penetrates through the gate insulating layer, the interlayer insulating layer, and the second part penetrates through the gate insulating layer, the interlayer insulating layer, the passivation layer, the barrier pattern, and the buffer layer.

[0023] Embodiments of the present application provide a display panel, which comprises the array substrate as described in any of the above embodiments.

[0024] Beneficial effects: by arranging the data line and the light shielding layer in the same layer, the distance between the data line and the common electrode is increased, thereby reducing the parasitic capacitance between the data line and the common electrode, and alleviating the technical problem of large parasitic capacitance between the data line and the common electrode in the existing array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 is a cross-sectional schematic view of the array substrate provided by the present application at A-A in Figure 2

[0027] Figure 2 is a schematic view of a pixel structure of the array substrate provided by the present application;

[0028] Figure 3 is a flowchart of the preparation method of the array substrate provided by the present application.

[0029] Explanation of reference signs:

[0030]

[0031] DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in combination with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application, and should not be regarded as limiting the protection scope of the present application.

[0033] ​In addition, the terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish different technical features. The term "multiple" and similar terms mean two or more, unless otherwise explicitly limited.

[0034] Please refer to Figure 1 、 Figure 2 The array substrate 1 provided by the present application comprises a substrate 10, a light shielding layer 20, an active layer 40, an interlayer insulating layer 70, a source-drain layer 80, a first electrode layer 90, a passivation layer 100, and a second electrode layer 110 arranged in sequence above the substrate 10, wherein the light shielding layer 20 comprises a data line 201, the second electrode layer 110 comprises a common electrode 120 and a connecting electrode 130 arranged in insulation, one end of the connecting electrode 130 is electrically connected to the source-drain layer 80 through a first via hole h1, and the other end of the connecting electrode 130 is connected to the data line 201 through a second via hole h2.

[0035] In the present embodiment, by arranging the data line 201 and the light shielding layer 20 in the same layer, the distance between the data line 201 and the common electrode 120 is increased, thereby reducing the parasitic capacitance between the data line 201 and the common electrode 120, and alleviating the technical problem of the existing array substrate 1 that the parasitic capacitance between the data line 201 and the common electrode 120 is large.

[0036] The technical solutions of the present application will be described in combination with specific embodiments.

[0037] The embodiments of the present application are only described by taking the array substrate 1 of a low temperature poly-silicon (LTPS) thin film transistor as an example, and for other array substrates 1, the parasitic capacitance between the data line 201 and the common electrode 120 can also be reduced by increasing the distance between the data line 201 and the common electrode 120.

[0038] In addition, the present application is only described by taking the array substrate 1 of a top gate structure as an example, and is also applicable to the array substrate 1 of a bottom gate structure.

[0039] In addition, the thickness, the selected material, and the position of the via hole in the present application are described by taking the best or better embodiments as examples, and other structure designs capable of reducing the parasitic capacitance between the data line 201 and the common electrode 120 also belong to the protection scope of the present application.

[0040] In one embodiment, please refer to Figure 1The array substrate 1 further comprises a touch unit, the touch unit comprises a touch wire 203 and a touch electrode 140, the touch wire 203 is arranged in the same layer as the data line 201 and is insulated, the touch electrode 140 is arranged in the same layer as the common electrode 120 and is insulated, wherein the touch wire 203 is connected with the touch electrode 140 through a third via hole h3.

[0041] The display panel further comprises an LTPS thin film transistor, and the touch unit can be arranged side by side with the LTPS thin film transistor.

[0042] It can be understood that, by arranging the touch wire 203 in the same layer as the light shielding layer 20, compared with the prior art that the touch wire 203 is arranged in the same layer as the source-drain layer 80, the distance between the touch wire 203 and the common electrode 120 can be increased, and the parasitic capacitance of the intersection between the touch wire 203 and the common electrode 120 in the film thickness direction can be reduced.

[0043] In the embodiment, by arranging the touch wire 203 in the touch unit in the same layer as the light shielding layer 20 in the LTPS thin film transistor, one mask for preparing the touch wire 203 can be saved, and the distance between the touch wire 203 and the common electrode 120 can be further increased, and the parasitic capacitance of the touch wire 203 and the common electrode 120 can be reduced.

[0044] In an embodiment, referring to Figure 1 The display panel further comprises a buffer layer 30, a gate 60 and a gate insulating layer 50, the buffer layer 30 is arranged above the substrate 10, the active layer 40 is arranged on a side of the buffer layer 30 away from the substrate 10, the gate insulating layer 50 is arranged on a side of the active layer 40 away from the substrate 10, and the gate 60 is arranged on a side of the gate insulating layer 50 away from the substrate 10, the active layer 40 further comprises a semiconductor pattern 401 and a barrier pattern 402 arranged in an insulating manner, the semiconductor pattern 401 is connected with the source-drain layer 80, and the barrier pattern 402 is arranged in alignment with the second via hole h2 and the third via hole h3, respectively, wherein the first via hole h1 penetrates the passivation layer 100, and the second via hole h2 and the third via hole h3 both penetrate the passivation layer 100, the interlayer insulating layer 70, the gate insulating layer 50, the barrier pattern 402, the buffer layer 30.

[0045] The preparation material of the barrier pattern 402 is the same as that of the semiconductor pattern 401.

[0046] It is understood that the blocking pattern 402 is aligned with the second via h2 and the third via h3. When the gate insulating layer 50 and the interlayer insulating layer 70 are etched to form contact vias, through holes penetrating the gate insulating layer 50 and the interlayer insulating layer 70 can be formed simultaneously at the blocking pattern 402. The contact vias are used to connect the source electrode 801, the drain electrode 802 and the semiconductor pattern 401. The through holes correspond to the second via h2 and the third via h3 respectively. Since the through holes are prepared simultaneously with the existing hole-drilling process, the preparation process of the second via h2 and the third via h3 can be simplified, so that the second via h2 and the third via h3 do not need to be etched with the interlayer insulating layer 70 and the gate insulating layer 50, thus simplifying the manufacturing process.

[0047] In this embodiment, while forming the contact via, a through-hole penetrating the gate insulating layer 50 and the interlayer insulating layer 70 is also formed at the blocking pattern 402. The function of the blocking pattern 402 is to prevent over-etching to the underlying buffer layer 30 when forming the through-hole, thus avoiding excessive etching.

[0048] In one embodiment, please refer to Figure 1 , Figure 2 The light-shielding layer 20 further includes a light-shielding pattern 202 that is insulated from the data line 201, and the active layer 40 falls within the light-shielding pattern 202 in the film thickness direction.

[0049] The light-shielding pattern 202 and the active layer 40 can be designed to mimic each other, that is, the light-shielding pattern 202 and the active layer 40 have the same shape, but different sizes.

[0050] In the film thickness direction, the area of ​​the light-shielding pattern 202 is larger than the area of ​​the active layer 40.

[0051] The active layer 40 includes a channel region, a source 801 doped region and a drain 802 doped region located on both sides of the channel region. The source 801 is connected to the active layer 40 in the source 801 doped region, and the drain 802 is connected to the active layer 40 in the drain 802 doped region.

[0052] It is understood that the light-shielding pattern 202 covers the entire active layer 40 rather than just the channel area. This not only enables the light-shielding pattern 202 to block light over a wider range and achieve a better light-shielding effect, but also avoids the formation of large film thickness differences between the active layer 40 and the area aligned with the light-shielding layer 20, as well as other areas, due to the terrain differences formed by the light-shielding layer 20.

[0053] It should be noted that, in the film thickness direction, the active layer 40 falls within the light-shielding pattern 202, which can provide a flat surface for the active layer 40 and improve the surface flatness of the active layer 40.

[0054] In the embodiment, by enabling the light-shielding layer 20 to cover at least the active layer 40, the active layer 40 can be arranged flat in the area of the light-shielding layer 20, reducing the step difference of the active layer 40 itself due to the underlying terrain difference, and improving the stability of the LTPS thin film transistor.

[0055] In an embodiment, in the film thickness direction, the thickness of the light-shielding layer 20 is greater than or equal to 1000 angstroms.

[0056] The thickness of the light-shielding layer 20 can be any one of 1000 angstroms, 1200 angstroms, 1500 angstroms, 1800 angstroms, and 2000 angstroms.

[0057] It can be understood that since the light-shielding layer 20 needs to be prepared synchronously with the data line 201, the greater the thickness of the data line 201, the smaller the impedance of the data line 201 itself. Therefore, compared with the thickness of the light-shielding layer 20 of less than 1000 angstroms in the prior art, the present application can increase the thickness of the light-shielding layer 20 to more than 1000 angstroms, so that the impedance of the data line 201 is smaller, and the transmission efficiency of the data line 201 signal is improved.

[0058] In the embodiment, by increasing the thickness of the light-shielding layer 20, the impedance of the data line 201 itself is reduced, and the transmission efficiency of the data line 201 signal is improved.

[0059] In an embodiment, the blocking pattern 402 includes a first blocking piece arranged in alignment with the touch trace 203, and a second blocking piece arranged in alignment with the data line 201. In the film thickness direction, the first blocking piece is arranged in coincidence with the touch trace 203, the second blocking piece is arranged in coincidence with the data line 201, and the active layer 40 is arranged in coincidence with the light-shielding pattern 202.

[0060] It can be understood that the active layer 40 and the light-shielding layer 20 can be prepared by using the same mask, and the patterns at the corresponding positions of the two layers coincide with each other. By sharing one mask for the active layer 40 and the light-shielding layer 20, one mask is saved, and the cost is reduced.

[0061] In the embodiment, the active layer 40 and the light-shielding layer 20 share one mask, which can reduce one mask.

[0062] In an embodiment, please refer to Figure 1The source-drain layer 80 includes a source electrode 801 and a drain electrode 802. The first electrode layer 90 includes an overlap portion 902 and a pixel electrode 901 that are insulated from each other. The pixel electrode 901 covers at least the top surface of one of the source electrode 801 or the drain electrode 802. The overlap portion 902 covers at least the top surface of the other of the source electrode 801 or the drain electrode 802. One end of the connecting electrode 130 is connected to the overlap portion 902 through a first via h1.

[0063] The pixel electrode 901 is disposed on the side of the common electrode 120 facing the substrate 10.

[0064] It is understood that the first electrode layer 90 can be directly disposed on the source and drain layer 80, and the pixel electrode 901 overlaps with the source electrode 801 or the drain electrode 802. Compared with the scheme of disposing the pixel electrode 901 on the side of the passivation layer 100 away from the substrate 10, a through-hole for overlapping the pixel electrode 901 with the source electrode 801 or the drain electrode 802 can be eliminated, thereby simplifying a process.

[0065] It should be noted that, since the pixel electrode 901 covers the top surface of the source electrode 801 or the drain electrode 802, compared with the solution of connecting the pixel electrode 901 to the source electrode 801 or the drain electrode 802 through a via, the contact area between the pixel electrode 901 and the source electrode 801 and the drain electrode 802 is larger and the contact resistance is smaller.

[0066] In this embodiment, by directly placing the pixel electrode 901 on the source electrode 801 or the drain electrode 802, and by placing the pixel electrode 901 on at least the top surface of the source electrode 801 or the drain electrode 802, not only is a via fabrication process saved, but the contact resistance between the pixel electrode 901 and the source electrode 801 or the drain electrode 802 is also reduced.

[0067] In one embodiment, the pixel electrode 901 is disposed covering the top surface and at least one side surface of one of the source electrode 801 and the drain electrode 802, and the overlapping portion 902 is disposed covering the top surface and at least one side surface of the other of the source electrode 801 and the drain electrode 802.

[0068] Please refer to Figure 1 The pixel electrode 901 covers one side of the source electrode 801 or the drain electrode 802.

[0069] The pixel electrode 901 covers both sides of the source electrode 801 or the drain electrode 802.

[0070] It is understood that the pixel electrode 901 also overlaps with the side of the source electrode 801 or the drain electrode 802. Compared with the solution where the pixel electrode 901 only covers the top surface of the source electrode 801 or the drain electrode 802, this further increases the contact area between the first electrode layer 90 and the source electrode 801 or the drain electrode 802, thereby further reducing the contact resistance.

[0071] In one embodiment, the second via h2 includes a first portion and a second portion arranged in a nested manner, the second portion being located inside the first portion, the first portion penetrating the gate insulating layer 50 and the interlayer insulating layer 70, and the second portion penetrating the gate insulating layer 50, the interlayer insulating layer 70, the passivation layer 100, the blocking pattern 402, and the buffer layer 30.

[0072] It is understandable that the second via h2 may include two nested parts, and the first part can be prepared simultaneously with the overlap via used in the existing process to overlap the source 801, drain 802 and active layer 40, which can simplify the process.

[0073] It should be noted that the third via h3 may also include a third part and a fourth part arranged in a nested manner. The fourth part is located inside the third part. The third part penetrates the gate insulating layer 50 and the interlayer insulating layer 70. The fourth part penetrates the gate insulating layer 50, the interlayer insulating layer 70, the passivation layer 100, the blocking pattern 402, and the buffer layer 30.

[0074] In this embodiment, by making the second via h2 and the third via h3 include at least two nested parts, the two parts are prepared by different etching processes, and at least one of them is prepared by existing process technology. On the one hand, the deep hole with a large depth is etched in at least two steps, which reduces the difficulty of the process. On the other hand, at least one etching in multiple etchings is implemented by existing etching process, which simplifies the process technology.

[0075] In one embodiment, the planarization layer can be removed, thereby saving the cost of the photomask and reducing production costs.

[0076] It is understandable that the planarization layer plays a planarization role and can be removed during the manufacturing process. However, removing the planarization layer will greatly shorten the distance between the data line 201 and the common electrode 120, thereby increasing the parasitic capacitance between the data line 201 and the common electrode 120. The design provided in this application, which forms a light-shielding layer 20 on the same layer as the data line 201 and the light-shielding pattern 202, can overcome the defect of increased parasitic capacitance between the data line 201 and the common electrode 120 caused by removing the planarization layer.

[0077] Please seeFigure 3 The embodiment of the present application further provides a preparation method of the array substrate 1, comprising:

[0078] S1: providing a substrate 10, and preparing a light-shielding layer 20 on the substrate 10, wherein the light-shielding layer 20 comprises a data line 201 and a light-shielding pattern 202 arranged in the same layer;

[0079] S2: sequentially preparing a buffer layer 30, an active layer 40, a gate insulating layer 50 and a gate 60 above the light-shielding layer 20;

[0080] S3: preparing an interlayer insulating layer 70 on the gate 60 and the gate insulating layer 50, and forming a lap joint hole penetrating through the interlayer insulating layer 70, wherein the lap joint hole is located at a source 801 doped region and a drain 802 doped region of the active layer 40 respectively;

[0081] S4: preparing a source-drain layer 80 on the interlayer insulating layer 70, wherein a source 801 of the source-drain layer 80 is connected with the source 801 doped region of the active layer 40 through a lap joint hole, and a drain 802 of the source-drain layer 80 is connected with the drain 802 doped region of the active layer 40 through another lap joint hole;

[0082] S5: directly preparing a layer of transparent electrode material on the source-drain layer 80, and patterning the transparent electrode material to prepare a first electrode layer 90;

[0083] S6: sequentially preparing a passivation layer 100 and a second electrode layer 110 on the first electrode layer 90, wherein the second electrode layer 110 comprises a common electrode 120 and a connecting electrode 130 arranged in an insulating manner, the connecting electrode 130 is electrically connected with the source-drain layer 80 through a first via hole h1, and the connecting electrode 130 is connected with the data line 201 through a second via hole h2.

[0084] The present application discloses a novel array substrate 1 architecture. Taking the array substrate 1 of LTPS thin film transistor as an example, the data line 201 is arranged in the same layer as the light-shielding layer 20, the vertical distance between the data line 201 and the upper common electrode 120 is increased, and thus the parasitic capacitance between the data line 201 and the common electrode 120 is reduced. Meanwhile, the touch control wire 203 can also be arranged in the same layer as the light-shielding layer 20, the distance between the touch control wire 203 and the common electrode 120 is increased, and thus the parasitic capacitance between the touch control wire 203 and the common electrode 120 is reduced.

[0085] The present application further provides a display module and a terminal device, wherein the display module and the terminal device both comprise the display panel, and the terminal device includes but is not limited to a mobile phone, a notebook computer and a tablet computer.

[0086] The array substrate provided by the embodiment of the present application comprises a substrate, a light-shielding layer, an active layer, an interlayer insulating layer, a source-drain layer, a first electrode layer, a passivation layer and a second electrode layer arranged in sequence above the substrate, the light-shielding layer comprises a data line, the second electrode layer comprises a common electrode and a connecting electrode arranged in insulation, one end of the connecting electrode is electrically connected with the source-drain layer through a first via, and the connecting electrode is connected with the data line through a second via; by arranging the data line and the light-shielding layer in the same layer, the distance between the data line and the common electrode is increased, thereby reducing the parasitic capacitance between the data line and the common electrode, and the technical problem of large parasitic capacitance between the data line and the common electrode existing in the prior art array substrate is solved.

[0087] The array substrate provided by the embodiment of the present application is described in detail above. Those skilled in the art can make various corresponding changes and modifications according to the present application without departing from the spirit and essential characteristics of the present application, and these corresponding changes and modifications shall all belong to the protection scope of the claims appended to the present application.

Claims

1. An array substrate, characterized in that, include: Substrate; A light-shielding layer is disposed above the substrate; An active layer is disposed on the side of the light-shielding layer away from the substrate; An interlayer insulating layer is disposed on the side of the active layer away from the substrate; A source / drain layer is disposed on the side of the interlayer insulating layer away from the substrate; A first electrode layer is disposed on the side of the source / drain layer away from the substrate; A passivation layer is disposed on the side of the first electrode layer away from the substrate; A second electrode layer is disposed on the side of the passivation layer away from the substrate; The light-shielding layer includes a data line, the second electrode layer includes a common electrode and a connecting electrode that are insulated from each other, the first electrode layer is in direct contact with the source and drain layers, one end of the connecting electrode is connected to the first electrode layer through a first via and is electrically connected to the source and drain layers, and the other end of the connecting electrode is connected to the data line through a second via. The active layer further includes a blocking pattern, which is aligned with the second via and the third via, respectively. The first via penetrates the passivation layer, and the second and third vias both penetrate the passivation layer and the blocking pattern.

2. The array substrate as described in claim 1, characterized in that, The array substrate further includes a touch unit, which includes touch traces and touch electrodes. The touch traces are on the same layer as the data lines and are insulated from each other. The touch electrodes are on the same layer as the common electrode and are insulated from each other. The touch traces and the touch electrodes are connected through the third via.

3. The array substrate as described in claim 2, characterized in that, The array substrate further includes a buffer layer, a gate, and a gate insulating layer. The buffer layer is disposed above the substrate. The active layer is disposed on the side of the buffer layer away from the substrate. The gate insulating layer is disposed on the side of the active layer away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The active layer further includes a semiconductor pattern that is insulated from the blocking pattern. The semiconductor pattern is connected to the source and drain layers. The second via and the third via both penetrate the passivation layer, the interlayer insulating layer, the gate insulating layer, the blocking pattern, and the buffer layer.

4. The array substrate as described in claim 3, characterized in that, The light-shielding layer also includes a light-shielding pattern that is disconnected from the data line. In the film thickness direction, the projection of the active layer falls within the light-shielding pattern. The material used to prepare the light-shielding layer is the same as the material used to prepare the source and drain layers.

5. The array substrate as described in claim 4, characterized in that, In the film thickness direction, the thickness of the light-shielding layer is greater than or equal to 1000 angstroms.

6. The array substrate as described in claim 4, characterized in that, The blocking pattern includes a first blocking member aligned with the touch trace and a second blocking member aligned with the data line. In the film thickness direction, the orthographic projection of the first blocking member and the orthographic projection of the touch trace are at least partially overlapped, the second blocking member and the data line are at least partially overlapped, and the active layer and the light-shielding pattern are at least partially overlapped.

7. The array substrate as claimed in claim 1, characterized in that, The source-drain layer includes a source and a drain. The first electrode layer includes an overlap portion and a pixel electrode that are insulated from each other. The pixel electrode covers at least the top surface of one of the source or the drain. The overlap portion covers at least the top surface of the other of the source or the drain. One end of the connecting electrode is connected to the overlap portion through a first via.

8. The array substrate as claimed in claim 7, characterized in that, The pixel electrode is disposed covering the top surface and at least one side surface of one of the source electrode and the drain electrode, and the overlapping portion is disposed covering the top surface and at least one side surface of the other of the source electrode and the drain electrode.

9. The array substrate as described in claim 3, characterized in that, The second via includes a first portion and a second portion arranged in a nested manner. The second portion is located inside the first portion. The first portion penetrates the gate insulating layer and the interlayer insulating layer. The second portion penetrates the gate insulating layer, the interlayer insulating layer, the passivation layer, the blocking pattern, and the buffer layer.

10. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 9.

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