A power semiconductor output capacitance detection device and method

Abstract

The application provides a power semiconductor output capacitor detection device and method, which is applied to a power conversion circuit. The power conversion circuit comprises an input DC source, a power semiconductor, an inductor and a diode. The input DC source comprises an input positive terminal and an input negative terminal. The positive electrode of the diode and the drain of the power semiconductor are connected to a target reference point. The voltage between the input DC source and the target reference point is compared by a comparator to obtain a comparison signal. The count value in a counting module is reset based on the comparison signal. The count value in the counting module is sampled at a specific position, so that the corresponding resonance period of the power semiconductor output capacitor can be obtained, and finally the power semiconductor output capacitor can be calculated. The detection device provided by the application does not need to make any hardware changes to the power conversion circuit, and can also overcome the detection influence of the parasitic capacitor on the power semiconductor output capacitor of the power conversion circuit, thereby improving the detection precision of the output capacitor.

Description

Technical Field

[0001] This application relates to the field of electronic power, and in particular to a power semiconductor output capacitance detection device and method. Background Technology

[0002] In power topologies such as BOOST or flyback, when the power semiconductor is turned off, the output capacitance (Coss) of the power semiconductor, along with the internal inductance, causes voltage oscillations across the power semiconductor. Due to these voltage oscillations, if the power semiconductor is turned on when the voltage across it is high, it will result in high switching losses.

[0003] To reduce the switching losses of power semiconductors, we can use the output capacitance of the power semiconductor to estimate the location of the voltage trough and turn on the power semiconductor at the trough location to achieve soft start of the power semiconductor quasi-zero voltage switching (ZVS), thereby reducing the switching losses of the power semiconductor.

[0004] However, the location of the voltage trough caused by the output capacitance varies among different types of power semiconductors. Especially with the development of wide-bandgap (WBG) power semiconductor devices, the output capacitance of WBG devices such as gallium nitride (GaN) and silicon carbide (SiC) is only in the hundreds of pF range, resulting in a significantly different trough location compared to traditional power semiconductors. Furthermore, differences in batches or manufacturing processes also exist. All these factors contribute to discrepancies between the actual output capacitance parameters of power semiconductor devices and their datasheets. Additionally, onboard parasitic parameters in the circuit also affect the output capacitance of the power semiconductor. Therefore, actual testing of the output capacitance of power semiconductors is necessary to obtain accurate values.

[0005] Traditional devices for measuring the output capacitance of power semiconductors are very expensive and generally require offline measurements using an oscilloscope or expensive field-programmable gate arrays (FPGAs) to implement the detection algorithm, resulting in high costs and difficulty in online measurement. Therefore, there is a need to design a low-cost power semiconductor output capacitance detection device that can perform online measurements. Attached Figure Description

[0006] Figure 1 This is a timing diagram of the power conversion topology;

[0007] Figure 2 A schematic diagram of the output capacitance detection circuit for a power semiconductor.

[0008] Figure 3This is a schematic diagram of a power semiconductor output capacitance detection device.

[0009] Figure 4 This is the timing logic diagram of a power semiconductor output capacitor detection device;

[0010] Figure 5 This is a schematic diagram of the structure of a counting module;

[0011] Figure 6A This is a schematic diagram of resetting a count value using a comparison signal. Figure 1 ;

[0012] Figure 6B This is a schematic diagram of resetting a count value using a comparison signal. Figure 2 ;

[0013] Figure 7 This is a schematic diagram of a sampling timing. Summary of the Invention

[0014] This application provides a power semiconductor output capacitance detection device and method for realizing online measurement of the output capacitance of power semiconductors under low cost conditions.

[0015] In a first aspect, this application provides a power semiconductor output capacitance detection device applied to a power conversion circuit. The power conversion circuit includes: an input DC source, a power semiconductor, an inductor, and a diode. The input DC source includes a positive input terminal and a negative input terminal, with the negative input terminal grounded. One end of the inductor is connected to the positive input terminal, and the negative terminal of the diode and the negative input terminal are connected to a load. The other end of the inductor, the positive terminal of the diode, and the drain of the power semiconductor are all connected to a target reference point, and the source of the power semiconductor is grounded. The device includes: a comparator, a detection module, an inverter, and a counting module. The first input terminal of the comparator is connected to the positive input terminal, and the second input terminal of the comparator is connected to the target reference point. The output terminal of the comparator is connected to the inverter and the counting module. The comparator outputs a first comparison signal based on the voltage at the positive input terminal and the voltage at the target reference point. The inverter generates a second comparison signal based on the first comparison signal. The counting module resets a first count value based on the first comparison signal and a second count value based on the second comparison signal. The detection module detects the first and second count values ​​of the counting module and determines the output capacitance of the power semiconductor based on the first and second count values.

[0016] The power semiconductor output capacitance detection device provided in this application enables online measurement of a power conversion circuit in operation. By comparing the voltage between the input DC source and the target reference point using a comparator, a comparison signal is obtained. Based on this signal, the count value in the counting module is reset, and the count value is sampled at a specific location to obtain the resonant period corresponding to the power semiconductor output capacitance. Finally, the power semiconductor output capacitance can be calculated. Furthermore, online detection of the power semiconductor output capacitance allows for early identification of faulty components in the power conversion circuit, preventing circuit failure during actual use. Moreover, the detection device provided in this application requires no hardware modifications to the power conversion circuit and eliminates the need for additional complex measuring fixtures. It also overcomes the influence of onboard parasitic capacitance on the power semiconductor output capacitance, thereby improving the accuracy of output capacitance detection.

[0017] In some possible implementations, the counting module includes: a first counter and a second counter; the output of a comparator is connected to the first counter, and the output of an inverter is connected to the second counter; the first counter is used to reset a first count value according to a first comparison signal; the second counter is used to reset a second count value according to a second comparison signal. The first and second counters can also perform pulse counting based on different pulse signals or the same pulse signal. Both the first and second counters can sample the pulses from the MCU clock crystal oscillator in the detection module.

[0018] In some possible implementations, the first counter is specifically configured to: receive a first comparison signal and reset a first count value when a set transition edge appears on the first comparison signal; the second counter is specifically configured to: receive a second comparison signal and reset a second count value when a set transition edge appears on the second comparison signal; the set transition edge is a rising edge transitioning from a low level to a high level, or a falling edge transitioning from a high level to a low level. This application may also reset the first count value when a rising edge appears on the first comparison signal and reset the second count value when a falling edge appears on the second comparison signal; or reset the first count value when a falling edge appears on the first comparison signal and reset the second count value when a rising edge appears on the second comparison signal.

[0019] In some cases, due to errors in the comparator's input voltage or detection errors, the output first comparison signal may not be completely out of phase. To address this issue, in some possible implementations, the detection module is further configured to: acquire the first comparison signal and the second comparison signal; sample the second counter using the first comparison signal to obtain a third count value; sample the first counter using the second comparison signal to obtain a fourth count value; and determine the output capacitance of the power semiconductor based on the third and fourth count values. Using this method, the detection error caused by incomplete phase misalignment of the comparison signal can be eliminated.

[0020] In some possible implementations, the detection module is specifically used for:

[0021] The second counter is sampled using the setting edge of the first comparison signal as the first sampling point to obtain the third count value. The first counter is sampled using the setting edge of the second comparison signal as the second sampling point to obtain the fourth count value. The setting edge is either a rising edge that transitions from a low level to a high level, or a falling edge that transitions from a high level to a low level.

[0022] In some possible implementations, the detection module is specifically used for:

[0023] When the voltage of the input DC source is at the target phase, the first count value of the first counter and the second count value of the second counter are detected. By means of the above method, the resonant period result obtained by detecting the count value at a specific phase is more accurate. In this application, a low-speed MCU can be used to detect the phase of the input DC source, and sampling can be performed at a specific phase after the input DC source crosses zero.

[0024] In some possible implementations, the detection module is specifically used to: calculate the sum of a first count value and a second count value to determine the resonant period of the output capacitor of the power semiconductor; and determine the output capacitor of the power semiconductor based on the resonant period.

[0025] In some possible implementations, the detection module is specifically used to: calculate the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; and determine the output capacitor of the power semiconductor based on the resonant period.

[0026] In one possible implementation, the power semiconductor output capacitance detection device of this application embodiment can be applied not only to power conversion circuits, but also to the output capacitance detection process of power semiconductor manufacturers. Compared with the prior art, which requires expensive devices for measuring the output capacitance of power semiconductors or expensive field-programmable gate arrays to implement detection algorithms, this application only uses low-cost comparators, counters and low-speed MCUs to complete the output capacitance detection of power semiconductors, which is low-cost, convenient to detect and widely applicable.

[0027] Secondly, this application also provides a method for detecting the output capacitance of a power semiconductor, applied to a power conversion circuit. The power conversion circuit includes: an input DC source, a power semiconductor, an inductor, and a diode. The input DC source includes a positive input terminal and a negative input terminal, with the negative input terminal grounded. One end of the inductor is connected to the positive input terminal, and the negative terminal of the diode and the negative input terminal are connected to a load. The other end of the inductor, the positive terminal of the diode, and the drain of the power semiconductor are all connected to a target reference point, and the source of the power semiconductor is grounded. The power conversion circuit further includes: a comparator, an inverter, and a counting module. The first input terminal of the comparator is connected to the positive input terminal, and the second input terminal of the comparator is connected to the target reference point. The output terminal of the comparator is connected to the inverter and the counting module. The comparator outputs a first comparison signal based on the voltage at the positive input terminal and the voltage at the target reference point. The inverter generates a second comparison signal based on the first comparison signal. The counting module resets a first count value based on the first comparison signal and resets a second count value based on the second comparison signal. The method includes: detecting a first count value of a first counter and a second count value of a second counter; and determining the output capacitance of the power semiconductor based on the first count value and the second count value.

[0028] As an optional implementation, the counting module includes: a first counter and a second counter; the output of the comparator is connected to the first counter, and the output of the inverter is connected to the second counter;

[0029] The detection of the first and second count values ​​of the counting module includes: detecting the first count value of the first counter and the second count value of the second counter when the voltage of the input DC source is at the target phase.

[0030] As an optional implementation, the method further includes: acquiring a first comparison signal and a second comparison signal; sampling a second counter using the first comparison signal to obtain a third count value, and sampling a first counter using the second comparison signal to obtain a fourth count value; and determining the output capacitance of the power semiconductor based on the third count value and the fourth count value.

[0031] As an optional implementation, the second counter is sampled using the first comparison signal to obtain a third count value, and the first counter is sampled using the second comparison signal to obtain a fourth count value. This includes: using the set edge of the first comparison signal as the first sampling point to sample the second counter to obtain a third count value, and using the set edge of the second comparison signal as the second sampling point to sample the first counter to obtain a fourth count value.

[0032] As an optional implementation, detecting the first count value of the first counter and the second count value of the second counter includes: detecting the first count value of the first counter and the second count value of the second counter when the voltage of the input DC source is at the target phase.

[0033] As an optional implementation, determining the output capacitance of the power semiconductor based on a first count value and a second count value includes: calculating the sum of the first count value and the second count value to determine the resonant period of the output capacitance of the power semiconductor; and determining the output capacitance of the power semiconductor based on the resonant period.

[0034] As an optional implementation, determining the output capacitance of the power semiconductor based on a first count value and a second count value includes: calculating the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitance of the power semiconductor; and determining the output capacitance of the power semiconductor based on the resonant period. Detailed Implementation

[0035] The following explanations will first clarify some of the terms used in the embodiments of this application, so that those skilled in the art can easily understand them.

[0036] Parasitic capacitance, also known as stray capacitance, is the capacitance formed between electronic components or circuit modules due to their proximity. Parasitic capacitance is a parasitic element and an undesirable capacitance characteristic in circuit design. It often causes stray oscillations. In practical designs, all circuit components, such as inductors, diodes, transistors, and diodes, have internal capacitance, which will cause the device's performance to differ from ideal conditions.

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0038] It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0039] See Figure 1 As shown in the timing diagram of the power conversion topology, in the current power circuit topology, after the power semiconductor is turned off, the output capacitance Coss of the power semiconductor and the inductance in the circuit will cause voltage oscillation (at point Vds). To reduce the switching losses of the power semiconductor, the tester can use the output capacitance of the power semiconductor to estimate the location of the oscillation trough, and turn on the power semiconductor at the trough to achieve soft start and reduce the switching losses of the power semiconductor. However, the location of the trough caused by the output capacitance of different types of power semiconductors is different. Moreover, the onboard parasitic capacitance parameters in the above circuit will also affect the output capacitance of the power semiconductor. Therefore, accurate detection of the output capacitance of the power semiconductor is required to better control the power semiconductor and reduce switching losses. However, traditional methods for measuring output capacitance are very complicated. For example, offline measurement is performed using an oscilloscope in an offline (not connected to the load) situation, or it requires the use of an expensive high-precision MCU for detection. The above methods are costly and cannot achieve online measurement. In view of this, it is necessary to design a low-cost power semiconductor output capacitance detection device that can achieve online measurement.

[0040] In some possible implementations, Figure 2 This application provides an output capacitance detection circuit for a power semiconductor. In this embodiment, the measurement circuit can be built offline using a capacitance meter or a bridge circuit. Specifically, it can be... Figure 2The following detection method is performed on the circuit to detect the output capacitance. First, the adjustable regulated power supply is adjusted to the voltage point to be measured, and switch K1 is closed. A capacitance meter or RCL bridge is connected to points J1 and J3 to measure the distributed capacitance Coss1 of the circuit before the power semiconductor is inserted. Then, the power semiconductor is inserted into position Q1 of the measurement circuit, and the capacitance meter or RCL bridge is connected to points J1 and J3 again to measure the distributed capacitance Coss2 of the circuit after the power semiconductor is inserted. Finally, the output capacitance of the power semiconductor is calculated as: Coss2 - Coss1. This implementation method can only be used in specific tooling environments and can only measure the output capacitance of the power semiconductor offline, but cannot measure the actual Coss value of the power semiconductor in the actual power conversion circuit (power supply, converter). Therefore, online measurement is still difficult to achieve.

[0041] To address the problems of high cost and difficulty in online measurement using traditional methods, this application provides a detection device for the output capacitance of power semiconductors that can be measured online. (See reference...) Figure 3 As shown, Figure 3 A power semiconductor output capacitance detection device 300 is provided and applied to a power conversion circuit 301. The power conversion circuit 301 includes: an input DC source 302, a power semiconductor 303, an inductor 304, and a diode 305. The input DC source 302 includes an input positive terminal 3021 and an input negative terminal 3022. The input negative terminal 3022 is grounded. One end of the inductor 304 is connected to the input positive terminal 3021. The cathode of the diode 305 and the input negative terminal 3022 are connected to the load. The other end of the inductor 304, the anode of the diode 305, and the drain 3031 of the power semiconductor 303 are all connected to a target reference point 3033. The source 3032 of the power semiconductor 303 is grounded.

[0042] The power semiconductor output capacitance detection device 300 includes: a comparator 306, a detection module 307, an inverter 308, and a counting module 309; wherein, the first input terminal 3061 of the comparator 306 is connected to the positive input terminal 3021, and the second input terminal 3062 of the comparator 306 is connected to the target reference point 3034; the output terminal 3063 of the comparator 306 is connected to the inverter 308 and the counting module 309; the comparator 306 is used to output a first comparison signal based on the voltage of the positive input terminal 3021 and the voltage of the target reference point 3033; the inverter 308 is used to generate a second comparison signal based on the first comparison signal; the counting module 309 is used to reset a first count value based on the first comparison signal and reset a second count value based on the second comparison signal; the detection module 307 is used to detect the first count value and the second count value of the counting module 309; and determine the output capacitance of the power semiconductor 303 based on the first count value and the second count value.

[0043] In this embodiment, the power semiconductor 303 can be one or more of various types of switching devices, such as a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a field-effect transistor (FET), a silicon carbide (SiC) power transistor, or a gallium nitride (GaN) power transistor. These types of power semiconductors will not be listed individually in this embodiment. All of the above types of power semiconductors can include a first electrode, a second electrode, and a control electrode, wherein the control electrode is used to control the closing or opening of the switch. When the switch is closed, current can be transmitted between the first electrode and the second electrode of the switch; when the switch is open, current cannot be transmitted between the first electrode and the second electrode of the switch. Taking a MOSFET as an example, the control electrode of the power semiconductor is the gate. The first electrode of the power semiconductor can be the source of the power semiconductor, and the second electrode can be the drain of the power semiconductor; alternatively, the first electrode can be the drain of the power semiconductor, and the second electrode can be the source of the power semiconductor.

[0044] Furthermore, in the power semiconductor output capacitor detection device 300 provided in this application embodiment, when the power conversion circuit 301 includes only one power semiconductor 303, the drain 3031 of the power semiconductor 303 is connected to the target reference point 3033, and the source 3032 of the power semiconductor 303 is grounded; while when multiple power semiconductors 303 are used, between each two adjacent power semiconductors 303, the drain of the previous power semiconductor 303 is connected to the source of the next power semiconductor 303, the drain of the first power semiconductor 303 is connected to the target reference point 3033, and the source of the last power semiconductor 303 is grounded.

[0045] The detection module 307 of this application can be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processing unit (DSP), or an application-specific integrated circuit (ASIC). Optionally, the detection module 307 can also be a field-programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof, which have higher costs and higher sampling frequencies. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The aforementioned processor can also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc. The detection module 307 can sample count values ​​by generating pulses with a fixed on-time (Ton) period. Optionally, Ton can be determined by the following parameters: the voltage of the inductor 304, the voltage of the input DC source 302, and the rated current of the input DC source 302. The specific method of generating interrupts for sampling should be known to those skilled in the art and will not be elaborated here.

[0046] The counting module 309 in this application is used to measure the number of pulses. The pulses measured by the counting module 309 can be generated by an external module or the microcontroller unit (MCU) in the detection module 307. The pulse signal can be a pulse width modulation (PWM) signal. Optionally, the counting module 309 can be composed of a counting unit and control gate circuits. The counting unit can include elements such as flip-flops, D flip-flops, RS flip-flops, T flip-flops, and JK flip-flops. The upper limit of the counter's count is related to the frequency of the pulse signal. Those skilled in the art can set different counters according to different clock frequencies to complete the counting. Furthermore, after receiving the first / second comparison signal, the counting module can reset different count values. Specific reset methods can include resetting the count value of the counting module to 0 or setting a value. Those skilled in the art can flexibly set the initial value after reset; no specific limitation is made here.

[0047] Because the voltage resonant frequency of the target reference point 3033 in the power conversion circuit 301 is too high (reaching 500kHz), it is impossible to use a low-cost, low-speed MCU (reaching 50kHz) to accurately detect the resonant period. Therefore, in order to achieve high-frequency resonant period detection and thus calculate the output capacitance in the power conversion circuit 301, this application uses a comparator 306 to compare the voltage between the input DC source 302 and the target reference point 3033. Since the voltage at the target reference point 3033 is in a state of continuous oscillation, the first comparison signal actually output by the comparator 306 can be regarded as a PWM signal with a duty cycle of 50%. After the first comparison signal passes through the inverter 308, a second comparison signal is obtained. The first comparison signal and the second comparison signal can be signals out of phase by 180°. (See reference...) Figure 4 The diagram shows the timing logic of a power semiconductor output capacitor detection device. A comparator compares the voltage of the input DC source with the voltage of the target reference point to generate a first comparison signal. In this embodiment, when the first comparison signal rises, the counting module 309 resets the first count value; when the second comparison signal rises, the counting module 309 resets the second count value. The detection module 307 can read the first and second count values ​​via an interrupt, and determine the resonant period using these values, thereby determining the output capacitor in the power conversion circuit 301. Specifically, the output capacitor can be calculated based on the resonant period using the following formula:

[0048]

[0049] Where P is the resonant period, L is the inductance value, and C is the resonant period. OSSThis is the output capacitor.

[0050] Optionally, in this application, different first count values ​​and second count values ​​can be obtained based on different sampling times / sampling points. Correspondingly, the way to determine the resonant period is also different based on different count values. For example, when the control module 307 samples the first counter and the second counter when the voltage of the input AC source reaches a phase value of 45° or 135° at zero crossing, the sum of the first count value and the second count value is the resonant period.

[0051] See Figure 5 As shown, Figure 5 This is a schematic diagram of a counting module. As one possible implementation, the counting module 309 includes: a first counter 3091 and a second counter 3092; the output of the comparator 306 is connected to the first counter, and the output of the inverter is connected to the second counter.

[0052] The first counter 3091 is used to reset the first count value according to the first comparison signal; the second counter 3092 is used to reset the second count value according to the second comparison signal. Specifically, the first counter 3091 and the second counter 3092 can also perform pulse counting based on different pulse signals or the same pulse signal. For example, both the first counter 3091 and the second counter 3092 can perform pulse sampling on the MCU clock crystal oscillator in the detection module 307.

[0053] In one possible implementation, the first counter 3091 is specifically used to: receive the first comparison signal and reset the first count value when a set transition edge appears on the first comparison signal; the second counter 3092 is specifically used to: receive the second comparison signal and reset the second count value when a set transition edge appears on the second comparison signal; the set transition edge is a rising edge that transitions from a low level to a high level, or a falling edge that transitions from a high level to a low level.

[0054] Figure 6A This is a schematic diagram of resetting a count value using a comparison signal. Figure 1 , Figure 6B This is a schematic diagram of resetting a count value using a comparison signal. Figure 2 .in, Figure 6A A timing diagram illustrating the reset of the count value when the first / second comparison signal experiences a rising edge; Figure 6BThis is a timing diagram illustrating the reset of the counter value when the first / second comparison signal experiences a falling edge. Furthermore, this application can also reset the first counter value when the first comparison signal experiences a rising edge and reset the second counter value when the second comparison signal experiences a falling edge; or reset the first counter value when the first comparison signal experiences a falling edge and reset the second counter value when the second comparison signal experiences a rising edge. This application does not impose excessive limitations on the specific method of resetting the counter.

[0055] In some scenarios, the voltage of the input DC source to comparator 306 and the voltage of the target reference point may have errors. This causes the first comparison signal and the second comparison signal to not be completely out of phase by 180°. For example, when the first comparison signal output by the comparator is a PWM signal with a duty cycle of 60%, then the second comparison signal is a PWM signal with a duty cycle of 40%. In this case, the detection module 307 has difficulty accurately determining the resonant period based on the first count value and the second count value. Therefore, as a possible implementation, the detection module 307 is further configured to: acquire the first comparison signal and the second comparison signal; sample the second counter using the first comparison signal to obtain a third count value, and sample the first counter using the second comparison signal to obtain a fourth count value; and determine the output capacitance of the power semiconductor based on the third count value and the fourth count value.

[0056] The detection module 307 is used to acquire a first comparison signal and a second comparison signal. The first comparison signal is used as a sampling signal to sample the second counter to obtain a third count value. The second comparison signal is used as a sampling signal to sample the first counter to obtain a fourth count value. In this way, the influence caused by the error of the voltage of the input DC source to the comparator 306 and the voltage of the target reference point can be eliminated.

[0057] See Figure 7 As shown, Figure 7 As a sampling timing diagram, in one possible implementation, the detection module is specifically used to: sample the second counter using the set jump edge of the first comparison signal as the first sampling point to obtain a third count value, and sample the first counter using the set jump edge of the second comparison signal as the second sampling point to obtain a fourth count value, wherein the set jump edge is a rising edge that jumps from a low level to a high level, or a falling edge that jumps from a high level to a low level.

[0058] Specifically, in this embodiment, after acquiring the first comparison signal and the second comparison signal, the detection module 307 can sample the second counter to obtain a third sampled value when the first comparison signal has a rising edge, and sample the first counter to obtain a fourth sampled value when the second comparison signal has a rising edge; the detection module 307 can also sample the second counter to obtain a third sampled value when the first comparison signal has a falling edge, and sample the first counter to obtain a fourth sampled value when the second comparison signal has a falling edge; the detection module 307 can also sample the second counter to obtain a third sampled value when the first comparison signal has a rising edge, and sample the first counter to obtain a fourth sampled value when the second comparison signal has a falling edge; the detection module 307 can also sample the second counter to obtain a third sampled value when the first comparison signal has a falling edge, and sample the first counter to obtain a fourth sampled value when the second comparison signal has a rising edge. Figure 7 The detection module 307 uses the rising edge of the first / second comparison signal as the sampling point to sample the second / first counter. Similarly, other sampling methods are based on similar approaches, which will not be elaborated on here.

[0059] Since sampling occurs at different sampling times or points, the first and second count values ​​obtained by the detection module 307 are different. To obtain more accurate sampling results, as a possible implementation, the detection module is specifically used to: detect the first count value of the first counter and the second count value of the second counter when the voltage of the input DC source is at the target phase. Optionally, the detection module 307 can first determine the phase of the input DC source. Since the input DC source is usually a 50Hz / 60Hz AC mains power, a lower-precision MCU (detection module) can still accurately acquire the phase of the input DC source.

[0060] After determining the phase of the input DC source, the detection module 307 can sample the first counter and the second counter based on the phase of the input DC source, using the input DC source as the sampling standard. For example, the detection module 307 can sample at a phase of 45° or 135° after each zero crossing of the input DC source. Furthermore, the specific sampling position of the detection module 307 is also related to the position where the counter is reset, as should be known to those skilled in the art, and will not be elaborated upon here.

[0061] In one possible implementation, the detection module is specifically used to: calculate the sum of the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; and determine the output capacitor of the power semiconductor based on the resonant period. Alternatively, the detection module is further used to: calculate the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; and determine the output capacitor of the power semiconductor based on the resonant period. For example, when the detection module 307 samples at a phase of 45° or 135° after each zero crossing of the input DC source, the resonant period of the output capacitor of the power semiconductor can be equal to the sum of the first count value and the second count value. Optionally, there are multiple ways to determine the resonant period based on the first count value and the second count value. Those skilled in the art should understand that the above two embodiments are merely examples and are not intended to limit this application.

[0062] Optionally, the power semiconductor output capacitance detection device of this application can be used not only in power conversion circuits, but also in the output capacitance detection process of power semiconductor manufacturers. Compared with the prior art, which requires expensive devices for measuring the output capacitance of power semiconductors or expensive field-programmable gate arrays to implement detection algorithms, this application can complete the output capacitance detection of power semiconductors using only low-cost comparators, counters and low-speed MCUs. It is low-cost, convenient to detect and has wide applicability.

[0063] The power semiconductor output capacitance detection device provided in this application enables online measurement in actual power conversion circuits. A comparator compares the voltage between the input DC source and the target reference point to obtain a comparison signal. Based on this signal, the count value in the counting module is reset, and the count value is sampled at a specific location to obtain the resonant period corresponding to the power semiconductor output capacitance, ultimately calculating the power semiconductor output capacitance. Furthermore, online detection of the power semiconductor output capacitance allows for early identification of faulty components in the power conversion circuit, preventing circuit failure during actual use. Moreover, the detection device provided in this application requires no hardware modifications to the power conversion circuit and eliminates the need for additional complex measuring fixtures. It also overcomes the influence of onboard parasitic capacitance on the power semiconductor output capacitance, thereby improving the accuracy of output capacitance detection. Additionally, this application solves the problem of difficulty in detecting high-frequency resonant periods. Using the power semiconductor output capacitance detection device provided in this application, even with a low-speed (e.g., 50kHz calculation frequency) MCU, detection of high-frequency resonant periods (500kHz) can be achieved, reducing detection costs.

[0064] This application also provides a method for detecting the output capacitance of a power semiconductor, applied to a power conversion circuit. The power conversion circuit includes: an input DC source, a power semiconductor, an inductor, and a diode. The input DC source includes a positive input terminal and a negative input terminal, the negative input terminal being grounded. One end of the inductor is connected to the positive input terminal. The cathode of the diode and the negative input terminal are connected to a load. The other end of the inductor, the anode of the diode, and the drain of the power semiconductor are all connected to a target reference point. The source of the power semiconductor is grounded. The power conversion circuit further includes: a comparator, an inverter, and a counting module. The first input terminal of the comparator is connected to the positive input terminal. The second input terminal of the comparator is connected to the target reference point; the output terminal of the comparator is connected to the inverter and the counting module; the comparator is used to output a first comparison signal based on the voltage at the positive input terminal and the voltage at the target reference point; the inverter is used to generate a second comparison signal based on the first comparison signal; the counting module is used to reset a first count value based on the first comparison signal; and reset a second count value based on the second comparison signal; the method includes: detecting the first count value of the first counter and the second count value of the second counter; and determining the output capacitance of the power semiconductor based on the first count value and the second count value.

[0065] As an optional implementation, the counting module includes: a first counter and a second counter; the output of the comparator is connected to the first counter, and the output of the inverter is connected to the second counter;

[0066] The detection of the first count value and the second count value of the counting module includes: when the voltage of the input DC source is at the target phase, detecting the first count value of the first counter and the second count value of the second counter.

[0067] As an optional implementation, the method further includes: acquiring the first comparison signal and the second comparison signal; sampling the second counter using the first comparison signal to obtain a third count value, and sampling the first counter using the second comparison signal to obtain a fourth count value; and determining the output capacitance of the power semiconductor based on the third count value and the fourth count value.

[0068] As an optional implementation, the step of sampling the second counter using the first comparison signal to obtain a third count value, and sampling the first counter using the second comparison signal to obtain a fourth count value, includes: sampling the second counter using the set edge of the first comparison signal as a first sampling point to obtain a third count value, and sampling the first counter using the set edge of the second comparison signal as a second sampling point to obtain a fourth count value.

[0069] As an optional implementation, detecting the first count value of the first counter and the second count value of the second counter includes: detecting the first count value of the first counter and the second count value of the second counter when the voltage of the input DC source is at the target phase.

[0070] As an optional implementation, determining the output capacitance of the power semiconductor based on the first count value and the second count value includes: calculating the sum of the first count value and the second count value to determine the resonant period of the output capacitance of the power semiconductor; and determining the output capacitance of the power semiconductor based on the resonant period.

[0071] As an optional implementation, determining the output capacitance of the power semiconductor based on the first count value and the second count value includes: calculating the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitance of the power semiconductor; and determining the output capacitance of the power semiconductor based on the resonant period.

[0072] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A power semiconductor output capacitance detection device applied to a power conversion circuit, characterized by, The power conversion circuit includes: an input DC source, a power semiconductor, an inductor, and a diode. The input DC source includes a positive input terminal and a negative input terminal, with the negative input terminal grounded. One end of the inductor is connected to the positive input terminal, and the negative terminal of the diode and the negative input terminal are connected to the load. The other end of the inductor, the positive terminal of the diode, and the drain of the power semiconductor are all connected to a target reference point, and the source of the power semiconductor is grounded. The device includes: a comparator, a detection module, an inverter, and a counting module; wherein, the first input terminal of the comparator is connected to the positive input terminal, the second input terminal of the comparator is connected to the target reference point, and the output terminal of the comparator is connected to the inverter and the counting module; The comparator is configured to output a first comparison signal based on the voltage at the positive input terminal and the voltage at the target reference point; The inverter is used to generate a second comparison signal based on the first comparison signal; The counting module is used to reset a first count value according to a first comparison signal and to reset a second count value according to a second comparison signal. The detection module is used to detect the first count value and the second count value of the counting module; and to determine the output capacitance of the power semiconductor based on the first count value and the second count value.

2. The apparatus of claim 1, wherein, The counting module includes: a first counter and a second counter; the output of the comparator is connected to the first counter, and the output of the inverter is connected to the second counter; The first counter is used to reset the first count value according to the first comparison signal; The second counter is used to reset the second count value according to the second comparison signal.

3. The apparatus according to claim 2, characterized in that, The first counter is specifically used for: Receive the first comparison signal, and reset the first count value when the first comparison signal has a set transition edge; The second counter is specifically used for: Receive the second comparison signal, and reset the second count value when the second comparison signal has a set transition edge; The set transition edge is a rising edge that transitions from a low level to a high level, or a falling edge that transitions from a high level to a low level.

4. The apparatus according to claim 2, characterized in that, The detection module is further configured to acquire the first comparison signal and the second comparison signal; The second counter is sampled using the first comparison signal to obtain a third count value, and the first counter is sampled using the second comparison signal to obtain a fourth count value; The output capacitance of the power semiconductor is determined based on the third and fourth count values.

5. The apparatus according to claim 4, characterized in that, The detection module is specifically used for: Using the set transition edge of the first comparison signal as the first sampling point, the second counter is sampled to obtain a third count value. Using the set transition edge of the second comparison signal as the second sampling point, the first counter is sampled to obtain a fourth count value. The set transition edge is a rising edge that transitions from a low level to a high level, or a falling edge that transitions from a high level to a low level.

6. The apparatus according to any one of claims 2-5, characterized in that, The detection module is specifically used for: When the voltage of the input DC source is at the target phase, the first count value of the first counter and the second count value of the second counter are detected.

7. The apparatus according to any one of claims 1-6, characterized in that, The detection module is specifically used for: Calculate the sum of the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; The output capacitance of the power semiconductor is determined based on the resonant period.

8. The apparatus according to any one of claims 1-6, characterized in that, The detection module is specifically used for: Calculate the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; The output capacitance of the power semiconductor is determined based on the resonant period.

9. A method for detecting the output capacitance of a power semiconductor, characterized in that, This invention is applied to a power conversion circuit, which includes: an input DC source, a power semiconductor, an inductor, and a diode. The input DC source includes a positive input terminal and a negative input terminal, with the negative input terminal grounded. One end of the inductor is connected to the positive input terminal, and the cathode of the diode and the negative input terminal are connected to a load. The other end of the inductor, the anode of the diode, and the drain of the power semiconductor are all connected to a target reference point, and the source of the power semiconductor is grounded. The power conversion circuit further includes a comparator, an inverter, and a counting module; wherein, the first input terminal of the comparator is connected to the positive input terminal, the second input terminal of the comparator is connected to the target reference point, and the output terminal of the comparator is connected to the inverter and the counting module; The comparator is configured to output a first comparison signal based on the voltage at the positive input terminal and the voltage at the target reference point; The inverter is used to generate a second comparison signal based on the first comparison signal; The counting module is used to reset a first count value according to a first comparison signal and to reset a second count value according to a second comparison signal. The method includes: The first count value and the second count value of the counting module are detected; The output capacitance of the power semiconductor is determined based on the first count value and the second count value.

10. The method according to claim 9, characterized in that, The counting module includes: a first counter and a second counter; the output of the comparator is connected to the first counter, and the output of the inverter is connected to the second counter; The detection of the first count value and the second count value of the counting module includes: When the voltage of the input DC source is at the target phase, the first count value of the first counter and the second count value of the second counter are detected.

11. The method according to claim 10, characterized in that, The method further includes: Acquire the first comparison signal and the second comparison signal; The second counter is sampled using the first comparison signal to obtain a third count value, and the first counter is sampled using the second comparison signal to obtain a fourth count value; The output capacitance of the power semiconductor is determined based on the third and fourth count values.

12. The method according to claim 11, characterized in that, The step of sampling the second counter using the first comparison signal to obtain a third count value, and sampling the first counter using the second comparison signal to obtain a fourth count value, includes: Using the set transition edge of the first comparison signal as the first sampling point, the second counter is sampled to obtain a third count value. Using the set transition edge of the second comparison signal as the second sampling point, the first counter is sampled to obtain a fourth count value.

13. The method according to any one of claims 10-12, characterized in that, Determining the output capacitance of the power semiconductor based on the first count value and the second count value includes: Calculate the sum of the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; The output capacitance of the power semiconductor is determined based on the resonant period.

14. The method according to any one of claims 10-12, characterized in that, Determining the output capacitance of the power semiconductor based on the first count value and the second count value includes: Calculate the absolute value of the difference between the first count value and the second count value to determine the resonant period of the output capacitor of the power semiconductor; The output capacitance of the power semiconductor is determined based on the resonant period.

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