Parasitic MIM capacitors and their fabrication methods, image sensors

Abstract

This application relates to a parasitic MIM capacitor and its fabrication method, as well as an image sensor. The method includes providing a semiconductor substrate with a shallow trench isolation structure; forming an etch deceleration structure and a gate structure on the side of the shallow trench isolation structure away from the semiconductor substrate based on a pre-set mask; sequentially forming an insulating layer and a wiring layer structure on the side of the etch deceleration structure away from the shallow trench isolation structure, the wiring layer structure including a first capacitor electrode plate; forming a first opening and a second opening from the side of the semiconductor substrate away from the shallow trench isolation structure; the first opening corresponds to the position of the etch deceleration structure and extends to the insulating layer, the second opening extends to the wiring layer structure; filling the first opening and the second opening with conductive material to form a second capacitor electrode plate in the first opening and a pad structure in the second opening. This application can fabricate MIM capacitors based on existing masks, eliminating the need to design and manufacture a dedicated mask for MIM capacitors, thus saving manufacturing costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a parasitic MIM capacitor and its fabrication method, and an image sensor. Background Technology

[0002] Metal-insulator-metal (MIM) capacitors are widely used in semiconductor integrated circuits due to their advantages such as low parasitic capacitance and low contact resistance.

[0003] Currently, when fabricating MIM capacitors on devices, an additional mask is usually required to form the dielectric and electrode plate shape of the MIM capacitor. This increases the manufacturing cost of the device and slows down the fabrication speed. Summary of the Invention

[0004] Therefore, it is necessary to provide a low-cost, simple-process parasitic MIM capacitor and its fabrication method, as well as an image sensor.

[0005] In a first aspect, this application provides a method for fabricating a parasitic MIM capacitor, comprising:

[0006] A semiconductor substrate is provided, wherein a shallow trench isolation structure is disposed therein;

[0007] Based on a preset mask, an etching deceleration structure and a gate structure are formed on the side of the shallow trench isolation structure away from the semiconductor substrate;

[0008] An insulating layer and a wiring layer structure are sequentially formed on the side of the etching deceleration structure away from the shallow trench isolation structure, and the wiring layer structure includes a first capacitor electrode plate.

[0009] A first opening and a second opening are formed on the side of the semiconductor substrate away from the shallow trench isolation structure; the first opening corresponds to the position of the etching deceleration structure, and the first opening extends to the insulating layer, and the second opening extends to the wiring layer structure;

[0010] Conductive material is filled into the first opening and the second opening to form a second capacitor electrode plate in the first opening and a pad structure in the second opening.

[0011] The first capacitor electrode plate, the second capacitor electrode plate, and the portion of the insulating layer between the first capacitor electrode plate and the second capacitor electrode plate constitute a MIM capacitor.

[0012] In one embodiment, the step of forming an etch deceleration structure and a gate structure on the side of the shallow trench isolation structure away from the semiconductor substrate based on a preset mask includes:

[0013] A gate material layer is deposited on one side of the semiconductor substrate where the shallow trench isolation structure is provided;

[0014] Based on the preset mask, photolithography is performed on the gate material layer to form the etching deceleration structure and the gate structure.

[0015] In one embodiment, after photolithography is performed on the gate material layer based on the preset mask to form the etching deceleration structure and the gate structure, the method further includes:

[0016] Sidewalls are formed on the sidewalls of the etching deceleration structure and the sidewalls of the gate structure.

[0017] In one embodiment, the step of photolithography on the gate material layer based on the preset mask to form the etching deceleration structure and the gate structure includes:

[0018] An anti-reflection layer is formed on the side of the gate material layer away from the shallow trench isolation structure;

[0019] A photoresist layer is formed on the side of the antireflective layer away from the gate material layer;

[0020] Based on the preset mask, the photoresist layer is patterned.

[0021] Based on the patterned photoresist layer, the gate material layer is etched to form the etching deceleration structure and the gate structure;

[0022] Remove the photoresist layer and the anti-reflective layer.

[0023] In one embodiment, the first opening includes a first sub-opening and a second sub-opening, and the second opening includes a third sub-opening and a fourth sub-opening. Forming the first and second openings from the side of the semiconductor substrate away from the shallow trench isolation structure includes:

[0024] The semiconductor substrate is etched from the side of the semiconductor substrate away from the shallow trench isolation structure to form a first sub-opening and a third sub-opening that expose the shallow trench isolation structure;

[0025] Based on the first sub-opening and the third sub-opening, the shallow trench isolation structure, the etching deceleration structure, and the insulating layer are etched to form the second sub-opening and the fourth sub-opening.

[0026] In one embodiment, the material of the etching deceleration structure includes at least one of polysilicon, metal, or a high dielectric constant material.

[0027] Secondly, this application also provides a parasitic MIM capacitor, which is prepared by the method for preparing a parasitic MIM capacitor provided in any of the above embodiments.

[0028] Thirdly, this application also provides an image sensor, comprising:

[0029] Semiconductor substrate;

[0030] A shallow trench isolation structure is located within the semiconductor substrate;

[0031] A gate structure is located on the side of the shallow trench isolation structure away from the semiconductor substrate;

[0032] An insulating layer is located on the side of the shallow trench isolation structure away from the semiconductor substrate;

[0033] A wiring layer structure is located on the side of the insulating layer away from the shallow trench isolation structure; the wiring layer structure includes a first capacitor electrode plate;

[0034] The second capacitor electrode plate extends through the semiconductor substrate, the shallow trench isolation structure, and a portion of the insulating layer from the side of the semiconductor substrate away from the shallow trench isolation structure; wherein the first capacitor electrode plate, the second capacitor electrode plate, and a portion of the insulating layer between the first capacitor electrode plate and the second capacitor electrode plate constitute a MIM capacitor.

[0035] The pad structure extends from the side of the semiconductor substrate away from the shallow trench isolation structure through the semiconductor substrate, the shallow trench isolation structure and a portion of the insulating layer, and extends to the wiring layer structure.

[0036] In one embodiment, the pad structure includes electrode leads connected to the first capacitor electrode plate.

[0037] In one embodiment, it further includes:

[0038] The photodiode is located on the side of the gate structure away from the shallow trench isolation structure and is offset from the MIM capacitor.

[0039] An unexpected benefit of this application is that, by forming an etch-decelerating structure and a gate structure on the side of the shallow trench isolation structure away from the semiconductor substrate based on a pre-set mask, the etch-decelerating structure can be formed simultaneously with the gate structure, saving the need for separate mask and process fabrication of the etch-decelerating structure. An insulating layer and a wiring layer structure are sequentially formed on the side of the etch-decelerating structure away from the shallow trench isolation structure. The wiring layer structure includes a first capacitor electrode plate. Then, the resulting structure is flipped over, and a first opening and a second opening are formed on the side of the semiconductor substrate away from the shallow trench isolation structure. The first opening corresponds to the position of the etch-decelerating structure. Due to the etch-decelerating structure… The etching selectivity of the gate structure and the insulating layer differs. The etching rate of the decelerated structure is slower, while the etching rate of the insulating layer is faster. This results in a portion of the insulating layer or interlayer insulating layer remaining between the first opening and the wiring layer structure while the second opening is being etched. This retained insulating layer or interlayer insulating layer can serve as the dielectric layer of the MIM capacitor. Then, conductive material is filled into the first and second openings to form the second capacitor electrode plate within the first opening and the pad structure within the second opening. The first capacitor electrode plate, the second capacitor electrode plate, and the insulating layer between them constitute the MIM capacitor. It can be understood that forming the decelerated structure simultaneously with the gate structure, the first opening simultaneously with the second opening, and the second capacitor electrode plate simultaneously with the pad structure saves the time required to separately fabricate the decelerated structure, the first opening, and the second capacitor electrode plate, thus accelerating the device fabrication rate. Furthermore, it eliminates the need for a dedicated mask for fabricating the first opening and the second capacitor electrode plate, reducing manufacturing costs. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of a method for fabricating an image sensor provided in one embodiment;

[0042] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S100 of the image sensor fabrication method provided in one embodiment;

[0043] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S200 of the image sensor fabrication method provided in one embodiment;

[0044] Figure 4This is a schematic cross-sectional view of the structure obtained in step S300 of the image sensor fabrication method provided in one embodiment;

[0045] Figure 5 This is a schematic cross-sectional view of the structure obtained by bonding the semiconductor structure after forming the wiring layer structure to another wafer in a step of the image sensor fabrication method provided in one embodiment.

[0046] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S410 of the image sensor fabrication method provided in one embodiment;

[0047] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S400 of the image sensor fabrication method provided in one embodiment;

[0048] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S500 of the image sensor fabrication method provided in one embodiment;

[0049] Figure 9 This is a schematic diagram of the composition of a preset mask provided in one embodiment.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - Semiconductor substrate, 200 - Shallow trench isolation structure, 300 - Etching deceleration structure, 400 - Insulating layer, 500 - Wiring layer structure, 510 - Metal layer, 511 - First capacitor electrode plate, 520 - Interlayer insulating layer, 610 - First opening, 611 - First sub-opening, 612 - Second sub-opening, 620 - Second opening, 621 - Third sub-opening, 622 - Fourth sub-opening, 710 - Second capacitor electrode plate, 720 - Pad structure, 800 - Wafer, 900 - Silicon oxide layer. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various regions, these regions should not be limited by these terms. These terms are only used to distinguish one region from another. Therefore, without departing from the teachings of this invention, the first region discussed below may be referred to as the second region; for example, a first opening may be referred to as a second opening, and similarly, a second opening may be referred to as a first opening; the first opening and the second opening are different openings.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, structures shown as rectangular areas typically have rounded or curved features at their edges. Therefore, the areas shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of areas of the device, nor do they limit the scope of the invention.

[0058] In one embodiment, such as Figure 1 As shown, this application provides a method for fabricating an image sensor, including steps S100-S500.

[0059] S100 provides a semiconductor substrate with a shallow trench isolation structure disposed therein.

[0060] like Figure 2 As shown, the semiconductor substrate 100 may include a substrate and an epitaxial wafer. The substrate and the epitaxial wafer may be made of the same material, and may be any known substrate material, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or may be double-sided polished wafers (DSP), or may be a ceramic substrate such as alumina, a quartz or glass substrate, etc., which are not limited in this embodiment. The shallow trench isolation structure 200 can be made of an oxide, such as silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof. Active devices, such as complementary metal-oxide-semiconductor (CMOS) devices, are also disposed on the semiconductor substrate. The shallow trench isolation structure 200 can be used to isolate different active devices.

[0061] S200, based on a preset mask, forms an etch deceleration structure and a gate structure on the side of the shallow trench isolation structure away from the semiconductor substrate.

[0062] The preset mask has an etching deceleration structure pattern. The preset mask can be a mask used in semiconductor manufacturing processes to fabricate gate structures, and the etching deceleration structure pattern can be added when designing the preset mask.

[0063] like Figure 3 As shown, an etch deceleration structure 300 and a gate structure (not shown) can be formed on the side of the shallow trench isolation structure 200 away from the semiconductor substrate 100 using photolithography, etching, deposition, and other processes based on a preset mask. The material of the etch deceleration structure 300 is the same as that of the gate structure. For example, the material of the etch deceleration structure may include at least one of polysilicon, metal, or a high dielectric constant material. The formation process parameters of the etch deceleration structure 300 and the gate structure are the same, and the etch deceleration structure 300 is formed in the region where the MIM capacitor needs to be formed while the gate structure is being fabricated normally.

[0064] S300, an insulating layer and a wiring layer are sequentially formed on the side of the etching deceleration structure away from the shallow trench isolation structure, and the wiring layer structure includes a first capacitor electrode plate.

[0065] like Figure 4 As shown, an insulating layer 400 and a wiring layer structure 500 can be sequentially formed on the side of the etch deceleration structure 300 away from the shallow trench isolation structure 200 using processes such as photolithography, etching, and deposition. The material of the insulating layer 400 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonide. The wiring layer structure 500 may include multiple metal layers 510 and interlayer insulating layers 520. The material of the metal layers 510 may be a combination of commonly used metal materials such as aluminum, copper, or tungsten with titanium or titanium nitride, and the interlayer insulating layer 520 may be an oxide. Figure 4 The diagram illustrates four metal layers 510. The number of metal layers 510 in the wiring layer structure 500 can also be one, two, three, five, or other numbers; this embodiment does not impose any limitations. In this embodiment, the metal layer closest to the shallow trench isolation structure 200 in the wiring layer structure 500 can be used as the first capacitor electrode plate 511.

[0066] like Figure 5 As shown, after forming the wiring layer structure 500, a silicon oxide layer 900 can be formed on the side of the wiring layer structure 500 away from the semiconductor substrate 100. The silicon oxide layer 900 is subjected to chemical mechanical polishing treatment. Afterwards, bonding can be achieved through the Si-O-Si bond formed between the silicon oxide layer 900 and another wafer 800.

[0067] S400, a first opening and a second opening are formed on the side of the semiconductor substrate away from the shallow trench isolation structure.

[0068] like Figure 7As shown, the bonded semiconductor structure can be flipped upside down (refer to the change in arrow direction in the figure). Then, photolithography and etching processes can be used to form a first opening 610 and a second opening 620 on the side of the semiconductor substrate 100 away from the shallow trench isolation structure 200. The first opening 610 corresponds to the position of the etching deceleration structure 300, and extends to the insulating layer 400, while the second opening 620 extends to the wiring layer structure 500. It can be understood that because the etching selectivity of the etching deceleration structure 300 and the insulating layer 400 is different, the etching rate of the etching deceleration structure 300 is slower, while the etching rate of the insulating layer 400 is faster. Thus, while etching to form the second opening 620 and exposing the wiring layer structure 500, a portion of the insulating layer 400 or interlayer insulating layer 520 below the etching deceleration structure 300 will be retained. The retained insulating layer 400 or interlayer insulating layer 520 can serve as a capacitor dielectric layer. The thickness of the retained insulating layer 400 or the interlayer insulating layer 520 can be changed by adjusting the thickness and material of the etching deceleration structure 300, as well as the etching time and etching rate for forming the first opening 610 and the second opening 620, thereby precisely controlling the capacitance value of the subsequently formed capacitor structure.

[0069] S500, conductive material is filled into the first opening and the second opening to form a second capacitor electrode plate in the first opening and a pad structure in the second opening.

[0070] like Figure 8As shown, the conductive material can be a combination of commonly used conductive materials such as aluminum, copper, or tungsten with titanium or titanium nitride. A deposition process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), can be used to fill the first opening 610 and the second opening 620 with conductive material, to form a second capacitor electrode plate 710 in the first opening 610 and a pad structure 720 in the second opening 620. It can be understood that the first capacitor electrode plate 511, the second capacitor electrode plate 710, and the insulating layer 400 or interlayer insulating layer 520 between the first capacitor electrode plate 511 and the second capacitor electrode plate 710 constitute a metal-insulator-metal capacitor (MIM) structure. The pad structure 720 can be used to bring out the first capacitor electrode plate 511 for connection to an external circuit, or to bring out other circuit structures in the wiring layer structure 500 for connection to an external circuit. It should be noted that the accompanying drawings of this application only illustrate the pad structure 720 used to bring out the first capacitor electrode plate 511 for connection to an external circuit; the pad structures used to bring out other circuit structures in the wiring layer structure 500 are not illustrated in the accompanying drawings.

[0071] In this embodiment, a semiconductor substrate 100 is provided, within which a shallow trench isolation structure 200 is disposed. Based on a preset mask, an etch deceleration structure 300 and a gate structure are formed on the side of the shallow trench isolation structure 200 away from the semiconductor substrate 100. Thus, the etch deceleration structure 300 can be formed simultaneously with the gate structure, saving the need for separately fabricating the mask and process for the etch deceleration structure. An insulating layer 400 and a wiring layer structure 500 are sequentially formed on the side of the etch deceleration structure 300 away from the shallow trench isolation structure 200. The wiring layer structure 500 includes a first capacitor electrode plate. Then, the resulting structure is flipped over, and a first opening 610 and a second opening 620 are formed on the side of the semiconductor substrate 100 away from the shallow trench isolation structure 200. The first opening 610 corresponds to the position of the etch deceleration structure 300. Since the etch deceleration structure 300 and the insulating layer 400 are formed simultaneously, the etch deceleration structure 300 and the gate structure 500 can be formed simultaneously, saving the need for separately fabricating the mask and process for the etch deceleration structure 300. An insulating layer 400 and a wiring layer structure 500 are sequentially formed on the side of the etch deceleration structure 300 away from the shallow trench isolation structure 200. The etching selectivity of the insulating layer 400 is different. The etching rate of the etching deceleration structure 300 is slower, while the etching rate of the insulating layer 400 is faster. This results in a portion of the insulating layer 400 or interlayer insulating layer 520 being retained between the first opening 610 and the wiring layer structure 500 while the second opening 620 is being etched. The retained insulating layer 400 or interlayer insulating layer 520 can serve as the capacitor dielectric layer of the capacitor structure to be formed later. Conductive material is filled in the first opening 610 and the second opening 620 to form the second capacitor electrode plate 710 in the first opening 610 and the pad structure 720 in the second opening 620. The first capacitor electrode plate 511, the second capacitor electrode plate 710, and the insulating layer 400 and interlayer insulating layer 520 between the first capacitor electrode plate 511 and the second capacitor electrode plate 710 constitute a metal-insulator-metal capacitor (MIM) structure. It is understood that forming the etch deceleration structure 300 simultaneously with forming the gate structure, forming the first opening 610 simultaneously with forming the second opening 620, and forming the second capacitor electrode plate 710 simultaneously with forming the pad structure 720 saves the steps of separately fabricating the etch deceleration structure 300, separately forming the first opening 610, and separately forming the second capacitor electrode plate 710, thus accelerating the device fabrication rate. Furthermore, it eliminates the need for a dedicated mask for fabricating the first opening 610 and the second capacitor electrode plate 710, thereby reducing manufacturing costs.

[0072] In one embodiment, based on a preset mask, an etch deceleration structure and a gate structure are formed on the side of the shallow trench isolation structure away from the semiconductor substrate, including steps S210-S220.

[0073] S210, deposits a gate material layer on one side of the semiconductor substrate where a shallow trench isolation structure is provided.

[0074] The gate material can be polysilicon, commonly used metal gate materials, or High-K materials. A deposition process, such as ALD, PVD, CVD, PECVD, or LPCVD, can be used to deposit the gate material on one side of the semiconductor substrate 100 where the shallow trench isolation structure 200 is provided, to form a gate material layer.

[0075] S220, based on a preset mask, performs photolithography on the gate material layer to form an etch deceleration structure and a gate structure.

[0076] like Figure 9 As shown, the preset mask can be a gate mask, including the gate pattern and the etch deceleration structure pattern. It should be noted that... Figure 9 This is merely an illustrative illustration of the added etching deceleration structure pattern on the gate mask, and does not represent the actual shape of the gate mask. The specific shape of the gate mask needs to be designed reasonably according to the actual business scenario, and this application embodiment does not impose any limitations here. Specifically, the above step S220 includes steps S221-S225.

[0077] S221, an anti-reflection layer is formed on the side of the gate material layer away from the shallow trench isolation structure.

[0078] An anti-reflection layer can be formed on the side of the gate material layer away from the shallow trench isolation structure 200 using deposition processes such as ALD, PVD, CVD, PECVD, or LPCVD. The material of the anti-reflection layer can be silicon oxynitride.

[0079] S222, a photoresist layer is formed on the side of the anti-reflective layer away from the gate material layer.

[0080] Photoresist can be coated on the side of the antireflective layer away from the gate material layer to form a photoresist layer.

[0081] S223, based on a preset mask, performs patterning processing on the photoresist layer.

[0082] The gate pattern and etching deceleration structure pattern on the preset mask can be transferred to the photoresist layer using lithography.

[0083] S224, based on the patterned photoresist layer, etches the gate material layer and anti-reflection layer to form an etching deceleration structure and a gate structure.

[0084] The dry etching process can be used to etch the gate material layer and the anti-reflection layer based on the patterned photoresist layer to form the etching deceleration structure 300 and the gate structure.

[0085] S225, remove the photoresist layer and anti-reflective layer.

[0086] In this embodiment, since the gate mask is a mask that must be designed and manufactured for the fabrication of most semiconductor devices, such as CMOS devices, the manufacturing cost is reduced by adding an etching deceleration structure pattern to the gate mask and forming the etching deceleration structure 300 at the same time as forming the gate.

[0087] In one embodiment, after photolithography is performed on the gate material layer based on a preset mask to form an etch-reducing structure and a gate structure, sidewalls can be formed on the sidewalls of the etch-reducing structure and the gate structure. Sidewalls can be formed on the sidewalls of the gate structure and the etch-reducing structure using a sidewall process. The sidewall material can be TEOS, silicon nitride, or a combination thereof. It is understood that by forming an etch-reducing pattern using the process for forming the gate structure, an etch-reducing structure is formed simultaneously with the gate structure. Similarly, if a sidewall process is used to form sidewalls on the sidewalls of the gate structure, sidewalls will also be formed on the sidewalls of the etch-reducing structure.

[0088] In one embodiment, such as Figure 6 and Figure 7 As shown, the first opening 610 includes a first sub-opening 611 and a second sub-opening 612. The second opening 620 includes a third sub-opening 621 and a fourth sub-opening 622. The first opening and the second opening are formed from the side of the semiconductor substrate away from the shallow trench isolation structure, including steps S410-S420.

[0089] S410, etching the semiconductor substrate from the side of the semiconductor substrate away from the shallow trench isolation structure to form a first sub-opening and a third sub-opening that expose the shallow trench isolation structure.

[0090] like Figure 6 As shown, a dry etching process can be used to etch the semiconductor substrate 100 from the side away from the shallow trench isolation structure 200 to form a first sub-opening 611 and a third sub-opening 621 that expose the shallow trench isolation structure 200.

[0091] S420, based on the first sub-aperture and the third sub-aperture, etch a shallow trench isolation structure, etch a deceleration structure and an insulating layer to form a second sub-aperture and a fourth sub-aperture.

[0092] like Figure 7 As shown, a dry etching process can be used to etch the shallow trench isolation structure 200, the etching deceleration structure 300, and part of the insulating layer 400 to form the second sub-opening 612 based on the first sub-opening 611. A dry etching process can also be used to etch the shallow trench isolation structure 200, the etching deceleration structure 300, and the insulating layer 400 based on the third sub-opening 621 to form the fourth sub-opening 622 that exposes the wiring layer structure 500.

[0093] In this embodiment, the third sub-opening 621 and the fourth sub-opening 622 are used to position the pad structure 720, and the first sub-opening 611 and the second sub-opening 612 are used to position the second capacitor electrode plate 710. The first sub-opening 611 is formed at the same time as the third sub-opening 621, and the second sub-opening 612 is formed at the same time as the fourth sub-opening 622. This can save the process steps of forming the first sub-opening 611 and the second sub-opening 612 separately. Moreover, the first sub-opening 611 and the third sub-opening 621 can use the same mask, and the second sub-opening 612 and the fourth sub-opening 622 can use the same mask, which saves the manufacturing cost of the mask.

[0094] It should be understood that, although Figure 1 The steps in the flowchart are shown in the order illustrated, but these steps are not necessarily executed in that order. Unless otherwise specified herein, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0095] In one embodiment, based on the same inventive concept, this application also provides a parasitic MIM capacitor, such as... Figure 8 As shown, it includes a first capacitor electrode plate, a capacitor dielectric layer, and a second capacitor electrode plate. It can be fabricated using the method for preparing parasitic MIM capacitors provided in any of the above embodiments.

[0096] In one embodiment, this application also provides an image sensor, such as... Figure 8As shown, the structure includes a semiconductor substrate 100, a shallow trench isolation structure 200, a gate structure (not shown), an insulating layer 400, a wiring layer structure 500, a second capacitor electrode plate 710, and a pad structure 720. The shallow trench isolation structure 200 is located within the semiconductor substrate 100. The gate structure is located on the side of the shallow trench isolation structure 200 away from the semiconductor substrate 100. The insulating layer 400 is located on the side of the shallow trench isolation structure 200 away from the semiconductor substrate 100. The material of the insulating layer 400 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonide. The wiring layer structure 500 is located on the side of the insulating layer 400 away from the shallow trench isolation structure 200 and includes a first capacitor electrode plate 511. The wiring layer structure 500 may include multiple metal layers 510 and interlayer insulating layers 520. The material of the metal layers 510 may be a combination of commonly used metal materials such as aluminum, copper, or tungsten with titanium or titanium nitride. The interlayer insulating layer 520 may be an oxide. The metal layer closest to the shallow trench isolation structure 200 in the wiring layer structure 500 can be used as the first capacitor electrode plate 511. The second capacitor electrode plate 710 extends through the semiconductor substrate 100, the shallow trench isolation structure 200, and part of the insulating layer 400 from the side of the semiconductor substrate 100 away from the shallow trench isolation structure 200. The pad structure 720 extends through the semiconductor substrate 100, the shallow trench isolation structure 200, and part of the insulating layer 400 from the side of the semiconductor substrate 100 away from the shallow trench isolation structure 200, and extends into the wiring layer structure 500. The materials of the second capacitor electrode plate 710 and the pad structure 720 can be combinations of commonly used conductive materials such as aluminum, copper, or tungsten with titanium or titanium nitride, respectively. The pad structure 720 can be used to lead out the first capacitor electrode plate for connection to an external circuit, or to lead out other circuit structures in the wiring layer structure 500 for connection to an external circuit.

[0097] In this embodiment, the image sensor includes a semiconductor substrate 100, a gate mechanism, a shallow trench isolation structure 200, an insulating layer 400, a wiring layer structure 500, a second capacitor electrode plate 710, and a pad structure 720. The wiring layer structure 500 includes a first capacitor electrode plate 511. The first capacitor electrode plate 511, the second capacitor electrode plate 710, and the insulating layer 400 between the first and second capacitor electrode plates 710 constitute a metal-insulator-metal capacitor (MIM) structure. This MIM capacitor can be completed simultaneously with the metal wiring and pad fabrication processes of the image sensor, reducing additional process steps such as photolithography and etching, and significantly lowering process complexity and production costs.

[0098] In one embodiment, the pad structure 720 includes electrode plate leads connected to a first capacitor electrode plate 511. The electrode plate leads are used to lead out the first capacitor electrode plate 511 and connect it to an external circuit.

[0099] In one embodiment, the image sensor further includes a photodiode. The photodiode is located on the side of the gate structure away from the shallow trench isolation structure 200 and is offset from the MIM capacitor, so that light can be directly incident on the photodiode, increasing the light sensitivity of the image sensor.

[0100] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a parasitic MIM capacitor, characterized in that, include: A semiconductor substrate is provided, wherein a shallow trench isolation structure is disposed therein; Based on a preset mask, an etching deceleration structure and a gate structure are formed on the side of the shallow trench isolation structure away from the semiconductor substrate; An insulating layer and a wiring layer structure are sequentially formed on the side of the etching deceleration structure away from the shallow trench isolation structure, and the wiring layer structure includes a first capacitor electrode plate. A first opening and a second opening are formed on the side of the semiconductor substrate away from the shallow trench isolation structure; The first opening corresponds to the position of the etching deceleration structure, and the first opening extends to the insulating layer, while the second opening extends to the wiring layer structure. Conductive material is filled into the first opening and the second opening to form a second capacitor electrode plate in the first opening and a pad structure in the second opening. The first capacitor electrode plate, the second capacitor electrode plate, and the portion of the insulating layer between the first capacitor electrode plate and the second capacitor electrode plate constitute a MIM capacitor.

2. The method according to claim 1, characterized in that, The step of forming an etch deceleration structure and a gate structure on the side of the shallow trench isolation structure away from the semiconductor substrate, based on a preset mask, includes: A gate material layer is deposited on one side of the semiconductor substrate where the shallow trench isolation structure is provided; Based on the preset mask, photolithography is performed on the gate material layer to form the etching deceleration structure and the gate structure.

3. The method according to claim 2, characterized in that, After performing photolithography on the gate material layer based on the preset mask to form the etching deceleration structure and the gate structure, the method further includes: Sidewalls are formed on the sidewalls of the etching deceleration structure and the sidewalls of the gate structure.

4. The method according to claim 2, characterized in that, The step of performing photolithography on the gate material layer based on the preset mask to form the etching deceleration structure and the gate structure includes: An anti-reflection layer is formed on the side of the gate material layer away from the shallow trench isolation structure; A photoresist layer is formed on the side of the antireflective layer away from the gate material layer; Based on the preset mask, the photoresist layer is patterned. Based on the patterned photoresist layer, the gate material layer is etched to form the etching deceleration structure and the gate structure; Remove the photoresist layer and the anti-reflective layer.

5. The method according to claim 1, characterized in that, The first opening includes a first sub-opening and a second sub-opening, and the second opening includes a third sub-opening and a fourth sub-opening. The formation of the first and second openings from the side of the semiconductor substrate away from the shallow trench isolation structure includes: The semiconductor substrate is etched from the side of the semiconductor substrate away from the shallow trench isolation structure to form a first sub-opening and a third sub-opening that expose the shallow trench isolation structure; Based on the first sub-opening and the third sub-opening, the shallow trench isolation structure, the etching deceleration structure, and the insulating layer are etched to form the second sub-opening and the fourth sub-opening.

6. The method according to any one of claims 1-5, characterized in that, The material of the etching deceleration structure includes at least one of polycrystalline silicon, metal, or a material with a high dielectric constant.

7. A parasitic MIM capacitor, characterized in that, It is prepared by the method for preparing parasitic MIM capacitors according to any one of claims 1-6.

8. An image sensor, characterized in that, include: Semiconductor substrate; A shallow trench isolation structure is located within the semiconductor substrate; A gate structure is located on the side of the shallow trench isolation structure away from the semiconductor substrate; An insulating layer is located on the side of the shallow trench isolation structure away from the semiconductor substrate; A wiring layer structure is located on the side of the insulating layer away from the shallow trench isolation structure; the wiring layer structure includes a first capacitor electrode plate; The second capacitor electrode plate extends through the semiconductor substrate, the shallow trench isolation structure, and a portion of the insulating layer from the side of the semiconductor substrate away from the shallow trench isolation structure; wherein the first capacitor electrode plate, the second capacitor electrode plate, and a portion of the insulating layer between the first capacitor electrode plate and the second capacitor electrode plate constitute a MIM capacitor. The pad structure extends from the side of the semiconductor substrate away from the shallow trench isolation structure through the semiconductor substrate, the shallow trench isolation structure and a portion of the insulating layer, and extends to the wiring layer structure.

9. The image sensor according to claim 8, characterized in that, The pad structure includes electrode plate leads, which are connected to the first capacitor electrode plate.

10. The image sensor according to claim 8, characterized in that, Also includes: The photodiode is located on the side of the gate structure away from the shallow trench isolation structure and is offset from the MIM capacitor.

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