Flip-light-emitting diode chip and method for manufacturing the same

Abstract

The present invention provides a flip light-emitting diode chip and a method for manufacturing the same, comprising a substrate, an N-type semiconductor layer sequentially deposited on the substrate, an active light-emitting layer, a P-type semiconductor layer, a current-diffusing layer, a first insulating layer, a Bragg reflective layer, a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer, and a pad layer, wherein the connecting metal layer comprises a reflective layer arranged from bottom to top, and a protective layer comprising a first protective matrix, a second protective matrix, and a third protective matrix arranged from bottom to top, wherein the second protective matrix comprises n first protective sublayers and second protective sublayers arranged in a periodically stacked manner, the thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a flip light-emitting diode chip and a manufacturing method thereof.

Background Art

[0002] In recent years, the manufacturing process of light-emitting diode chips has developed rapidly under the competition of major manufacturers and is widely applied in various fields such as general lighting, special lighting, direct-view displays, backlight displays, lamps, and the like. The flip light-emitting diode chip has higher color contrast, brightness, color gamut, longer lifespan, thinner thickness, is more resistant to the impact of high current, has high reliability, high luminous efficiency, emits light from the back surface, has high heat dissipation capacity, high soldering property, and high reliability, and is widely applied.

[0003] In the prior art, in the manufacturing process of conventional flip light-emitting diode chips, the manufacturing method of the opening of the third insulating layer is a dry etching manufacturing process, and the wet etching manufacturing process cannot be used. Wet etching causes etching of Al, which is the reflective metal at the bottom of the connecting electrode, resulting in cavities and bulges of Al, and ultimately affecting the optoelectronic performance and reliability of the flip light-emitting diode chip. Moreover, when the opening of the third insulating layer is provided by a dry etching method, separate photolithography needs to be performed in the area where the opening needs to be provided in the third insulating layer.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of this, an object of the present invention is to provide a flip light-emitting diode chip and a manufacturing method thereof that can preferentially solve the above-mentioned drawbacks of the prior art.

Means for Solving the Problems

[0005] A method for manufacturing a flip light-emitting diode chip, The system includes a substrate, an N-type semiconductor layer sequentially deposited on the substrate, an active light-emitting layer, a P-type semiconductor layer, a current-diffusing layer, a first insulating layer, a Bragg reflective layer, a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer, and a pad layer. The connecting metal layer includes a reflective layer arranged from bottom to top, and a protective layer comprising a first protective matrix, a second protective matrix, and a third protective matrix arranged from bottom to top, wherein the second protective matrix includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner. A manufacturing method in which the thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer. Furthermore, the material of the reflective layer is metal A1, and the thickness of the reflective layer is greater than 1200 Å. Furthermore, the material of the first protective matrix is ​​metallic Cr, and the thickness of the first protective matrix is ​​greater than 5000 Å. Furthermore, the aforementioned second protective matrix has a period of n ≥ 3. Furthermore, the material of the first protective sublayer is metallic Ni, and the thickness of the first protective sublayer increases linearly from 200 Å to 500 Å toward the third insulating layer. Furthermore, the material of the second protective sublayer is metallic Cr, and the thickness of the second protective sublayer gradually decreases linearly from 500 Å to 1000 Å toward the third insulating layer. Furthermore, the material of the third protective matrix is ​​metallic Ni, and the thickness of the third protective matrix is ​​3000 Å to 5000 Å. In another embodiment, the present invention further provides a method for manufacturing a flip light-emitting diode chip, which includes the following steps: Step S1 involves providing a substrate and sequentially depositing an N-type semiconductor layer, an active luminescence layer, and a P-type semiconductor layer onto the substrate; Step S2: Manufacturing an N-type semiconductor conductive step on the P-type semiconductor layer; Step S3: Manufacturing a current diffusion layer on the P-type semiconductor layer and the N-type semiconductor conductive step; Step S4: Manufacturing a first insulating layer on the current diffusion layer; Step S5: Forming a Bragg reflective layer and through holes for the Bragg reflective layer on the first insulating layer; Step S6: Manufacturing the Bragg reflective layer, the through-holes for the Bragg reflective layer, and the first through-holes for the first insulating layer on the first insulating layer; Step S7: Manufacturing a metal reflective layer on the Bragg reflective layer, the through-holes for the Bragg reflective layer, and the through-holes for the first insulating layer; Step S8: To manufacture a second insulating layer and through holes for the second insulating layer in the area not covered by the metal reflective layer; Step S9: Manufacturing a connecting metal layer on the second insulating layer and the through-hole for the second insulating layer; Step S10: to manufacture a third insulating layer and through holes for the third insulating layer on the connecting metal layer and a second insulating layer not covered by the connecting metal layer; and Step S11: Manufacturing a pad layer on the through-hole for the third insulating layer; The connecting metal layer includes a reflective layer arranged from bottom to top, and a protective layer comprising a first protective matrix, a second protective matrix, and a third protective matrix arranged from bottom to top, wherein the second protective matrix includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner. The thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer. Furthermore, step S10 includes the following steps for manufacturing the third insulating layer and the through-holes for the third insulating layer. SiO2 is deposited as a third insulating layer on the connecting metal layer and the second insulating layer not covered by the connecting metal layer by the PECVD method, then a photoresist is applied to the third insulating layer, and then a portion of the photoresist is removed by exposure and development to expose a portion of the third insulating layer, and further a portion of the exposed third insulating layer is removed with a BOE etching solution to form through holes for the third insulating layer. Furthermore, step S11 includes the following steps for manufacturing the pad layer: Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, and AuSn metal are sequentially deposited as pad layers on the through-holes for the third insulating layer by electron beam deposition. Then, the metal on the photoresist is removed by a bloom-type peeling process, and finally the photoresist is removed. Compared to the prior art, the present invention provides the advantage of providing a connecting metal layer that includes a reflective layer and a protective layer from below, and providing the protective layer that includes a first protective matrix, a second protective matrix, and a third protective matrix from below, thereby protecting the reflective layer of the connecting electrode with the protective layer, and effectively preventing the etching solution from etching the reflective layer of the connecting electrode when the through-hole for the third insulating layer is manufactured by a wet etching process. By setting it up in this way, the pad layer can be manufactured together with the through-hole for the third insulating layer in a single photolithography process, eliminating the need to perform a separate photolithography process on the opening region of the third insulating layer, and thus reducing the manufacturing cost of the flip light-emitting diode chip. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic cross-sectional view showing a flip-light-emitting diode chip in Embodiment 1 of the present invention. [Figure 2] This is a schematic cross-sectional view showing the connecting metal layer in Embodiment 1 of the present invention. [Figure 3] This is a flowchart showing the manufacturing method for a flip-light-emitting diode chip in Example 2 of the present invention. [Explanation of Symbols]

[0007] JPEG2026529030000002.jpg76147 Hereinafter, embodiments of the present invention will be described with reference to the above drawings. [Modes for carrying out the invention]

[0008] To facilitate understanding of the present invention, the invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be realized in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for the purpose of making the disclosure of the present invention more complete and comprehensive. When an element is said to be “attached” to another element, it may be directly on top of the other element or the elements may exist between them. When an element is considered to be “connected” to another element, it may be directly connected to the other element or the elements may exist simultaneously between them. The terms “vertical,” “horizontal,” “left,” and “right” and similar expressions used herein are for illustrative purposes only.

[0009] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art relating to the present invention. Terms used in this specification are solely for the purpose of describing specific embodiments and are not intended to limit the invention. The terms "and / or" used herein include any and all combinations of one or more items listed in relation to the present invention.

[0010] Example 1 Referring to Figures 1 and 2, the flip light-emitting diode chip according to an embodiment of the present invention includes a substrate 10, an N-type semiconductor layer 111 sequentially deposited on the substrate, an active light-emitting layer 112, a P-type semiconductor layer 113, a current diffusion layer 12, a first insulating layer 13, a Bragg reflective layer 14, a metal reflective layer 15, a second insulating layer 16, a connecting metal layer 17, a third insulating layer 18, and a pad layer 19. The connecting metal layer 17 includes a reflective layer 171 arranged from bottom to top, and a protective layer 172 which includes a first protective matrix 1721, a second protective matrix 1722, and a third protective matrix 1723 arranged from bottom to top, wherein the second protective matrix 1722 includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner.

[0011] Furthermore, the material of the reflective layer 171 is metal Al, and the thickness of the reflective layer 171 is greater than 1200 Å.

[0012] Furthermore, the material of the first protective mother layer 1721 is metal Cr, and the thickness of the first protective mother layer 1721 is greater than 5000 Å.

[0013] Furthermore, the second protective mother layer 1722 has a period n≥3.

[0014] Furthermore, the material of the third protective mother layer 1723 is metal Ni, and the thickness of the third protective mother layer 1723 is in the range of 3000 Å to 5000 Å.

[0015] The thickness of the first protective sub-layer increases linearly towards the third insulating layer 18, and the thickness of the second protective sub-layer decreases linearly towards the third insulating layer 18.

[0016] Furthermore, the material of the first protective sub-layer is metal Ni, and the thickness of the first protective sub-layer increases linearly by 200 Å to 500 Å towards the third insulating layer.

[0017] Furthermore, the material of the second protective sub-layer is metal Cr, and the thickness of the second protective sub-layer decreases linearly by 500 Å to 1000 Å towards the third insulating layer.

[0018] By providing the connecting metal layer 17 from below to include the reflective layer 171 and the protective layer 172, and providing the protective layer 172 from below to include a first protective matrix 1721, a second protective matrix 1722, and a third protective matrix 1723, the protective layer 172 protects the reflective layer 171 of the connecting electrode. When the through-hole for the third insulating layer is then manufactured by a wet etching process, the etching solution can be effectively prevented from etching the reflective layer 171 of the connecting electrode. By providing the pad layer 19 together with the through-hole for the third insulating layer in a single photolithography process, there is no need to perform a separate photolithography process for the opening region of the third insulating layer 18, thus reducing the manufacturing cost of the flip light-emitting diode chip.

[0019] Example 2 Referring to Figure 3, Embodiment 2 of the present invention provides a manufacturing method for producing the flip light-emitting diode chip described in Embodiment 1, comprising the following steps.

[0020] Step S1 involves providing a substrate 10 and sequentially depositing an N-type semiconductor layer 111, an active luminescence layer 112, and a P-type semiconductor layer 113 onto the substrate 10; In this embodiment, the specific process for depositing the N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 is as follows.

[0021] The substrate 10 is provided, and thereafter, the N-type semiconductor layer 111, the active luminescence layer 112, and the P-type semiconductor layer 113 are sequentially deposited on the substrate 10 by MOCVD, and the substrate 10 may be a GaN substrate, an Al2O3 substrate, or a Si substrate.

[0022] Step S2: Manufacturing an N-type semiconductor conductive step 114 on the P-type semiconductor layer 113; In this embodiment, the specific process for manufacturing the N-type semiconductor conductive step 114 is as follows.

[0023] A photoresist is applied to the surface of the P-type semiconductor layer 113, then a portion of the photoresist is removed by exposure and development to expose a portion of the P-type semiconductor layer, and then a portion of the exposed P-type semiconductor layer and the active light-emitting layer beneath it are removed by inductively coupled plasma etching to form the N-type semiconductor conductive step 114, and the photoresist is removed.

[0024] Step S3: Manufacturing a current diffusion layer 12 on the P-type semiconductor layer 113 and the N-type semiconductor conductive step 114; In this embodiment, the specific process for manufacturing the current diffusion layer 12 is as follows: Indium tin oxide is deposited onto the surfaces of the P-type semiconductor layer 113 and the N-type semiconductor conductive step 114 by a magnetron sputtering process. Next, a photoresist is applied to the surface of the indium tin oxide, and a portion of the photoresist is removed by exposure and development to expose a portion of the indium tin oxide. Next, a portion of the exposed indium tin oxide is removed with an etching solution for the indium tin oxide, the temperature of which is controlled to 45±5℃. Finally, the photoresist is removed to form the current diffusion layer 12.

[0025] Step S4: Manufacturing a first insulating layer 13 on the current diffusion layer 12; In this embodiment, the specific process for manufacturing the first insulating layer 13 is as follows. SiO2 is deposited as the first insulating layer 13 on the surfaces of the current diffusion layer 12, the P-type semiconductor layer 113, and the N-type semiconductor conductive step 114 by PECVD, the thickness of the first insulating layer 13 is greater than 5000 Å, and the temperature during the execution of the PECVD method is controlled to 270 ± 10°C. Step S5: Forming a Bragg reflective layer 14 and through holes for the Bragg reflective layer on the first insulating layer 13; In this embodiment, the specific process for manufacturing the Bragg reflective layer 14 and the through-holes for the Bragg reflective layer is as follows.

[0026] Using an electron beam deposition method, 2 to 10 sets of TiO2 and SiO2 layers are sequentially deposited on the surface of the first insulating layer 13 as the Bragg reflective layer 14. Next, a photoresist is applied to the surface of the Bragg reflective layer 14, and a portion of the photoresist on the Bragg reflective layer is removed by exposure and development. A portion of the exposed Bragg reflective layer is removed by inductively coupled plasma etching to form through-holes for the Bragg reflective layer. The first insulating layer below these through-holes for the Bragg reflective layer is then exposed, and the photoresist is removed.

[0027] Step S6: Manufacturing the Bragg reflective layer 14, the through-holes for the Bragg reflective layer, and the first through-holes for the first insulating layer on the first insulating layer 13; In this embodiment, the specific process for manufacturing the through-hole for the first insulating layer is as follows:

[0028] Photoresist is applied to the surface of the Bragg reflective layer 14, the through-hole for the Bragg reflective layer, and the first insulating layer 13. Part of the photoresist in the through-hole for the Bragg reflective layer is removed by exposure and development to expose the first insulating layer below the through-hole for the Bragg reflective layer. Subsequently, the exposed first insulating layer is removed with BOE etching solution to form the first through-hole for the insulating layer, and the photoresist is removed.

[0029] Step S7: Manufacturing a metal reflective layer 15 on the Bragg reflective layer, the through-holes for the Bragg reflective layer, and the through-holes for the first insulating layer; In this embodiment, the specific process for manufacturing the metal reflective layer 15 is as follows. Photoresist is applied to the Bragg reflective layer 14, the through-holes for the Bragg reflective layer, the through-holes for the first insulating layer, and the exposed areas of the first insulating layer through-holes. Then, a portion of the photoresist is removed by exposure and development. Ag metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, and Ti metal are sequentially deposited as the metal reflective layer 15 by electron beam deposition. Then, the metal on the photoresist is removed by a bloom-type peeling process, and then the photoresist is removed.

[0030] Step S8: To create a second insulating layer 16 and through holes for the second insulating layer in the area not covered by the metal reflective layer 15; In this embodiment, the specific process for manufacturing the second insulating layer 16 and the through-holes for the second insulating layer is as follows.

[0031] Al2O3 is deposited on the surface of the metal reflective layer 15 and the area not covered by the metal reflective layer 15 by atomic layer deposition, with the temperature of the atomic layer deposition controlled to 200±10℃. Subsequently, SiO2 is deposited on the surface of the Al2O3 by plasma chemical vapor deposition, with the temperature of the plasma chemical vapor deposition controlled to 270±10℃. The Al2O3 and SiO2 laminate is deposited as the second insulating layer 16. A photoresist is applied to the surface of the second insulating layer 16. Part of the photoresist is removed by exposure and development to expose part of the second insulating layer. Part of the exposed second insulating layer is removed by inductively coupled plasma etching to form through holes for the second insulating layer, and the photoresist is removed.

[0032] Step S9: Manufacturing a connecting metal layer 17 on the second insulating layer 16 and the through-hole for the second insulating layer; In this embodiment, the specific process for manufacturing the connecting metal layer 17 is as follows. Photoresist is applied to the surface of the second insulating layer 16 and the through-holes for the second insulating layer, a portion of the photoresist is removed by exposure and development, metallic Al with a thickness greater than 1200 Å is deposited as the reflective layer 171 by electron beam deposition, the protective layer 172 is then deposited on the reflective layer 171 by electron beam deposition, the laminate of the reflective layer 171 and the protective layer 172 is deposited as the connecting metal layer 17, the metal on the photoresist is removed by a bloom-type peeling process, and then the photoresist is removed.

[0033] In this embodiment, the specific process for manufacturing the protective layer 172 is as follows: As the first protective matrix 1721, metallic Cr with a thickness greater than 5000 Å is deposited on the reflective layer 171 by electron beam deposition; as the first protective sublayer 1721, metallic Ni is deposited on the first protective matrix 1721 by electron beam deposition; as the second protective sublayer 1722, metallic Cr is deposited on the first protective sublayer by electron beam deposition; as the second protective matrix 1722, the first protective sublayer and the second protective sublayer are repeated N times to produce the protective matrix 1722; and finally, as the third protective matrix 1723, metallic Ni with a thickness of 3000 Å to 5000 Å is deposited on the second protective matrix 1722 by electron beam deposition; and the stacked layers of the first protective matrix 1721, the second protective matrix 1722, and the third protective matrix 1723 are deposited as the protective layer 172.

[0034] Furthermore, the thickness of the first protective sublayer increases linearly by 200 Å to 500 Å toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly by 500 Å to 1000 Å toward the third insulating layer.

[0035] Specifically, in this embodiment, the first protective matrix 1721 is metallic Cr with a thickness of 10,000 Å. The first and second protective sublayers in the second protective matrix 1722 have a period n of 3. The thickness of the first protective sublayer increases linearly by 500 Å toward the third insulating layer. The thickness of the second protective sublayer decreases linearly by 1,000 Å toward the third insulating layer. The thicknesses of the first protective sublayers from bottom to top are 500 Å, 1,000 Å, and 1,500 Å. The thicknesses of the second protective sublayers from bottom to top are 3,000 Å, 2,000 Å, and 1,000 Å. The third protective matrix 1723 is metallic Ni with a thickness of 5,000 Å.

[0036] Step S10: To manufacture a third insulating layer and through holes for the third insulating layer on the connecting metal layer 17 and the second insulating layer 16 not covered by the connecting metal layer 17; Furthermore, step S10 includes the following steps for manufacturing the third insulating layer and the through-holes for the third insulating layer.

[0037] SiO2 is deposited as a third insulating layer 18 on the connecting metal layer 17 and the second insulating layer 16 not covered by the connecting metal layer 17 by PECVD, with the temperature during the execution of the PECVD method controlled to 270±10℃. Next, a photoresist is applied on the third insulating layer 18, and then a portion of the photoresist is removed by exposure and development to expose a portion of the third insulating layer. Further, a portion of the exposed third insulating layer is removed with BOE etching solution to form through holes for the third insulating layer.

[0038] Step S11: Manufacturing a pad layer 19 on the through-hole for the third insulating layer; Furthermore, step S11 includes the following steps for manufacturing the pad layer 19.

[0039] Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, and AuSn metal are sequentially deposited as a pad layer 19 on the through-holes for the third insulating layer by electron beam deposition. Then, the metal on the photoresist is removed by a bloom-type peeling process, and finally the photoresist is removed.

[0040] The connecting metal layer 17 includes a reflective layer 171 arranged from bottom to top, and a protective layer 172 which includes a first protective matrix 1721, a second protective matrix 1722, and a third protective matrix 1723 arranged from bottom to top, wherein the second protective matrix 1722 includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner.

[0041] The thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer.

[0042] Comparative Example 1 This is a flip-up light-emitting diode chip, and the differences from the flip-up light-emitting diode chip manufactured in Example 2 are as follows: The thickness of the first protective sublayer increases linearly by 200 Å toward the third insulating layer. The thickness of the second protective sublayer decreases linearly by 500 Å toward the third insulating layer. The thicknesses of the first protective sublayers from bottom to top are 200 Å, 400 Å, and 600 Å. The thicknesses of the second protective sublayers from bottom to top are 2000 Å, 1500 Å, and 1000 Å. Comparative Example 2 This is a flip-up light-emitting diode chip, and the differences from the flip-up light-emitting diode chip manufactured in Example 2 are as follows: The first protective matrix is ​​metallic Cr with a thickness of 8000 Å, and the third protective matrix is ​​metallic Ni with a thickness of 3000 Å.

[0043] Comparative Example 3 This is a flip-up light-emitting diode chip, and the differences from the flip-up light-emitting diode chip manufactured in Example 2 are as follows: The first protective matrix is ​​metallic Cr with a thickness of 8000 Å, and the thickness of the first protective sublayer increases linearly by 200 Å toward the third insulating layer. The thickness of the second protective sublayer decreases linearly by 500 Å toward the third insulating layer. The thicknesses of the first protective sublayers from bottom to top are 200 Å, 400 Å, and 600 Å. The thicknesses of the second protective sublayers from bottom to top are 2000 Å, 1500 Å, and 1000 Å. The third protective matrix is ​​metallic Ni with a thickness of 3000 Å.

[0044] Comparative Example 4 This is a flip-up light-emitting diode chip, and the differences from the flip-up light-emitting diode chip manufactured in Example 2 are as follows: The protective layer does not include a second protective matrix; the first protective matrix is ​​metallic Ti with a thickness of 2000 Å, and the third protective matrix is ​​metallic Pt with a thickness of 500 Å.

[0045] Comparative Example 5 This is a flip-up light-emitting diode chip, and the differences from the flip-up light-emitting diode chip manufactured in Example 2 are as follows: The protective layer does not include the second and third protective matrix layers, and the first protective matrix layer is metallic Pt with a thickness of 500 Å.

[0046] The table below shows the results of comparing the ESD yield of the flip-light-emitting diode chip manufactured in Example 2 and the flip-light-emitting diode chips of Comparative Examples 1 to 5.

[0047] JPEG2026529030000003.jpg59152

[0048] Furthermore, in order to guarantee the reliability of the verification results, when comparing the ESD yield of the flip-light-emitting diode chip manufactured in Example 2 of the present invention with the flip-light-emitting diode chips of Comparative Examples 1 to 5, all other processes and parameters must be the same, except for the above-mentioned parameters.

[0049] As can be seen from the table above, the flip-light-emitting diode chip manufactured in Example 2 of the present invention and the flip-light-emitting diode chips provided in Comparative Examples 1 to 3 showed a significant improvement in ESD yield compared to the flip-light-emitting diode chips provided in Comparative Examples 4 and 5.

[0050] As described above, in the flip light-emitting diode chip and its manufacturing method according to the above embodiment of the present invention, the connecting metal layer is provided with a reflective layer and a protective layer from below, and the protective layer is provided with a first protective matrix, a second protective matrix, and a third protective matrix from below, thereby protecting the reflective layer of the connecting electrode with the protective layer, and when the through-hole for the third insulating layer is manufactured by a wet etching process, the etching solution can be effectively prevented from etching the reflective layer of the connecting electrode. By setting it up in this way, the pad layer can be manufactured together with the through-hole for the third insulating layer in a single photolithography process, eliminating the need to perform a separate photolithography process on the opening region of the third insulating layer, and thus reducing the manufacturing cost of the flip light-emitting diode chip. In this specification, reference terms such as “one example,” “several examples,” “example,” “specific example,” or “several examples” mean that the specific features, structures, materials, or properties described in that example or example are included in at least one example or example of the present invention in combination with those features, structures, materials, or properties. In this specification, illustrative descriptions of the above terms do not necessarily refer to the same example or example. Furthermore, the specific features, structures, materials, or properties described may be combined in an appropriate manner in any of the one or more examples or examples.

[0051] The embodiments described above merely illustrate some of the embodiments of the present invention, and although the description is relatively specific and detailed, it should not be understood as limiting the scope of the patent for the present invention. Furthermore, those skilled in the art can make some modifications and improvements without deviating from the spirit of the present invention, and all of these fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for the present invention should be in accordance with the appended claims.

Claims

1. The system includes a substrate, an N-type semiconductor layer sequentially deposited on the substrate, an active light-emitting layer, a P-type semiconductor layer, a current-diffusing layer, a first insulating layer, a Bragg reflective layer, a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer, and a pad layer. The connecting metal layer includes a reflective layer arranged from bottom to top, and a protective layer including a first protective matrix, a second protective matrix, and a third protective matrix arranged from bottom to top, wherein the second protective matrix includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner. A flip-light-emitting diode chip characterized in that the thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer.

2. The flip-light-emitting diode chip according to claim 1, characterized in that the material of the reflective layer is metal A1, and the thickness of the reflective layer is greater than 1200 Å.

3. The flip-light-emitting diode chip according to claim 1, characterized in that the material of the first protective matrix is ​​metallic Cr, and the thickness of the first protective matrix is ​​greater than 5000 Å.

4. The flip-light-emitting diode chip according to claim 1, characterized in that the second protective matrix has a period n ≥ 3.

5. The flip light-emitting diode chip according to claim 1, characterized in that the material of the first protective sublayer is metallic Ni, and the thickness of the first protective sublayer increases linearly from 200 Å to 500 Å toward the third insulating layer.

6. The flip light-emitting diode chip according to claim 1, characterized in that the material of the second protective sublayer is metallic Cr, and the thickness of the second protective sublayer gradually decreases linearly from 500 Å to 1000 Å toward the third insulating layer.

7. The flip light-emitting diode chip according to claim 1, characterized in that the material of the third protective matrix is ​​metallic Ni, and the thickness of the third protective matrix is ​​3000 Å to 5000 Å.

8. A method for manufacturing a flip light-emitting diode chip, comprising the following steps: Step S1 involves providing a substrate and sequentially depositing an N-type semiconductor layer, an active luminescence layer, and a P-type semiconductor layer onto the substrate. Step S2 is to manufacture an N-type semiconductor conductive step on the P-type semiconductor layer, Step S3 involves manufacturing a current diffusion layer on the P-type semiconductor layer and the N-type semiconductor conductive step, Step S4 involves manufacturing a first insulating layer on the current diffusion layer, Step S5 involves forming a Bragg reflective layer and through holes for the Bragg reflective layer on the first insulating layer, Step S6 involves manufacturing the Bragg reflective layer, the through-holes for the Bragg reflective layer, and the first through-holes for the first insulating layer on the first insulating layer, Step S7 involves manufacturing a metal reflective layer on the Bragg reflective layer, the through-holes for the Bragg reflective layer, and the through-holes for the first insulating layer. Step S8 involves manufacturing a second insulating layer and through holes for the second insulating layer in the region not covered by the metal reflective layer, Step S9 involves manufacturing a connecting metal layer on the second insulating layer and the through-hole for the second insulating layer, Step S10 involves manufacturing a third insulating layer and through holes for the third insulating layer on the connecting metal layer and a second insulating layer not covered by the connecting metal layer, The process includes step S11 of manufacturing a pad layer on the third through-hole for the insulating layer, The connecting metal layer includes a reflective layer arranged from bottom to top, and a protective layer including a first protective matrix, a second protective matrix, and a third protective matrix arranged from bottom to top, wherein the second protective matrix includes n first protective sublayers and second protective sublayers arranged in a periodically stacked manner. A manufacturing method characterized in that the thickness of the first protective sublayer increases linearly toward the third insulating layer, and the thickness of the second protective sublayer decreases linearly toward the third insulating layer.

9. In step S10, the step of manufacturing the third insulating layer and the through-hole for the third insulating layer is: On the connecting metal layer and the second insulating layer not covered by the connecting metal layer, a third insulating layer is provided: SiO ２ A method for manufacturing a flip light-emitting diode chip according to claim 8, characterized in that it includes depositing a material by the PECVD method, then applying a photoresist to the third insulating layer, then removing a portion of the photoresist by exposure and development to expose a portion of the third insulating layer, and further removing a portion of the exposed third insulating layer with a BOE etching solution to form through holes for the third insulating layer.

10. In step S11, the step of manufacturing the pad layer is: A method for manufacturing a flip light-emitting diode chip according to claim 8, characterized in that Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal and AuSn metal are sequentially deposited as a pad layer on the third through-hole for insulating layer by electron beam deposition, the metal on the photoresist is removed by a bloom-type peeling process, and finally the photoresist is removed.

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