Drive circuit

Abstract

To provide a drive circuit that can be driven with a stable voltage, a liquid crystal device, and a drive method for the same.SOLUTION: A drive circuit according to the present embodiment charges a capacitive element with electricity and includes a constant current circuit 47 for source followers, the drive circuit comprising: a buffer circuit 43 for outputting an electric current in accordance with an input signal; and switches s+, s- connected between a buffer circuit 44 and the capacitive element, with the constant current circuit 47 for source followers shutting off the electric current after the switches s+, s- are closed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a drive circuit, a liquid crystal device, and a drive method thereof. [Background technology]

[0002] Patent Document 1 discloses a liquid crystal display device and a drive circuit for the same. In Patent Document 1, two data lines are grouped into one set, and a positive video signal is supplied to one data line and a negative video signal is supplied to the other data line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-223289 A Summary of the Invention [Problem to be solved by the invention]

[0004] A buffer circuit for holding a positive polarity video signal and a negative polarity video signal is provided in the pixel. Furthermore, a switch is provided in the pixel to switch between a positive polarity video signal and a negative polarity video signal within one frame. In such a liquid crystal display device, the luminance changes according to the voltage applied to the pixel electrode. Therefore, it is desirable to drive the device with a more stable voltage.

[0005] The present disclosure has been made in consideration of the above-mentioned points, and has an object to provide a drive circuit, a liquid crystal device, and a drive method thereof that can be driven with a stable voltage. [Means for solving the problem]

[0006] The drive circuit of this embodiment is a drive circuit that charges a capacitive element, and includes a source follower constant current circuit, a buffer circuit that outputs a current according to an input signal, and a switch connected between the buffer circuit and the capacitive element, and the source follower constant current circuit cuts off the current after the switch is closed.

[0007] A liquid crystal device according to the present embodiment includes a plurality of sets of data lines, each set consisting of two data lines, a plurality of gate lines intersecting the data lines, pixels connected to the gate lines and the set of data lines, a plurality of switches that sequentially supply a positive video signal to one of the sets of data lines and a negative video signal to the other data line in a set unit for the plurality of sets of data lines, a horizontal driving circuit that drives the plurality of switches within a horizontal scanning period, and a vertical driving circuit that performs vertical driving to select the plurality of gate lines for each horizontal scanning period, and the pixels are source follower transistors. a first sample and hold circuit comprising a source follower constant current circuit for sampling the positive video signal at the pixel electrode of the pixel and holding the signal for a certain period of time; a second sample and hold circuit comprising a source follower constant current circuit for sampling the negative video signal at the pixel electrode and holding the signal for a certain period of time; and a changeover switch for switching between the positive video signal held in the first sample and hold circuit and the negative video signal held in the second sample and hold circuit at a frequency higher than a vertical scanning frequency and applying the signal to the pixel electrode alternately, wherein the source follower constant current circuit cuts off the current after the changeover switch is closed.

[0008] A method for driving a liquid crystal device according to the present embodiment includes a plurality of sets of data lines, each set consisting of two data lines, a plurality of gate lines intersecting the data lines, pixels connected to the gate lines and the set of data lines, a plurality of switches for sequentially supplying a positive polarity video signal to one of the sets of data lines and a negative polarity video signal to the other data line in a set unit for the plurality of sets of data lines, a horizontal direction drive circuit for driving the plurality of switches in a set unit within a horizontal scanning period, and a vertical direction drive circuit for performing vertical direction drive to select the plurality of gate lines for each horizontal scanning period, the method including the steps of: a first sampling step of sampling the positive polarity video signal and holding it for a certain period; and a step of alternately applying to a pixel electrode the positive video signal held in the first sampling step and the negative video signal held in the second sampling step at a frequency higher than a vertical scanning frequency, wherein the pixel comprises a buffer circuit having a source follower constant current circuit provided for sampling the video signal to a pixel electrode of the pixel and holding the video signal for a certain period of time, and a changeover switch for alternately applying to a pixel electrode the positive video signal held in the first sampling step and the negative video signal held in the second sampling step at a frequency higher than a vertical scanning frequency, wherein the source follower constant current circuit cuts off current after the changeover switch is closed. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a drive circuit, a liquid crystal device, and a drive method thereof that can be driven with a stable voltage. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of a liquid crystal display device. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of a pixel. [Diagram 3] FIG. 2 is a circuit diagram showing a configuration of a buffer circuit. [Figure 4] FIG. 4 is a diagram showing signal waveforms of a drive circuit according to a comparative example. [Diagram 5] 11 is a diagram showing a signal waveform when jitter occurs in a drive circuit according to a comparative example. FIG. [Figure 6] FIG. 4 is a diagram showing signal waveforms of the drive circuit according to the first embodiment. [Figure 7] 11A and 11B are diagrams illustrating signal waveforms when jitter occurs in the drive circuit according to the embodiment. [Figure 8] FIG. 11 is a circuit diagram showing a drive circuit according to a second embodiment. [Figure 9] FIG. 11 is a diagram showing signal waveforms of a drive circuit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In addition, the following description and drawings are appropriately simplified for clarity of explanation.

[0012] Embodiment 1 The liquid crystal device according to this embodiment is, for example, a reflective liquid crystal display device configured using LCOS (Liquid Crystal on Silicon) technology. The liquid crystal display device according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a diagram showing the panel configuration of the liquid crystal display device. The liquid crystal display device 100 includes a horizontal drive circuit 10, a vertical drive circuit 20, a pixel display unit 30, and a controller 60.

[0013] The pixel display section 30 is provided with a plurality of data lines 6, a plurality of gate lines 8, and a plurality of pixels 42. The plurality of data lines 6 are arranged parallel to one another. The plurality of gate lines 8 are arranged parallel to one another. The plurality of data lines 6 and the plurality of gate lines 8 are arranged so as to intersect with one another. The gate lines 8 serve as row scanning lines.

[0014] The liquid crystal display device 100 includes a plurality of sets of data lines 6, with two lines forming one set. The liquid crystal display device 100 inverts and drives the pixels 42 using one set of data lines 6. Hereinafter, of one set of data lines 6, the positive data line 6 is referred to as data line 6a, and the negative data line 6 is referred to as data line 6b. Similarly, the switch 1 and the video signal line 5 are identified by their polarities as switch 1a, switch 1b, and video signal lines 5a, 5b. To invert the polarity, two systems of data lines 6, switches 1, and video signal lines 5 are provided.

[0015] Pixels 42 are arranged at the intersections of data lines 6 and gate lines 8. The pixels 42 are arranged in a matrix. Each pixel 42 is driven by one set of data lines 6 and one gate line 8. For example, if there are n gate lines 8 and 2m data lines 6, the pixels 42 are arranged in an n×m matrix. Note that m and n are each an integer of 2 or more.

[0016] Furthermore, the pixel display section 30 is provided with a common electrode line 7 for supplying a common potential to each pixel 42. The common electrode line 7 is connected to a storage capacitor provided in the pixel 42.

[0017] The vertical driving circuit 20 performs vertical driving in which a plurality of gate lines are selected for each horizontal scanning period. The vertical driving circuit 20 supplies scanning signals to the plurality of gate lines 8. That is, the vertical driving circuit 20 supplies scanning signals to sequentially select the gate lines 8 from the first row to the nth row. This causes the pixels 42 to be selected row by row. All the gate lines 8 are selected within one vertical scanning period. It becomes possible to write video signals to the pixels 42 of the selected row. Vertical driving is performed in which a plurality of gate lines are selected for each horizontal scanning period.

[0018] The horizontal driving circuit 10 performs horizontal driving to drive a plurality of switches 1 within a horizontal scanning period. This causes a video signal to be supplied to a plurality of data lines 6. As described above, two data lines 6a, 6b are connected to a pixel 42 as a set. Therefore, two data lines 6a, 6b are commonly connected to one row of pixels 42.

[0019] The data line 6a is connected to a video signal line 5a via a switch 1a. The data line 6b is connected to a video signal line 5b via a switch 1b. A positive video signal 71a is supplied to the video signal line 5a. A negative video signal 71b is supplied to the video signal line 5b. A horizontal drive circuit 10 controls the switches 1a and 1b.

[0020] Therefore, a positive video signal 71a is supplied to one data line 6a of a pair of data lines 6a, 6b, and a negative video signal 71b is supplied to the other data line 6b. The positive video signal 71a is a positive voltage with respect to the common potential of the common electrode line 7, and the negative video signal 71b is a negative voltage with respect to the common potential of the common electrode line 7. The positive video signal 71a and the negative video signal 71b can be supplied to the pixels 42 of a selected row. The horizontal driving circuit 10 turns each switch 1 on and off multiple times within a horizontal scanning period.

[0021] The controller 60 supplies various clock signals generated to synchronize with the video signals 71a and 71b to the horizontal drive circuit 10 and the vertical drive circuit 20 (paths are not shown). The horizontal drive circuit 10 and the vertical drive circuit 20 drive the data lines 6 and the gate lines 8 in synchronization with the video signals 71a and 71b, respectively, to perform pixel selection accompanied by horizontal and vertical scanning. This makes it possible to perform high-speed AC driving of the liquid crystal in this embodiment.

[0022] 2 is a circuit diagram showing the configuration of the pixel 42. The pixel 42 includes pixel selection transistors Q1 and Q2, storage capacitors C1, C2, and C3, and buffer circuits 44a and 44b. The pixel 42 further includes a pixel electrode PE, a common electrode CE, and a liquid crystal LC. The liquid crystal LC is sandwiched between the pixel electrode PE and the common electrode CE. In other words, the pixel electrode PE, the liquid crystal LC, and the common electrode CE form a capacitive element. The liquid crystal LC is driven by a voltage corresponding to a video signal supplied to the pixel electrode PE.

[0023] The pixel 42 includes a positive pixel circuit 43a and a negative pixel circuit 43b. The pixel circuits 43a and 43b have the same circuit configuration. The pixel circuit 43a includes a buffer circuit 44a, a storage capacitor C1, a pixel selection transistor Q1, and a switch s+. The pixel circuit 43b includes a buffer circuit 44b, a storage capacitor C2, a pixel selection transistor Q2, and a switch s-.

[0024] The gate line 8 branches into two at the pixel 42. One of the two branched gate lines 8 is gate line 8a, and the other is gate line 8b. The gate line 8a is connected to the gate of the pixel selection transistor Q1. The gate line 8b is connected to the gate of the pixel selection transistor Q2. The drain of the pixel selection transistor Q1 is connected to the data line 6a. The drain of the pixel selection transistor Q2 is connected to the data line 6b.

[0025] The source of the pixel selection transistor Q1 is connected to one end of a storage capacitor C1. The other end of the storage capacitor C1 is connected to a common electrode line 7. The source of the pixel selection transistor Q2 is connected to one end of a storage capacitor C2. The other end of the storage capacitor C2 is connected to the common electrode line 7. The storage capacitors C1 and C2 serve as capacitors that store electric charges.

[0026] The pixel 42 includes a buffer circuit 44a and a buffer circuit 44b. The buffer circuits 44a and 44b have the same configuration. The buffer circuits 44a and 44b are collectively referred to as the buffer circuits 44.

[0027] The input terminal (in in the figure) of the buffer circuit 44a is connected to the connection node between the pixel selection transistor Q1 and the storage capacitor C1. The input terminal of the buffer circuit 44b is connected to the connection node between the pixel selection transistor Q2 and the storage capacitor C2. The output terminal (out in the figure) of the buffer circuit 44a is connected to the pixel electrode PE via the switch s+. The output terminal of the buffer circuit 44b is connected to the pixel electrode PE via the switch s-. The buffer circuits 44a and 44b serve as sample-and-hold circuits that sample the video signal and hold it for a certain period of time.

[0028] The buffer circuit 44a samples and holds a positive-polarity video signal at a predetermined cycle shorter than the vertical scanning period. The buffer circuit 44b samples and holds a negative-polarity video signal at a predetermined cycle shorter than the vertical scanning period. Sampling by the buffer circuit 44a is referred to as a first sampling step, and sampling by the buffer circuit 44b is referred to as a second sampling step.

[0029] Furthermore, the output terminal of the switch s+ and the output terminal of the switch s- are connected at a connection node 45. One end of a storage capacitor C3 is connected between the connection node 45 and the pixel electrode PE. The other end of the storage capacitor C3 is connected to the common electrode line 7.

[0030] In this way, one pixel 42 is driven by two systems of data lines 6a, 6b, buffer circuits 44a, 44b, and switches s+, s-. The buffer circuit 44a is a circuit that samples and holds the positive polarity video signal. The buffer circuit 44b is a circuit that samples and holds the negative polarity video signal. The switches s+ and s- are changeover switches that switch the polarity of the video signal at a frequency higher than the vertical scanning frequency and apply it alternately to the pixel electrode PE.

[0031] The switches s+ and s- are alternately controlled to be turned on and off. When the switch s+ is turned on with the switch s- off, the positive polarity video signal held by the buffer circuit 44a is written to the pixel electrode PE. When the switch s- is turned on with the switch s+ off, the negative polarity video signal held by the buffer circuit 44b is written to the pixel electrode PE.

[0032] A positive video signal from the data line 6a and a positive video signal from the data line 6b are alternately supplied to the pixel electrode PE. Once per frame, the video signal is written into the storage capacitors C1 and C2 and held until writing in the next frame. Then, the switches s+ and s- are turned on and off multiple times until writing in the next frame. By alternately turning on the switches s+ and s-, polarity inversion is possible. For example, if the vertical scanning frequency (frame frequency) is 60Hz (60fps) and the number of times that the positive and negative video signals are switched in one frame is 30, AC driving at 1.8kHz is possible.

[0033] In this embodiment, video signals are written to the storage capacitors C1 and C2 once within one vertical scanning period. Positive and negative voltages can be applied to the pixel electrode PE multiple times within one vertical scanning period. The liquid crystal can be AC-driven at high speed without increasing the writing frequency to the pixel 42. This reduces the DC component between the pixel electrode PE and the common electrode CE, improving image quality and reliability, such as preventing burn-in of the liquid crystal. In this embodiment, the pixel 42 is provided with pixel circuits 43a and 43b capable of inverting polarity. By controlling the pixel circuits 43a and 43b at high speed, AC driving at a high frequency without the constraints of the vertical scanning frequency is possible.

[0034] The buffer circuit 44a and the switch s+ function as a drive circuit for charging the holding capacitance C3. Similarly, the buffer circuit 44b and the switch s- function as a drive circuit for charging the holding capacitance C3. The configurations of the buffer circuits 44a and 44b will be described. Since the buffer circuit 44a and the buffer circuit 44 have the same circuit configuration, they will be collectively described as the buffer circuit 44 below. FIG. 3 is a circuit diagram showing the configuration of the buffer circuit 44.

[0035] The buffer circuit 44 includes a transistor Tr1 and a transistor Tr2. The transistors Tr1 and Tr2 are p-type MOS transistors. The gate of the transistor Tr1 is connected to the input terminal in. The drain of the transistor Tr1 is connected to the ground GND. The source of the transistor Tr1 is connected to the drain of the transistor Tr2.

[0036] The source of the transistor Tr2 is connected to a power supply potential VDD. The gate of the transistor Tr2 is connected to a bias potential. The drain of the transistor Tr2 and the source of the transistor Tr1 are connected to the output terminal out.

[0037] The transistor Tr2 serves as a constant current circuit 47 for supplying a constant current to the transistor Tr1. By supplying a bias potential to the gate of the transistor Tr2, the transistor Tr2 operates as a source follower and supplies a constant current to the transistor Tr1. The buffer circuit 44 includes a source follower constant current circuit 47, and outputs a current according to an input signal input to the input terminal in. When the transistor Tr2 does not operate as a source follower, the constant current can be cut off by setting the bias terminal to the power supply potential VDD.

[0038] Next, the signal waveforms of the drive circuit having the buffer circuit 44, the switch s+, and the switch s- will be described. Fig. 4 is a diagram showing an example of the pulse signal waveforms of the drive circuit. From the top, Fig. 4 shows the vertical synchronization signal Vsync, the bias signal of the bias potential bias, the control signal of the switch s+, the control signal of the switch s-, the pixel voltage Vpe of the pixel electrode PE, and the common voltage Vcom of the common electrode CE.

[0039] The vertical synchronization signal Vsync is a signal indicating a vertical scanning period. In one vertical scanning period, the switches s+ and s- are turned on and off multiple times. The switches s+ and s- are turned on when the control signals are at high level and turned off when the control signals are at low level. The bias potential bias is connected to the gate of the transistor Tr2 as shown in FIG. 3. When the bias potential bias is at low level, the constant current circuit 47 is turned on and a current flows. When the bias potential bias is at high level (power supply potential VDD), the constant current circuit 47 is turned off and no current flows. In other words, the constant current circuit 47 cuts off the current at the timing when the bias potential bias goes from low level to high level (for example, timing A and B in FIG. 4).

[0040] The switches s+ and s- are alternately turned on. Specifically, when the switch s+ is turned on while the switch s- is off, the pixel electrode PE and the storage capacitor C3 are charged, and the pixel voltage Vpe becomes high level. After the charging is completed, the switch s+ is turned off. This causes both the switches s+ and s- to be turned off.

[0041] After that, switch s- is turned on while switch s+ is off. The pixel voltage Vpe is held at a high level until switch s- is turned on. When switch s- is turned on, the pixel electrode PE and the storage capacitor C3 are discharged, and the pixel voltage Vpe becomes a low level. Then, after the discharge is completed, switch s- is turned off. As a result, both switches s+ and s- are turned off. Also, the polarity of the common voltage Vcom is inverted at the timing when switch s+ is turned on and the timing when switch s- is turned on. That is, the common voltage Vcom becomes a low level when switch s+ is turned on, and becomes a high level when switch s- is turned on.

[0042] The above process is repeated within one vertical scanning period. In this way, the polarity of the voltage applied to the liquid crystal LC can be inverted multiple times within one vertical scanning period. Here, the timing at which the bias potential bias changes coincides with the timing at which the switches s+ and s- are turned off.

[0043] 4, at timing A when the bias potential bias changes from low to high, the switch s+ changes from on to off. At timing B when the bias potential bias changes from low to high, the switch s- changes from on to off. At timings A and B when the bias potential bias changes from low to high, the current of the constant current circuit 47 is cut off.

[0044] Here, the problem that occurs when the switching timing of the bias potential bias and the off timing of the switch s+ or switch s- are misaligned will be explained with reference to Fig. 5. Fig. 5 shows a voltage waveform when the off timing E of the switch s+ is delayed by Δt from the switching timing D of the bias potential bias. In other words, it shows a case where a jitter of Δt occurs in the control signal of the switch s+.

[0045] If the bias potential bias becomes high before the off timing E of the switch s+, a current continues to flow through the transistor Tr1. As a current continues to flow to the drive side of the source follower, the pixel voltage Vpe, which has been constant, drops. The pixel voltage Vpe drops until the switch s+ turns off, resulting in ΔVpe. In other words, the pixel voltage Vpe of the pixel electrode PE drops by ΔVpe during the period from the switching timing D to the off timing E. As a result, the pixel voltage Vpe cannot be set to a desired value. Similarly, the pixel voltage Vpe cannot be set to a desired value for the switch s-.

[0046] Since the liquid crystal LC cannot be driven with the desired pixel voltage Vpe, the display quality may be degraded. In this way, if there is a discrepancy between the off timing of the switch s+ or switch s- and the switching timing of the bias potential bias, the pixel voltage Vpe cannot be set to the desired value. If the off timing of the switch s+ or switch s- and the switching timing of the bias potential bias are simultaneous, jitter or the like will cause the desired voltage to be unable to be written to the pixel electrode PE. and the storage capacitor C3.

[0047] Therefore, in this embodiment, the source follower constant current circuit 47 is configured to cut off the current after the switch s+ or the switch s- is closed. An example of a pulse waveform in this embodiment is shown in FIG.

[0048] In Fig. 6, the pulse waveform of the bias potential bias is different from that in Fig. 4. Specifically, the period during which the bias potential bias is at a low level is longer. In Fig. 4, the period during which the bias potential bias is at a low level coincides with the period during which the switch s+ or s- is at a high level, but in Fig. 6, the period during which the bias potential bias is at a low level is longer than the period during which the switch s+ or s- is at a high level. Note that, since everything other than the bias potential bias is the same as in Fig. 4, the explanation will be omitted as appropriate.

[0049] The period during which the constant current circuit 47 passes a current is longer than the period during which the switches s+ and s- are on. In this way, when writing a video signal on the positive polarity side, the switching timing G of the bias potential bias is later than the off timing F of the switch s+. Similarly, when writing a video signal on the negative polarity side, the switching timing I of the bias potential bias is later than the off timing H of the switch s-. Therefore, the switch s+ or switch s- can be turned off while keeping the transistor Tr2 on. In other words, the switch s+ or switch s- is turned off while the constant current circuit 47 passes a current. This makes it possible to suppress a voltage drop in the pixel voltage Vpe.

[0050] The effect of this embodiment will be described in detail with reference to Fig. 7. Fig. 7 shows a voltage waveform when the control signal of the switch s+ is delayed by Δt. This is the case when jitter occurs in the control signal of the switch s+, and the off timing J of the switch s+ does not lag behind the switching timing K of the bias potential bias.

[0051] When switch s+ is turned on, pixel voltage Vpe rises. After pixel voltage Vpe becomes constant at the desired voltage value, switch s+ is turned off to fix pixel voltage Vpe. Since switch s+ is turned off while constant current circuit 47 is on, no voltage drop of ΔVpe occurs as shown in FIG. 5. Therefore, stable voltage transfer is possible even if jitter occurs. Since liquid crystal LC can be driven with the desired pixel voltage Vpe, degradation of display quality can be suppressed.

[0052] Embodiment 2 In this embodiment, an example of a configuration for generating a switch s+, a control signal for the switch, and a bias signal will be described. The circuit configuration according to the embodiment will be described with reference to Fig. 8. Fig. 8 is a circuit diagram showing a configuration of a generation circuit 80 that generates a bias signal and the like. Fig. 9 is a diagram showing a signal waveform of the generation circuit 80.

[0053] The generation circuit 80 includes a shift register 81, a flip-flop circuit 82, an inverter 83, and a NOR circuit 84. A clock signal ksck and an input signal ik2p(m) are input to the shift register 81. The shift register 81 sequentially transmits the input signal ik2p(m) in synchronization with the clock signal ksck. The shift register 81 can be, for example, a shift register provided in the vertical drive circuit 20 of FIG. 1. The clock signal ksck is, for example, a clock signal supplied from the controller 60 to the horizontal drive circuit 10 and the vertical drive circuit 20. The clock signal ksck operates at a constant repetition frequency.

[0054] When an input signal ik2p is input, the switch s+ operates, and when an input signal ik2m is input, the switch s- operates. The input signal ik2p(m) is a signal having two pulses p1 and p2 with different pulse widths, as shown in Fig. 9. The pulse width of the first pulse p1 is longer than the pulse width of the second pulse p2.

[0055] Assume that the output signal of the jth row of the shift register 81 is k2p(m). As shown in Fig. 9, the output signal k2p(m) is output in synchronization with the falling edge of the clock signal ksck. That is, the value of the output signal k2p is the value of the input signal ik2p at the falling edge of the clock signal ksck. The value of the output signal k2m is the value of the input signal ik2m at the falling edge of the clock signal ksck. The shift register 81 samples and holds the data of the input signal ik2p(m) at the falling edge of the clock signal ksck.

[0056] Therefore, the output signal k2p(m) has two pulses, just like the input signal ik2p(m). The two pulses of the output signal k2p(m) are p3 and p4. The pulse p3 corresponds to the first pulse p1 of the input signal, and the pulse p4 corresponds to the second pulse p2 of the input signal. The pulse p3 has a pulse width of two cycles of the clock signal ksck. The pulse p3 has a pulse width of one cycle of the clock signal ksck.

[0057] The output signal k2p(m) is input to a flip-flop circuit 82. The flip-flop circuit 82 is a d-type flip-flop. The flip-flop circuit 82 includes a clock input terminal cl, a data input terminal d, an output terminal q, an inverted output terminal qn, and a reset terminal rset. The inverted output terminal qn outputs a value opposite to that of the output terminal q.

[0058] An output signal k2p(m) of the shift register 81 is input to a clock input terminal cl of the flip-flop circuit 82. A data input terminal d is connected to an inverting output terminal qn. The output terminal q is connected to a bias circuit (not shown) that generates a bias voltage. The output terminal q is connected to a bias circuit (not shown) for generating a bias potential. That is, a bias circuit (not shown) generates a bias potential bias based on a bias signal biasb output from the output terminal q. For example, an inverting circuit of the bias circuit generates a bias potential bias by inverting the bias signal biasb.

[0059] The flip-flop circuit 82 generates a bias signal biasb based on the output signal k2p(m) from the shift register 81. A signal with the polarity of the bias signal biasb inverted becomes the bias potential bias supplied to the transistor Tr2 in FIG. 3. When the output signal k2p(m) becomes high level, the bias potential bias becomes low level. That is, the bias potential bias becomes low level at the rising edge of the pulse p3. When the output signal k2p(m) next becomes high level, the bias potential bias becomes high level. That is, the bias potential bias becomes high level at the rising edge of the pulse p4. The period during which the bias potential bias is low level is the period from the rising edge of the pulse p3 to the rising edge of the pulse p4.

[0060] Moreover, the output signal k2p(m) of the shift register 81 is input to the inverter 83. The inverter 83 is a logic circuit that inverts and outputs the output signal k2p(m). The output terminal of the inverter 83 is connected to one input terminal of the NOR circuit 84. The inverted output terminal qn is connected to the other input terminal of the NOR circuit 84. The NOR circuit 84 is a logic circuit that outputs the NOR (negative logical sum) of two signals. The output of the NOR circuit 84 becomes a control signal for the switch s+ or s-. The flip-flop circuit 82, the inverter 83, and the NOR circuit 84 generate a control signal for the switch s+ or s- based on the output signal k2p(m) from the shift register 81.

[0061] Specifically, when the output signal k2p(m) becomes H level, the control signal for the switch s+ or the switch s- becomes H level. When the output signal k2p(m) becomes Low level, the control signal for the switch s+ or the switch s- becomes Low level. In other words, the period during which the switch s+ or the switch s- is on is the period from the rising edge to the falling edge of the pulse p3.

[0062] The timing when the bias potential bias is switched to a low level coincides with the timing when the switch s+ or the switch s- is switched on. The period during which the bias potential bias is at a low level is longer than the period during which the switch s+ or the switch s- is switched on by one clock of the clock signal ksck. In other words, the constant current circuit 47 cuts off the current one clock after the switch s+ or the switch s- is switched off. In this way, stable signal transfer can be realized regardless of subtle variations in the circuit. By adjusting the frequency of the clock signal ksck, the time difference between the timing when the constant current circuit 47 cuts off the current and the timing when the switch is turned off can be adjusted. By increasing the clock frequency of the clock signal ksck, the time difference can be reduced, and by decreasing the clock frequency, the time difference can be increased. In addition, the pulse width of the pulse p1 can be controlled independently of the time difference, which increases the degree of freedom of driving.

[0063] In this way, an input signal having two pulses is input to the shift register 81. The shift register 81 sequentially transmits and outputs the input signal in synchronization with the clock signal ksck. The flip-flop circuit 82 has a clock input terminal to which the output from the shift register 81 is supplied. The switches s+ and s- are controlled to be turned on and off by a control signal corresponding to the first pulse p3 of the two pulses. During the period from the edge of the first pulse p3 to the edge of the second pulse p4, the constant current circuit 47 outputs a constant current.

[0064] Furthermore, since a d-flip-flop is used as the flip-flop circuit 82, the operation can be easily returned to the initial state. That is, the operation can be returned to the initial state by inputting a reset signal to the reset terminal rset of the flip-flop circuit 82. For example, in the signal waveform of FIG. 9, if the second pulse p4 of the output signal k2p(m) is not input to the flip-flop circuit 82, a constant current continues to flow to the constant current circuit 47. The flip-flop circuit 82 may be reset every time by supplying a reset signal to the reset terminal rset before the input signal ik2p(m) is input to the shift register 71. This makes it possible to prevent a constant current from continuing to flow to the constant current circuit 47 even if some malfunction occurs.

[0065] The mechanisms of the liquid crystal display devices according to the first and second embodiments can also be applied to a spatial light modulator (SLM) mounted on a wavelength selective switch (WWS) used in the field of wavelength multiplexing optical communication. The spatial light modulator is configured using, for example, LCOS (Liquid Crystal on Silicon) technology, and deflects an optical signal input to an input port, and outputs the signal from one or a selected one of a plurality of output ports.

[0066] More specifically, the wavelength selective optical switch device includes, for example, an input port, one or more output ports, a wavelength disperser, an optical coupler, and a spatial light modulator. The wavelength disperser spatially disperses an optical signal input to the input port into a plurality of wavelength components. The optical coupler collects the plurality of wavelength components dispersed by the wavelength disperser. The spatial light modulator has, for example, a plurality of pixels 12 arranged in a matrix on an xy plane consisting of an x-axis direction expanded according to wavelength and a y-axis direction perpendicular to the x-axis direction. The plurality of pixels 12 change the reflection direction (i.e., deflect) of the optical signal collected by the optical coupler for each wavelength, and output it from any one of one or more output ports selected.

[0067] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0068] 100 LCD display device 1 Switch 5 Video signal line 6 Data lines 7 Common electrode wire 8 Gate Lines 10 Horizontal drive circuit 20 Vertical drive circuit 30 pixel display 42 pixels 43a Positive side pixel circuit 43b Negative pixel circuit 44a Buffer circuit 44b Buffer circuit 45 Connecting Nodes 60 Controller 71a, 71b Video signal 81 Shift Register 82 Flip-flop circuit 83 Inverter 84 NOR Circuit C1 holding capacity C2 holding capacity C3 holding capacity PE pixel electrode LC Liquid Crystal CE Common electrode s+ switch s- Switch

Claims

1. A drive circuit for charging a capacitive element a buffer circuit including a source follower constant current circuit and outputting a current in response to an input signal; a switch connected between the buffer circuit and the capacitive element; the source follower constant current circuit cuts off current after the switch is closed; a shift register that sequentially transmits the input signal having two pulses in synchronization with a clock signal and outputs the input signal as an output signal having two pulses; a flip-flop circuit having a clock input terminal to which the output signal output from the shift register is supplied, the switch is controlled by a control signal corresponding to a first pulse of the two pulses of the output signal; The constant current circuit outputs a constant current during the period from the rising edge of the first pulse of the output signal to the rising edge of the second pulse of the output signal. Drive circuit.

2. The buffer circuit includes: a first p-type MOS transistor; a second p-type MOS transistor; a gate of the second p-type MOS transistor is connected to a bias potential for driving the constant current circuit of the source follower; the drain of the second p-type MOS transistor is connected to the switch; the source of the second p-type MOS transistor is connected to a first potential; a gate of the first p-type MOS transistor is connected to an input terminal to which the input signal is supplied; the source of the first p-type MOS transistor is connected to the switch; The drain of the first p-type MOS transistor is connected to a second potential; 2. The drive circuit according to claim 1, wherein the bias potential changes after the switch is closed, causing the constant current circuit to cut off the current.

3. The buffer circuit and the switch are provided in two systems, The buffer circuit of one of the two systems applies a positive voltage to the capacitance element, the other of the two buffer circuits applies a negative voltage to the capacitance element; 3. The drive circuit according to claim 1, wherein the two systems of switches are alternately turned on.

Images