Electronic Control Unit

Abstract

To make it possible to perform processing by a parallel arithmetic processor even if processing of the same arithmetic instruction group is requested overlappingly.SOLUTION: A graph management part Y enqueues request information to a queueing mechanism Y1 when the request information of a graph is transmitted from control functions A to C of a control function part X, and transmits the processing request to a parallel arithmetic processor 13 if request information of a graph identical to a graph is enqueued when the parallel arithmetic processor 13 can receive processing of the graph. Accordingly, by using the queueing mechanism Y1, a processing request of a graph identical to a graph under processing by the parallel arithmetic processor 13 can be received and processed. A control function related to a process until the parallel arithmetic processor 13 returns a processing result after the control functions A to C of the control function part X request processing and execution and completion of an arithmetic instruction group and the processing are associated with each other and managed. Accordingly, a processing result by the parallel arithmetic processor 13 can be passed to the control functions A to C of the control function part X of a processing request source.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an electronic control device. [Background technology]

[0002] In recent years, for example, in electronic control devices for automobiles, the processing power of microcomputers has been improved due to the increasing complexity of control. As an example, a microcomputer equipped with multiple cores and a parallel processor is installed, and the core requests the parallel processor to process a set of arithmetic instructions, which is a collection of arithmetic instructions, and the parallel processor processes the arithmetic instructions in parallel, thereby speeding up the arithmetic processing.

[0003] The parallel arithmetic processor extracts an arithmetic instruction from a set of arithmetic instructions requested by the core, and uses the hardware functions to automatically allocate optimal resources to multiple arithmetic units, enabling high-speed parallel arithmetic operations. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-126426 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the parallel processor is configured to receive a group of operation instructions requested for processing from a core, and to process the received group of operation instructions in order. However, a parallel processor may be configured to accept requests for processing a set of operation instructions different from the set of operation instructions currently being processed, but not for the same set of operation instructions. In such a configuration, there is a problem that the parallel processor cannot process the same set of operation instructions when multiple cores make duplicate requests to process the same set of operation instructions.

[0006] The present invention has been made in consideration of the above circumstances, and its object is to provide an electronic control device that can process a group of identical calculation instructions using a parallel calculation processor even when the same group of calculation instructions is requested to be processed in duplicate. [Means for solving the problem]

[0007] According to the invention of claim 1, the control functions (A to C) of the control function unit (X) request a set of operation instructions for processing. When a processing request is received from a control function of the control function unit, the holding unit (Y1) puts the processing request into a standby state. The management function unit (Y2) manages the standby state of the processing request by the holding unit and the processing state of the operation instructions by the parallel arithmetic processor (13), so that when the control functions of the control function unit request processing of the same set of operation instructions in duplicate, the management function unit puts the processing request from the control function unit into a standby state in the holding unit until the parallel arithmetic processor completes processing of the set of operation instructions, and as soon as the parallel arithmetic processor completes processing of the set of operation instructions, the management function unit acquires the processing request waiting in the holding unit and arbitrates so that the parallel arithmetic processor can execute it. This makes it possible to avoid requests to the parallel arithmetic processors for processing the same set of operation instructions, and even when a processing request is received for a set of operation instructions that is the same as the set of operation instructions being processed in the parallel arithmetic processor, the request can be accepted.

[0008] In addition, the management function unit manages the control functions related to the process from when the control function of the control function unit requests processing to when the parallel processor returns the processing result, in association with the operation instruction groups and the execution / completion of the processing. This allows the processing result by the parallel processor to be passed to the control function of the control function unit that requested processing. When a control function of the control function unit makes a processing request, it provides the holding unit with request information for a group of operation instructions corresponding to the processing request. When a processing request is received from the control function of the control function unit, the holding unit enqueues the request information for the received group of operation instructions in a queuing mechanism (Y1). The management function unit has a management function corresponding to each group of operation instructions processed by the parallel processing unit, and obtains request information corresponding to a group of operation instructions that the parallel processing unit can accept from the queuing mechanism and provides it to the parallel processing unit. The parallel processing unit processes the group of operation instructions based on the request information provided from the management function unit. The queuing mechanism has a queue corresponding to each group of operation instructions processed by the parallel processing unit, and when request information for a group of operation instructions is received from the control function of the control function unit, it enqueues the request information in the queue for the corresponding group of operation instructions. The management function obtains request information corresponding to a group of operation instructions that the parallel processing unit can accept from the queue for the corresponding group of operation instructions and provides it to the parallel processing unit. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a functional block diagram showing a configuration of a microcomputer according to an embodiment. [Diagram 2] Block diagram showing the connections between the engine ECU and each ECU [Diagram 3] A block diagram showing the schematic configuration of a parallel arithmetic processor. [Figure 4]Diagram showing graph structure [Diagram 5] A schematic diagram showing the functions of the graph manager [Figure 6] Diagram showing the operation of each function DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings. As shown in Fig. 2, the vehicle is equipped with an engine ECU (Electronic Control Unit) 1. The engine ECU 1 corresponds to an electronic control device. The engine ECU 1 is communicatively connected to other ECUs, such as an automatic transmission ECU 3, a meter ECU 4, and an air conditioning ECU 5, via an in-vehicle LAN 2. The protocol of the in-vehicle LAN 2 is, for example, CAN (Controller Area Network). CAN is a registered trademark.

[0011] The engine ECU 1 is mainly composed of a microcomputer 11. As shown in Fig. 1, the microcomputer 11 is configured with a core group 12 consisting of multiple cores 12a to 12c and a parallel arithmetic processor 13, and these cores 12a to 12c and the parallel arithmetic processor 13 process multiple arithmetic operations in parallel to achieve high speed processing.

[0012] The cores 12a to 12c and the parallel arithmetic processor 13 are connected to each other via an internal bus 14, and are also connected to memories such as a ROM 15 and a RAM 16, and an I / O 17 such as a CAN interface. The microcomputer 11 is also connected to another microcomputer 18 and peripheral circuits 19 such as an AD converter.

[0013] The cores 12a to 12c receive detection signals from various sensors for detecting the operating state of the engine via an input circuit 20, and process detection values ​​indicated by the detection signals to control actuators for controlling the engine via an output circuit 21, or transmit and receive communication signals to and from other ECUs via a communication circuit 22. When a predetermined calculation process is required to control the engine, the cores 12a to 12c request the parallel calculation processor 13 to perform the process.

[0014] 3, the parallel arithmetic processor 13 is composed of a memory 23, a control circuit 24, and a plurality of arithmetic units 25. The memory 23 sequentially stores information for processing a group of arithmetic instructions provided by the plurality of cores 12a to 12c.

[0015] The control circuit 24 performs arithmetic processing of the arithmetic instruction group stored in the memory 23 in cooperation with the arithmetic unit 25. In other words, the control circuit 24 has a scheduler function, and automatically allocates the arithmetic instructions constituting the arithmetic instruction group stored in the memory 23 to the corresponding arithmetic unit 25.

[0016] The arithmetic unit 25 sequentially processes the arithmetic instructions assigned by the control circuit 24. The multiple arithmetic units 25 may be of the same type or different types, and parallel processing is possible by assigning the same type or different types of arithmetic instructions to the arithmetic units 25. The arithmetic unit 25 stores the arithmetic processing results in the memory 23.

[0017] When the multiple cores 12a to 12c request the parallel arithmetic processor 13 to process a group of arithmetic instructions, they obtain the arithmetic results via the memory 23 and execute the subsequent processes based on the arithmetic results.

[0018] The processing order of the calculation instructions requested by the cores 12a to 12c is specified. For example, the calculation instruction set shown in Fig. 4 specifies that the calculation instruction A is processed first, followed by the next calculation instructions B to D, and then the next calculation instruction E is processed after all the calculation instructions B to D are processed. Hereinafter, the calculation instruction set is referred to as a graph.

[0019] Incidentally, the parallel arithmetic processor 13 of this embodiment is configured to accept a processing request for a graph different from the graph being processed, but not to accept a processing request for the same graph. Therefore, when the cores 12a to 12c make redundant processing requests for the same graph, the parallel arithmetic processor 13 cannot process the graph.

[0020] In view of these circumstances, in this embodiment, an arbitration function is provided between the cores 12a to 12c and the parallel processor 13. This arbitration function puts graph processing requests from the cores 12a to 12c into a standby state, monitors the standby state and the processing state of the parallel processor 13, and provides to the parallel processor 13 graph processing requests that the parallel processor 13 can accept.

[0021] The arbitration function will now be described. As shown in Fig. 5, the electronic control device 1 is configured to include a control function unit X and a graph management unit Y in addition to a parallel calculation processor 13. The control function unit X is configured to have a plurality of control functions. The graph management unit Y is configured to have a queuing mechanism Y1 and a graph management function Y2. The queuing mechanism Y1 corresponds to the holding unit, and the graph management function Y2 corresponds to the management function unit.

[0022] The queuing mechanism Y1 has a plurality of graph request queues corresponding to the graphs, and in response to a graph processing request from each control function of the control function unit X, enqueues graph request information in the corresponding graph request queue.

[0023] The graph management function Y2 has a plurality of graph request information management functions corresponding to the graphs and a graph state management function. The graph request information management function manages the control functions and graphs related to the process from when each control function of the control function unit X makes a processing request to when the parallel processing unit 13 returns the processing result, as well as identification information for identifying the execution / completion of the processing, by linking them together. The graph state management function monitors the processing state of the graphs in the parallel processing unit 13, and when the parallel processing unit 13 is able to accept the processing of the graph, it dequeues and acquires the graph request information enqueued in the graph request queue, and transmits it to the parallel processing unit 13.

[0024] In this embodiment, the cores 12a to 12c each have a control function of one or more control function units X. The core 12c has the function of a graph management unit Y in addition to the control functions of the control function units X.

[0025] An example of processing a graph requested for processing by each control function of the control function unit X using each control function of the control function unit X possessed by the cores 12a to 12c and the function of the graph management unit Y possessed by the core 12c will be described with reference to FIG. 6.

[0026] In the example shown in FIG. 6, the control function unit X has control functions A to C, the queuing mechanism Y1 has a graph 0 request queue and a graph 1 request queue, and the graph management function Y2 has a graph 0 management function and a graph 1 management function.

[0027] The parallel calculation processor 13 is configured to be able to accept graph 0 and graph 1, but not to accept a processing request for the same graph as the graph currently being processed. When neither graph 0 nor graph 1 is being processed, the parallel calculation processor 13 is able to accept graph 0 and graph 1, and is configured to process, for example, the first accepted graph 0 and then the second accepted graph 1.

[0028] 6 shows a case where control function A requests graph 0 for processing, then control function B requests graph 1 for processing, and then control function C requests graph 0 for processing. In this case, control function A and control function C are making overlapping requests to process graph 0. First, control function A requests graph 0 to graph management unit Y for processing. This request to process graph 0 is made by simultaneously sending request information of control function A to graph management unit Y. The request information includes information on the control function that made the request, control information required for graph processing, and result storage address information.

[0029] When there is a processing request for graph 0, the queuing mechanism Y1 enqueues the request information of control function A in the corresponding request queue for graph 0. In other words, the processing request for graph 0 is put into a waiting state. The graph management function Y2 manages the states of graph 0 and graph 1 processed by the parallel processing unit 13. That is, when a graph processing trigger is sent to the parallel processing unit 13, the corresponding graph is determined to be in a BUSY state, and when a graph completion trigger is received from the parallel processing unit 13, the corresponding graph is determined to be in an IDLE state. However, in the initial state, graph 0 and graph 1 are determined to be in an IDLE state.

[0030] The graph management function Y2 determines request information required for the parallel processor 13 to process the graph, and acquires the request information by dequeuing it from the corresponding graph request queue. That is, the parallel processor 13 determines a graph in an IDLE state, and acquires the request information by dequeuing a control function from the graph request queue in the IDLE state according to a predetermined rule, for example, FIFO (First In First Out).

[0031] 6, the graph 0 management function of the graph management function Y2 determines that the graph 0 of the parallel processing unit 13 is in the IDLE state. In this case, since the request information of control function A has been enqueued in the graph 0 request queue of the queuing mechanism Y1, the graph 0 management function dequeues and acquires the request information of control function A, and transmits the request information of control function A and a graph 0 processing trigger to the parallel processing unit 13.

[0032] When the parallel calculation processor 13 receives the graph 0 processing trigger, the parallel calculation processor 13 is not processing graph 0, so it accepts the graph 0 processing trigger and starts processing graph 0 based on the request information.

[0033] Next, if control function B requests the processing of graph 1 while the parallel processing unit 13 is processing graph 0 of control function A, the queuing mechanism Y1 enqueues the request information of control function B in the graph 1 request queue. In this case, since the parallel processing unit 13 determines that graph 1 is in the IDLE state, it dequeues and acquires the request information of control function B from the graph 1 request queue and transmits the request information of control function B and a graph 1 processing trigger to the parallel processing unit 13. At this time, since the parallel processing unit 13 is processing graph 0 but not processing graph 1, it accepts the request information of control function B in response to receiving the graph 1 processing trigger.

[0034] Next, if control function C requests the processing of graph 0 while the parallel processing unit 13 is processing graph 0, the request information of control function C is enqueued in the graph 0 request queue. In other words, the processing request of control function C goes into a waiting state. At this time, the graph 0 management function of graph management function Y2 determines that graph 0 of the parallel processing unit 13 is in a BUSY state, and therefore maintains the enqueued state of the request information of control function C. In other words, the waiting state of the processing request of graph 0 of control function C continues. When the parallel calculation processor 13 finishes the processing of graph 0, it transmits a graph 0 completion trigger and then starts processing the request information of graph 1, which is in a waiting state.

[0035] When the graph 0 management function of the graph management function Y2 receives a graph 0 completion trigger from the parallel processing unit 13, it transmits a graph 0 processing completion notification to the control function A. This allows the control function A to recognize that the processing of graph 0 by the parallel processing unit 13 has ended, and to execute subsequent processing based on the processing result of graph 0. In this case, the graph management function Y2 excludes the processing request for graph 0 from the control function A from its management target.

[0036] On the other hand, when the graph 0 management function of the graph management function Y2 receives a graph 0 completion trigger from the parallel processing unit 13, it determines that graph 0 is in the IDLE state, dequeues and acquires the request information of control function C enqueued in the graph 0 request queue, and transmits the request information of control function C and a graph 0 processing trigger to the parallel processing unit 13. As a result, the parallel processing unit 13 accepts the request information, and starts processing of graph 0 when the processing of graph 1 is completed. In this manner, even if the parallel processor 13 is processing graph 0 or graph 1, it is possible to accept a processing request for the same graph from the control functions A to C due to the arbitration function of the graph management function Y2.

[0037] Here, the graph management function Y2 manages the above-mentioned control functions, graphs, graph processing, and graph completion triggers by IDs. That is, it assigns an ID for identifying the control functions A to C of the control function unit X, a graph ID for identifying the graph, and an ID for identifying the graph processing trigger and the graph completion trigger, and manages them in association with IDs related to the process from when the control functions A to C of the control function unit X make a processing request until the parallel processing unit 13 returns the processing result. This makes it possible to pass the processing result by the parallel processing unit 13 to the cores 12a to 12c that are the source of the processing request. The ID corresponds to the identification information. In this case, the graph management function Y2 excludes the processing request of graph 1 from the control function C from its management targets.

[0038] According to this embodiment, the following effects can be obtained. When graph request information is transmitted from the control functions A to C of the control function unit X, the graph management unit Y enqueues the request information in the queuing mechanism Y1, and when the parallel processing unit 13 is capable of accepting processing of the graph and request information of the same graph as the graph in question has been enqueued, the graph management unit Y transmits the processing request to the parallel processing unit 13. In this way, by using the queuing mechanism Y1, a processing request of the same graph as the graph being processed by the parallel processing unit 13 can be accepted and processed.

[0039] In addition, the control functions and graphs related to the process from when the control functions A to C of the control function unit X that originated the processing request make a processing request to when the parallel arithmetic processor 13 returns the processing result are linked and managed, as well as identification information that identifies the execution and completion of the processing. This makes it possible to pass the processing result by the parallel arithmetic processor 13 to the control functions A to C of the control function unit X that originated the processing request.

[0040] When the control functions A to C of the control function unit X make a processing request, they provide graph request information corresponding to the processing request to the queuing mechanism Y1, and when the queuing mechanism Y1 provides graph request information from the control functions A to C of the control function unit X, it enqueues the request information in the corresponding graph request queue, and the graph management function Y2 obtains request information corresponding to a graph that the parallel processing unit 13 can accept from the corresponding graph request queue of the queuing mechanism Y1 and provides it to the parallel processing unit 13, and the parallel processing unit 13 processes the graph based on the request information provided from the graph management function Y2. In this way, by providing a graph request queue as the queuing mechanism Y1, it is possible to process processing requests via the graph request queue.

[0041] When the graph management unit Y requests the parallel processing unit 13 to process a graph, it transmits a processing trigger corresponding to the graph to the parallel processing unit 13, and the parallel processing unit 13 processes the graph based on the request information in response to the received processing trigger. This allows the parallel processing unit 13 to process the graph based on the request information from the graph management unit Y in synchronization with the graph processing trigger.

[0042] When the parallel arithmetic processor 13 completes the processing of a graph, it transmits a completion trigger corresponding to that graph, and when the graph management unit Y receives a completion trigger from the parallel arithmetic processor 13, it notifies the control functions A to C of the control function unit X that sent the completion of the processing, and the control functions A to C of the control function unit X acquire the processing result in response to the received processing completion notification and execute subsequent processing based on the processing result. This makes it possible to notify the control functions A to C of the control function unit X that the processing by the parallel arithmetic processor 13 has been completed in synchronization with the completion trigger.

[0043] The graph management unit Y determines that the graph corresponding to the processing trigger is in a BUSY state when a processing trigger is transmitted, and determines that the graph corresponding to the graph processing trigger is in an IDLE state when a graph completion trigger is received, thereby managing the processing state of the parallel processing unit 13, and dequeues and acquires request information from the graph request queue corresponding to the graph determined to be in an IDLE state. This makes it possible to manage the processing state of the parallel processing unit 13 in synchronization with the graph processing trigger and the graph completion trigger.

[0044] The graph management unit Y attaches IDs to the control functions A to C of the control function unit X, graphs, processing triggers, and completion triggers, thereby linking and managing IDs related to the process from when the control functions A to C of the control function unit X that originated the processing request make a processing request to when the parallel processing unit 13 returns the processing result. This makes it possible to manage the graph that is requested to be processed by the parallel processing unit 13 based on the request information from the control functions A to C of the control function unit X, and the control functions A to C of the control function unit X that originated the processing request, and to notify the control functions A to C of the control function unit X that originated the processing request of the processing completion based on the completion trigger transmitted when the graph processing is completed.

[0045] (Other embodiments) When the graph management unit Y has not enqueued request information in the graph request queue corresponding to the graph determined to be in the IDLE state, the graph management unit Y may determine request information in response to a processing request received from the control functions A to C of the control function unit X, and transmit the request information and a graph processing trigger to the parallel processing unit 13, which may process the graph based on the request information in response to receiving the graph processing trigger. In this case, the parallel processing unit 13 can obtain the request information even when the request information has not been enqueued in the graph request queue. The electronic control device is not limited to the engine ECU, and may be any device that controls a controlled object.

[0046] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0047] In the drawing, 1 is an engine ECU (electronic control unit), 11 is a microcomputer, 12a to 12c are cores, 13 is a parallel processing unit, 25 is a calculator, X is a control function unit, A to C are control functions, Y is a management unit, Y1 is a queuing mechanism (holding unit), and Y2 is a graph management function.

Claims

1. An electronic control device including a microcomputer (11) equipped with a parallel arithmetic processor (13) capable of parallel processing a plurality of arithmetic instructions constituting an arithmetic instruction group by a plurality of arithmetic units (25), control functions (A to C) of a control function unit (X) for requesting processing of a group of arithmetic instructions; a holding unit (Y1) that holds a processing request in a standby state when the processing request is received from a control function of the control function unit; a management function unit (Y2) that arbitrates processing requests for each of the operation instruction groups to the parallel processor by managing a standby state of a processing request by the holding unit and a processing state of the operation instruction groups by the parallel processor, and that manages a control function related to a process from when a control function of the control function unit makes a processing request to when the parallel processor returns a processing result, the operation instruction groups, and the execution and completion of the process in association with each other; Equipped with When a control function of the control function unit requests processing, the control function unit provides request information of a set of operation instructions corresponding to the processing request to the holding unit; the holding unit, when a processing request is received from a control function of the control function unit, enqueues request information of a given set of operation instructions in a queuing mechanism (Y1); the management function unit has a management function corresponding to each operation instruction group processed by the parallel processing unit, acquires request information corresponding to an operation instruction group that can be accepted by the parallel processing unit from the queuing mechanism, and provides the request information to the parallel processing unit; the parallel arithmetic processor processes a group of arithmetic instructions based on request information provided by the management function unit; the queuing mechanism includes a queue corresponding to each operation instruction group processed by the parallel operation processor, and when request information of an operation instruction group is given from a control function of the control function unit, enqueues the request information in the queue of the corresponding operation instruction group; The management function is an electronic control device that obtains request information corresponding to a group of operation instructions that the parallel processor can accept from a queue of the corresponding group of operation instructions and provides the request information to the parallel processor.

2. 2. The electronic control device according to claim 1, wherein when a processing request for a group of operation instructions is available to the parallel arithmetic processor and a processing request for a group of operation instructions identical to the group of operation instructions is in a waiting state, the management function unit arbitrates by providing the processing request to the parallel arithmetic processor.

3. when the management function unit issues a processing request for a group of operation instructions to the parallel processor, the management function unit transmits a processing trigger corresponding to the group of operation instructions; 3. The electronic control device according to claim 1, wherein the parallel operation processor processes a group of operation instructions based on request information in response to receiving a processing trigger.

4. The parallel arithmetic processor transmits a completion trigger corresponding to a group of arithmetic instructions when the processing of the group of arithmetic instructions is completed; The management function unit notifies the control function of the control function unit, which is a transmission source, of the completion of processing in response to receiving the completion trigger; The electronic control device according to claim 1 , wherein the control function of the control function unit acquires a processing result in response to receiving a processing completion notification, and executes a subsequent process based on the processing result.

5. 5. The electronic control device according to claim 3 or 4, wherein the management function unit manages the processing state of the parallel arithmetic processor by determining that a processing trigger corresponding to the processing trigger is in a BUSY state when a processing trigger is sent, and determining that a processing instruction group corresponding to the processing trigger is in an IDLE state when a completion trigger is received, and dequeues and acquires request information from a queue of an arithmetic instruction group corresponding to the arithmetic instruction group determined to be in an IDLE state.

6. An electronic control device as described in Claim 5, wherein the management function unit acquires request information corresponding to a processing request provided from a control function of the control function unit when no request information is enqueued in a queue of an operation instruction group corresponding to an operation instruction group determined to be in an IDLE state.

7. 7. The electronic control device according to claim 5 or 6, wherein the management function unit identifies the control function of the control function unit, the calculation instruction group, the processing trigger, and the completion trigger by IDs, and manages the control function related to the process from when the control function of the control function unit makes a processing request to when the parallel calculation processor returns the processing result, in association with the calculation instruction group, and identification information that identifies the execution and completion of the processing.

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