Transmission / reception system and transmission / reception method

Abstract

To secure excellent communication quality in data transmission using an LDPC code.SOLUTION: There is decoded an LDPC code obtained by performing LDPC coding on the basis of a check matrix where a code length N is 69120 bits and a coding rate r is a 8 / 16 LDPC code. The check matrix includes: an A-matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K=N×r of the LDPC coding; a B-matrix of a step structure of M1 rows and M1 columns; a Z-matrix as a zero matrix of M1 rows and N-K-M1 columns; a C-matrix of a N-K-M1 rows and K+M1 columns; and a D-matrix as a unit matrix of N-K-M1 rows and N-K-M1 columns. The A-matrix and the C-matrix are represented by a check matrix initial value table. The check matrix initial value table is a table representing positions of elements of 1 of the A-matrix and the C-matrix for every 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using an LDPC code.SELECTED DRAWING: Figure 22

Description

[Technical field]

[0001] This technology is Transmission / reception system and transmission / reception method To ensure good communication quality, particularly in data transmission using LDPC codes, Transmission / reception system and transmission / reception method Regarding. [Background technology]

[0002] Low Density Parity Check (LDPC) codes have high error correction capabilities, and in recent years have been widely adopted in transmission methods for digital broadcasting, such as DVB (Digital Video Broadcasting)-S.2, DVB-T.2, and DVB-C.2 in Europe, and ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

[0003] Recent research has shown that LDPC codes, like turbo codes, can achieve performance approaching the Shannon limit as the code length is increased. In addition, LDPC codes have the property that the minimum distance is proportional to the code length, and therefore have good block error probability characteristics. Another advantage is that the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like hardly occurs. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] ATSC Standard:Physical Layer Protocol(A / 322), 7 September 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] In data transmission using an LDPC code, for example, the LDPC code is made into a symbol (symbolized) for orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbol is mapped to a signal point of the orthogonal modulation and transmitted.

[0006] Data transmission using LDPC codes as described above is becoming more widespread worldwide, and there is a demand to ensure good communication (transmission) quality.

[0007] The present technology has been made in view of these circumstances, and makes it possible to ensure good communication quality in data transmission using LDPC codes. [Means for solving the problem]

[0008] A first transmission device / method of the present technology includes an encoding unit / step for performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix being an A matrix at the top left of the parity check matrix, having M1 rows and K columns, a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, and a B matrix of a staircase structure adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns. a Z matrix which is a zero matrix adjacent to the A matrix and the B matrix, a C matrix which is adjacent below the A matrix and the B matrix, and which has N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 The transmitting device / method is as follows.

[0009] In the first transmitting device / method, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 5 / 16. The check matrix includes an A matrix in the upper left of the check matrix, which is M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which is M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which is M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which is N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which is N-K-M1 rows and N-K-M1 columns, and the predetermined value M1 is 1800, and the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 It has become.

[0010] A first receiving device / method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16, the parity check matrix including an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix that is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix that is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents positions of elements of 1 in the A matrix and the C matrix every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted from a transmitting device.

[0011] In a first receiving device / method, a coding unit is provided that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16, the check matrix including an A matrix at the top left of the check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 The LDPC code obtained from the data transmitted from the transmitting device is decoded.

[0012] A second transmission device / method of the present technology includes an encoding unit / step for performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix being an A matrix at the top left of the parity check matrix, having M1 rows and K columns, a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, and a B matrix of a staircase structure adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns. a Z matrix which is a zero matrix adjacent to the A matrix and the B matrix, a C matrix which is adjacent below the A matrix and the B matrix, and which has N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227 481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286 1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914 1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572 244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150 15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337 1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873 638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342 1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405 1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064 1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149 189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534 125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429 1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235 1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116 463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668 630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944 716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467 1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969 775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454 25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992 781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606 729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704 122 1378 1660 7448 7659 11900 13039 13796 19908 504 716 1551 5655 6245 8365 9825 16627 29100 88 900 1057 2620 16729 17278 17444 26106 26587 30 1697 1736 8718 11664 20885 27043 42569 42913 293 634 1188 4005 5266 6205 26756 30207 37757 254 755 1187 4631 13433 25055 28354 28583 30446 316 1381 1522 3131 4340 27284 28246 28282 43174 84 293 645 2148 7925 13104 25010 36836 39033 982 1486 1660 4287 5335 18350 26913 30774 31280 418 1028 1039 3334 4577 6553 7011 17259 31922 1324 1361 1690 5991 7740 16880 18479 25713 31823 735 1322 1727 8629 14655 15815 16762 23263 36859 19 928 1561 11161 12894 14226 21331 41128 41883 327 940 1004 13616 15894 31400 34106 34443 37957 576 953 1226 2122 4900 5002 10248 25476 30787 249 632 1240 5432 23019 29225 31719 36658 41360 980 1154 1783 4351 10245 23347 27442 28328 38555 581 863 1552 5057 7572 14544 20482 29482 31672 4 502 1450 4883 5176 6824 10430 32680 39581 81 761 1558 2269 5391 13213 24184 25523 39429 1085 1163 1244 7694 9125 17387 22223 26343 37933 204 1127 1483 18302 19939 20576 31599 32619 42911 345 387 591 8727 18080 20628 32251 34562 42821 957 1126 1133 4099 12272 15595 20906 23606 34564 409 1310 1335 2761 11952 26853 27941 29262 31647 329 818 1527 3890 5238 8742 15586 28739 43015 231 1158 1677 4314 15937 17526 18391 22963 39232 34 275 526 2975 4742 16109 17346 29145 37673 497 735 1261 7468 8769 17342 19763 32646 33497 879 1233 1633 11612 22941 23723 31969 35571 39510 886 954 1355 5532 8283 26965 29267 30820 40402 356 1199 1452 8833 14845 21722 23840 26539 27970 553 1570 1732 8249 16820 23181 23234 30754 40399 457 1304 1698 2774 11357 32906 34484 38700 41799 456 579 1155 23844 27261 29172 30980 35000 40984 301 1290 1782 6798 9735 23655 31040 35554 36366 228 483 561 12346 16698 32688 34518 38648 41677 35 184 997 4915 7077 9878 16772 26263 27270 181 193 1255 7548 17103 34511 36590 38107 42065 697 1024 1541 2164 15638 20061 32499 32667 32732 654 968 1632 3215 4901 6286 12414 13963 29636 89 150 450 5771 10863 29809 36886 37914 42983 517 1046 1153 5458 18093 25579 31084 37779 42050 345 914 1372 4548 6720 13678 13755 15422 41938 301 518 1107 3603 6076 9265 19580 41645 42621 155 1013 1441 10166 10545 22042 30084 33026 34505 899 1308 1766 22228 24520 24589 30833 32126 37147 177 230 349 6309 9642 25713 30455 34964 40524 802 1364 1703 3573 17317 20364 22849 24265 24925 3952 10609 11011 16296 31430 39995 40207 41606 42424 16548 19896 22579 23043 23126 24141 34331 34959 37990 12197 15244 22990 23110 25507 30011 37681 38902 39432 2292 11871 15562 22304 33059 35126 39158 41206 41866 3497 7847 11510 16212 19408 26780 27967 33953 34451 The transmitting device / method is as follows.

[0013] In the second transmission device / method, LDPC coding is performed based on a check matrix of an LDPC code whose code length N is 69120 bits and whose coding rate r is 6 / 16. The check matrix includes an A matrix in the upper left of the check matrix, which is M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which is M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which is M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which is N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which is N-K-M1 rows and N-K-M1 columns, and the predetermined value M1 is 1800, and the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table which represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227 481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286 1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914 1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572 244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150 15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337 1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873 638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342 1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405 1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064 1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149 189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534 125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429 1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235 1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116 463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668 630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944 716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467 1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969 775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454 25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992 781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606 729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704 122 1378 1660 7448 7659 11900 13039 13796 19908 504 716 1551 5655 6245 8365 9825 16627 29100 88 900 1057 2620 16729 17278 17444 26106 26587 30 1697 1736 8718 11664 20885 27043 42569 42913 293 634 1188 4005 5266 6205 26756 30207 37757 254 755 1187 4631 13433 25055 28354 28583 30446 316 1381 1522 3131 4340 27284 28246 28282 43174 84 293 645 2148 7925 13104 25010 36836 39033 982 1486 1660 4287 5335 18350 26913 30774 31280 418 1028 1039 3334 4577 6553 7011 17259 31922 1324 1361 1690 5991 7740 16880 18479 25713 31823 735 1322 1727 8629 14655 15815 16762 23263 36859 19 928 1561 11161 12894 14226 21331 41128 41883 327 940 1004 13616 15894 31400 34106 34443 37957 576 953 1226 2122 4900 5002 10248 25476 30787 249 632 1240 5432 23019 29225 31719 36658 41360 980 1154 1783 4351 10245 23347 27442 28328 38555 581 863 1552 5057 7572 14544 20482 29482 31672 4 502 1450 4883 5176 6824 10430 32680 39581 81 761 1558 2269 5391 13213 24184 25523 39429 1085 1163 1244 7694 9125 17387 22223 26343 37933 204 1127 1483 18302 19939 20576 31599 32619 42911 345 387 591 8727 18080 20628 32251 34562 42821 957 1126 1133 4099 12272 15595 20906 23606 34564 409 1310 1335 2761 11952 26853 27941 29262 31647 329 818 1527 3890 5238 8742 15586 28739 43015 231 1158 1677 4314 15937 17526 18391 22963 39232 34 275 526 2975 4742 16109 17346 29145 37673 497 735 1261 7468 8769 17342 19763 32646 33497 879 1233 1633 11612 22941 23723 31969 35571 39510 886 954 1355 5532 8283 26965 29267 30820 40402 356 1199 1452 8833 14845 21722 23840 26539 27970 553 1570 1732 8249 16820 23181 23234 30754 40399 457 1304 1698 2774 11357 32906 34484 38700 41799 456 579 1155 23844 27261 29172 30980 35000 40984 301 1290 1782 6798 9735 23655 31040 35554 36366 228 483 561 12346 16698 32688 34518 38648 41677 35 184 997 4915 7077 9878 16772 26263 27270 181 193 1255 7548 17103 34511 36590 38107 42065 697 1024 1541 2164 15638 20061 32499 32667 32732 654 968 1632 3215 4901 6286 12414 13963 29636 89 150 450 5771 10863 29809 36886 37914 42983 517 1046 1153 5458 18093 25579 31084 37779 42050 345 914 1372 4548 6720 13678 13755 15422 41938 301 518 1107 3603 6076 9265 19580 41645 42621 155 1013 1441 10166 10545 22042 30084 33026 34505 899 1308 1766 22228 24520 24589 30833 32126 37147 177 230 349 6309 9642 25713 30455 34964 40524 802 1364 1703 3573 17317 20364 22849 24265 24925 3952 10609 11011 16296 31430 39995 40207 41606 42424 16548 19896 22579 23043 23126 24141 34331 34959 37990 12197 15244 22990 23110 25507 30011 37681 38902 39432 2292 11871 15562 22304 33059 35126 39158 41206 41866 3497 7847 11510 16212 19408 26780 27967 33953 34451 It has become.

[0014] A second receiving device / method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6 / 16, the parity check matrix including an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix that is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix that is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents positions of elements of 1 in the A matrix and the C matrix every 360 columns, 608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227 481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286 1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914 1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572 244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150 15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337 1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873 638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342 1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405 1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064 1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149 189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534 125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429 1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235 1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116 463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668 630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944 716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467 1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969 775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454 25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992 781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606 729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704 122 1378 1660 7448 7659 11900 13039 13796 19908 504 716 1551 5655 6245 8365 9825 16627 29100 88 900 1057 2620 16729 17278 17444 26106 26587 30 1697 1736 8718 11664 20885 27043 42569 42913 293 634 1188 4005 5266 6205 26756 30207 37757 254 755 1187 4631 13433 25055 28354 28583 30446 316 1381 1522 3131 4340 27284 28246 28282 43174 84 293 645 2148 7925 13104 25010 36836 39033 982 1486 1660 4287 5335 18350 26913 30774 31280 418 1028 1039 3334 4577 6553 7011 17259 31922 1324 1361 1690 5991 7740 16880 18479 25713 31823 735 1322 1727 8629 14655 15815 16762 23263 36859 19 928 1561 11161 12894 14226 21331 41128 41883 327 940 1004 13616 15894 31400 34106 34443 37957 576 953 1226 2122 4900 5002 10248 25476 30787 249 632 1240 5432 23019 29225 31719 36658 41360 980 1154 1783 4351 10245 23347 27442 28328 38555 581 863 1552 5057 7572 14544 20482 29482 31672 4 502 1450 4883 5176 6824 10430 32680 39581 81 761 1558 2269 5391 13213 24184 25523 39429 1085 1163 1244 7694 9125 17387 22223 26343 37933 204 1127 1483 18302 19939 20576 31599 32619 42911 345 387 591 8727 18080 20628 32251 34562 42821 957 1126 1133 4099 12272 15595 20906 23606 34564 409 1310 1335 2761 11952 26853 27941 29262 31647 329 818 1527 3890 5238 8742 15586 28739 43015 231 1158 1677 4314 15937 17526 18391 22963 39232 34 275 526 2975 4742 16109 17346 29145 37673 497 735 1261 7468 8769 17342 19763 32646 33497 879 1233 1633 11612 22941 23723 31969 35571 39510 886 954 1355 5532 8283 26965 29267 30820 40402 356 1199 1452 8833 14845 21722 23840 26539 27970 553 1570 1732 8249 16820 23181 23234 30754 40399 457 1304 1698 2774 11357 32906 34484 38700 41799 456 579 1155 23844 27261 29172 30980 35000 40984 301 1290 1782 6798 9735 23655 31040 35554 36366 228 483 561 12346 16698 32688 34518 38648 41677 35 184 997 4915 7077 9878 16772 26263 27270 181 193 1255 7548 17103 34511 36590 38107 42065 697 1024 1541 2164 15638 20061 32499 32667 32732 654 968 1632 3215 4901 6286 12414 13963 29636 89 150 450 5771 10863 29809 36886 37914 42983 517 1046 1153 5458 18093 25579 31084 37779 42050 345 914 1372 4548 6720 13678 13755 15422 41938 301 518 1107 3603 6076 9265 19580 41645 42621 155 1013 1441 10166 10545 22042 30084 33026 34505 899 1308 1766 22228 24520 24589 30833 32126 37147 177 230 349 6309 9642 25713 30455 34964 40524 802 1364 1703 3573 17317 20364 22849 24265 24925 3952 10609 11011 16296 31430 39995 40207 41606 42424 16548 19896 22579 23043 23126 24141 34331 34959 37990 12197 15244 22990 23110 25507 30011 37681 38902 39432 2292 11871 15562 22304 33059 35126 39158 41206 41866 3497 7847 11510 16212 19408 26780 27967 33953 34451 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted from a transmitting device.

[0015] In a second receiving device / method, a coding unit is provided that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 6 / 16, the check matrix including an A matrix at the top left of the check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, 608 1394 3635 14404 15203 19848 22161 23175 26651 31945 41227 481 570 11088 11673 11866 17145 17247 17564 21607 25992 31286 1207 1257 1870 8472 8855 10511 15656 17064 22720 28352 30914 1171 1585 6218 7621 10121 11374 13184 22714 27207 27959 38572 244 548 2073 4937 7509 11840 12850 18762 25618 27902 37150 15 1352 7060 7886 8151 10574 14172 15258 24838 30827 35337 1009 1651 13300 13958 26240 29983 32340 40743 41553 42475 42873 638 1405 5544 6797 10001 14934 24766 35758 40719 41787 42342 1467 1481 3202 11324 14048 15217 17608 22544 26736 32073 33405 1274 1343 3576 4166 8712 10756 21175 26866 37021 40341 42064 1232 1590 4409 8705 13307 28481 30893 36031 36780 37697 39149 189 1678 9943 10774 11765 25520 26133 27351 27353 40664 41534 125 1421 5009 9365 12792 15933 16231 25975 27076 27997 32429 1361 1764 5376 11071 14456 16324 20318 26168 28445 30392 34235 1017 1303 3312 6738 7813 18149 25506 29032 36789 38742 43116 463 967 10876 13874 14303 16789 21656 26555 38738 39195 40668 630 1104 3029 3165 5157 12880 14175 16498 35121 38917 40944 716 1054 10011 11739 16913 19396 20892 23370 24392 27614 38467 1081 1238 2872 10259 13618 16943 17363 23570 29721 32411 38969 775 1002 2978 9202 16618 22697 30716 31750 36517 37294 40454 25 497 10687 13308 15302 17525 17539 21865 22279 24516 26992 781 878 6426 8551 12328 21375 27626 28192 29731 35423 35606 729 1734 3479 6850 14347 14776 21998 33617 34690 38597 38704 122 1378 1660 7448 7659 11900 13039 13796 19908 504 716 1551 5655 6245 8365 9825 16627 29100 88 900 1057 2620 16729 17278 17444 26106 26587 30 1697 1736 8718 11664 20885 27043 42569 42913 293 634 1188 4005 5266 6205 26756 30207 37757 254 755 1187 4631 13433 25055 28354 28583 30446 316 1381 1522 3131 4340 27284 28246 28282 43174 84 293 645 2148 7925 13104 25010 36836 39033 982 1486 1660 4287 5335 18350 26913 30774 31280 418 1028 1039 3334 4577 6553 7011 17259 31922 1324 1361 1690 5991 7740 16880 18479 25713 31823 735 1322 1727 8629 14655 15815 16762 23263 36859 19 928 1561 11161 12894 14226 21331 41128 41883 327 940 1004 13616 15894 31400 34106 34443 37957 576 953 1226 2122 4900 5002 10248 25476 30787 249 632 1240 5432 23019 29225 31719 36658 41360 980 1154 1783 4351 10245 23347 27442 28328 38555 581 863 1552 5057 7572 14544 20482 29482 31672 4 502 1450 4883 5176 6824 10430 32680 39581 81 761 1558 2269 5391 13213 24184 25523 39429 1085 1163 1244 7694 9125 17387 22223 26343 37933 204 1127 1483 18302 19939 20576 31599 32619 42911 345 387 591 8727 18080 20628 32251 34562 42821 957 1126 1133 4099 12272 15595 20906 23606 34564 409 1310 1335 2761 11952 26853 27941 29262 31647 329 818 1527 3890 5238 8742 15586 28739 43015 231 1158 1677 4314 15937 17526 18391 22963 39232 34 275 526 2975 4742 16109 17346 29145 37673 497 735 1261 7468 8769 17342 19763 32646 33497 879 1233 1633 11612 22941 23723 31969 35571 39510 886 954 1355 5532 8283 26965 29267 30820 40402 356 1199 1452 8833 14845 21722 23840 26539 27970 553 1570 1732 8249 16820 23181 23234 30754 40399 457 1304 1698 2774 11357 32906 34484 38700 41799 456 579 1155 23844 27261 29172 30980 35000 40984 301 1290 1782 6798 9735 23655 31040 35554 36366 228 483 561 12346 16698 32688 34518 38648 41677 35 184 997 4915 7077 9878 16772 26263 27270 181 193 1255 7548 17103 34511 36590 38107 42065 697 1024 1541 2164 15638 20061 32499 32667 32732 654 968 1632 3215 4901 6286 12414 13963 29636 89 150 450 5771 10863 29809 36886 37914 42983 517 1046 1153 5458 18093 25579 31084 37779 42050 345 914 1372 4548 6720 13678 13755 15422 41938 301 518 1107 3603 6076 9265 19580 41645 42621 155 1013 1441 10166 10545 22042 30084 33026 34505 899 1308 1766 22228 24520 24589 30833 32126 37147 177 230 349 6309 9642 25713 30455 34964 40524 802 1364 1703 3573 17317 20364 22849 24265 24925 3952 10609 11011 16296 31430 39995 40207 41606 42424 16548 19896 22579 23043 23126 24141 34331 34959 37990 12197 15244 22990 23110 25507 30011 37681 38902 39432 2292 11871 15562 22304 33059 35126 39158 41206 41866 3497 7847 11510 16212 19408 26780 27967 33953 34451 The LDPC code obtained from the data transmitted from the transmitting device is decoded.

[0016] A third transmission device / method of the present technology includes an encoding unit / step for performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix being an A matrix in the upper left corner of the parity check matrix, an A matrix in the upper left corner of the parity check matrix, an A matrix in the upper left corner of the parity check matrix, an A matrix in the upper left corner of the parity check matrix, and an B matrix in the upper left corner of the parity check matrix. a Z matrix which is a zero matrix adjacent to the A matrix and the B matrix, a C matrix which is adjacent below the A matrix and the B matrix, and which has N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and which has N-K-M1 rows and N-K-M1 columns, wherein the predetermined value M1 is 4680, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 1012 3997 5398 5796 21940 23609 25002 28007 32214 33822 38194 1110 4016 5752 10837 15440 15952 17802 27468 32933 33191 35420 95 1953 6554 11381 12839 12880 22901 26742 26910 27621 37825 1146 2232 5658 13131 13785 16771 17466 20561 29400 32962 36879 2023 3420 5107 10789 12303 13316 14428 24912 35363 36348 38787 3283 3637 12474 14376 20459 22584 23093 28876 31485 31742 34849 1807 3890 4865 7562 9091 13778 18361 21934 24548 34267 38260 1613 3620 10165 11464 14071 20675 20803 26814 27593 29483 36485 849 3946 8585 9208 9939 14676 14990 19276 23459 30577 36838 1890 2583 5951 6003 11943 13641 16319 18379 22957 24644 33430 1936 3939 5267 6314 12665 19626 20457 22010 27958 30238 32976 2153 4318 6782 13048 17730 17923 24137 24741 25594 32852 33209 1869 4262 6616 13522 19266 19384 22769 28883 30389 35102 36019 3037 3116 7478 7841 10627 10908 14060 14163 23772 27946 37835 1668 3125 7485 8525 14659 22834 24080 24838 30890 33391 36788 1623 2836 6776 8549 11448 23281 32033 32729 33650 34069 34607 101 1420 5172 7475 11673 18807 21367 23095 26368 30888 37882 3874 3940 4823 16485 21601 21655 21885 25541 30177 31656 35067 592 643 4847 6870 7671 10412 25081 33412 33478 33495 35976 2578 2677 12592 17140 17185 21962 23206 23838 27624 32594 34828 3058 3443 4959 21179 22411 24033 26004 26489 26775 33816 36694 91 2998 10137 11957 12444 22330 24300 26008 26441 26521 38191 889 1840 8881 10228 12495 18162 22259 23385 25687 35853 38848 1332 3031 13482 14262 15897 23112 25954 28035 34898 36286 36991 2505 2599 10980 15245 20084 20114 24496 26309 31139 34090 37258 599 1778 8935 16154 19546 23537 24938 32059 32406 35564 37175 392 1777 4793 8050 10543 10668 14823 25252 32922 36658 37832 1680 2630 7190 7880 10894 20675 27523 33460 33733 34000 35829 532 3750 5075 10603 12466 19838 24231 24998 27647 35111 38617 1786 3066 11367 12452 13896 15346 24646 25509 26109 30358 37392 1027 1659 6483 16919 17636 18905 19741 30579 35934 36515 37617 2064 2354 14085 16460 21378 21719 22981 23329 31701 32057 32640 2009 4421 7595 8790 12803 17649 18527 24246 27584 28757 31794 364 646 9398 13898 17486 17709 20911 31493 31810 32019 33341 2246 3760 4911 19338 25792 27511 28689 30634 31928 34984 36605 3178 3544 8858 9336 9602 12290 16521 27872 28391 28422 36105 1981 2209 12718 20656 21253 22574 28653 29967 33692 36759 37871 787 1545 7652 8376 9628 9995 10289 16260 17606 22673 34564 795 4580 12749 16670 18727 19131 19449 26152 29165 30820 31678 1577 2980 8659 12301 13813 14838 20782 23068 30185 34308 34676 84 434 13572 21777 24581 28397 28490 32547 33282 34655 37579 2927 4440 8979 14992 19009 20435 23558 26280 31320 35106 37704 1974 2712 6552 8585 10051 14848 15186 22968 24285 25878 36054 585 1990 3457 5010 8808 9 2792 4678 22666 32922 342 507 861 18844 32947 554 3395 4094 8147 34616 356 2061 2801 20330 38214 425 2432 4573 7323 28157 73 1192 2618 7812 17947 842 1053 4088 10818 24053 1234 1249 4171 6645 37350 1498 2113 4175 6432 17014 524 2135 2205 6311 7502 191 954 3166 28938 31869 548 586 4101 12129 25819 127 2352 3215 6791 13523 286 4262 4423 14087 38061 1645 3551 4209 14083 15827 719 1087 2813 32857 34499 651 2752 4548 25139 25514 1702 4186 4478 10785 33263 34 3157 4196 5811 36555 643 649 1524 6587 27246 291 836 1036 18936 19201 78 1099 4174 18305 36119 3083 3173 4667 27349 32057 3449 4090 4339 18334 24596 503 3816 4465 29204 35316 102 1693 1799 17180 35877 288 324 1237 16167 33970 224 2831 3571 17861 28530 1202 2803 2834 4943 31485 1112 2196 3027 29308 37101 4242 4291 4503 16344 28769 1020 1927 3349 9686 33845 3179 3304 3891 8448 37247 1076 2319 4512 17010 18781 987 1391 3781 12318 35710 2268 3467 3619 15764 25608 764 1135 2224 8647 17486 2091 4081 4648 8101 33818 471 3668 4069 14925 36242 932 2140 3428 12523 33270 5840 8959 12039 15972 38496 5960 7759 10493 31160 38054 10380 14835 26024 35399 36517 5260 7306 13419 28804 31112 12747 23075 32458 36239 37437 14096 16976 21598 32228 34672 5024 5769 21798 22675 25316 8617 14189 17874 22776 29780 7628 13623 16676 30019 33213 14090 14254 18987 21720 38550 17306 17709 19135 22995 28597 13137 18028 23943 27468 37156 7704 8171 10815 28138 29526 The transmitting device / method is as follows.

[0017] In the third transmitting device / method, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 7 / 16. The check matrix includes an A matrix in the upper left of the check matrix, which is M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which is M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which is M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which is N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which is N-K-M1 rows and N-K-M1 columns, and the predetermined value M1 is 4680, and the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 1012 3997 5398 5796 21940 23609 25002 28007 32214 33822 38194 1110 4016 5752 10837 15440 15952 17802 27468 32933 33191 35420 95 1953 6554 11381 12839 12880 22901 26742 26910 27621 37825 1146 2232 5658 13131 13785 16771 17466 20561 29400 32962 36879 2023 3420 5107 10789 12303 13316 14428 24912 35363 36348 38787 3283 3637 12474 14376 20459 22584 23093 28876 31485 31742 34849 1807 3890 4865 7562 9091 13778 18361 21934 24548 34267 38260 1613 3620 10165 11464 14071 20675 20803 26814 27593 29483 36485 849 3946 8585 9208 9939 14676 14990 19276 23459 30577 36838 1890 2583 5951 6003 11943 13641 16319 18379 22957 24644 33430 1936 3939 5267 6314 12665 19626 20457 22010 27958 30238 32976 2153 4318 6782 13048 17730 17923 24137 24741 25594 32852 33209 1869 4262 6616 13522 19266 19384 22769 28883 30389 35102 36019 3037 3116 7478 7841 10627 10908 14060 14163 23772 27946 37835 1668 3125 7485 8525 14659 22834 24080 24838 30890 33391 36788 1623 2836 6776 8549 11448 23281 32033 32729 33650 34069 34607 101 1420 5172 7475 11673 18807 21367 23095 26368 30888 37882 3874 3940 4823 16485 21601 21655 21885 25541 30177 31656 35067 592 643 4847 6870 7671 10412 25081 33412 33478 33495 35976 2578 2677 12592 17140 17185 21962 23206 23838 27624 32594 34828 3058 3443 4959 21179 22411 24033 26004 26489 26775 33816 36694 91 2998 10137 11957 12444 22330 24300 26008 26441 26521 38191 889 1840 8881 10228 12495 18162 22259 23385 25687 35853 38848 1332 3031 13482 14262 15897 23112 25954 28035 34898 36286 36991 2505 2599 10980 15245 20084 20114 24496 26309 31139 34090 37258 599 1778 8935 16154 19546 23537 24938 32059 32406 35564 37175 392 1777 4793 8050 10543 10668 14823 25252 32922 36658 37832 1680 2630 7190 7880 10894 20675 27523 33460 33733 34000 35829 532 3750 5075 10603 12466 19838 24231 24998 27647 35111 38617 1786 3066 11367 12452 13896 15346 24646 25509 26109 30358 37392 1027 1659 6483 16919 17636 18905 19741 30579 35934 36515 37617 2064 2354 14085 16460 21378 21719 22981 23329 31701 32057 32640 2009 4421 7595 8790 12803 17649 18527 24246 27584 28757 31794 364 646 9398 13898 17486 17709 20911 31493 31810 32019 33341 2246 3760 4911 19338 25792 27511 28689 30634 31928 34984 36605 3178 3544 8858 9336 9602 12290 16521 27872 28391 28422 36105 1981 2209 12718 20656 21253 22574 28653 29967 33692 36759 37871 787 1545 7652 8376 9628 9995 10289 16260 17606 22673 34564 795 4580 12749 16670 18727 19131 19449 26152 29165 30820 31678 1577 2980 8659 12301 13813 14838 20782 23068 30185 34308 34676 84 434 13572 21777 24581 28397 28490 32547 33282 34655 37579 2927 4440 8979 14992 19009 20435 23558 26280 31320 35106 37704 1974 2712 6552 8585 10051 14848 15186 22968 24285 25878 36054 585 1990 3457 5010 8808 9 2792 4678 22666 32922 342 507 861 18844 32947 554 3395 4094 8147 34616 356 2061 2801 20330 38214 425 2432 4573 7323 28157 73 1192 2618 7812 17947 842 1053 4088 10818 24053 1234 1249 4171 6645 37350 1498 2113 4175 6432 17014 524 2135 2205 6311 7502 191 954 3166 28938 31869 548 586 4101 12129 25819 127 2352 3215 6791 13523 286 4262 4423 14087 38061 1645 3551 4209 14083 15827 719 1087 2813 32857 34499 651 2752 4548 25139 25514 1702 4186 4478 10785 33263 34 3157 4196 5811 36555 643 649 1524 6587 27246 291 836 1036 18936 19201 78 1099 4174 18305 36119 3083 3173 4667 27349 32057 3449 4090 4339 18334 24596 503 3816 4465 29204 35316 102 1693 1799 17180 35877 288 324 1237 16167 33970 224 2831 3571 17861 28530 1202 2803 2834 4943 31485 1112 2196 3027 29308 37101 4242 4291 4503 16344 28769 1020 1927 3349 9686 33845 3179 3304 3891 8448 37247 1076 2319 4512 17010 18781 987 1391 3781 12318 35710 2268 3467 3619 15764 25608 764 1135 2224 8647 17486 2091 4081 4648 8101 33818 471 3668 4069 14925 36242 932 2140 3428 12523 33270 5840 8959 12039 15972 38496 5960 7759 10493 31160 38054 10380 14835 26024 35399 36517 5260 7306 13419 28804 31112 12747 23075 32458 36239 37437 14096 16976 21598 32228 34672 5024 5769 21798 22675 25316 8617 14189 17874 22776 29780 7628 13623 16676 30019 33213 14090 14254 18987 21720 38550 17306 17709 19135 22995 28597 13137 18028 23943 27468 37156 7704 8171 10815 28138 29526 It has become.

[0018] A third receiving device / method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16, the parity check matrix including an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix that is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix that is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 4680, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents positions of elements of 1 in the A matrix and the C matrix every 360 columns, 1012 3997 5398 5796 21940 23609 25002 28007 32214 33822 38194 1110 4016 5752 10837 15440 15952 17802 27468 32933 33191 35420 95 1953 6554 11381 12839 12880 22901 26742 26910 27621 37825 1146 2232 5658 13131 13785 16771 17466 20561 29400 32962 36879 2023 3420 5107 10789 12303 13316 14428 24912 35363 36348 38787 3283 3637 12474 14376 20459 22584 23093 28876 31485 31742 34849 1807 3890 4865 7562 9091 13778 18361 21934 24548 34267 38260 1613 3620 10165 11464 14071 20675 20803 26814 27593 29483 36485 849 3946 8585 9208 9939 14676 14990 19276 23459 30577 36838 1890 2583 5951 6003 11943 13641 16319 18379 22957 24644 33430 1936 3939 5267 6314 12665 19626 20457 22010 27958 30238 32976 2153 4318 6782 13048 17730 17923 24137 24741 25594 32852 33209 1869 4262 6616 13522 19266 19384 22769 28883 30389 35102 36019 3037 3116 7478 7841 10627 10908 14060 14163 23772 27946 37835 1668 3125 7485 8525 14659 22834 24080 24838 30890 33391 36788 1623 2836 6776 8549 11448 23281 32033 32729 33650 34069 34607 101 1420 5172 7475 11673 18807 21367 23095 26368 30888 37882 3874 3940 4823 16485 21601 21655 21885 25541 30177 31656 35067 592 643 4847 6870 7671 10412 25081 33412 33478 33495 35976 2578 2677 12592 17140 17185 21962 23206 23838 27624 32594 34828 3058 3443 4959 21179 22411 24033 26004 26489 26775 33816 36694 91 2998 10137 11957 12444 22330 24300 26008 26441 26521 38191 889 1840 8881 10228 12495 18162 22259 23385 25687 35853 38848 1332 3031 13482 14262 15897 23112 25954 28035 34898 36286 36991 2505 2599 10980 15245 20084 20114 24496 26309 31139 34090 37258 599 1778 8935 16154 19546 23537 24938 32059 32406 35564 37175 392 1777 4793 8050 10543 10668 14823 25252 32922 36658 37832 1680 2630 7190 7880 10894 20675 27523 33460 33733 34000 35829 532 3750 5075 10603 12466 19838 24231 24998 27647 35111 38617 1786 3066 11367 12452 13896 15346 24646 25509 26109 30358 37392 1027 1659 6483 16919 17636 18905 19741 30579 35934 36515 37617 2064 2354 14085 16460 21378 21719 22981 23329 31701 32057 32640 2009 4421 7595 8790 12803 17649 18527 24246 27584 28757 31794 364 646 9398 13898 17486 17709 20911 31493 31810 32019 33341 2246 3760 4911 19338 25792 27511 28689 30634 31928 34984 36605 3178 3544 8858 9336 9602 12290 16521 27872 28391 28422 36105 1981 2209 12718 20656 21253 22574 28653 29967 33692 36759 37871 787 1545 7652 8376 9628 9995 10289 16260 17606 22673 34564 795 4580 12749 16670 18727 19131 19449 26152 29165 30820 31678 1577 2980 8659 12301 13813 14838 20782 23068 30185 34308 34676 84 434 13572 21777 24581 28397 28490 32547 33282 34655 37579 2927 4440 8979 14992 19009 20435 23558 26280 31320 35106 37704 1974 2712 6552 8585 10051 14848 15186 22968 24285 25878 36054 585 1990 3457 5010 8808 9 2792 4678 22666 32922 342 507 861 18844 32947 554 3395 4094 8147 34616 356 2061 2801 20330 38214 425 2432 4573 7323 28157 73 1192 2618 7812 17947 842 1053 4088 10818 24053 1234 1249 4171 6645 37350 1498 2113 4175 6432 17014 524 2135 2205 6311 7502 191 954 3166 28938 31869 548 586 4101 12129 25819 127 2352 3215 6791 13523 286 4262 4423 14087 38061 1645 3551 4209 14083 15827 719 1087 2813 32857 34499 651 2752 4548 25139 25514 1702 4186 4478 10785 33263 34 3157 4196 5811 36555 643 649 1524 6587 27246 291 836 1036 18936 19201 78 1099 4174 18305 36119 3083 3173 4667 27349 32057 3449 4090 4339 18334 24596 503 3816 4465 29204 35316 102 1693 1799 17180 35877 288 324 1237 16167 33970 224 2831 3571 17861 28530 1202 2803 2834 4943 31485 1112 2196 3027 29308 37101 4242 4291 4503 16344 28769 1020 1927 3349 9686 33845 3179 3304 3891 8448 37247 1076 2319 4512 17010 18781 987 1391 3781 12318 35710 2268 3467 3619 15764 25608 764 1135 2224 8647 17486 2091 4081 4648 8101 33818 471 3668 4069 14925 36242 932 2140 3428 12523 33270 5840 8959 12039 15972 38496 5960 7759 10493 31160 38054 10380 14835 26024 35399 36517 5260 7306 13419 28804 31112 12747 23075 32458 36239 37437 14096 16976 21598 32228 34672 5024 5769 21798 22675 25316 8617 14189 17874 22776 29780 7628 13623 16676 30019 33213 14090 14254 18987 21720 38550 17306 17709 19135 22995 28597 13137 18028 23943 27468 37156 7704 8171 10815 28138 29526 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted from a transmitting device.

[0019] In a third receiving device / method, a coding unit is provided that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16, the check matrix including an A matrix at the top left of the check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 4680, the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, 1012 3997 5398 5796 21940 23609 25002 28007 32214 33822 38194 1110 4016 5752 10837 15440 15952 17802 27468 32933 33191 35420 95 1953 6554 11381 12839 12880 22901 26742 26910 27621 37825 1146 2232 5658 13131 13785 16771 17466 20561 29400 32962 36879 2023 3420 5107 10789 12303 13316 14428 24912 35363 36348 38787 3283 3637 12474 14376 20459 22584 23093 28876 31485 31742 34849 1807 3890 4865 7562 9091 13778 18361 21934 24548 34267 38260 1613 3620 10165 11464 14071 20675 20803 26814 27593 29483 36485 849 3946 8585 9208 9939 14676 14990 19276 23459 30577 36838 1890 2583 5951 6003 11943 13641 16319 18379 22957 24644 33430 1936 3939 5267 6314 12665 19626 20457 22010 27958 30238 32976 2153 4318 6782 13048 17730 17923 24137 24741 25594 32852 33209 1869 4262 6616 13522 19266 19384 22769 28883 30389 35102 36019 3037 3116 7478 7841 10627 10908 14060 14163 23772 27946 37835 1668 3125 7485 8525 14659 22834 24080 24838 30890 33391 36788 1623 2836 6776 8549 11448 23281 32033 32729 33650 34069 34607 101 1420 5172 7475 11673 18807 21367 23095 26368 30888 37882 3874 3940 4823 16485 21601 21655 21885 25541 30177 31656 35067 592 643 4847 6870 7671 10412 25081 33412 33478 33495 35976 2578 2677 12592 17140 17185 21962 23206 23838 27624 32594 34828 3058 3443 4959 21179 22411 24033 26004 26489 26775 33816 36694 91 2998 10137 11957 12444 22330 24300 26008 26441 26521 38191 889 1840 8881 10228 12495 18162 22259 23385 25687 35853 38848 1332 3031 13482 14262 15897 23112 25954 28035 34898 36286 36991 2505 2599 10980 15245 20084 20114 24496 26309 31139 34090 37258 599 1778 8935 16154 19546 23537 24938 32059 32406 35564 37175 392 1777 4793 8050 10543 10668 14823 25252 32922 36658 37832 1680 2630 7190 7880 10894 20675 27523 33460 33733 34000 35829 532 3750 5075 10603 12466 19838 24231 24998 27647 35111 38617 1786 3066 11367 12452 13896 15346 24646 25509 26109 30358 37392 1027 1659 6483 16919 17636 18905 19741 30579 35934 36515 37617 2064 2354 14085 16460 21378 21719 22981 23329 31701 32057 32640 2009 4421 7595 8790 12803 17649 18527 24246 27584 28757 31794 364 646 9398 13898 17486 17709 20911 31493 31810 32019 33341 2246 3760 4911 19338 25792 27511 28689 30634 31928 34984 36605 3178 3544 8858 9336 9602 12290 16521 27872 28391 28422 36105 1981 2209 12718 20656 21253 22574 28653 29967 33692 36759 37871 787 1545 7652 8376 9628 9995 10289 16260 17606 22673 34564 795 4580 12749 16670 18727 19131 19449 26152 29165 30820 31678 1577 2980 8659 12301 13813 14838 20782 23068 30185 34308 34676 84 434 13572 21777 24581 28397 28490 32547 33282 34655 37579 2927 4440 8979 14992 19009 20435 23558 26280 31320 35106 37704 1974 2712 6552 8585 10051 14848 15186 22968 24285 25878 36054 585 1990 3457 5010 8808 9 2792 4678 22666 32922 342 507 861 18844 32947 554 3395 4094 8147 34616 356 2061 2801 20330 38214 425 2432 4573 7323 28157 73 1192 2618 7812 17947 842 1053 4088 10818 24053 1234 1249 4171 6645 37350 1498 2113 4175 6432 17014 524 2135 2205 6311 7502 191 954 3166 28938 31869 548 586 4101 12129 25819 127 2352 3215 6791 13523 286 4262 4423 14087 38061 1645 3551 4209 14083 15827 719 1087 2813 32857 34499 651 2752 4548 25139 25514 1702 4186 4478 10785 33263 34 3157 4196 5811 36555 643 649 1524 6587 27246 291 836 1036 18936 19201 78 1099 4174 18305 36119 3083 3173 4667 27349 32057 3449 4090 4339 18334 24596 503 3816 4465 29204 35316 102 1693 1799 17180 35877 288 324 1237 16167 33970 224 2831 3571 17861 28530 1202 2803 2834 4943 31485 1112 2196 3027 29308 37101 4242 4291 4503 16344 28769 1020 1927 3349 9686 33845 3179 3304 3891 8448 37247 1076 2319 4512 17010 18781 987 1391 3781 12318 35710 2268 3467 3619 15764 25608 764 1135 2224 8647 17486 2091 4081 4648 8101 33818 471 3668 4069 14925 36242 932 2140 3428 12523 33270 5840 8959 12039 15972 38496 5960 7759 10493 31160 38054 10380 14835 26024 35399 36517 5260 7306 13419 28804 31112 12747 23075 32458 36239 37437 14096 16976 21598 32228 34672 5024 5769 21798 22675 25316 8617 14189 17874 22776 29780 7628 13623 16676 30019 33213 14090 14254 18987 21720 38550 17306 17709 19135 22995 28597 13137 18028 23943 27468 37156 7704 8171 10815 28138 29526 The LDPC code obtained from the data transmitted from the transmitting device is decoded.

[0020] A fourth transmission device / method of the present technology includes an encoding unit / step for performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix being an A matrix in the upper left corner of the parity check matrix, having M1 rows and K columns, a B matrix of a staircase structure adjacent to the right of the A matrix, having M1 rows and M1 columns, and a B matrix of a staircase structure adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns. a Z matrix which is a zero matrix adjacent to the A matrix and the B matrix, a C matrix which is adjacent below the A matrix and the B matrix, and which has N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and which has N-K-M1 rows and N-K-M1 columns, wherein the predetermined value M1 is 3240, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 772 2281 3473 15662 19233 22166 24358 31768 34191 3072 3151 3484 20863 23023 26841 27472 27784 29651 2021 3203 4955 5144 12966 13620 14648 18456 30842 1806 2504 3675 6095 15703 15906 16025 19622 24749 745 954 14959 19379 21307 27232 30747 31580 34498 1289 2798 3630 11125 14405 16833 17549 27047 34127 744 805 5289 15458 24911 26399 28735 32526 32568 732 2368 7341 7508 9188 15676 18894 28544 32643 932 1971 3577 13308 13857 23512 27614 30417 34011 509 2152 3819 15873 18472 18916 20285 21421 29629 2475 3045 7516 12450 19365 21118 22154 22988 29632 1826 1847 4147 15787 16852 18336 22299 30945 33813 265 2184 9121 12341 12405 18908 29587 31365 33794 2599 2683 4025 6139 8989 15158 18010 28167 31929 845 2103 6653 7355 12824 15366 16277 17519 23286 1399 2887 11163 25401 26413 26782 27209 28194 33477 921 2171 5580 5853 10183 11788 27575 31160 34061 1908 2156 5805 13283 14262 19954 21960 29163 32575 252 1729 10690 18304 18921 23512 23540 28800 29738 1471 2630 5594 8245 15787 25205 28758 30257 30851 348 1947 5694 17122 20090 21065 22347 29035 33466 737 1373 6599 6614 19068 26595 27778 28013 28882 364 430 6008 6607 8543 13936 23464 29610 31484 2229 2680 18999 20491 21334 26172 28296 28546 33400 1397 3104 5116 6493 6538 13889 25830 28978 32982 1620 2845 3850 10010 18108 18460 22770 23335 27961 498 2120 6084 9410 13331 14260 23516 23987 34035 1231 2804 7437 13770 20375 30750 32395 32396 34111 953 1902 5780 10797 22700 24101 26068 30912 32091 861 936 12129 19924 20120 21381 21388 21447 27204 731 2953 7262 17370 18981 22098 23033 28091 33702 490 583 7131 15101 16559 28310 28868 29782 32476 774 2299 4672 6318 8582 23242 31128 33233 33525 1180 1856 6398 11619 18864 23107 26863 27068 32107 1254 2724 9924 14935 17381 20494 28231 28315 29981 1421 1859 10349 13014 13756 16003 20857 21287 24049 894 1864 5740 6223 7764 10832 14172 16277 25480 401 1753 10617 11842 17705 25037 26925 28610 32447 836 1680 6209 10558 11877 18052 19470 19596 28767 1388 3186 6150 8082 8270 12210 22672 29391 33400 2539 2632 4691 6341 8535 18093 18920 20974 31393 1611 2540 4975 11114 13694 15237 15296 18284 29706 619 1682 11939 18221 23276 24770 25283 25410 32475 453 465 4205 7369 10207 12725 19737 20902 29125 1417 1526 17833 18009 18408 23118 28438 28886 34324 537 2396 6629 6707 6725 16691 17338 20424 23712 800 2808 6021 8438 10096 17394 21026 29668 33876 841 2257 10435 14237 16470 16753 23284 27020 30550 1524 2908 5865 10368 19372 26633 29011 30192 30678 32 1640 6508 11257 26512 26659 28075 30862 33427 1520 2860 15351 20014 20361 22955 23045 25940 29105 1848 3061 5809 6815 8987 17563 20524 22236 34381 1733 3082 5621 9635 12551 21520 21557 28829 31273 573 1926 3702 4446 7768 11703 12656 16747 32712 2705 2727 5610 6984 7075 9535 21223 23408 32966 1483 2888 5752 13993 22125 25473 27225 30868 34054 408 931 7731 7880 16550 16761 22642 25286 26968 217 2319 5061 6695 12187 17401 28224 30334 32593 1319 3188 10631 11963 17985 23154 24420 28803 32833 1471 2891 4175 5199 6623 6832 13063 18914 25227 757 1672 5079 7155 8150 11799 21473 27494 32731 1140 2034 7259 10518 12677 13273 17037 23868 29066 1250 3144 4255 8848 14589 25473 25509 27133 32673 2185 2773 2904 19831 32400 526 2408 2978 4992 9564 578 1746 2082 18696 24913 116 264 3061 4871 10963 447 1822 3231 18207 27174 2651 2999 3121 23668 27550 1255 1992 2049 4049 25914 64 79 1151 5004 13816 200 927 2939 13713 17084 2733 2798 3029 13090 32805 853 2811 2992 22211 26911 1514 2268 2539 23500 25820 395 2466 2940 8672 18048 806 1216 3135 6930 20670 997 1840 1910 17014 23446 672 1229 1879 24074 33504 661 1711 2178 10269 28513 2271 2396 2924 21728 27477 529 1049 1530 10830 33896 287 553 3234 5247 9578 2540 2755 2823 8364 25923 1273 1477 1899 10801 33426 115 1682 3012 7235 34142 770 875 1902 7121 27451 2021 3016 3161 8460 31418 827 1239 3118 9614 27521 54 763 2991 20076 33220 1048 1090 2609 8009 16443 1164 1181 1986 3586 19697 1249 1580 2088 6836 12021 402 847 3128 5938 29404 900 1802 2632 16352 23618 1236 1745 2266 14737 16547 20017 20848 24075 11014 15424 32909 5987 6407 24724 8867 22426 26033 4688 8615 28486 4008 17476 26160 6202 16436 21222 7867 9461 20071 8927 32032 33217 The transmitting device / method is as follows.

[0021] In the fourth transmitting device / method, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 8 / 16. The check matrix includes an A matrix at the top left of the check matrix, which is M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which is M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which is M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which is N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which is N-K-M1 rows and N-K-M1 columns, and the predetermined value M1 is 3240, and the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 772 2281 3473 15662 19233 22166 24358 31768 34191 3072 3151 3484 20863 23023 26841 27472 27784 29651 2021 3203 4955 5144 12966 13620 14648 18456 30842 1806 2504 3675 6095 15703 15906 16025 19622 24749 745 954 14959 19379 21307 27232 30747 31580 34498 1289 2798 3630 11125 14405 16833 17549 27047 34127 744 805 5289 15458 24911 26399 28735 32526 32568 732 2368 7341 7508 9188 15676 18894 28544 32643 932 1971 3577 13308 13857 23512 27614 30417 34011 509 2152 3819 15873 18472 18916 20285 21421 29629 2475 3045 7516 12450 19365 21118 22154 22988 29632 1826 1847 4147 15787 16852 18336 22299 30945 33813 265 2184 9121 12341 12405 18908 29587 31365 33794 2599 2683 4025 6139 8989 15158 18010 28167 31929 845 2103 6653 7355 12824 15366 16277 17519 23286 1399 2887 11163 25401 26413 26782 27209 28194 33477 921 2171 5580 5853 10183 11788 27575 31160 34061 1908 2156 5805 13283 14262 19954 21960 29163 32575 252 1729 10690 18304 18921 23512 23540 28800 29738 1471 2630 5594 8245 15787 25205 28758 30257 30851 348 1947 5694 17122 20090 21065 22347 29035 33466 737 1373 6599 6614 19068 26595 27778 28013 28882 364 430 6008 6607 8543 13936 23464 29610 31484 2229 2680 18999 20491 21334 26172 28296 28546 33400 1397 3104 5116 6493 6538 13889 25830 28978 32982 1620 2845 3850 10010 18108 18460 22770 23335 27961 498 2120 6084 9410 13331 14260 23516 23987 34035 1231 2804 7437 13770 20375 30750 32395 32396 34111 953 1902 5780 10797 22700 24101 26068 30912 32091 861 936 12129 19924 20120 21381 21388 21447 27204 731 2953 7262 17370 18981 22098 23033 28091 33702 490 583 7131 15101 16559 28310 28868 29782 32476 774 2299 4672 6318 8582 23242 31128 33233 33525 1180 1856 6398 11619 18864 23107 26863 27068 32107 1254 2724 9924 14935 17381 20494 28231 28315 29981 1421 1859 10349 13014 13756 16003 20857 21287 24049 894 1864 5740 6223 7764 10832 14172 16277 25480 401 1753 10617 11842 17705 25037 26925 28610 32447 836 1680 6209 10558 11877 18052 19470 19596 28767 1388 3186 6150 8082 8270 12210 22672 29391 33400 2539 2632 4691 6341 8535 18093 18920 20974 31393 1611 2540 4975 11114 13694 15237 15296 18284 29706 619 1682 11939 18221 23276 24770 25283 25410 32475 453 465 4205 7369 10207 12725 19737 20902 29125 1417 1526 17833 18009 18408 23118 28438 28886 34324 537 2396 6629 6707 6725 16691 17338 20424 23712 800 2808 6021 8438 10096 17394 21026 29668 33876 841 2257 10435 14237 16470 16753 23284 27020 30550 1524 2908 5865 10368 19372 26633 29011 30192 30678 32 1640 6508 11257 26512 26659 28075 30862 33427 1520 2860 15351 20014 20361 22955 23045 25940 29105 1848 3061 5809 6815 8987 17563 20524 22236 34381 1733 3082 5621 9635 12551 21520 21557 28829 31273 573 1926 3702 4446 7768 11703 12656 16747 32712 2705 2727 5610 6984 7075 9535 21223 23408 32966 1483 2888 5752 13993 22125 25473 27225 30868 34054 408 931 7731 7880 16550 16761 22642 25286 26968 217 2319 5061 6695 12187 17401 28224 30334 32593 1319 3188 10631 11963 17985 23154 24420 28803 32833 1471 2891 4175 5199 6623 6832 13063 18914 25227 757 1672 5079 7155 8150 11799 21473 27494 32731 1140 2034 7259 10518 12677 13273 17037 23868 29066 1250 3144 4255 8848 14589 25473 25509 27133 32673 2185 2773 2904 19831 32400 526 2408 2978 4992 9564 578 1746 2082 18696 24913 116 264 3061 4871 10963 447 1822 3231 18207 27174 2651 2999 3121 23668 27550 1255 1992 2049 4049 25914 64 79 1151 5004 13816 200 927 2939 13713 17084 2733 2798 3029 13090 32805 853 2811 2992 22211 26911 1514 2268 2539 23500 25820 395 2466 2940 8672 18048 806 1216 3135 6930 20670 997 1840 1910 17014 23446 672 1229 1879 24074 33504 661 1711 2178 10269 28513 2271 2396 2924 21728 27477 529 1049 1530 10830 33896 287 553 3234 5247 9578 2540 2755 2823 8364 25923 1273 1477 1899 10801 33426 115 1682 3012 7235 34142 770 875 1902 7121 27451 2021 3016 3161 8460 31418 827 1239 3118 9614 27521 54 763 2991 20076 33220 1048 1090 2609 8009 16443 1164 1181 1986 3586 19697 1249 1580 2088 6836 12021 402 847 3128 5938 29404 900 1802 2632 16352 23618 1236 1745 2266 14737 16547 20017 20848 24075 11014 15424 32909 5987 6407 24724 8867 22426 26033 4688 8615 28486 4008 17476 26160 6202 16436 21222 7867 9461 20071 8927 32032 33217 It has become.

[0022] A fourth receiving device / method of the present technology includes an encoding unit that performs LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16, the parity check matrix including an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix that is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix that is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 3240, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 772 2281 3473 15662 19233 22166 24358 31768 34191 3072 3151 3484 20863 23023 26841 27472 27784 29651 2021 3203 4955 5144 12966 13620 14648 18456 30842 1806 2504 3675 6095 15703 15906 16025 19622 24749 745 954 14959 19379 21307 27232 30747 31580 34498 1289 2798 3630 11125 14405 16833 17549 27047 34127 744 805 5289 15458 24911 26399 28735 32526 32568 732 2368 7341 7508 9188 15676 18894 28544 32643 932 1971 3577 13308 13857 23512 27614 30417 34011 509 2152 3819 15873 18472 18916 20285 21421 29629 2475 3045 7516 12450 19365 21118 22154 22988 29632 1826 1847 4147 15787 16852 18336 22299 30945 33813 265 2184 9121 12341 12405 18908 29587 31365 33794 2599 2683 4025 6139 8989 15158 18010 28167 31929 845 2103 6653 7355 12824 15366 16277 17519 23286 1399 2887 11163 25401 26413 26782 27209 28194 33477 921 2171 5580 5853 10183 11788 27575 31160 34061 1908 2156 5805 13283 14262 19954 21960 29163 32575 252 1729 10690 18304 18921 23512 23540 28800 29738 1471 2630 5594 8245 15787 25205 28758 30257 30851 348 1947 5694 17122 20090 21065 22347 29035 33466 737 1373 6599 6614 19068 26595 27778 28013 28882 364 430 6008 6607 8543 13936 23464 29610 31484 2229 2680 18999 20491 21334 26172 28296 28546 33400 1397 3104 5116 6493 6538 13889 25830 28978 32982 1620 2845 3850 10010 18108 18460 22770 23335 27961 498 2120 6084 9410 13331 14260 23516 23987 34035 1231 2804 7437 13770 20375 30750 32395 32396 34111 953 1902 5780 10797 22700 24101 26068 30912 32091 861 936 12129 19924 20120 21381 21388 21447 27204 731 2953 7262 17370 18981 22098 23033 28091 33702 490 583 7131 15101 16559 28310 28868 29782 32476 774 2299 4672 6318 8582 23242 31128 33233 33525 1180 1856 6398 11619 18864 23107 26863 27068 32107 1254 2724 9924 14935 17381 20494 28231 28315 29981 1421 1859 10349 13014 13756 16003 20857 21287 24049 894 1864 5740 6223 7764 10832 14172 16277 25480 401 1753 10617 11842 17705 25037 26925 28610 32447 836 1680 6209 10558 11877 18052 19470 19596 28767 1388 3186 6150 8082 8270 12210 22672 29391 33400 2539 2632 4691 6341 8535 18093 18920 20974 31393 1611 2540 4975 11114 13694 15237 15296 18284 29706 619 1682 11939 18221 23276 24770 25283 25410 32475 453 465 4205 7369 10207 12725 19737 20902 29125 1417 1526 17833 18009 18408 23118 28438 28886 34324 537 2396 6629 6707 6725 16691 17338 20424 23712 800 2808 6021 8438 10096 17394 21026 29668 33876 841 2257 10435 14237 16470 16753 23284 27020 30550 1524 2908 5865 10368 19372 26633 29011 30192 30678 32 1640 6508 11257 26512 26659 28075 30862 33427 1520 2860 15351 20014 20361 22955 23045 25940 29105 1848 3061 5809 6815 8987 17563 20524 22236 34381 1733 3082 5621 9635 12551 21520 21557 28829 31273 573 1926 3702 4446 7768 11703 12656 16747 32712 2705 2727 5610 6984 7075 9535 21223 23408 32966 1483 2888 5752 13993 22125 25473 27225 30868 34054 408 931 7731 7880 16550 16761 22642 25286 26968 217 2319 5061 6695 12187 17401 28224 30334 32593 1319 3188 10631 11963 17985 23154 24420 28803 32833 1471 2891 4175 5199 6623 6832 13063 18914 25227 757 1672 5079 7155 8150 11799 21473 27494 32731 1140 2034 7259 10518 12677 13273 17037 23868 29066 1250 3144 4255 8848 14589 25473 25509 27133 32673 2185 2773 2904 19831 32400 526 2408 2978 4992 9564 578 1746 2082 18696 24913 116 264 3061 4871 10963 447 1822 3231 18207 27174 2651 2999 3121 23668 27550 1255 1992 2049 4049 25914 64 79 1151 5004 13816 200 927 2939 13713 17084 2733 2798 3029 13090 32805 853 2811 2992 22211 26911 1514 2268 2539 23500 25820 395 2466 2940 8672 18048 806 1216 3135 6930 20670 997 1840 1910 17014 23446 672 1229 1879 24074 33504 661 1711 2178 10269 28513 2271 2396 2924 21728 27477 529 1049 1530 10830 33896 287 553 3234 5247 9578 2540 2755 2823 8364 25923 1273 1477 1899 10801 33426 115 1682 3012 7235 34142 770 875 1902 7121 27451 2021 3016 3161 8460 31418 827 1239 3118 9614 27521 54 763 2991 20076 33220 1048 1090 2609 8009 16443 1164 1181 1986 3586 19697 1249 1580 2088 6836 12021 402 847 3128 5938 29404 900 1802 2632 16352 23618 1236 1745 2266 14737 16547 20017 20848 24075 11014 15424 32909 5987 6407 24724 8867 22426 26033 4688 8615 28486 4008 17476 26160 6202 16436 21222 7867 9461 20071 8927 32032 33217 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted from a transmitting device.

[0023] In a fourth receiving device / method, a coding unit is provided that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16, the check matrix including an A matrix at the top left of the check matrix, which has M1 rows and K columns, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 3240, the A matrix and the C matrix are represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 772 2281 3473 15662 19233 22166 24358 31768 34191 3072 3151 3484 20863 23023 26841 27472 27784 29651 2021 3203 4955 5144 12966 13620 14648 18456 30842 1806 2504 3675 6095 15703 15906 16025 19622 24749 745 954 14959 19379 21307 27232 30747 31580 34498 1289 2798 3630 11125 14405 16833 17549 27047 34127 744 805 5289 15458 24911 26399 28735 32526 32568 732 2368 7341 7508 9188 15676 18894 28544 32643 932 1971 3577 13308 13857 23512 27614 30417 34011 509 2152 3819 15873 18472 18916 20285 21421 29629 2475 3045 7516 12450 19365 21118 22154 22988 29632 1826 1847 4147 15787 16852 18336 22299 30945 33813 265 2184 9121 12341 12405 18908 29587 31365 33794 2599 2683 4025 6139 8989 15158 18010 28167 31929 845 2103 6653 7355 12824 15366 16277 17519 23286 1399 2887 11163 25401 26413 26782 27209 28194 33477 921 2171 5580 5853 10183 11788 27575 31160 34061 1908 2156 5805 13283 14262 19954 21960 29163 32575 252 1729 10690 18304 18921 23512 23540 28800 29738 1471 2630 5594 8245 15787 25205 28758 30257 30851 348 1947 5694 17122 20090 21065 22347 29035 33466 737 1373 6599 6614 19068 26595 27778 28013 28882 364 430 6008 6607 8543 13936 23464 29610 31484 2229 2680 18999 20491 21334 26172 28296 28546 33400 1397 3104 5116 6493 6538 13889 25830 28978 32982 1620 2845 3850 10010 18108 18460 22770 23335 27961 498 2120 6084 9410 13331 14260 23516 23987 34035 1231 2804 7437 13770 20375 30750 32395 32396 34111 953 1902 5780 10797 22700 24101 26068 30912 32091 861 936 12129 19924 20120 21381 21388 21447 27204 731 2953 7262 17370 18981 22098 23033 28091 33702 490 583 7131 15101 16559 28310 28868 29782 32476 774 2299 4672 6318 8582 23242 31128 33233 33525 1180 1856 6398 11619 18864 23107 26863 27068 32107 1254 2724 9924 14935 17381 20494 28231 28315 29981 1421 1859 10349 13014 13756 16003 20857 21287 24049 894 1864 5740 6223 7764 10832 14172 16277 25480 401 1753 10617 11842 17705 25037 26925 28610 32447 836 1680 6209 10558 11877 18052 19470 19596 28767 1388 3186 6150 8082 8270 12210 22672 29391 33400 2539 2632 4691 6341 8535 18093 18920 20974 31393 1611 2540 4975 11114 13694 15237 15296 18284 29706 619 1682 11939 18221 23276 24770 25283 25410 32475 453 465 4205 7369 10207 12725 19737 20902 29125 1417 1526 17833 18009 18408 23118 28438 28886 34324 537 2396 6629 6707 6725 16691 17338 20424 23712 800 2808 6021 8438 10096 17394 21026 29668 33876 841 2257 10435 14237 16470 16753 23284 27020 30550 1524 2908 5865 10368 19372 26633 29011 30192 30678 32 1640 6508 11257 26512 26659 28075 30862 33427 1520 2860 15351 20014 20361 22955 23045 25940 29105 1848 3061 5809 6815 8987 17563 20524 22236 34381 1733 3082 5621 9635 12551 21520 21557 28829 31273 573 1926 3702 4446 7768 11703 12656 16747 32712 2705 2727 5610 6984 7075 9535 21223 23408 32966 1483 2888 5752 13993 22125 25473 27225 30868 34054 408 931 7731 7880 16550 16761 22642 25286 26968 217 2319 5061 6695 12187 17401 28224 30334 32593 1319 3188 10631 11963 17985 23154 24420 28803 32833 1471 2891 4175 5199 6623 6832 13063 18914 25227 757 1672 5079 7155 8150 11799 21473 27494 32731 1140 2034 7259 10518 12677 13273 17037 23868 29066 1250 3144 4255 8848 14589 25473 25509 27133 32673 2185 2773 2904 19831 32400 526 2408 2978 4992 9564 578 1746 2082 18696 24913 116 264 3061 4871 10963 447 1822 3231 18207 27174 2651 2999 3121 23668 27550 1255 1992 2049 4049 25914 64 79 1151 5004 13816 200 927 2939 13713 17084 2733 2798 3029 13090 32805 853 2811 2992 22211 26911 1514 2268 2539 23500 25820 395 2466 2940 8672 18048 806 1216 3135 6930 20670 997 1840 1910 17014 23446 672 1229 1879 24074 33504 661 1711 2178 10269 28513 2271 2396 2924 21728 27477 529 1049 1530 10830 33896 287 553 3234 5247 9578 2540 2755 2823 8364 25923 1273 1477 1899 10801 33426 115 1682 3012 7235 34142 770 875 1902 7121 27451 2021 3016 3161 8460 31418 827 1239 3118 9614 27521 54 763 2991 20076 33220 1048 1090 2609 8009 16443 1164 1181 1986 3586 19697 1249 1580 2088 6836 12021 402 847 3128 5938 29404 900 1802 2632 16352 23618 1236 1745 2266 14737 16547 20017 20848 24075 11014 15424 32909 5987 6407 24724 8867 22426 26033 4688 8615 28486 4008 17476 26160 6202 16436 21222 7867 9461 20071 8927 32032 33217 The LDPC code obtained from the data transmitted from the transmitting device is decoded.

[0024] The transmitting device and the receiving device may be independent devices or may be internal blocks constituting a single device. Effect of the Invention

[0025] According to the present technology, good communication quality can be ensured in data transmission using LDPC codes.

[0026] Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in this disclosure. [Brief description of the drawings]

[0027] [Figure 1] FIG. 2 is a diagram illustrating a check matrix H of an LDPC code. [Diagram 2] 1 is a flowchart illustrating a procedure for decoding an LDPC code. [Diagram 3] FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 4] FIG. 13 is a diagram illustrating an example of a Tanner graph of a parity check matrix. [Diagram 5] FIG. 13 is a diagram illustrating an example of a variable node. [Figure 6] FIG. 2 is a diagram illustrating an example of a check node. [Figure 7] 1 is a diagram illustrating an example of the configuration of an embodiment of a transmission system to which the present technology is applied. [Figure 8] 2 is a block diagram showing an example of the configuration of a transmission device 11. FIG. [Figure 9] 13 is a block diagram showing an example of the configuration of a bit interleaver 116. FIG. [Figure 10] FIG. 13 is a diagram illustrating an example of a check matrix. [Figure 11] FIG. 13 is a diagram illustrating an example of a parity matrix. [Figure 12] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 13] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 14] FIG. 1 is a diagram illustrating an example of a Tanner graph for decoding an LDPC code. [Figure 15] FIG. 1 is a diagram showing an example of a parity matrix HT having a staircase structure and a Tanner graph corresponding to the parity matrix HT. [Figure 16] 11 is a diagram showing an example of a parity matrix HT of a check matrix H corresponding to an LDPC code after parity interleaving. FIG. [Figure 17] 11 is a flowchart illustrating an example of processing performed by the bit interleaver 116 and the mapper 117. [Figure 18] 2 is a block diagram showing an example of the configuration of an LDPC encoder 115. FIG. [Figure 19] 11 is a flowchart illustrating an example of a process of the LDPC encoder 115. [Figure 20] FIG. 13 is a diagram showing an example of a parity check matrix initial value table with a coding rate of 1 / 4 and a code length of 16200. [Figure 21] 11 is a diagram for explaining a method of obtaining a check matrix H from a check matrix initial value table. FIG. [Figure 22] FIG. 2 is a diagram illustrating a structure of a check matrix. [Diagram 23] FIG. 13 is a diagram illustrating an example of a check matrix initial value table. [Figure 24] 13 is a diagram for explaining matrix A generated from the check matrix initial value table. FIG. [Diagram 25] FIG. 1 is a diagram for explaining parity interleaving of a B matrix. [Figure 26] 11 is a diagram illustrating a C matrix generated from a check matrix initial value table. FIG. [Figure 27] FIG. 1 is a diagram for explaining parity interleaving of a D matrix. [Figure 28] FIG. 13 is a diagram showing a parity check matrix obtained by performing column permutation as parity deinterleaving to restore parity interleaving to its original state. [Figure 29] FIG. 13 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix. [Diagram 30] FIG. 13 is a diagram illustrating an example of a check matrix initial value table for a type-A code where N=69120 bits and r=2 / 16. [Diagram 31] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=3 / 16. [Diagram 32] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=3 / 16. [Diagram 33] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=4 / 16. [Diagram 34] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=5 / 16. [Diagram 35] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=5 / 16. [Diagram 36] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=6 / 16. [Figure 37] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=6 / 16. [Figure 38] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=7 / 16. [Figure 39] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=7 / 16. [Diagram 40] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=8 / 16. [Diagram 41] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=69120 bits and r=8 / 16. [Diagram 42] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=7 / 16. [Diagram 43]FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=7 / 16. [Diagram 44] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=7 / 16. [Diagram 45] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=7 / 16. [Diagram 46] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=8 / 16. [Figure 47] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=8 / 16. [Figure 48] FIG. 13 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=8 / 16. [Figure 49] FIG. 13 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=8 / 16. [Figure 50] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 51] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 52] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 53] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 54] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 55] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 56]FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 57] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 58] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 59] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 60] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 61] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 62] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=11 / 16. [Figure 63] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=11 / 16. [Figure 64] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=11 / 16. [Figure 65] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 66] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 67] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 68] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 69]FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 70] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 71] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 72] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 73] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 74] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 75] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 76] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 77] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 78] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 79] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 80] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 81] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 82]FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 83] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 84] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 85] FIG. 13 is a diagram showing another example of a check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 86] FIG. 13 is a diagram showing an example of a Tanner graph of an ensemble of degree sequences with column weight 3 and row weight 6. [Figure 87] FIG. 13 is a diagram showing an example of a Tanner graph of a multi-edge type ensemble. [Figure 88] FIG. 1 is a diagram illustrating a parity check matrix of the Type A method. [Figure 89] FIG. 1 is a diagram illustrating a parity check matrix of the Type A method. [Figure 90] FIG. 1 is a diagram illustrating a check matrix of the Type B method. [Figure 91] FIG. 1 is a diagram illustrating a check matrix of the Type B method. [Figure 92] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=2 / 16. [Figure 93] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=2 / 16. [Figure 94] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=3 / 16. [Figure 95] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=3 / 16. [Figure 96]FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=4 / 16. [Figure 97] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=4 / 16. [Figure 98] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=5 / 16. [Figure 99] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=5 / 16. [Figure 100] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=6 / 16. [Figure 101] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=6 / 16. [Figure 102] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=7 / 16. [Figure 103] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=7 / 16. [Figure 104] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=8 / 16. [Figure 105] FIG. 13 is a diagram showing the results of a simulation performed using a type A code with N=69120 bits and r=8 / 16. [Fig. 106] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=7 / 16. [Figure 107] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=7 / 16. [Figure 108] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=7 / 16. [Fig. 109] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=7 / 16. [Figure 110] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=8 / 16. [Figure 111] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=8 / 16. [Figure 112] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=8 / 16. [Figure 113] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=8 / 16. [Fig. 114] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=9 / 16. [Fig. 115] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=9 / 16. [Fig. 116] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=9 / 16. [Figure 117] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=9 / 16. [Figure 118] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=10 / 16. [Figure 119]FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=10 / 16. [Figure 120] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=10 / 16. [Figure 121] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=10 / 16. [Figure 122] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=11 / 16. [Figure 123] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=11 / 16. [Figure 124] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=11 / 16. [Fig. 125] FIG. 13 shows the simulation results of a simulation performed using another type-B code with N=69120 bits and r=11 / 16. [Fig. 126] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=12 / 16. [Figure 127] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=12 / 16. [Figure 128] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=12 / 16. [Figure 129] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=12 / 16. [Fig. 130]FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=13 / 16. [Fig. 131] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=13 / 16. [Fig. 132] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=13 / 16. [Fig. 133] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=13 / 16. [Fig. 134] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=14 / 16. [Fig. 135] FIG. 13 shows the results of a simulation performed using a Type B code with N=69120 bits and r=14 / 16. [Fig. 136] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=14 / 16. [Fig. 137] FIG. 13 shows simulation results of a simulation performed using another type-B code with N=69120 bits and r=14 / 16. [Fig. 138] FIG. 11 is a diagram illustrating an example of coordinates of a UC signal point when the modulation method is QPSK. [Figure 139] FIG. 13 is a diagram illustrating an example of the coordinates of signal points of a 2D NUC when the modulation method is 16QAM. [Fig. 140] FIG. 11 is a diagram showing an example of the coordinates of signal points of a 1D NUC when the modulation method is 1024QAM. [Fig. 141] FIG. 13 is a diagram showing the relationship between a 1024QAM symbol y and the real part Re(zs) and imaginary part Im(zs) of a complex number as the coordinates of a 1D NUC signal point zs corresponding to the symbol y. [Fig. 142] 13 is a block diagram showing an example of the configuration of a block interleaver 25. FIG. [Fig. 143] FIG. 2 is a diagram for explaining block interleaving performed by block interleaver 25. [Fig. 144] FIG. 2 is a diagram for explaining group-wise interleaving performed by group-wise interleaver 24. [Fig. 145] 2 is a block diagram showing an example of the configuration of a receiving device 12. FIG. [Fig. 146] 13 is a block diagram showing an example of the configuration of a bit deinterleaver 165. FIG. [Fig. 147] 11 is a flowchart illustrating an example of processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166. [Fig. 148] FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 149] 11 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix. FIG. [Fig. 150] FIG. 13 is a diagram showing an example of a transformed check matrix divided into 5×5 units. [Fig. 151] FIG. 11 is a block diagram showing an example of the configuration of a decoding device that performs P node operations collectively. [Fig. 152] 2 is a block diagram showing an example of the configuration of an LDPC decoder 166. FIG. [Fig. 153] 13 is a block diagram showing an example of the configuration of a block deinterleaver 54. FIG. [Fig. 154] 13 is a block diagram showing another example configuration of the bit deinterleaver 165. FIG. [Fig. 155] 1 is a block diagram showing a first exemplary configuration of a receiving system to which a receiving device 12 can be applied. [Fig. 156] 13 is a block diagram showing a second exemplary configuration of a receiving system to which the receiving device 12 can be applied. FIG. [Fig. 157] FIG. 13 is a block diagram showing a third exemplary configuration of a receiving system to which the receiving device 12 can be applied. [Fig. 158]It is a block diagram showing a configuration example of an embodiment of a computer to which this technology is applied.

Embodiment for Carrying Out the Invention

[0028] Hereinafter, embodiments of this technology will be described. Before that, however, LDPC codes will be described.

[0029] <LDPC Code>

[0030] Note that an LDPC code is a linear code and does not necessarily have to be binary, but here it will be described as being binary.

[0031] The most prominent feature of an LDPC code is that the parity check matrix that defines the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1"s in the elements of the matrix is very small (a matrix in which most elements are 0).

[0032] FIG. 1 is a diagram showing an example of a parity check matrix H of an LDPC code.

[0033] In the parity check matrix H of FIG. 1, the weight of each column (column weight) (the number of "1"s) (weight) is "3", and the weight of each row (row weight) is "6".

[0034] In encoding by an LDPC code (LDPC encoding), for example, a generator matrix G is generated based on the parity check matrix H, and this generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code).

[0035] Specifically, an encoding device that performs LDPC encoding first calculates the transpose matrix H of the parity check matrix H T and between them, the equation GH THere, when generator matrix G is a K×N matrix, the encoding device multiplies generator matrix G by a bit string (vector u) of K information bits to generate a codeword c (=uG) of N bits. The codeword (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication path.

[0036] Decoding of LDPC codes is an algorithm proposed by Gallager called Probabilistic Decoding, and can be performed by a message passing algorithm using belief propagation on a so-called Tanner graph consisting of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be referred to simply as nodes where appropriate.

[0037] FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

[0038] In the following, the real value (received LLR) that expresses the likelihood of the value being "0" of the i-th code bit of the LDPC code (one codeword) received on the receiving side as a log likelihood ratio is referred to as the received value u 0i Also, the message output from the check node is called u j Let the message output from the variable node be v i Let us assume that.

[0039] First, in decoding an LDPC code, as shown in FIG. 2, in step S11, an LDPC code is received, and a message (check node message) u j is initialized to "0", and a variable k, which is an integer and serves as a counter for repeated processing, is initialized to "0", and the process proceeds to step S12. In step S12, the received value u0i Based on this, the message (variable node message) v is generated by performing the calculation (variable node calculation) shown in Eq. (1). i is required, and this message v i Based on this, the message u is generated by performing the operation (check node operation) shown in equation (2). j is required.

[0040]

number

[0041]

number

[0042] Here, d in Eq. (1) and Eq. (2) v and d c are parameters that can be arbitrarily selected and indicate the number of "1"s in the vertical direction (columns) and horizontal direction (rows) of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H with a column weight of 3 and a row weight of 6 as shown in FIG. 1, d v =3,d c =6.

[0043] In the variable node operation of formula (1) and the check node operation of formula (2), messages input from edges (lines connecting variable nodes and check nodes) that are trying to output messages are not included in the operation, so the range of operation is 1 to d v -1 or 1 to d c -1. Also, the check node operation in equation (2) is actually a two-input v 1 ,v 2 The function R(v 1 ,v 2 ) table is created in advance and used successively (recursively) as shown in equation (4).

[0044]

number

[0045]

number

[0046] In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is greater than a predetermined number of iterative decoding cycles C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and the same processes are repeated thereafter.

[0047] Also, in step S13, if it is determined that the variable k is greater than C, the process proceeds to step S14, where the message v i is calculated and output, and the LDPC code decoding process is completed.

[0048]

number

[0049] Here, the calculation of formula (5) is different from the variable node calculation of formula (1) in that it returns messages u from all edges connected to the variable node. j This is done using

[0050] FIG. 3 is a diagram showing an example of a parity check matrix H of a (3,6) LDPC code (coding rate 1 / 2, code length 12).

[0051] In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, similarly to FIG.

[0052] FIG. 4 is a diagram showing a Tanner graph of the parity check matrix H in FIG.

[0053] Here, in Figure 4, a plus sign "+" indicates a check node, and an equal sign "=" indicates a variable node. The check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connections between the check nodes and variable nodes are edges, which correspond to the elements "1" of the parity check matrix.

[0054] That is, when the element in the j-th row and i-th column of the parity check matrix is ​​1, the i-th variable node from the top (the node marked "=") and the j-th check node from the top (the node marked "+") in Fig. 4 are connected by a branch. The branch indicates that the code bit corresponding to the variable node has a constraint corresponding to the check node.

[0055] In a Sum Product Algorithm, which is a decoding method for LDPC codes, variable node calculations and check node calculations are performed repeatedly.

[0056] FIG. 5 is a diagram showing variable node operations performed at the variable node.

[0057] At the variable node, the message v corresponding to the branch to be calculated is i is the message u from the remaining branches connected to the variable node. 1 and u 2 and the received value u 0i The messages corresponding to the other edges can be calculated in a similar manner.

[0058] FIG. 6 is a diagram illustrating check node operations performed at a check node.

[0059] Here, the check node operation of formula (2) can be rewritten as formula (6) using the relationship of the formula a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), where sign(x) is 1 when x≧0 and −1 when x<0.

[0060]

number

[0061] If we define the function φ(x) as φ(x)=ln(tanh(x / 2)) for x≧0, then the formula φ -1 (x)=2tanh -1 (e -x ) holds, so equation (6) can be transformed into equation (7).

[0062]

number

[0063] At the check node, the check node operation of equation (2) is performed according to equation (7).

[0064] That is, at the check node, as shown in Figure 6, the message u corresponding to the branch to be calculated is j is the message v from the remaining edges connected to the check node. 1 ,v 2 ,v 3 ,v 4 ,v 5 The messages corresponding to the other branches are calculated in the same way.

[0065] The function φ(x) in equation (7) is expressed as φ(x)=ln((e x +1) / (e x -1), and for x>0, φ(x)=φ -1 (x). The functions φ(x) and φ -1When (x) is implemented in hardware, it may be implemented using a look-up table (LUT), but both will use the same LUT.

[0066] <Example of a transmission system configuration using this technology>

[0067] FIG. 7 is a diagram showing an example of the configuration of an embodiment of a transmission system to which the present technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices are located in the same housing or not).

[0068] In FIG. 7, the transmission system includes a transmitting device 11 and a receiving device 12 .

[0069] The transmitting device 11 transmits (broadcasts) (transmits), for example, a television broadcast program, etc. That is, the transmitting device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits the encoded data via a communication path 13, such as a satellite line, terrestrial wave, or cable (wired line).

[0070] The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

[0071] Here, the LDPC code used in the transmission system of FIG. 7 is known to exhibit extremely high performance in an AWGN (Additive White Gaussian Noise) communication channel.

[0072] On the other hand, burst errors and erasures may occur in the communication path 13. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, particularly when the communication path 13 is a terrestrial wave, in a multipath environment where the D / U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power), the power of a specific symbol may become 0 (erasure) depending on the delay of the echo (path other than the main path).

[0073] Even in the case of flutter (a communication channel with zero delay and where an echo with a Doppler frequency is added), if the D / U is 0 dB, the Doppler frequency can cause the power of the entire OFDM symbol at a specific time to become 0 (erasure).

[0074] Furthermore, burst errors may occur due to the condition of the wiring from a receiving section (not shown) such as an antenna that receives a signal from the transmitting device 11 to the receiving device 12, or due to instability in the power supply of the receiving device 12.

[0075] On the other hand, in decoding the LDPC code, in the variable node corresponding to the column of the check matrix H, and in turn, the code bit of the LDPC code (the received value u 0i Since the variable node calculation of equation (1) involves the addition of (a), if an error occurs in the code bit used in the variable node calculation, the accuracy of the obtained message decreases.

[0076] In decoding an LDPC code, at a check node, the check node calculation of equation (7) is performed using a message obtained at a variable node connected to that check node. Therefore, if there are a large number of check nodes where multiple connected variable nodes (corresponding code bits of the LDPC code) simultaneously have errors (including erasures), the decoding performance deteriorates.

[0077] That is, for example, when two or more variable nodes connected to the check node are simultaneously erased, the check node returns to all the variable nodes a message with equal probability of the value being 0 and the value being 1. In this case, the check node returning the message with equal probability does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, the decoding process needs to be repeated many times, degrading the decoding performance and increasing the power consumption of the receiving device 12 that decodes the LDPC code.

[0078] Therefore, in the transmission system of FIG. 7, it is possible to improve the tolerance to burst errors and erasures while maintaining the performance in an AWGN communication path (AWGN channel).

[0079] <Configuration example of the transmitting device 11>

[0080] FIG. 8 is a block diagram showing an example of the configuration of the transmission device 11 of FIG.

[0081] In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation / multiplexer 111.

[0082] The mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112 .

[0083] The padder 112 performs necessary zero padding (insertion of nulls) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to a BB scrambler 113.

[0084] The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on ​​the data from the padder 112 and supplies the resulting data to a BCH encoder 114 .

[0085] The BCH encoder 114 BCH-encodes the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is to be LDPC-encoded.

[0086] The LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114 in accordance with, for example, a check matrix in which the parity matrix, which is the part corresponding to the parity bits of the LDPC code, has a dual diagonal structure, and outputs an LDPC code in which the LDPC target data is information bits.

[0087] That is, the LDPC encoder 115 performs LDPC encoding on the LDPC target data, for example, into an LDPC code (corresponding to a parity check matrix) defined in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, ATSC3.0, or another LDPC code, and outputs the resulting LDPC code.

[0088] Here, the LDPC code defined in the DVB-S.2 and ATSC3.0 standards and the LDPC code to be adopted in ATSC3.0 are IRA (Irregular Repeat Accumulate) codes, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described, for example, in "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

[0089] The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116 .

[0090] The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 , and supplies the bit-interleaved LDPC code to a mapper 117 .

[0091] The mapper 117 performs orthogonal modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code.

[0092] That is, the mapper 117 performs orthogonal modulation by mapping the LDPC code from the bit interleaver 116 to a signal point determined by a modulation method that performs orthogonal modulation of the LDPC code on an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with the carrier wave and a Q axis representing a Q component orthogonal to the carrier wave.

[0093] The number of signal points determined by the modulation method of the quadrature modulation performed by the mapper 117 is 2 m In this case, the m-bit code bits of the LDPC code are treated as a symbol (1 symbol), and the mapper 117 divides the LDPC code from the bit interleaver 116 into 2 m are mapped to a signal point representing a symbol among the signal points.

[0094] Here, the modulation method of the quadrature modulation performed by the mapper 117 includes, for example, modulation methods defined in the standards such as DVB-S.2 and ATSC3.0, and other modulation methods, that is, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. In the mapper 117, which modulation method is used for the quadrature modulation is set in advance according to, for example, the operation of the operator of the transmission device 11.

[0095] The data obtained by the processing in the mapper 117 (the mapping result of mapping symbols to signal points) is supplied to a time interleaver 118 .

[0096] The time interleaver 118 performs time interleaving (interleaving in the time direction) on a symbol-by-symbol basis on the data from the mapper 117, and supplies the resulting data to a SISO / MISO (Single Input Single Output / Multiple Input Single Output) encoder) 119.

[0097] The SISO / MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies the result to a frequency interleaver 120 .

[0098] The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on a symbol-by-symbol basis on the data from the SISO / MISO encoder 119 , and supplies the data to a frame builder & resource allocation unit (Frame Builder & Resource Allocation) 131 .

[0099] On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control, such as BB signaling (Base Band Signalling) (BB Header), for example.

[0100] The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114 , and supplies the resulting data to the LDPC encoder 122 .

[0101] The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115 , and supplies the resulting LDPC code to the mapper 123 .

[0102] Similar to mapper 117, mapper 123 performs orthogonal modulation by mapping the LDPC code from LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code, and supplies the resulting data to frequency interleaver 124.

[0103] Similar to the frequency interleaver 120 , the frequency interleaver 124 performs frequency interleaving on the data from the mapper 123 in symbol units, and supplies the data to a frame builder / resource allocation unit 131 .

[0104] The frame builder / resource allocation unit 131 inserts pilot symbols into required positions in the data (symbols) from the frequency interleavers 120 and 124, and constructs a frame consisting of a predetermined number of symbols (e.g., a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) from the resulting data (symbols), and supplies it to an OFDM generation unit 132.

[0105] The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder / resource allocating unit 131, and transmits the signal via the communication path 13 (FIG. 7).

[0106] The transmitting device 11 can be configured without some of the blocks shown in FIG. 8, such as the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

[0107] <Example of the configuration of the bit interleaver 116>

[0108] FIG. 9 is a block diagram showing an example of the configuration of the bit interleaver 116 in FIG.

[0109] The bit interleaver 116 has a function of interleaving data, and is made up of a parity interleaver 23 , a group-wise interleaver 24 , and a block interleaver 25 .

[0110] The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0111] The groupwise interleaver 24 performs groupwise interleaving on the LDPC code from the parity interleaver 23, and supplies the LDPC code after the groupwise interleaving to the block interleaver 25.

[0112] Here, in the groupwise interleaving, the LDPC code for one code is divided into 360-bit units equal to the unit size P described later from the beginning, and the 360 bits of one division are interleaved in bit group units by the LDPC code from the parity interleaver 23 as bit groups.

[0113] When performing groupwise interleaving, the error rate can be improved compared to the case where groupwise interleaving is not performed. As a result, good communication quality can be ensured in data transmission.

[0114] The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the groupwise interleaver 24. For example, the LDPC code for one code is symbolized into m-bit symbols that are the units of mapping, and supplied to the mapper 117 (FIG. 8).

[0115] Here, in the block interleaving, for example, columns as storage areas for storing a predetermined number of bits in the column (vertical) direction are arranged in the row (horizontal) direction by a number equal to the number of bits m of the symbol. The LDPC code from the groupwise interleaver 24 is written in the column direction and read in the row direction, so that the LDPC code is symbolized into m-bit symbols.

[0116] <Check Matrix of LDPC Code>

[0117] FIG. 10 is a diagram showing an example of a check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

[0118] The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and the information matrix H A and the parity matrix H corresponding to the parity bits T Therefore, the formula H = [H A |H T ](information matrix H A The elements of are the left elements, and the parity matrix H T The right-hand elements of the matrix are

[0119] Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are called the information length K and the parity length M, respectively, and the number of code bits of one LDPC code (one code word) is called the code length N (=K+M).

[0120] The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. Also, the check matrix H is a matrix with M×N rows and N columns (a matrix with M rows and N columns). A is an M × K matrix, and the parity matrix H T is an M × M matrix.

[0121] FIG. 11 shows a parity matrix H of a check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. T FIG.

[0122] Parity matrix H of check matrix H used for LDPC encoding by LDPC encoder 115 T For example, a parity matrix H similar to the check matrix H of the LDPC code defined in standards such as DVB-T.2 is used. T can be adopted.

[0123] Parity matrix H of the check matrix H of the LDPC code specified in standards such as DVB-T.2 TAs shown in FIG. 11, the parity matrix H T The row weight is 1 for the first row and 2 for all remaining rows. The column weight is 1 for the last column and 2 for all remaining columns.

[0124] As mentioned above, the parity matrix H T An LDPC code for a check matrix H having a staircase structure can be easily generated using the check matrix H.

[0125] That is, the LDPC code (one code word) is represented by a row vector c, and the column vector obtained by transposing the row vector is represented by c. T In addition, the information bit portion of row vector c, which is an LDPC code, is represented by row vector A, and the parity bit portion is represented by row vector T.

[0126] In this case, row vector c can be expressed as c = [A|T] (a row vector with the elements of row vector A as the left elements and the elements of row vector T as the right elements) with row vector A as the information bits and row vector T as the parity bits.

[0127] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c = [A|T] is the check matrix H = [H A |H T ]'s parity matrix H T When the step structure shown in FIG. 11 is used, the formula Hc T = 0 column vector Hc T This can be found sequentially (in order) by setting the elements of each row to 0, starting from the first row.

[0128] FIG. 12 is a diagram for explaining a check matrix H of an LDPC code defined in standards such as DVB-T.2.

[0129] The first KX columns of the check matrix H of an LDPC code defined in standards such as DVB-T.2 have a column weight of X, the next K3 columns have a column weight of 3, the next M-1 columns have a column weight of 2, and the last column has a column weight of 1.

[0130] Here, KX+K3+M-1+1 is equal to the code length N.

[0131] FIG. 13 is a diagram showing the column numbers KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in standards such as DVB-T.2.

[0132] Standards such as DVB-T.2 prescribe LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

[0133] For an LDPC code with a code length N of 64,800 bits, eleven nominal rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are specified, and for an LDPC code with a code length N of 16,200 bits, ten nominal rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are specified.

[0134] Hereinafter, a code length N of 64,800 bits will also be referred to as 64 kbits, and a code length N of 16,200 bits will also be referred to as 16 kbits.

[0135] Regarding LDPC codes, the code bits corresponding to columns with larger column weights in the parity check matrix H tend to have lower error rates.

[0136] In the check matrix H defined in standards such as DVB-T.2 and shown in Figures 12 and 13, the column weight tends to be larger toward the beginning (left side). Therefore, for the LDPC code corresponding to the check matrix H, the code bits at the beginning tend to be more resistant to errors (more resistant to errors), and the code bits at the end tend to be more vulnerable to errors.

[0137] <Parity interleave>

[0138] 14 to 16, the parity interleaving by the parity interleaver 23 of FIG. 9 will be described.

[0139] FIG. 14 is a diagram showing an example (part of) a Tanner graph of a parity check matrix of an LDPC code.

[0140] As shown in Fig. 14, when two or more of the variable nodes (corresponding code bits) connected to the check node simultaneously become erroneous such as erasure, the check node returns a message to all variable nodes connected to the check node, with equal probability that the value is 0 and that the value is 1. For this reason, when multiple variable nodes connected to the same check node simultaneously become erroneous such as erasure, the decoding performance deteriorates.

[0141] Incidentally, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in standards such as DVB-T.2, and the parity matrix H T As shown in Figure 11, it has a staircase structure.

[0142] Figure 15 shows the parity matrix H T and its parity matrix H T FIG. 1 is a diagram showing an example of a Tanner graph corresponding to

[0143] A in Fig. 15 shows the step structure of the parity matrix H TFIG. 15B shows an example of the parity matrix H T The Tanner graph corresponding to

[0144] The parity matrix H has a step structure. T In the parity matrix H, elements with a value of 1 are adjacent (except for the first row). T In the Tanner graph of, the parity matrix H T Two adjacent variable nodes corresponding to a column of two adjacent elements with a value of 1 are connected to the same check node.

[0145] Therefore, when parity bits corresponding to the above-mentioned two adjacent variable nodes become erroneous at the same time due to a burst error, erasure, or the like, the check nodes connected to the two variable nodes (variable nodes that use the parity bits to find a message) corresponding to the two erroneous parity bits return messages with equal probability of being 0 and 1 to the variable nodes connected to those check nodes, degrading the decoding performance.And, when the burst length (the number of consecutive erroneous parity bits) becomes large, the number of check nodes that return messages with equal probability increases, further degrading the decoding performance.

[0146] Therefore, in order to prevent the above-mentioned degradation of decoding performance, the parity interleaver 23 (FIG. 9) performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits.

[0147] FIG. 16 shows a parity matrix H of a check matrix H corresponding to an LDPC code after parity interleaving performed by the parity interleaver 23 in FIG. T FIG.

[0148] Here, the information matrix H of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is Ahas a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

[0149] A cyclic structure refers to a structure in which a column is equal to a cyclic shift of another column, and includes, for example, a structure in which the position of 1 in each row of each of P columns is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the first column of the P columns by the parity length M. Hereinafter, the P columns in the cyclic structure will be referred to as the unit size as appropriate.

[0150] As described with reference to Figs. 12 and 13, there are two types of LDPC codes defined in standards such as DVB-T.2, with code lengths N of 64,800 bits and 16,200 bits, and for both of these two types of LDPC codes, the unit size P is defined as 360, which is one of the divisors of the parity length M excluding 1 and M.

[0151] Also, the parity length M is a value other than a prime number expressed by the formula M=q×P=q×360, with the value q varying depending on the coding rate. Therefore, like the unit size P, the value q is one of the divisors of the parity length M other than 1 and M, and is obtained by dividing the parity length M by the unit size P (the product of P and q, which are divisors of the parity length M, is the parity length M).

[0152] As described above, the parity interleaver 23 interleaves the K+qx+y+1-th code bit of the code bits of the N-bit LDPC code into the K+Py+x+1-th code bit position, where K is the information length, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q, as parity interleaving.

[0153] The K+qx+y+1th code bit and the K+Py+x+1th code bit are both parity bits since they are code bits after the K+1th bit. Therefore, according to parity interleaving, the position of the parity bit of the LDPC code is moved.

[0154] With this type of parity interleaving, variable nodes (corresponding parity bits) connected to the same check node are spaced apart by the unit size P, i.e., 360 bits in this case. Therefore, if the burst length is less than 360 bits, it is possible to avoid a situation in which multiple variable nodes connected to the same check node experience an error at the same time, thereby improving resistance to burst errors.

[0155] In addition, the LDPC code after parity interleaving in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position matches the LDPC code of a check matrix (hereinafter also referred to as a transformed check matrix) obtained by performing column permutation in which the K+qx+y+1th column of the original check matrix H is replaced with the K+Py+x+1th column.

[0156] Furthermore, in the parity matrix of the converted check matrix, as shown in FIG. 16, a quasi-cyclic structure appears with P columns (360 columns in FIG. 16) as a unit.

[0157] Here, the pseudo-cyclic structure means a structure in which all but a few parts are cyclic structures.

[0158] The transformed check matrix obtained by performing column permutation equivalent to parity interleaving on the check matrix of the LDPC code defined in standards such as DVB-T.2 has a 360 row by 360 column portion in the upper right corner of the transformed check matrix (the shift matrix described below) that is missing one element of 1 (it becomes an element of 0). In that respect, it is not a (completely) cyclic structure, but rather a quasi-cyclic structure.

[0159] The conversion check matrix for the check matrix of the LDPC code output by the LDPC encoder 115 has a quasi-cyclic structure, similar to the conversion check matrix for the check matrix of the LDPC code defined in standards such as DVB-T.2.

[0160] In addition, the transformed check matrix in Figure 16 is a matrix in which, in addition to column permutation equivalent to parity interleaving, row permutation (row permutation) has also been performed on the original check matrix H so that the transformed check matrix is ​​composed of the constituent matrices described below.

[0161] FIG. 17 is a flowchart illustrating the processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 in FIG.

[0162] The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101 encodes the LDPC target data into an LDPC code and supplies the LDPC code to the bit interleaver 116, after which the process proceeds to step S102.

[0163] In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, and supplies the symbols obtained by the bit interleaving to the mapper 117, and the process proceeds to step S103.

[0164] That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0165] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 , and supplies the result to a block interleaver 25 .

[0166] The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24 , and supplies the m-bit symbol obtained as a result to the mapper 117 .

[0167] In step S103, the mapper 117 converts the symbols from the block interleaver 25 into binary symbols determined by the modulation method of the quadrature modulation performed by the mapper 117. m signal points and orthogonally modulated, and the resulting data is supplied to a time interleaver 118.

[0168] As described above, by performing parity interleaving or group-wise interleaving, it is possible to improve the error rate when a plurality of code bits of an LDPC code are transmitted as one symbol.

[0169] Here, in FIG. 9, for ease of explanation, parity interleaver 23, which is a block that performs parity interleaving, and groupwise interleaver 24, which is a block that performs groupwise interleaving, are configured separately, but parity interleaver 23 and groupwise interleaver 24 can be configured as an integrated unit.

[0170] In other words, both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to memory, and can be represented by a matrix that converts the address at which the code bits are written (write address) into the address at which the code bits are read (read address).

[0171] Therefore, if a matrix obtained by multiplying a matrix representing parity interleaving and a matrix representing group-wise interleaving is obtained, by these matrices, by converting the code bits, parity interleaving can be performed, and further, as a result of group-wise interleaving the LDPC code after the parity interleaving can be obtained.

[0172] In addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can also be integrally configured.

[0173] That is, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write address of the memory storing the LDPC code into the read address.

[0174] Therefore, if a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing group-wise interleaving, and a matrix representing block interleaving is obtained, by these matrices, parity interleaving, group-wise interleaving, and block interleaving can be performed collectively.

[0175] Note that one or both of the parity interleaving and the group-wise interleaving can be not performed.

[0176] <Configuration example of LDPC encoder 115>

[0177] FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

[0178] Note that the LDPC encoder 122 of FIG. 8 is also configured in the same manner.

[0179] As described with reference to FIGS. 12 and 13, in standards such as DVB-T.2, LDPC codes with two code lengths N of 64800 bits and 16200 bits are defined.

[0180] For an LDPC code with a code length N of 64,800 bits, eleven coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10. For an LDPC code with a code length N of 16,200 bits, ten coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 (Figures 12 and 13).

[0181] The LDPC encoder 115 can perform, for example, such encoding (error correction encoding) using LDPC codes with each coding rate having a code length N of 64,800 bits or 16,200 bits, in accordance with a check matrix H prepared for each code length N and each coding rate.

[0182] Additionally, the LDPC encoder 115 can perform LDPC encoding in accordance with a check matrix H of an LDPC code with an arbitrary code length N and an arbitrary coding rate r.

[0183] The LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602 .

[0184] The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616, and performs LDPC encoding of the LDPC target data supplied to the LDPC encoder 115, and supplies the resulting LDPC code to the bit interleaver 116 (FIG. 8).

[0185] That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information for specifying the LDPC code, in response to, for example, an operation by an operator.

[0186] The initial value table reading unit 612 reads from the storage unit 602 a check matrix initial value table, which will be described later, indicating a check matrix of an LDPC code specified by the specification information set by the coding rate setting unit 611 .

[0187] The check matrix generating unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612, and stores the check matrix H in the storage unit 602. For example, the check matrix generating unit 613 generates an information matrix H corresponding to an information length K (=code length N-parity length M) according to the code length N and coding rate r set by the coding rate setting unit 611. A The check matrix H is generated by arranging elements of 1 in the column direction at a period of 360 columns (unit size P), and is stored in the storage unit 602.

[0188] The information bit reading unit 614 reads (extracts) information bits of an information length K from the LDPC target data supplied to the LDPC encoder 115.

[0189] The encoded parity calculation unit 615 reads out the check matrix H generated by the check matrix generation unit 613 from the memory unit 602, and uses the check matrix H to calculate parity bits for the information bits read out by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

[0190] The control unit 616 controls each block constituting the encoding processing unit 601 .

[0191] The storage unit 602 stores a plurality of check matrix initial value tables and the like corresponding to a plurality of coding rates and the like shown in Fig. 12 and Fig. 13 for each code length N of, for example, 64800 bits, 16200 bits, etc. Also, the storage unit 602 temporarily stores data necessary for the processing of the encoding processing unit 601.

[0192] FIG. 19 is a flowchart illustrating an example of the processing of the LDPC encoder 115 in FIG.

[0193] In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for performing LDPC coding, and other specific information for specifying the LDPC code.

[0194] In step S202, the initial value table reading unit 612 reads from the storage unit 602 a predetermined check matrix initial value table specified by the code length N, the coding rate r, and the like, which are specified information set by the coding rate setting unit 611.

[0195] In step S203, the check matrix generation unit 613 uses the check matrix initial value table read out from the memory unit 602 by the initial value table reading unit 612 to determine (generate) a check matrix H of the LDPC code having the code length N and coding rate r set by the coding rate setting unit 611, and supplies the check matrix H to the memory unit 602 for storage.

[0196] In step S204, the information bit reading unit 614 reads out information bits of an information length K (=N×r) corresponding to the code length N and coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and also reads out the check matrix H calculated by the check matrix generation unit 613 from the storage unit 602 and supplies it to the encoding parity calculation unit 615.

[0197] In step S205, the encoded parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate parity bits of the codeword c that satisfies equation (8).

[0198] Hc T =0 (8)

[0199] In equation (8), c represents a row vector as a codeword (LDPC code), and T represents the transpose of the row vector c.

[0200] Here, as described above, in the row vector c as an LDPC code (one code word), when the information bit portion is represented by row vector A and the parity bit portion is represented by row vector T, the row vector c can be expressed by the equation c = [A|T] with row vector A as the information bit and row vector T as the parity bit.

[0201] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c = [A|T] is the check matrix H = [H A |H T ]'s parity matrix H T When the step structure shown in FIG. 11 is used, the formula Hc T = 0 column vector Hc T This can be calculated sequentially by setting the elements of each row to 0, starting from the first row.

[0202] The encoded parity calculation unit 615 calculates a parity bit T for the information bit A from the information bit reading unit 614, and outputs a codeword c = [A|T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

[0203] After that, in step S206, the control unit 616 judges whether or not to end the LDPC encoding. In step S206, if it is judged that the LDPC encoding is not to end, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the processes of steps S201 (or step S204) to S206 are repeated.

[0204] Also, in step S206, if it is determined that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, LDPC encoder 115 ends the process.

[0205] For the LDPC encoder 115, a check matrix initial value table (representing a check matrix) of LDPC codes having various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform LDPC encoding into LDPC codes having various code lengths N and coding rates r by using a check matrix H generated from the check matrix initial value table prepared in advance.

[0206] <Example of check matrix initial value table>

[0207] The check matrix initial value table is, for example, an information matrix H corresponding to an information length K according to the code length N and the coding rate r of the LDPC code (LDPC code defined by the check matrix H) of the check matrix H. A This is a table showing the positions of elements of 1 in (FIG. 10) for every 360 columns (unit size P), and is created in advance for each parity check matrix H for each code length N and each coding rate r.

[0208] That is, the check matrix initial value table includes at least the information matrix H A Represents the position of element 1 for every 360 columns (unit size P).

[0209] In addition, the check matrix H contains a parity matrix H T All of the check matrices have a step structure, and the parity matrix H T There is a parity check matrix in which a part of it has a staircase structure and the remaining part is a diagonal matrix (unit matrix).

[0210] Below, the parity matrix H T The representation method of the parity check matrix initial value table, which represents a parity check matrix in which a part of the matrix has a staircase structure and the remaining part is a diagonal matrix, is also called the Type A method. TThe representation method of the check matrix initial value table representing the check matrix in which all of the check matrices have a staircase structure is also called the Type B method.

[0211] An LDPC code for a check matrix represented by a check matrix initial value table of the Type A method is also called a Type A code, and an LDPC code for a check matrix represented by a check matrix initial value table of the Type B method is also called a Type B code.

[0212] The designations "Type A" and "Type B" are based on the ATSC 3.0 standard. For example, ATSC 3.0 uses both Type A and Type B codes.

[0213] In addition, type B coding is adopted in DVB-T.2 and the like.

[0214] FIG. 20 is a diagram showing an example of a parity check matrix initial value table of the Type B method.

[0215] That is, FIG. 20 shows a check matrix initial value table (representing check matrix H) for a type B code having a code length N of 16,200 bits and a coding rate (the notational coding rate in DVB-T.2) r of 1 / 4, as specified in the DVB-T.2 standard.

[0216] The check matrix generating unit 613 (FIG. 18) uses the check matrix initial value table of the Type B method to obtain the check matrix H as follows.

[0217] FIG. 21 is a diagram for explaining a method of obtaining a check matrix H from a check matrix initial value table of the Type B method.

[0218] That is, FIG. 21 shows a check matrix initial value table for a type B code having a code length N of 16200 bits and a coding rate r of 2 / 3, which is defined in the DVB-T.2 standard.

[0219] The check matrix initial value table of the Type B method is an information matrix H corresponding to an information length K according to the code length N and the coding rate r of the LDPC code. AIn the i-th row, row numbers of elements that are 1 in the 1+360×(i-1)-th column of the parity check matrix H (row numbers assuming that the row number of the 1st row of the parity check matrix H is 0) are listed as many times as the column weight of the 1+360×(i-1)-th column.

[0220] Here, the parity matrix H corresponding to the parity length M of the check matrix H of the Type B method is T Since (FIG. 10) is determined to have a staircase structure as shown in FIG. 15, the information matrix H corresponding to the information length K is determined by the check matrix initial value table. A If (FIG. 10) can be obtained, the check matrix H can be obtained.

[0221] The number of rows k+1 of the check matrix initial value table of the Type B method varies depending on the information length K.

[0222] The relationship of equation (9) holds between the information length K and the number of rows (k+1) of the parity check matrix initial value table.

[0223] K = (k + 1) × 360 (9)

[0224] Here, 360 in equation (9) is the unit size P described in FIG.

[0225] In the parity check matrix initial value table in FIG. 21, 13 numerical values ​​are arranged in the first to third rows, and 3 numerical values ​​are arranged in the fourth to k+1 rows (the 30th row in FIG. 21).

[0226] Therefore, the column weight of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 21 is 13 from the 1st column to the 1+360×(3−1)−1th column, and is 3 from the 1+360×(3−1)th column to the Kth column.

[0227] The first row of the parity check matrix initial value table in Figure 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of parity check matrix H, the elements of the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

[0228] In addition, the second row of the parity check matrix initial value table in Figure 21 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which indicates that in the 361st (=1+360×(2-1))th column of parity check matrix H, the elements of the rows with row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 are 1.

[0229] As described above, the check matrix initial value table is the information matrix H A Represents the position of elements with a value of 1 in every 360 columns.

[0230] Columns other than the 1+360×(i-1)th column of the check matrix H, i.e., each column from the 2+360×(i-1)th column to the 360×ith column, are arranged by periodically cyclically shifting an element of 1 in the 1+360×(i-1)th column, as determined by the check matrix initial value table, downward (downward in the column) according to the parity length M.

[0231] That is, for example, the 2+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by M / 360(=q), and the next 3+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by 2×M / 360(=2×q) (the 2+360×(i-1)th column cyclically shifted downward by M / 360(=q)).

[0232] Now, let the value in the i-th row (i-th from the top) and j-th column (j-th from the left) of the check matrix initial value table be h i,j The row number of the j-th element of 1 in the w-th column of the check matrix H is expressed as H w-j Then, the row number H of the element of 1 in the w-th column, which is a column other than the 1+360×(i-1)-th column of the check matrix H, is w-j can be calculated using equation (10).

[0233] H w-j =mod{h i,j +mod((w-1),P)×q,M) (10)

[0234] Here, mod(x,y) means the remainder when x is divided by y.

[0235] Moreover, P is the unit size described above, and in this embodiment, it is 360, similar to the standards such as DVB-T.2 and ATSC3.0. Furthermore, q is a value M / 360 obtained by dividing the parity length M by the unit size P (=360).

[0236] The check matrix generating unit 613 (FIG. 18) identifies the row number of the element equal to 1 in the 1+360×(i−1)th column of the check matrix H, using the check matrix initial value table.

[0237] Furthermore, the check matrix generation unit 613 (FIG. 18) calculates the row number H of the element 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the check matrix H. w-j is calculated according to equation (10), and a check matrix H is generated in which the elements of the row numbers obtained above are set to 1.

[0238] FIG. 22 is a diagram showing the structure of parity check matrix H of the Type A method.

[0239] The check matrix of the Type A method is made up of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

[0240] Matrix A is an upper left matrix of parity check matrix H, with M1 rows and K columns, expressed by a predetermined value M1 and information length K of the LDPC code=code length N×coding rate r.

[0241] The B matrix is ​​a step structure matrix adjacent to the right of the A matrix, with M1 rows and M1 columns.

[0242] The C matrix is ​​a matrix adjacent below the A matrix and the B matrix, with N-K-M1 rows and K+M1 columns.

[0243] The D matrix is ​​an identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns.

[0244] The Z matrix is ​​a zero matrix (0 matrix) adjacent to the right of the B matrix, with M1 rows and NK-M1 columns.

[0245] In the type A check matrix H composed of the above-mentioned A matrices through D matrices and Z matrix, the A matrix and a part of the C matrix constitute an information matrix, and the remaining parts of the B matrix, the C matrix, the D matrix, and the Z matrix constitute a parity matrix.

[0246] Since matrix B is a matrix with a staircase structure and matrix D is a unit matrix, a part of the parity matrix of check matrix H of the Type A method (the part of matrix B) has a staircase structure and the remaining part (the part of matrix D) is a diagonal matrix (unit matrix).

[0247] Like the information matrix of the parity check matrix H of the Type B method, the A matrix and the C matrix have a cyclic structure for each column of unit size P (e.g., 360 columns), and the parity check matrix initial value table of the Type A method represents the positions of elements of 1 in the A matrix and the C matrix for each 360 columns.

[0248] Here, as described above, the A matrix and a part of the C matrix constitute an information matrix, so it can be said that the Type A method check matrix initial value table, which represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, at least represents the positions of elements of 1 in the information matrix every 360 columns.

[0249] In addition, since the Type A method parity check matrix initial value table represents the positions of elements of 1 in the A matrix and C matrix every 360 columns, it can also be said that it represents the positions of elements of 1 in a part of the parity check matrix (the remaining part of the C matrix) every 360 columns.

[0250] FIG. 23 is a diagram showing an example of a parity check matrix initial value table of the Type A method.

[0251] That is, FIG. 23 shows an example of a parity check matrix initial value table representing a parity check matrix H with a code length N of 35 bits and a coding rate r of 2 / 7.

[0252] The Type A method check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for each unit size P, and in its i-th row, the row numbers of elements of 1 in the 1+P×(i-1)th column of check matrix H (row numbers assuming that the row number of the 1st row of check matrix H is 0) are listed in the same order as the column weight of the 1+P×(i-1)th column.

[0253] For ease of explanation, it is assumed here that the unit size P is, for example, 5.

[0254] The check matrix H of the Type A system has parameters M1, M2, Q1, and Q2.

[0255] M1 (FIG. 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the unit size P. By adjusting M1, the performance of the LDPC code changes, and it is adjusted to a predetermined value when determining the check matrix H. Here, it is assumed that 15, which is three times the unit size P=5, is adopted as M1.

[0256] M2 (FIG. 22) is the value M-M1 obtained by subtracting M1 from the parity length M.

[0257] Here, the information length K is N×r=35×2 / 7=10, and the parity length M is NK=35-10=25, so M2 is M-M1=25-15=10.

[0258] Q1 is calculated according to the equation Q1=M1 / P, and represents the number of cyclic shifts (number of rows) in the A matrix.

[0259] In other words, the columns other than the 1+P×(i-1)th column of the A matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting an element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

[0260] Q2 is calculated according to the equation Q2=M2 / P, and represents the number of cyclic shifts (number of rows) in the C matrix.

[0261] In other words, columns other than the 1+P×(i-1)th column of the C matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting elements of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q2 represents the number of cyclic shifts in the C matrix.

[0262] Here, Q1 is M1 / P=15 / 5=3, and Q2 is M2 / P=10 / 5=2.

[0263] In the parity check matrix initial value table of FIG. 23, three numerical values ​​are listed in the first and second rows, and one numerical value is listed in the third to fifth rows. According to this arrangement of numerical values, the column weights of the A matrix and C matrix portions of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 23 are 3 from the 1=1+5×(1-1)th column to the 10=5×2nd column, and 1 from the 11=1+5×(3-1)th column to the 25=5×5th column.

[0264] That is, the first row of the parity check matrix initial value table in FIG. 23 is 2, 6, 18, which indicates that in the first column of the parity check matrix H, the elements in the rows with row numbers 2, 6, 18 are 1 (and the other elements are 0).

[0265] In this case, since matrix A (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns) and matrix C (Figure 22) is a matrix with 10 rows and 25 columns (NK-M1 rows and K+M1 columns), the rows with row numbers 0 to 14 of check matrix H are rows of matrix A, and the rows with row numbers 15 to 24 of check matrix H are rows of matrix C.

[0266] Therefore, of the rows with row numbers 2, 6, and 18 (hereinafter referred to as rows #2, #6, #18, etc.), rows #2 and #6 are rows of the A matrix, and row #18 is a row of the C matrix.

[0267] The second row of the parity check matrix initial value table in FIG. 23 is 2, 10, 19, which indicates that the elements of rows #2, #10, and #19 in the 6th (=1+5×(2−1)) column of parity check matrix H are 1.

[0268] Here, in the 6th (=1+5×(2−1)) column of parity check matrix H, of rows #2, #10, and #19, rows #2 and #10 are rows of the A matrix, and row #19 is a row of the C matrix.

[0269] The third row of the parity check matrix initial value table in FIG. 23 is 22, which indicates that the element of row #22 in the 11th (=1+5×(3−1)) column of parity check matrix H is 1.

[0270] Here, in the 11th (=1+5×(3−1)) column of parity check matrix H, row #22 is a row of the C matrix.

[0271] Similarly, the 19 in the 4th row of the parity check matrix initial value table of FIG. 23 indicates that the element of row #19 in the 16th (=1+5×(4-1)) column of parity check matrix H is 1, and the 15 in the 5th row of the parity check matrix initial value table of FIG. 23 indicates that the element of row #15 in the 21st (=1+5×(5-1)) column of parity check matrix H is 1.

[0272] As described above, the parity check matrix initial value table indicates the positions of elements of 1 in the A matrix and C matrix of the parity check matrix H for each unit size P=5 columns.

[0273] Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the check matrix H, i.e., each column from the 2+5×(i-1)th column to the 5×ith column, are arranged by periodically cyclically shifting elements of 1 in the 1+5×(i-1)th column determined by the check matrix initial value table downward (downward in the column direction) according to parameters Q1 and Q2.

[0274] That is, for example, the 2+5×(i-1)th column of matrix A is the 1+5×(i-1)th column cyclically shifted downward by Q1 (=3), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q1 (=2×3) (the 2+5×(i-1)th column cyclically shifted downward by Q1).

[0275] For example, the 2+5×(i-1)th column of matrix C is the 1+5×(i-1)th column cyclically shifted downward by Q2 (=2), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q2 (=2×2) (the 2+5×(i-1)th column cyclically shifted downward by Q2).

[0276] FIG. 24 is a diagram showing matrix A generated from the check matrix initial value table of FIG.

[0277] In matrix A in FIG. 24, elements of rows #2 and #6 in the 1st (=1+5×(1−1)) column are 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0278] Each of the columns from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) is a cyclic shift of the previous column downward by Q1=3.

[0279] Furthermore, in matrix A in FIG. 24, elements in rows #2 and #10 of the 6th (=1+5×(2−1)) column are 1, in accordance with the second row of the parity check matrix initial value table in FIG.

[0280] Each column from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column is a cyclic shift of the previous column downward by Q1=3.

[0281] FIG. 25 is a diagram showing parity interleaving of a B matrix.

[0282] The check matrix generating unit 613 (FIG. 18) uses a check matrix initial value table to generate matrix A, and places matrix B of a staircase structure to the immediate right of matrix A. Then, the check matrix generating unit 613 regards matrix B as a parity matrix, and performs parity interleaving so that adjacent elements of 1 in matrix B of the staircase structure are spaced apart by unit size P=5 in the row direction.

[0283] FIG. 25 shows the A and B matrices after parity interleaving of the B matrix of FIG.

[0284] FIG. 26 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG.

[0285] 26, the element in row #18 of the 1st (=1+5×(1−1))th column of parity check matrix H is 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0286] Each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) columns of matrix C is a cyclic shift of the previous column downward by Q2=2.

[0287] Furthermore, in matrix C of FIG. 26, in accordance with the second to fifth rows of the parity check matrix initial value table of FIG. 23, the elements of row #19, the 6th (=1+5×(2-1)) column, row #22, the 11th (=1+5×(3-1)) column, row #19, the 16th (=1+5×(4-1)) column, and row #15, the 21st (=1+5×(5-1)) column of parity check matrix H are 1.

[0288] Furthermore, each of the columns from the 7th (=2+5×(2-1)) to the 10th (=5+5×(2-1)), each of the columns from the 12th (=2+5×(3-1)) to the 15th (=5+5×(3-1)), each of the columns from the 17th (=2+5×(4-1)) to the 20th (=5+5×(4-1)), and each of the columns from the 22nd (=2+5×(5-1)) to the 25th (=5+5×(5-1)) are cyclically shifted downward by Q2=2 from the previous column.

[0289] The check matrix generation unit 613 (FIG. 18) generates matrix C using the check matrix initial value table, and places matrix C below matrix A and matrix B (after parity interleaving).

[0290] Furthermore, parity check matrix generation section 613 places matrix Z to the right of matrix B, and matrix D to the right of matrix C, thereby generating parity check matrix H shown in FIG.

[0291] FIG. 27 is a diagram showing parity interleaving of a D matrix.

[0292] After generating the parity check matrix H of FIG. 26, the parity check matrix generation unit 613 regards the D matrix as a parity matrix and performs parity interleaving (of only the D matrix) so that elements of 1 in an odd row and the next even row of the unit matrix D matrix are separated in the row direction by unit size P=5.

[0293] FIG. 27 shows the parity check matrix H after performing parity interleaving of the D matrix on the parity check matrix H in FIG.

[0294] The LDPC encoder 115 (the encoding parity calculation unit 615 (FIG. 18)) performs LDPC encoding (generation of an LDPC code) using, for example, the check matrix H in FIG.

[0295] Here, the LDPC code generated using the check matrix H of FIG. 27 is an LDPC code that has been parity interleaved. Therefore, for the LDPC code generated using the check matrix H of FIG. 27, there is no need to perform parity interleaving in the parity interleaver 23 (FIG. 9).

[0296] FIG. 28 is a diagram showing a parity check matrix H in which column permutation is performed on the B matrix, part of the C matrix (the part of the C matrix that is placed under the B matrix), and the D matrix of the parity check matrix H in FIG. 27 as parity deinterleaving that restores the parity interleaving.

[0297] The LDPC encoder 115 can perform LDPC encoding (generation of an LDPC code) using the parity check matrix H in FIG.

[0298] When LDPC coding is performed using the check matrix H in Fig. 28, an LDPC code that is not parity interleaved is obtained by the LDPC coding. Therefore, when LDPC coding is performed using the check matrix H in Fig. 28, parity interleaving is performed in the parity interleaver 23 (Fig. 9).

[0299] FIG. 29 is a diagram showing a converted parity check matrix H obtained by performing row permutation on the parity check matrix H in FIG.

[0300] As will be described later, the conversion check matrix is ​​a matrix expressed by a combination of a P×P unit matrix, a quasi-unit matrix in which one or more of the 1s in the unit matrix are changed to 0, a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, a sum matrix which is the sum of two or more of a unit matrix, a quasi-unit matrix, or a shift matrix, and a P×P 0 matrix.

[0301] By using the converted parity check matrix for decoding an LDPC code, it is possible to employ an architecture for simultaneously performing P check node operations and variable node operations in decoding the LDPC code, as will be described later.

[0302] <New LDPC code>

[0303] In data transmission using LDPC codes, one method for ensuring good communication quality is to use LDPC codes with good performance.

[0304] A new LDPC code with good performance (hereinafter, also referred to as a new LDPC code) will be described below.

[0305] As the new LDPC code, for example, a type A code or type B code can be adopted in which the unit size P is 360, which is the same as that of DVB-T.2, ATSC3.0, etc., and which corresponds to a check matrix H having a cyclic structure.

[0306] The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC encoding into a new LDPC code using a check matrix initial value table (a check matrix H obtained from) of a new LDPC code in which the code length N is longer than 64 k bits, for example, 69120 bits, and the coding rate r is, for example, 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0307] In this case, a check matrix initial value table for a new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

[0308] FIG. 30 is a diagram showing an example of a check matrix initial value table (for the Type A method) that represents a check matrix H of a Type A code (hereinafter also referred to as a Type A code where r=2 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 2 / 16.

[0309] 31 and 32 are diagrams showing examples of check matrix initial value tables representing a check matrix H of a type A code (hereinafter also referred to as a type A code where r=3 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 3 / 16.

[0310] FIG. 32 is a sequel to FIG.

[0311] FIG. 33 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=4 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16.

[0312] 34 and 35 are diagrams showing examples of check matrix initial value tables representing check matrix H of a type A code (hereinafter also referred to as type A code where r=5 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16.

[0313] FIG. 35 is a sequel to FIG.

[0314] 36 and 37 are diagrams showing examples of check matrix initial value tables representing check matrix H of a type A code (hereinafter also referred to as type A code where r=6 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 6 / 16.

[0315] FIG. 37 is a sequel to FIG.

[0316] 38 and 39 are diagrams showing examples of check matrix initial value tables representing check matrix H of a type A code (hereinafter also referred to as type A code where r=7 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16.

[0317] FIG. 39 is a sequel to FIG.

[0318] 40 and 41 are diagrams showing examples of check matrix initial value tables representing check matrix H of a type A code (hereinafter also referred to as type A code where r=8 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16.

[0319] FIG. 41 is a sequel to FIG.

[0320] 42 and 43 are diagrams showing examples of check matrix initial value tables (for the Type B method) representing check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=7 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16.

[0321] It should be noted that FIG. 43 is a sequel to FIG.

[0322] 44 and 45 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=7 / 16.

[0323] Fig. 45 is a diagram following Fig. 44. The type B code with r=7 / 16 obtained from (the check matrix H represented by) the check matrix initial value table in Fig. 44 and Fig. 45 is hereinafter also referred to as another type B code with r=7 / 16.

[0324] 46 and 47 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code where r=8 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16.

[0325] FIG. 47 is a sequel to FIG.

[0326] 48 and 49 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=8 / 16.

[0327] Note that Fig. 49 is a sequel to Fig. 48. The type B code with r=8 / 16 obtained from the parity check matrix initial value tables in Fig. 48 and Fig. 49 will hereinafter also be referred to as another type B code with r=8 / 16.

[0328] 50, 51, and 52 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code, where r=9 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 9 / 16.

[0329] Note that FIG. 51 is a continuation of FIG. 50, and FIG. 52 is a continuation of FIG. 51.

[0330] 53, 54, and 55 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=9 / 16.

[0331] FIG. 54 is a diagram continuing from FIG. 53, and FIG. 55 is a diagram continuing from FIG. 54. The type B code with r=9 / 16 obtained from the check matrix initial value tables of FIG. 53 to FIG. 55 will hereinafter also be referred to as other type B code with r=9 / 16.

[0332] 56, 57, and 58 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code where r=10 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 10 / 16.

[0333] Note that FIG. 57 is a continuation of FIG. 56, and FIG. 58 is a continuation of FIG. 57.

[0334] 59, 60, and 61 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=10 / 16.

[0335] Fig. 60 is a diagram continuing from Fig. 59, and Fig. 61 is a diagram continuing from Fig. 60. The type B code of r=10 / 16 obtained from the check matrix initial value tables of Figs. 59 to 61 is hereinafter also referred to as other type B code of r=10 / 16.

[0336] 62, 63, and 64 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=11 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 11 / 16.

[0337] Note that FIG. 63 is a continuation of FIG. 62, and FIG. 64 is a continuation of FIG. 63.

[0338] 65, 66, and 67 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=11 / 16.

[0339] Note that Fig. 66 is a diagram continuing from Fig. 65, and Fig. 67 is a diagram continuing from Fig. 66. The type B code of r=11 / 16 obtained from the check matrix initial value tables of Figs. 65 to 67 is also referred to as other type B code of r=11 / 16 hereinafter.

[0340] 68, 69, and 70 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=12 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 12 / 16.

[0341] Note that FIG. 69 is a continuation of FIG. 68, and FIG. 70 is a continuation of FIG.

[0342] 71, 72, and 73 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=12 / 16.

[0343] Note that Fig. 72 is a diagram continuing from Fig. 71, and Fig. 73 is a diagram continuing from Fig. 72. The type B code of r=12 / 16 obtained from the check matrix initial value tables of Figs. 71 to 73 is hereinafter also referred to as other type B code of r=12 / 16.

[0344] 74, 75, and 76 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=13 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 13 / 16.

[0345] Note that FIG. 75 is a continuation of FIG. 74, and FIG. 76 is a continuation of FIG.

[0346] 77, 78, and 79 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=13 / 16.

[0347] FIG78 is a diagram following FIG77, and FIG79 is a diagram following FIG78. The type B code of r=13 / 16 obtained from the check matrix initial value tables of FIG77 to FIG79 is hereinafter also referred to as other type B code of r=13 / 16.

[0348] 80, 81, and 82 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=14 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 14 / 16.

[0349] Note that FIG. 81 is a continuation of FIG. 80, and FIG. 82 is a continuation of FIG.

[0350] 83, 84, and 85 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=14 / 16.

[0351] FIG. 84 is a diagram continuing from FIG. 83, and FIG. 85 is a diagram continuing from FIG. 84. The type B code of r=14 / 16 obtained from the check matrix initial value tables of FIG. 83 to FIG. 85 is also hereinafter referred to as other type B code of r=14 / 16.

[0352] The new LDPC code is an LDPC code with good performance.

[0353] Here, an LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

[0354] An appropriate check matrix H is, for example, an LDPC code obtained from the check matrix H with low E s / N 0 , or E b / N o A check matrix satisfies certain conditions and reduces the bit error rate (BER) (and frame error rate (FER)) when transmitted at a signal power to noise power ratio (SPR) per bit.

[0355] For example, an appropriate check matrix H can be obtained by combining LDPC codes obtained from various check matrices that satisfy a certain condition with a low E s / N o This can be obtained by performing a simulation to measure the BER when transmitting at 100 Mbps.

[0356] The predetermined conditions that an appropriate check matrix H should satisfy include, for example, that the analysis results obtained by a code performance analysis method called Density Evolution are good, that there is no loop of elements of 1, called cycle 4, and so on.

[0357] Here, the information matrix H A It is known that if elements of 1 are concentrated, such as in cycle 4, the decoding performance of the LDPC code deteriorates. For this reason, it is desirable that cycle 4 does not exist in the parity check matrix H.

[0358] In the parity check matrix H, the minimum length of a loop formed by elements of 1 is called a girth. The absence of a cycle of 4 means that the girth is greater than 4.

[0359] The predetermined conditions that an appropriate check matrix H should satisfy can be appropriately determined from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and so on.

[0360] 86 and 87 are diagrams for explaining density evolution that obtains analysis results as predetermined conditions that an appropriate parity check matrix H should satisfy.

[0361] Density evolution is a code analysis method that calculates the expected error probability for an ensemble of LDPC codes with a code length N of ∞, characterized by a degree sequence (described later).

[0362] For example, in an AWGN channel, if the noise variance is increased from 0, the expected error probability of a certain ensemble is initially 0, but once the noise variance exceeds a certain threshold, it is no longer 0.

[0363] According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the noise variance threshold (hereinafter referred to as the performance threshold) at which the expected value of the error probability is no longer zero.

[0364] It should be noted that, for a specific LDPC code, if the ensemble to which that LDPC code belongs is determined and density evolution is performed on that ensemble, the rough performance of that LDPC code can be predicted.

[0365] Therefore, if an ensemble with good performance is found, a good LDPC code can be found from among the LDPC codes that belong to that ensemble.

[0366] Here, the above-mentioned degree sequence indicates the proportion of variable nodes and check nodes having each weight value with respect to the code length N of the LDPC code.

[0367] For example, a regular (3,6) LDPC code with a coding rate of 1 / 2 belongs to an ensemble characterized by a degree sequence in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6.

[0368] Figure 86 shows the Tanner graph of such an ensemble.

[0369] In the Tanner Bluff of Figure 86, there are N variable nodes, indicated by circles (○) in the figure, which is equal to the code length N, and there are N / 2 check nodes, indicated by squares (□) in the figure, which is equal to the code length N multiplied by the coding rate 1 / 2.

[0370] Each variable node has three edges connected to it, equal to the column weight, so there are a total of 3N edges connecting the N variable nodes.

[0371] Also, each check node has 6 edges connected to it, equal to the row weight. Therefore, there are a total of 3N edges connecting to the N / 2 check nodes.

[0372] Furthermore, in the Tanner graph of Figure 86, there is one interleaver.

[0373] The interleaver randomly rearranges the 3N branches connected to the N variable nodes, and then connects each rearranged branch to one of the 3N branches connected to the N / 2 check nodes.

[0374] There are only (3N)! (=(3N)×(3N-1)×···×1) possible permutations of the 3N branches connected to N variable nodes in the interleaver. Therefore, an ensemble characterized by a degree sequence in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

[0375] In a simulation to find a high-performance LDPC code (appropriate check matrix), a multi-edge type ensemble was used in density evolution.

[0376] In the multi-edge type, the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes pass is divided into multiple (multi-edge), which allows for more precise characterization of the ensemble.

[0377] Figure 87 shows an example of a Tanner graph for a multi-edge type ensemble.

[0378] In the Tanner graph of FIG. 87, there are two interleavers: a first interleaver and a second interleaver.

[0379] In addition, in the Tanner graph of Figure 87, there is only v1 variable node with one edge connecting to the first interleaver and zero edges connecting to the second interleaver, there is only v2 variable node with one edge connecting to the first interleaver and two edges connecting to the second interleaver, and there is only v3 variable node with zero edges connecting to the first interleaver and two edges connecting to the second interleaver.

[0380] Furthermore, in the Tanner graph of Figure 87, there are only c1 check nodes with two edges connecting to the first interleaver and zero edges connecting to the second interleaver, there are only c2 check nodes with two edges connecting to the first interleaver and two edges connecting to the second interleaver, and there are only c3 check nodes with zero edges connecting to the first interleaver and three edges connecting to the second interleaver.

[0381] Here, density evolution and its implementation are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SY Chung, GD Forney, TJ Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2, Feb. 2001.

[0382] In a simulation to find a new LDPC code (check matrix), the BER starts to drop (become smaller) due to the multi-edge type density evolution. b / N 0 We found an ensemble for which the performance threshold, which is the signal power to noise power ratio per bit, is below a specified value, and from among the LDPC codes belonging to that ensemble, we selected the LDPC code that reduces the BER when using one or more orthogonal modulations such as QPSK as the LDPC code with good performance.

[0383] The new LDPC code (the check matrix initial value table representing the check matrix of the new LDPC code) was obtained by the above simulation.

[0384] Therefore, the new LDPC code can ensure good communication quality in data transmission.

[0385] FIG. 88 is a diagram for explaining column weights of a check matrix H of a type-A code as a new LDPC code.

[0386] As for the check matrix H of a type-A code, as shown in FIG. 88, the column weight of the first K1 columns of the A matrix is ​​represented as Y1, the column weight of the subsequent K2 columns of the A matrix is ​​represented as Y2, the column weight of the first K1 columns of the C matrix is ​​represented as X1, the column weight of the subsequent K2 columns of the C matrix is ​​represented as X2, and the column weight of the further subsequent M1 columns of the C matrix is ​​represented as X3.

[0387] Note that K1+K2 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+M1+M2 is equal to the code length N=69120 bits.

[0388] As for the check matrix H of the type A code, the column weight of the 1st column to the M1-1th column of the B matrix is ​​2, and the column weight of the M1th column (the last column) of the B matrix is ​​1. Furthermore, the column weight of the D matrix is ​​1, and the column weight of the Z matrix is ​​0.

[0389] FIG. 89 is a diagram showing parameters of the check matrix H of the type-A code (represented by the check matrix initial value tables) of FIGS.

[0390] X1, Y1, K1, X2, Y2, K2, X3, M1, M2 as parameters of check matrix H of type A code for r=2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, and performance thresholds are as shown in FIG. 89.

[0391] The parameters X1, Y1, K1 (or K2), X2, Y2, X3, and M1 (or M2) are set so as to further improve the performance (for example, error rate, etc.) of the LDPC code.

[0392] FIG. 90 is a diagram for explaining column weights of a check matrix H of a Type B code as a new LDPC code.

[0393] As for the check matrix H of a Type B code, as shown in FIG. 90, the column weight of the first to KX1 columns is represented as X1, the column weight of the subsequent KX2 columns is represented as X2, the column weight of the subsequent KY1 columns is represented as Y1, and the column weight of the subsequent KY2 columns is represented as Y2.

[0394] Note that KX1+KX2+KY1+KY2 is equal to the information length K, and KX1+KX2+KY1+KY2+M is equal to the code length N=69120 bits.

[0395] Furthermore, in the parity check matrix H of the type B code, of the last M columns, the column weight of M−1 columns excluding the last column is 2, and the column weight of the last column is 1.

[0396] FIG. 91 is a diagram showing parameters of the check matrix H of the type B code (represented by the check matrix initial value tables) of FIGS.

[0397] The parameters X1, KX1, X2, KX2, Y1, KY1, Y2, KY2, M and performance thresholds of the check matrix H of the type B codes for r=7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 and other type B codes are as shown in Figure 91.

[0398] The parameters X1, KX1, X2, KX2, Y1, KY1, Y2, and KY2 are set so as to further improve the performance of the LDPC code.

[0399] <Simulation results>

[0400] 92 and 93 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=2 / 16 by QPSK.

[0401] In the simulation, an AWGN channel was used as the communication path 13 (FIG. 7), and 50 times was used as the number of iterative decoding iterations C(it) of the LDPC code.

[0402] Capacity (communication channel capacity) represents the amount of information that can be transmitted with one symbol. In the simulation, -6 When a BER of s / N 0 The capacity was calculated in terms of the signal power to noise power ratio per symbol.

[0403] In the BER / FER curve diagram, the solid line represents the BER and the dotted line represents the FER. In the capacity diagram, the Shannon limit is shown along with the capacity for the LDPC code. The same is true for the following simulation result diagrams.

[0404] 94 and 95 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=3 / 16 by QPSK.

[0405] 96 and 97 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=4 / 16 by QPSK.

[0406] 98 and 99 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=5 / 16 using QPSK.

[0407] 100 and 101 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which a Type A code with r=6 / 16 is transmitted by QPSK.

[0408] 102 and 103 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=7 / 16 using QPSK.

[0409] 104 and 105 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type A code with r=8 / 16 using QPSK.

[0410] 106 and 107 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type B code with r=7 / 16 using QPSK.

[0411] 108 and 109 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting another type B code with r=7 / 16 using QPSK.

[0412] 110 and 111 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which a Type B code with r=8 / 16 is transmitted by QPSK.

[0413] 112 and 113 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=8 / 16 is transmitted by QPSK.

[0414] 114 and 115 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which a Type B code with r=9 / 16 is transmitted by QPSK.

[0415] 116 and 117 are diagrams respectively showing the BER / FER curve and capacity as the simulation results of transmitting another type B code with r=9 / 16 using QPSK.

[0416] 118 and 119 are diagrams respectively showing a BER / FER curve and capacity as the simulation results of transmitting a Type B code with r=10 / 16 using QPSK.

[0417] 120 and 121 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=10 / 16 is transmitted by QPSK.

[0418] 122 and 123 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type B code with r=11 / 16 using QPSK.

[0419] 124 and 125 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=11 / 16 is transmitted by QPSK.

[0420] 126 and 127 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which a Type B code with r=12 / 16 is transmitted by QPSK.

[0421] 128 and 129 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=12 / 16 is transmitted by QPSK.

[0422] 130 and 131 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type B code with r=13 / 16 using QPSK.

[0423] 132 and 133 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=13 / 16 is transmitted by QPSK.

[0424] 134 and 135 are diagrams showing the BER / FER curve and capacity, respectively, as the simulation results of transmitting a Type B code with r=14 / 16 using QPSK.

[0425] 136 and 137 are diagrams respectively showing a BER / FER curve and a capacity as a result of a simulation in which another type B code with r=14 / 16 is transmitted by QPSK.

[0426] According to the simulation results of FIGS. 92 to 137, it can be confirmed that the new LDPC code realizes a good BER / FER and also realizes a capacity close to the Shannon limit.

[0427] <Constellation>

[0428] 138 to 141 are diagrams showing examples of constellations employed in the transmission system of FIG.

[0429] In the transmission system of FIG. 7, for example, for MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), a constellation to be used in that MODCOD can be set.

[0430] For a MODCOD of 1, one or more constellations can be set.

[0431] Constellations include UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the signal points are not arranged uniformly.

[0432] In addition, there are many types of NUCs, such as 1D NUCs (1-dimensional M 2There are constellations called 2D NUC (2-dimensional QQAM non-uniform constellation), and 2D NUC (2-dimensional QQAM non-uniform constellation).

[0433] In general, 1D NUC improves the BER more than UC, and 2D NUC improves the BER more than 1D NUC.

[0434] The constellation for the modulation method QPSK is UC. For example, 2D NUC can be used as a constellation for modulation methods such as 16QAM, 64QAM, and 256QAM, and for example, 1D NUC can be used as a constellation for modulation methods such as 1024QAM and 4096QAM.

[0435] In the transmission system of FIG. 7, for example, constellations defined in ATSC3.0 or the like can be used.

[0436] That is, when the modulation scheme is QPSK, for example, the same constellation can be used for each coding rate r of the LDPC code.

[0437] Furthermore, when the modulation scheme is 16QAM, 64QAM, or 256QAM, for example, it is possible to use different 2D NUC constellations for each coding rate r of the LDPC code.

[0438] Furthermore, when the modulation method is 1024QAM or 4096QAM, for example, a different 1D NUC constellation can be used for each coding rate r of the LDPC code.

[0439] Below, we will explain some of the constellations specified in ATSC3.0.

[0440] FIG. 138 is a diagram showing the coordinates of signal points of a UC constellation used for all coding rates of LDPC codes defined in ATSC3.0 when the modulation scheme is QPSK.

[0441] In Figure 138, "Input Data cell y" represents a 2-bit symbol to be mapped to UC of QPSK, and "Constellation point z s " is the signal point z s The coordinates of the signal point z s The index s in represents the discrete time of the symbols (the time interval between one symbol and the next).

[0442] In Figure 138, signal point z s The coordinates of are expressed in the form of complex numbers, with j representing the imaginary unit (√(-1)).

[0443] FIG. 139 is a diagram showing the coordinates of signal points of the 2D NUC constellation used for the coding rates r(CR)=2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, and 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 16QAM.

[0444] In FIG. 139, like FIG. 138, signal point z s The coordinates of are expressed in the form of complex numbers, with j representing the imaginary unit.

[0445] In FIG. 139, w#k represents the coordinates of a signal point in the first quadrant of the constellation.

[0446] In 2D NUC, the signal points in the second quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the Q axis, the signal points in the third quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the origin, and the signal points in the fourth quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the I axis.

[0447] Here, the modulation method is 2 m In the case of QAM, m bits are treated as one symbol, and each symbol is mapped to a signal point corresponding to that symbol.

[0448] An m-bit symbol can be, for example, 0 to 2 m It can be expressed as an integer value of -1, but now, b=2 m / 4 means 0 to 2 m The symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) through y(b-1), y(b) through y(2b-1), y(2b) through y(3b-1), and y(3b) through y(4b-1).

[0449] In FIG. 139, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of a signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

[0450] The coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0451] Here, conj(w#k) represents the complex conjugate of w#k.

[0452] For example, when the modulation method is 16QAM, the m=4-bit symbols y(0), y(1), . . . , y(15) are 4 / 4=4, it is classified into four symbols: y(0) through y(3), y(4) through y(7), y(8) through y(11), and y(12) through y(15).

[0453] Among the symbols y(0) to y(15), for example, the symbol y(12) is a symbol y(k+3b)=y(0+3×4) in the range of symbols y(3b) to y(4b-1), where k=0, and therefore the coordinates of the signal point corresponding to the symbol y(12) are -w#k=-w0.

[0454] Now, if the coding rate r(CR) of the LDPC code is, for example, 9 / 15, according to FIG. 139, when the modulation method is 16QAM and the coding rate r is 9 / 15, w0 is 0.2386+j0.5296, so the coordinate −w0 of the signal point corresponding to the symbol y(12) is −(0.2386+j0.5296).

[0455] Figure 140 is a diagram showing an example of the coordinates of 1D NUC signal points used for the coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM.

[0456] In FIG. 140, u#k is the signal point z of the 1D NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s )

[0457] Figure 141 shows the 1024QAM symbol y and the 1D NUC signal point z corresponding to that symbol y. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) as well as u#k.

[0458] Now, let us consider the 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s Let us express it as follows.

[0459] A in Figure 141 represents the even-numbered 5 bits of symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to the symbol y s The real part of the coordinate system Re(z s ) represents the correspondence with u#k.

[0460] B in Figure 141 shows the odd-numbered 5 bits of the symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to the symbol y s Imaginary Part Im(z s ) represents the correspondence with u#k.

[0461] 1024QAM 10-bit symbol y=(y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ) is, for example, (0,0,1,0,0,1,1,1,0,0), then the odd-numbered 5 bits (y 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s ) is (0,1,0,1,0), and the even-numbered 5 bits (y 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ) is (0,0,1,1,0).

[0462] In FIG. 141A, the even-numbered 5 bits (0,0,1,1,0) are associated with u11, and therefore the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11.

[0463] In FIG. 141B, the odd-numbered 5 bits (0,1,0,1,0) are associated with u3, and therefore the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s Imaginary Part Im(z s ) becomes u3.

[0464] On the other hand, if the coding rate r of the LDPC code is, for example, 6 / 15, according to the above-mentioned FIG. 140, for a 1D NUC used when the modulation method is 1024QAM and the coding rate of the LDPC code r(CR)=6 / 15, u3 is 0.1295 and u11 is 0.7196.

[0465] Therefore, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11=0.7196, and the imaginary part Im(z s ) results in u3 = 0.1295. As a result, the signal point z corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) s The coordinates of are expressed as 0.7196+j0.1295.

[0466] In the constellation, the signal points of a 1D NUC are arranged in a grid pattern on lines parallel to the I axis or the Q axis. However, the intervals between signal points are not constant. In addition, when transmitting a signal point (the data mapped to the signal point), the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates of the signal points) on the constellation as P aveThen, the mean square P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z s This can be done by multiplying

[0467] In the transmission system of FIG. 7, the constellations and the like defined in ATSC3.0 as described above can be used.

[0468] <Block Interleaver 25>

[0469] FIG. 142 is a block diagram showing an example of the configuration of the block interleaver 25 of FIG.

[0470] The block interleaver 25 has a storage area called part 1 and a storage area called part 2.

[0471] Both parts 1 and 2 are composed of columns, which are memory areas that store one bit in the row (horizontal) direction and a predetermined number of bits in the column (vertical) direction, lined up in the row direction, a number C of columns equal to the number of bits m of the symbol.

[0472] If the number of bits stored in the column direction of the column of part 1 (hereinafter also referred to as the part column length) is represented as R1, and the part column length of the column of part 2 is represented as R2, then (R1+R2)×C is equal to the code length N of the LDPC code to be block interleaved.

[0473] In addition, the part column length R1 is equal to a multiple of the unit size P, which is 360 bits, and the part column length R2 is equal to the remainder when the sum of the part column length R1 of part 1 and the part column length R2 of part 2 (hereinafter also referred to as the column length) R1+R2 is divided by the unit size P, which is 360 bits.

[0474] Here, the column length R1+R2 is equal to the value obtained by dividing the code length N of the LDPC code to be block interleaved by the number of bits m of a symbol.

[0475] For example, when 16QAM is adopted as the modulation scheme for an LDPC code with a code length N of 69120 bits, the number of bits m of a symbol is 4 bits, so that the column length R1+R2 is 17280 (=69120 / 4) bits.

[0476] Furthermore, the remainder when the column length R1+R2=17280 is divided by the unit size P of 360 bits is 0, so the part column length R2 of part 2 is 0 bits.

[0477] The part column length R1 of part 1 is R1+R2-R2=17280-0=17280 bits.

[0478] FIG. 143 is a diagram for explaining the block interleaving performed in the block interleaver 25 of FIG.

[0479] The block interleaver 25 performs block interleaving on parts 1 and 2 by writing and reading LDPC codes.

[0480] That is, in block interleaving, as shown in A of FIG. 143, code bits of an LDPC code of one codeword are written from the top of the column of part 1 downward (column direction) toward the column from left to right.

[0481] Then, when the writing of the code bits is completed down to the bottom of the rightmost column (Cth column) of part 1, the remaining code bits are written from top to bottom (column direction) of the columns of part 2, proceeding from left to right columns.

[0482] After that, when the writing of the code bits is completed down to the bottom of the rightmost column (Cth column) of part 2, the code bits are read out in the row direction from the first row of all C columns of part 1 in units of C=m bits, as shown in B of Figure 143.

[0483] Then, the code bits are read out from all C columns of part 1 in sequence, moving down the rows. When reading is completed up to the last row, row R1, the code bits are read out from the first row of all C columns of part 2 in the row direction, in units of C=m bits.

[0484] The reading of the code bits from all C columns of part 2 is done row by row, down to the last row, row R2.

[0485] In this manner, the code bits read out in m-bit units from parts 1 and 2 are supplied as symbols to the mapper 117 (FIG. 8).

[0486] <Group-wise interleaving>

[0487] FIG. 144 is a diagram for explaining group-wise interleaving performed in group-wise interleaver 24 of FIG.

[0488] In group-wise interleaving, the LDPC code of one codeword is divided into 360-bit units, which is equal to the unit size P, from the beginning of the codeword. The 360 ​​bits of each division are treated as bit groups, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as a GW pattern).

[0489] Here, when an LDPC code of one codeword is divided into bit groups, the (i+1)th bit group from the beginning will hereinafter also be referred to as bit group i.

[0490] When the unit size P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800 / 360) bit groups of bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code with a code length N of 16200 bits is divided into 45 (=16200 / 360) bit groups of bit groups 0, 1, . . . , 44, and an LDPC code with a code length N of 64800 bits is divided into 180 (=64800 / 360) bit groups of bit groups 0, 1, . . . , 179. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120 / 360) bit groups of bit groups 0, 1, . . . , 191.

[0491] Here, the GW pattern is represented by a sequence of numbers representing bit groups. For example, for an LDPC code with a code length N of 1800 bits, the GW pattern 4,2,0,3,1 represents interleaving (rearranging) the sequence of bit groups 0,1,2,3,4 into the sequence of bit groups 4,2,0,3,1.

[0492] The GW pattern can be set at least for each code length N of the LDPC code.

[0493] For example, as a GW pattern for an LDPC code with a code length N of 64800 bits, the sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is 39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167 ,35,127,156,55,82,85,66,114,8,147,115,113,5,31,100,106,48,52,67,107,18,126,112,50,9,143,28,160,71,79,43,98,86,94,64,3,166,105,103,118,63,51,139,172,141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99 ,22,123,72,177,131,116,44,158,73,11,65,164,119,174,34,83,53,24,42,60,26,161,68,178,41,148,109,87,144,135,20,62,81,169,124,6,19,30,163,61,179,136,97,16,88 There are also patterns in which the above are interleaved.

[0494] <Configuration example of receiving device 12>

[0495] FIG. 145 is a block diagram showing an example of the configuration of the receiving device 12 of FIG.

[0496] The OFDM operation unit 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data obtained by the signal processing by the OFDM operation unit 151 is supplied to a frame management unit 152.

[0497] The frame management unit 152 processes (frame interprets) frames composed of data supplied from the OFDM processing unit 151, and supplies the resulting target data signal and control data signal to frequency deinterleavers 161 and 153, respectively.

[0498] The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a demapper 154 .

[0499] The demapper 154 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the frequency deinterleaver 153 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data (LDPC code (likelihood)) to an LDPC decoder 155.

[0500] The LDPC decoder 155 performs LDPC decoding on the LDPC code from the demapper 154, and supplies the resulting LDPC target data (here, a BCH code) to a BCH decoder 156.

[0501] The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs the resulting control data (signaling).

[0502] On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a SISO / MISO decoder 162 .

[0503] The SISO / MISO decoder 162 performs space-time decoding on the data from the frequency deinterleaver 161 and supplies the decoded data to a time deinterleaver 163 .

[0504] The time deinterleaver 163 performs time deinterleaving on the data from the SISO / MISO decoder 162 on a symbol-by-symbol basis, and supplies the result to a demapper 164 .

[0505] The demapper 164 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data to a bit deinterleaver 165.

[0506] The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164, and supplies the LDPC code (the likelihood of the LDPC code), which is the bit deinterleaved data, to the LDPC decoder 166.

[0507] The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165, and supplies the resulting LDPC target data (here, a BCH code) to a BCH decoder 167.

[0508] The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155 , and supplies the resulting data to a BB descrambler 168 .

[0509] The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to a null deletion unit (Null Deletion) 169 .

[0510] The null deletion unit 169 deletes the nulls inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the data to a demultiplexer 170.

[0511] The demultiplexer 170 separates one or more streams (target data) multiplexed into the data from the null deletion unit 169, performs necessary processing on the separated data, and outputs the separated data as an output stream.

[0512] The receiving device 12 can be configured without some of the blocks shown in Fig. 145. That is, for example, when the transmitting device 11 (Fig. 8) is configured without the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without the time deinterleaver 163, the SISO / MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are blocks corresponding to the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

[0513] <Example of the configuration of the bit deinterleaver 165>

[0514] FIG. 146 is a block diagram showing an example of the configuration of the bit deinterleaver 165 of FIG. 145.

[0515] The bit deinterleaver 165 is made up of a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols that are the data from the demapper 164 (FIG. 145).

[0516] That is, the block deinterleaver 54 performs block deinterleaving (the inverse process of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 in FIG. 9 on the symbol bits of the symbols from the demapper 164, that is, block deinterleaving that returns the positions of the code bits (of the likelihoods) of the LDPC code rearranged by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0517] The group-wise deinterleaver 55 performs group-wise deinterleaving (the inverse process of group-wise interleaving) on ​​the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9. In other words, the group-wise deinterleaver 55 performs group-wise deinterleaving to return the code bits of the LDPC code, whose order has been changed on a bit group basis by the group-wise interleaving described in FIG. 144, to their original order by rearranging them on a bit group basis.

[0518] Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, group-wise interleaving, and block interleaving, the bit deinterleaver 165 can perform all of the following: parity deinterleaving corresponding to parity interleaving (the inverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and group-wise deinterleaving corresponding to group-wise interleaving.

[0519] However, in bit deinterleaver 165 of FIG. 146, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving, and a group-wise deinterleaver 55 that performs group-wise deinterleaving corresponding to group-wise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

[0520] Therefore, the LDPC decoder 166 is supplied with an LDPC code that has been subjected to block deinterleaving and group-wise deinterleaving but not parity deinterleaving from the bit deinterleaver 165 (the group-wise deinterleaver 55 thereof).

[0521] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the type B parity check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. 8, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the type A parity check matrix (FIG. 27), and outputs the data obtained as a result of the decoding of the LDPC target data.

[0522] FIG. 147 is a flowchart explaining the processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 in FIG.

[0523] In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to signal points), and supplies the data to the bit deinterleaver 165, and the process proceeds to step S112.

[0524] In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleaves) the data from the demapper 164, and the process proceeds to step S113.

[0525] That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

[0526] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the LDPC code (the likelihood of the LDPC code) obtained as a result to the LDPC decoder 166.

[0527] In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG. 8, that is, using, for example, a converted check matrix obtained from the check matrix H, and outputs the data obtained as a result to the BCH decoder 167 as the decoded result of the LDPC target data.

[0528] In addition, in FIG. 146, as in the case of FIG. 9, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately, but the block deinterleaver 54 and the group-wise deinterleaver 55 can be configured as an integrated unit.

[0529] Furthermore, in the case where group-wise interleaving is not performed in transmitting device 11, receiving device 12 can be configured without providing group-wise deinterleaver 55 that performs group-wise deinterleaving.

[0530] <LDPC Decoding>

[0531] The LDPC decoding performed by the LDPC decoder 166 in FIG. 145 will be further described.

[0532] In the LDPC decoder 166 of FIG. 145, as described above, LDPC decoding of an LDPC code in which block deinterleaving and group-wise deinterleaving are performed from the group-wise deinterleaver 55 and parity deinterleaving is not performed is performed using a transformed check matrix obtained by performing at least column replacement corresponding to parity deinterleaving on a type B check matrix H of the type used by the LDPC encoder 115 in FIG. 8 for LDPC encoding, or a transformed check matrix (FIG. 29) obtained by performing row replacement on a type A check matrix (FIG. 27).

[0533] Here, LDPC decoding using a transformed check matrix has been previously proposed (see, for example, Japanese Patent No. 4224777), which makes it possible to suppress the circuit scale and keep the operating frequency within a sufficiently achievable range while performing LDPC decoding.

[0534] Therefore, first, with reference to FIGS. 148 to 151, the previously proposed LDPC decoding using a transformed check matrix will be described.

[0535] FIG. 148 is a diagram showing an example of a check matrix H of an LDPC code with a code length N of 90 and a coding rate of 2 / 3.

[0536] In FIG. 148 (similarly in FIGS. 149 and 150 described later), 0 is represented by a period (.).

[0537] In the check matrix H of FIG. 148, the parity matrix has a staircase structure.

[0538] FIG. 149 is a diagram showing a check matrix H' obtained by performing row replacement of Equation (11) and column replacement of Equation (12) on the check matrix H of FIG. 148.

[0539] Line replacement: 6s+t+1st line → 5t+s+1st line (11)

[0540] Column replacement: 6x+y+61st column → 5y+x+61st column (12)

[0541] In formulas (11) and (12), s, t, x, and y are integers in the ranges of 0≦s<5, 0≦t<6, 0≦x<5, and 0≦t<6, respectively.

[0542] According to the row permutation of equation (11), lines 1, 7, 13, 19, and 25, which have a remainder of 1 when divided by 6, are permuted into lines 1, 2, 3, 4, and 5, respectively; lines 2, 8, 14, 20, and 26, which have a remainder of 2 when divided by 6, are permuted into lines 6, 7, 8, 9, and 10, respectively.

[0543] Furthermore, according to the column permutation in equation (12), for columns 61 and onwards (parity matrix), columns 61, 67, 73, 79, and 85, which have a remainder of 1 when divided by 6, are permuted into columns 61, 62, 63, 64, and 65, respectively, and columns 62, 68, 74, 80, and 86, which have a remainder of 2 when divided by 6, are permuted into columns 66, 67, 68, 69, and 70, respectively.

[0544] In this manner, the matrix obtained by permuting rows and columns on the parity check matrix H in FIG. 148 is the parity check matrix H' in FIG.

[0545] Here, even if row permutation is performed on the check matrix H, the arrangement of the code bits of the LDPC code is not affected.

[0546] In addition, the column permutation in equation (12) corresponds to the above-mentioned parity interleaving in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position, where the information length K is 60, the unit size P is 5, and the divisor q (=M / P) of the parity length M (here, 30) is 6.

[0547] Therefore, the check matrix H' in Figure 149 is a transformed check matrix obtained by at least performing column permutation to replace the K+qx+y+1th column of the check matrix H in Figure 148 (hereinafter referred to as the original check matrix, as appropriate) with the K+Py+x+1th column.

[0548] For the converted parity check matrix H' in FIG. 149, when the LDPC code of the original parity check matrix H in FIG. 148 is multiplied by the same permutation as in equation (12), a zero vector is output. In other words, if the row vector c obtained by performing the column permutation in equation (12) on the row vector c as the LDPC code (one codeword) of the original parity check matrix H is expressed as c', then, according to the nature of the parity check matrix, Hc T is a 0 vector, so H'c' T Naturally, this is also a zero vector.

[0549] From the above, the converted parity check matrix H' in FIG. 149 is a parity check matrix of an LDPC code c' obtained by performing column permutation of equation (12) on the LDPC code c of the original parity check matrix H.

[0550] Therefore, by performing column permutation of equation (12) on the LDPC code c of the original check matrix H, and then decoding (LDPC decoding) the LDPC code c' after column permutation using the converted check matrix H' in FIG. 149, and then performing the inverse permutation of the column permutation of equation (12) on the decoded result, it is possible to obtain the same decoding result as when the LDPC code of the original check matrix H is decoded using that check matrix H.

[0551] FIG. 150 is a diagram showing the converted parity check matrix H' in FIG. 149, in which intervals are provided in units of a 5×5 matrix.

[0552] In FIG. 150, the conversion check matrix H' is represented as a combination of a 5×5 (=P×P) unit matrix, where P is the unit size, a matrix in which one or more of the 1s in the unit matrix have become 0 (hereinafter referred to as a quasi-unit matrix, as appropriate), a matrix obtained by cyclic shifting a unit matrix or a quasi-unit matrix (hereinafter referred to as a shift matrix, as appropriate), a sum of two or more unit matrices, quasi-unit matrices, or shift matrices (hereinafter referred to as a sum matrix, as appropriate), and a 5×5 0 matrix.

[0553] It can be said that the conversion check matrix H' in Fig. 150 is composed of a 5x5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5x5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, and 0 matrix) constituting the conversion check matrix H' are hereinafter referred to as constituent matrices as appropriate.

[0554] To decode an LDPC code of a parity check matrix represented by a P×P configuration matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

[0555] FIG. 151 is a block diagram showing an example of the configuration of a decoding device that performs such decoding.

[0556] That is, FIG. 151 shows an example of the configuration of a decoding device that decodes an LDPC code using a transformed check matrix H′ in FIG. 150 obtained by performing at least the column permutation of equation (12) on the original check matrix H in FIG. 148.

[0557] The decoder of FIG. 151 has six FIFOs 300. 1 or 300 6 The edge data storage memory 300, FIFO 300 1 or 300 6 A selector 301 for selecting a check node, a check node calculation unit 302, two cyclic shift circuits 303 and 308, and 18 FIFOs 304 1 or 304 18 The edge data storage memory 304, the FIFO 304 1 or 304 18 a receive data memory 306 for storing receive data, a variable node calculation unit 307, a decoded word calculation unit 309, a receive data rearrangement unit 310, and a decoded data rearrangement unit 311.

[0558] First, a method of storing data in the edge data storage memories 300 and 304 will be described.

[0559] The edge data storage memory 300 has six FIFOs 300, the number of which is obtained by dividing the number of rows of the conversion check matrix H′ in FIG. 150 (30) by the number of rows of the constituent matrix (unit size P) (5). 1 or 300 6 It consists of FIFO300 y (y=1,2,...,6) consists of a number of storage areas, and each storage area can simultaneously read and write messages corresponding to five edges, which are the number of rows and columns (unit size P) of the configuration matrix. y The number of stages of the storage area is 9, which is the maximum number of 1s (Hamming weights) in the row direction of the conversion check matrix in FIG.

[0560] FIFO300 1 The data corresponding to the positions of 1 from the first row to the fifth row of the conversion check matrix H' in FIG. 150 (message v from the variable node i ) are stored in a horizontally packed manner (ignoring 0) in each row. In other words, if the jth row and ith column are represented as (j, i), then the FIFO 300 1 The first-stage memory area stores data corresponding to the positions of 1 in the 5×5 unit matrix from (1,1) to (5,5) of the conversion check matrix H'. The second-stage memory area stores data corresponding to the positions of 1 in the shift matrix from (1,21) to (5,25) of the conversion check matrix H' (a shift matrix obtained by cyclically shifting a 5×5 unit matrix by three places to the right). Similarly, the third to eighth-stage memory areas store data in association with the conversion check matrix H'. The ninth-stage memory area stores data corresponding to the positions of 1 in the shift matrix from (1,86) to (5,90) of the conversion check matrix H' (a shift matrix obtained by replacing the 1 in the first row of the 5×5 unit matrix with 0 and cyclically shifting one place to the left).

[0561] FIFO300 2 The data corresponding to the positions of 1 from the sixth row to the tenth row of the conversion check matrix H' in FIG. 150 is stored in FIFO 300. 2The first-stage memory area stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of the transformed check matrix H' (the sum matrix being the sum of a first shift matrix obtained by cyclically shifting a 5×5 unit matrix to the right by one position and a second shift matrix obtained by cyclically shifting the matrix to the right by two positions) of the transformed check matrix H'. The second-stage memory area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of the transformed check matrix H'.

[0562] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix are changed to 0, or a shift matrix in which the unit matrix or the quasi-unit matrix is ​​cyclically shifted, data corresponding to the position of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) is stored at the same address (FIFO 300 1 or 300 6 The data is stored in the same FIFO.

[0563] Similarly, in the storage areas in the third to ninth stages, data is stored in association with the converted check matrix H'.

[0564] FIFO300 3 or 300 6 Similarly, data is stored in association with the conversion check matrix H′.

[0565] The edge data storage memory 304 has 18 FIFOs 304 obtained by dividing the number of columns of the conversion check matrix H′, 90, by the number of columns of the configuration matrix (unit size P), which is 5. 1 or 304 18 It is composed of FIFO304. x (x=1,2,...,18) consists of memory areas with multiple stages, and the memory areas of each stage can simultaneously read and write messages corresponding to five branches, which are the number of rows and columns of the constituent matrix (unit size P).

[0566] FIFO304 1 The data corresponding to the positions of 1 in the first to fifth columns of the conversion check matrix H' in FIG. 150 (message u from the check node) j ) are stored in a vertically packed manner (ignoring zeros) in each column. 1 The first-stage memory area stores data corresponding to the positions of 1 in the 5×5 unit matrix from (1,1) to (5,5) of the transformed parity check matrix H'. The second-stage memory area stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of the transformed parity check matrix H' (the sum matrix being the sum of a first shift matrix obtained by cyclically shifting a 5×5 unit matrix to the right by one position and a second shift matrix obtained by cyclically shifting a 5×5 unit matrix to the right by two positions). The third-stage memory area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of the transformed parity check matrix H'.

[0567] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix are changed to 0, or a shift matrix in which the unit matrix or the quasi-unit matrix is ​​cyclically shifted, data corresponding to the position of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) is stored at the same address (FIFO 304). 1 or 304 18 The data is stored in the same FIFO.

[0568] Similarly, in the fourth and fifth storage areas, data is stored in association with the conversion check matrix H′. 1 The number of stages of the storage area is 5, which is the maximum number of 1's (Hamming weights) in the row direction from the first column to the fifth column of the converted check matrix H'.

[0569] FIFO304 2 and 304 3Similarly, FIFO 304 stores data in association with the conversion check matrix H′, and each has a length (number of stages) of 5. 4 or 304 12 Similarly, FIFO 304 stores data in association with the conversion check matrix H′, and each has a length of 3. 13 or 304 18 Similarly, data is stored in association with the converted check matrix H′, and each has a length of 2.

[0570] Next, the operation of the decoding device in FIG. 151 will be described.

[0571] The edge data storage memory 300 includes six FIFOs 300. 1 or 300 6 The FIFO for storing data is determined according to information (Matrix data) D312 indicating which row of the conversion check matrix H' in FIG. 150 each of five messages D311 supplied from the preceding cyclic shift circuit 308 belongs to. 1 or 300 6 Then, five messages D311 are stored in the selected FIFO in order. 1 5 messages from D300 1 The edge data storage memory 300 is a FIFO 300. 1 After reading the message from FIFO300, 2 or 300 6 302, in order, and supplies the messages to the selector 301.

[0572] The selector 301 selects the FIFO 300 according to the select signal D301. 1 or 300 6 Among these, the five messages from the FIFO from which data is currently being read are selected and supplied to the check node calculation unit 302 as message D 302 .

[0573] The check node calculation unit 302 includes five check node calculators 302 1 or 302 5 A message D302 (D302 1 Or D302 5 )(Message v in Eq. (7) i ) to perform check node calculation according to equation (7), and the five messages D303 (D303 1 Or D303 5 )(Message u in Eq. (7) j ) is supplied to the cyclic shift circuit 303.

[0574] The cyclic shift circuit 303 converts the five messages D303 obtained by the check node calculation unit 302 into 1 Or D303 5 is cyclically shifted based on information (Matrix data) D305 indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the converted check matrix H' that corresponds to the corresponding branch is, and the result is supplied to the branch data storage memory 304 as a message D304.

[0575] The edge data storage memory 304 includes 18 FIFOs 304 1 or 304 18 The FIFO for storing data is selected according to information D305 indicating which row of the conversion check matrix H' each of the five messages D304 supplied from the previous stage cyclic shift circuit 303 belongs to. 1 or 304 18 Then, five messages D304 are stored in the selected FIFO in order. 1 5 Messages from D306 1 The edge data storage memory 304 is a FIFO 304. 1 After reading data from FIFO304 2 or 304 18, and supplies the messages to the selector 305.

[0576] The selector 305 selects the FIFO 304 according to the select signal D307. 1 or 304 18 Among these, the five messages from the FIFO from which data is currently being read are selected and supplied to the variable node calculation unit 307 and the decoded word calculation unit 309 as message D308.

[0577] On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H in FIG. 148 received through the communication path 13 by performing column permutation of equation (12), and supplies the result as received data D314 to the received data memory 306. The received data memory 306 calculates and stores received LLRs (log-likelihood ratios) from the received data D314 supplied from the received data rearrangement unit 310, and supplies the received LLRs in groups of five to the variable node calculation unit 307 and the decoded word calculation unit 309 as received values ​​D309.

[0578] The variable node calculation unit 307 includes five variable node calculators 307 1 or 307 5 and a message D308 (D308 1 Or D308 5 )(Message u in Eq. (1) j ) and five received values ​​D309 (received values ​​u 0i ), a variable node operation is performed according to formula (1), and the message D310 (D310 1 Or D310 5 )(Message v in Eq. (1) i ) to the cyclic shift circuit 308.

[0579] The cyclic shift circuit 308 converts the message D310 calculated by the variable node calculation unit 307 into 1 Or D310 5is cyclically shifted based on information indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the converted parity check matrix H' that corresponds to the corresponding branch is obtained by, and the result is supplied to the branch data storage memory 300 as a message D311.

[0580] By performing the above operations once, one decoding (variable node calculation and check node calculation) of the LDPC code can be performed. After the decoding device in Fig. 151 decodes the LDPC code a predetermined number of times, the decoded word calculation unit 309 and the decoded data rearrangement unit 311 obtain and output the final decoding result.

[0581] That is, the decoded word calculation unit 309 has five decoded word calculators 309 1 or 309 5 The five messages D308 (D308 1 Or D308 5 )(Message u in Eq. (5) j ) and five received values ​​D309 (received values ​​u 0i ), and in the final stage of multiple decoding operations, calculates a decoding result (decoded word) based on equation (5), and supplies the resulting decoded data D315 to the decoded data rearrangement unit 311.

[0582] The decoded data rearrangement unit 311 performs the inverse permutation of the column permutation in equation (12) on the decoded data D315 supplied from the decoded word calculation unit 309, thereby rearranging the order, and outputs the result as the final decoded result D316.

[0583] As described above, by performing row permutation and / or column permutation on the parity check matrix (original parity check matrix), a P×P identity matrix, a quasi-identity matrix with one or more of its elements changed to 0, a shift matrix obtained by cyclically shifting an identity matrix or a quasi-identity matrix, a unit matrix, a quasi-identity matrix, or a sum matrix which is a sum of a plurality of shift matrices, and a combination of P×P 0 matrices, that is, a parity check matrix (transformed parity check matrix) that can be expressed by a combination of constituent matrices, it becomes possible to adopt an architecture for simultaneously performing P check node operations and variable node operations, which is a number smaller than the number of rows and columns of the parity check matrix, for decoding LDPC codes.When adopting an architecture for simultaneously performing P node operations (check node operations and variable node operations), which is a number smaller than the number of rows and columns of the parity check matrix, it is possible to suppress the operating frequency to a feasible range and perform a large number of repeated decodings, compared to the case where node operations are performed simultaneously for a number equal to the number of rows and columns of the parity check matrix.

[0584] The LDPC decoder 166 constituting the receiving device 12 in FIG. 145 performs LDPC decoding by simultaneously performing P check node operations and variable node operations, similar to the decoding device in FIG. 151, for example.

[0585] That is, for the sake of simplicity, if the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 in FIG. 8 is, for example, the parity check matrix H shown in FIG. 148 in which the parity matrix has a staircase structure, then in the parity interleaver 23 of the transmitting device 11, parity interleaving is performed to interleave the K+qx+y+1-th code bit at the K+Py+x+1-th code bit position, with the information length K set to 60, the unit size P set to 5, and the divisor q (=M / P) of the parity length M set to 6, respectively.

[0586] As described above, this parity interleaving corresponds to the column permutation in equation (12), and therefore LDPC decoder 166 does not need to perform the column permutation in equation (12).

[0587] For this reason, in the receiving device 12 of FIG. 145, as described above, an LDPC code that has not been subjected to parity deinterleaving, that is, an LDPC code in a state in which the column permutation of equation (12) has been performed, is supplied from the group-wise deinterleaver 55 to the LDPC decoder 166, and the LDPC decoder 166 performs processing similar to that of the decoding device of FIG. 151, except that the column permutation of equation (12) is not performed.

[0588] 152 is a diagram showing an example of the configuration of the LDPC decoder 166 in FIG.

[0589] In FIG. 152, LDPC decoder 166 is configured in the same manner as the decoding device in FIG. 151, except that received data rearrangement unit 310 in FIG. 151 is not provided, and performs the same processing as the decoding device in FIG. 151, except that the column permutation of equation (12) is not performed, so a description thereof will be omitted.

[0590] As described above, the LDPC decoder 166 can be configured without providing the received data rearrangement section 310, and therefore the size can be reduced compared to the decoding device in FIG.

[0591] In addition, in FIG. 148 to FIG. 152, for the sake of simplicity, the code length N of the LDPC code is set to 90, the information length K is set to 60, the unit size (number of rows and columns of the constituent matrix) P is set to 5, and the divisor q (=M / P) of the parity length M is set to 6, but each of the code length N, information length K, unit size P, and divisor q (=M / P) is not limited to the above-mentioned values.

[0592] That is, in the transmitting device 11 of FIG. 8, the LDPC encoder 115 outputs an LDPC code having, for example, a code length N of 64800, 16200, 69120, etc., an information length K of N-Pq (=NM), a unit size P of 360, and a divisor q of M / P. The LDPC decoder 166 of FIG. 152 is applicable to the case where LDPC decoding is performed by simultaneously performing P check node operations and variable node operations on such an LDPC code.

[0593] Furthermore, if after LDPC decoder 166 decodes the LDPC code, the parity portion of the decoded result is not necessary and only the information bits of the decoded result are output, LDPC decoder 166 can be configured without decoded data rearrangement unit 311.

[0594] <Example of the configuration of the block deinterleaver 54>

[0595] FIG. 153 is a block diagram showing an example of the configuration of the block deinterleaver 54 shown in FIG.

[0596] The block deinterleaver 54 is configured in the same manner as the block interleaver 25 described in FIG.

[0597] Therefore, the block deinterleaver 54 has a memory area called part 1 and a memory area called part 2, and both parts 1 and 2 are configured with columns arranged in the row direction as memory areas each storing 1 bit in the row direction and storing a predetermined number of bits in the column direction, the number C being equal to the number of bits m of a symbol.

[0598] The block deinterleaver 54 performs block deinterleaving on parts 1 and 2 by writing and reading LDPC codes.

[0599] However, in block deinterleaving, the LDPC codes (which are symbols) are written in the order in which the block interleaver 25 in FIG. 142 reads the LDPC codes.

[0600] Furthermore, in block deinterleaving, the LDPC codes are read out in the order in which the block interleaver 25 in FIG. 142 writes the LDPC codes.

[0601] That is, in the block interleaving by the block interleaver 25 in FIG. 142, the LDPC code is written in the column direction for parts 1 and 2 and read out in the row direction, whereas in the block deinterleaving by the block deinterleaver 54 in FIG. 153, the LDPC code is written in the row direction for parts 1 and 2 and read out in the column direction.

[0602] <Other configuration examples of the bit deinterleaver 165>

[0603] FIG. 154 is a block diagram showing another example of the configuration of the bit deinterleaver 165 of FIG.

[0604] In the figure, parts corresponding to those in FIG. 146 are given the same reference numerals, and their explanation will be omitted below as appropriate.

[0605] That is, the bit deinterleaver 165 in FIG. 154 has the same configuration as that in FIG. 146, except that a parity deinterleaver 1011 is newly provided.

[0606] 154, the bit deinterleaver 165 is composed of a block deinterleaver 54, a group-wise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164.

[0607] That is, the block deinterleaver 54 performs block deinterleaving (the inverse process of block interleaving) on ​​the LDPC code from the demapper 164, which corresponds to the block interleaving performed by the block interleaver 25 of the transmitting device 11, i.e., block deinterleaving that returns the positions of the code bits swapped by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0608] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving as rearrangement processing performed by the group-wise interleaver 24 of the transmission device 11.

[0609] The LDPC code resulting from the group-wise deinterleaving is supplied from the group-wise deinterleaver 55 to a parity deinterleaver 1011 .

[0610] The parity deinterleaver 1011 performs parity deinterleaving (the inverse process of parity interleaving) on ​​the code bits after group-wise deinterleaving in the group-wise deinterleaver 55, which corresponds to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by the parity interleaving to their original order.

[0611] The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166 .

[0612] Therefore, in the bit deinterleaver 165 of FIG. 154, an LDPC code that has been block deinterleaved, group-wise deinterleaved, and parity deinterleaved, that is, an LDPC code obtained by LDPC encoding in accordance with the parity check matrix H, is supplied to the LDPC decoder 166.

[0613] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 by using the parity check matrix H used by the LDPC encoder 115 of the transmission device 11 for LDPC encoding.

[0614] That is, for the Type B method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H (of the Type B method) that the LDPC encoder 115 of the transmitting device 11 used for LDPC encoding, or using a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the parity check matrix H. Also, for the Type A method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a parity check matrix (FIG. 28) obtained by performing column permutation on the parity check matrix (FIG. 27) (of the Type A method) that the LDPC encoder 115 of the transmitting device 11 used for LDPC encoding, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the parity check matrix (FIG. 27) used for LDPC encoding.

[0615] Here, in FIG. 154, an LDPC code obtained by LDPC encoding according to check matrix H is supplied from (parity deinterleaver 1011 of) bit deinterleaver 165 to LDPC decoder 166. In the case where LDPC decoding of the LDPC code is performed using check matrix H of the type B method itself used for LDPC encoding by LDPC encoder 115 of transmitting device 11, or a check matrix (FIG. 28) obtained by applying column permutation to the check matrix of the type A method (FIG. 27) used for LDPC encoding, LDPC decoder 166 can be configured, for example, as a decoding device that performs LDPC decoding by a full serial decoding method in which calculations of messages (check node messages, variable node messages) are performed sequentially for each node, or as a decoding device that performs LDPC decoding by a full parallel decoding method in which calculations of messages are performed simultaneously (in parallel) for all nodes.

[0616] Furthermore, in the LDPC decoder 166, when LDPC decoding of the LDPC code is performed using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on the check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix H of the Type A method used for LDPC encoding (FIG. 27), the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor of P other than 1) check node operations and variable node operations, and can be configured as a decoding device (FIG. 151) having a received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column permutation similar to the column permutation (parity interleaving) for obtaining the transformed check matrix on the LDPC code.

[0617] In FIG. 154, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving, the group-wise deinterleaver 55 that performs group-wise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are each configured separately, but two or more of the block deinterleaver 54, group-wise deinterleaver 55, and parity deinterleaver 1011 can be configured integrally, similar to the parity interleaver 23, group-wise interleaver 24, and block interleaver 25 of the transmitting device 11.

[0618] <Example of receiving system configuration>

[0619] FIG. 155 is a block diagram showing a first example configuration of a receiving system to which the receiving device 12 can be applied.

[0620] In FIG. 155, the receiving system includes an acquisition unit 1101, a transmission path decoding unit 1102, and an information source decoding unit 1103.

[0621] The acquisition unit 1101 acquires a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as image data and audio data of a program via a transmission path (communication path) not shown, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies the signal to a transmission path decoding processing unit 1102.

[0622] Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcast station via terrestrial waves, satellite waves, a CATV (Cable Television) network, etc., the acquisition unit 1101 is configured with a tuner, an STB (Set Top Box), etc. When the signal acquired by the acquisition unit 1101 is transmitted by multicast from a web server, such as IPTV (Internet Protocol Television), the acquisition unit 1101 is configured with a network I / F (Interface) such as a NIC (Network Interface Card).

[0623] The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs a transmission path decoding process including at least a process of correcting an error occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and supplies the resulting signal to the information source decoding processing unit 1103.

[0624] In other words, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding to correct errors that occur on the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing such as error correction processing on such a signal.

[0625] Here, examples of error correction coding include LDPC coding, BCH coding, etc. Here, at least LDPC coding is performed as the error correction coding.

[0626] Furthermore, the transmission path decoding process may include demodulation of a modulated signal.

[0627] The information source decoding unit 1103 performs information source decoding on the signal that has been subjected to the transmission channel decoding process, which includes at least a process of expanding compressed information to the original information.

[0628] In other words, the signal acquired by the acquisition unit 1101 via the transmission path may have been subjected to compression encoding, which compresses the information in order to reduce the amount of data such as images and audio.In this case, the information source decoding processing unit 1103 performs information source decoding processing, such as a process of expanding the compressed information to the original information (decompression processing), on the signal that has been subjected to transmission path decoding processing.

[0629] In addition, if the signal acquired by the acquisition unit 1101 via the transmission path has not been compression-encoded, the information source decoding processing unit 1103 does not perform processing to expand the compressed information to the original information.

[0630] Here, the decompression process includes, for example, MPEG decoding, etc. Furthermore, the transmission line decoding process may include descrambling and the like in addition to the decompression process.

[0631] In the receiving system configured as described above, in the acquisition unit 1101, for example, data such as images and audio are subjected to compression encoding such as MPEG encoding, and the signal that has been further subjected to error correction encoding such as LDPC encoding is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

[0632] In the transmission path decoding processing unit 1102, the signal from the acquisition unit 1101 is subjected to transmission path decoding processing, such as processing similar to that performed by the receiving device 12, and the resulting signal is supplied to the information source decoding processing unit 1103.

[0633] The information source decoding processor 1103 performs information source decoding such as MPEG decoding on the signal from the transmission path decoding processor 1102, and outputs the resulting image or sound.

[0634] The receiving system of FIG. 155 as described above can be applied to, for example, a television tuner that receives television broadcasts as digital broadcasts.

[0635] In addition, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as a single independent device (hardware (IC (Integrated Circuit) etc.) or software module).

[0636] In addition, with regard to the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, it is possible to configure a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 as a single independent device.

[0637] FIG. 156 is a block diagram showing a second exemplary configuration of a receiving system to which the receiving device 12 can be applied.

[0638] In the figure, parts corresponding to those in FIG. 155 are given the same symbols, and their explanations will be omitted below as appropriate.

[0639] The receiving system in Figure 156 is similar to that in Figure 155 in that it has an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103, but differs from that in Figure 155 in that an output unit 1111 is newly provided.

[0640] The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs sound, and outputs images, sound, and the like as signals output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs sound.

[0641] The receiving system in FIG. 156 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, a radio receiver that receives radio broadcasts, and the like.

[0642] If the signal acquired by the acquisition unit 1101 has not been subjected to compression encoding, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111 .

[0643] FIG. 157 is a block diagram showing a third example configuration of a receiving system to which the receiving device 12 can be applied.

[0644] In the figure, parts corresponding to those in FIG. 155 are given the same symbols, and their explanations will be omitted below as appropriate.

[0645] The receiving system in FIG. 157 is common to the case in FIG. 155 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.

[0646] However, the receiving system in FIG. 157 differs from that in FIG. 155 in that the information source decoding processing unit 1103 is not provided and a recording unit 1121 is newly provided.

[0647] The recording unit 1121 records (stores) the signal (for example, TS packets of MPEG TS) output by the transmission path decoding processing unit 1102 in a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

[0648] The receiving system of FIG. 157 as described above can be applied to a recorder for recording television broadcasts.

[0649] In addition, in FIG. 157, the receiving system is configured to include an information source decoding processing unit 1103, and the signal after information source decoding processing has been performed by the information source decoding processing unit 1103, i.e., the image and audio obtained by decoding, can be recorded in a recording unit 1121.

[0650] <An embodiment of the computer>

[0651] Next, the above-mentioned series of processes can be performed by hardware or software. When the series of processes is performed by software, a program constituting the software is installed in a general-purpose computer or the like.

[0652] FIG. 158 shows an example of the configuration of an embodiment of a computer in which a program for executing the series of processes described above is installed.

[0653] The program can be recorded in advance on the hard disk 705 or ROM 703 as a recording medium built into the computer.

[0654] Alternatively, the program can be temporarily or permanently stored (recorded) in a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, a semiconductor memory, etc. Such a removable recording medium 711 can be provided as a so-called package software.

[0655] In addition to being installed in a computer from the removable recording medium 711 as described above, the program can also be transferred wirelessly to a computer from a download site via an artificial satellite for digital satellite broadcasting, or transferred to a computer by wire via a network such as a LAN (Local Area Network) or the Internet, and the computer can receive the program transferred in this manner via communication unit 708 and install it in its built-in hard disk 705.

[0656] The computer includes a CPU (Central Processing Unit) 702. An input / output interface 710 is connected to the CPU 702 via a bus 701. When a command is input to the CPU 702 via the input / output interface 710 by a user operating an input unit 707 including a keyboard, a mouse, a microphone, etc., the CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance with the command. Alternatively, the CPU 702 loads into a RAM (Random Access Memory) 704 a program stored in a hard disk 705, a program transferred from a satellite or a network, received by a communication unit 708, and installed in the hard disk 705, or a program read from a removable recording medium 711 mounted on a drive 709 and installed in the hard disk 705. As a result, the CPU 702 executes the process according to the above-mentioned flowchart or the process performed by the configuration of the above-mentioned block diagram. Then, the CPU 702 outputs the processing results from an output unit 706 consisting of an LCD (Liquid Crystal Display) and a speaker, etc., via an input / output interface 710, or transmits the results from a communication unit 708, or even records the results on a hard disk 705, as necessary.

[0657] Here, in this specification, the processing steps that describe a program for causing a computer to perform various processes do not necessarily have to be processed chronologically in the order described in the flowchart, but also include processes that are executed in parallel or individually (for example, parallel processing or processing by objects).

[0658] The program may be processed by one computer, or may be distributed among multiple computers, and may be transferred to a remote computer for execution.

[0659] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0660] For example, the above-mentioned new LDPC code (its check matrix initial value table) can be used for the communication channel 13 (FIG. 7) whether it is a satellite line, a terrestrial wave, a cable (wired line), or any other. Furthermore, the new LDPC code can be used for data transmission other than digital broadcasting.

[0661] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained. [Explanation of symbols]

[0662] 11 transmitter, 12 receiver, 23 parity interleaver, 24 group-wise interleaver, 25 block interleaver, 54 block deinterleaver, 55 group-wise deinterleaver, 111 mode adaptation / multiplexer, 112 padder, 113 BB scrambler, 114 BCH encoder, 115 LDPC encoder, 116 bit interleaver, 117 mapper, 118 time interleaver, 119 SISO / MISO encoder, 120 frequency interleaver, 121 BCH encoder, 122 LDPC encoder, 123 mapper, 124 frequency interleaver, 131 frame builder / resource allocation unit, 132 OFDM generator, 151 OFDM processor, 152 frame manager, 153 frequency deinterleaver, 154 Demapper, 155 LDPC decoder, 156 BCH decoder, 161 Frequency deinterleaver, 162 SISO / MISO decoder, 163 Time deinterleaver, 164 Demapper, 165 Bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 Demultiplexer, 300 Edge data storage memory, 301 Selector, 302 Check node calculation unit, 303 Cyclic shift circuit, 304 Edge data storage memory, 305 Selector, 306 Received data memory, 307 Variable node calculation unit, 308 Cyclic shift circuit, 309 Decoded word calculation unit, 310 Received data rearrangement unit, 311 Decoded data rearrangement unit, 601 Encoding unit, 602 storage unit, 611 coding rate setting unit, 612 initial value table reading unit, 613 check matrix generation unit, 614 information bit reading unit, 615 coding parity calculation unit, 616 control unit, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk, 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input / output interface, 711, removable recording medium, 1001 reverse exchange unit, 1002 memory,1011 parity deinterleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit,

Claims

1. A transmitting device having an encoding unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16; A receiving device including a decoding unit that decodes the LDPC code; Equipped with The check matrix is A matrix A in the upper left corner of the check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a step structure adjacent to the right of the A matrix, the B matrix having M1 rows and M1 columns; A Z matrix, which is a zero matrix adjacent to the right of the B matrix and has M1 rows and N-K-M1 columns; A matrix C having N-M1 rows and K+M1 columns adjacent below the matrix A and the matrix B; A matrix D, which is an identity matrix adjacent to the right of the matrix C, and has N-K-M1 rows and N-K-M1 columns. Including, The predetermined value M1 is 1800, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 is Transmitting and receiving system.

2. A coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16; a decoding step of decoding the LDPC code; Equipped with The check matrix is A matrix A in the upper left corner of the check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a step structure adjacent to the right of the A matrix, the B matrix having M1 rows and M1 columns; A Z matrix, which is a zero matrix adjacent to the right of the B matrix and has M1 rows and N-K-M1 columns; A matrix C having N-M1 rows and K+M1 columns adjacent below the matrix A and the matrix B; A matrix D, which is an identity matrix adjacent to the right of the matrix C, and has N-K-M1 rows and N-K-M1 columns. Including, The predetermined value M1 is 1800, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 152 1634 7484 23081 24142 26799 33620 40989 41902 44319 44378 45067 140 701 5137 7313 12672 16929 20359 27052 30236 33846 36254 46973 748 769 2891 7812 9964 15629 19104 20551 25796 28144 31518 34124 542 976 2279 18904 20877 24190 25903 28129 36804 41152 41957 46888 173 960 2926 11682 12304 13284 18037 22702 30255 33718 34073 37152 78 1487 4898 7472 8033 10631 11732 19334 24577 34586 38651 43639 594 1095 1857 2368 8909 17295 17546 21865 23257 31273 37013 41454 72 419 1596 7849 16093 23167 26923 31883 36092 40348 44500 866 1120 1568 1986 3532 20094 21663 26664 26970 33542 42578 868 917 1216 12018 15402 20691 24736 33133 36692 40276 46616 955 1070 1749 7988 10235 19174 22733 24283 27985 38200 44029 613 1729 1787 19542 21227 21376 31057 36104 36874 38078 42445 86 1555 1644 4633 14402 14997 25724 31382 31911 32224 43900 353 1132 1246 5544 7248 17887 25769 27008 28773 33188 44663 600 958 1376 6417 6814 17587 20680 25376 29522 31396 40526 179 528 1472 2481 5589 15696 20148 28040 29690 32370 42163 122 144 681 6613 11230 20862 26396 27737 35928 39396 42713 934 1256 1420 3881 4487 5830 7897 9587 17940 40333 41925 622 1458 1490 16541 18443 19401 24860 26981 28157 32875 38755 1017 1143 1511 2169 17322 24662 25971 29149 31450 31670 34779 935 1084 1534 2918 10596 11534 17476 27269 30344 31104 37975 173 532 1766 8001 10483 17002 19002 26759 31006 43466 47443 221 610 1795 9197 11770 12793 14875 30177 30610 42274 43888 188 439 1332 7030 9246 15150 26060 26541 27190 28259 36763 812 1643 1750 7446 7888 7995 18804 21646 28995 30727 39065 44 481 555 5618 9621 9873 19182 22059 42510 45343 46058 156 532 1799 6258 18733 19988 23237 27657 30835 34738 39503 1128 1553 1790 8372 11543 13764 17062 28627 38502 40796 42461 564 777 1286 3446 5566 12105 16038 18918 21802 25954 28137 1167 1178 1770 4151 11422 11833 16823 17799 19188 22517 29979 576 638 1364 12257 22028 24243 24297 31788 36398 38409 47211 334 592 940 2865 12075 12708 21452 31961 32150 35723 46278 1205 1267 1721 9293 18685 18917 23490 27678 37645 40114 45733 189 628 821 17066 19218 21462 25452 26858 38408 38941 42354 190 951 1019 5572 7135 15647 32613 33863 33981 35670 43727 84 1003 1597 12597 15567 21221 21891 23151 23964 24816 46178 756 1262 1345 6694 6893 9300 9497 17950 19082 35668 38447 848 948 1560 6591 12529 12535 20567 23882 34481 46531 46541 504 631 777 10585 12330 13822 15388 23332 27688 35955 38051 676 1484 1575 2215 5830 6049 13558 25034 33602 35663 41025 1298 1427 1732 13930 15611 19462 20975 23200 30460 30682 34883 1491 1593 1615 4289 7010 10264 21047 26704 27024 29658 46766 969 1730 1748 2217 7181 7623 15860 21332 28133 28998 36077 302 1216 1374 5177 6849 7239 10255 34952 37908 39911 41738 220 362 1491 5235 5439 22708 29228 29481 33272 36831 46487 4 728 1279 4579 8325 8505 27604 31437 33574 41716 45082 472 735 1558 4454 6957 14867 18307 22437 38304 42054 45307 85 466 851 3669 7119 32748 32845 41914 42595 42600 45101 52 553 824 2994 4569 12505 24738 33258 37121 43381 44753 37 495 1553 7684 8908 12412 15563 16461 17872 29292 30619 254 1057 1481 9971 18408 19815 28569 29164 39281 42723 45604 16 1213 1614 4352 8091 8847 10022 24394 35661 43800 44362 395 750 888 2582 3772 4151 26025 36367 42326 42673 47393 862 1379 1441 6413 25621 28378 34869 35491 41774 44165 45411 46 213 1597 2771 4694 4923 17101 17212 19347 22002 43226 1339 1544 1610 13522 14840 15355 29399 30125 33685 36350 37672 251 1162 1260 9766 13137 34769 36646 43313 43736 43828 45151 214 1002 1688 5357 19091 19213 24460 28843 32869 35013 39791 646 733 1735 11175 11336 12043 22962 33892 35646 37116 38655 293 927 1064 4818 5842 10983 12871 17804 33127 41604 46588 10927 15514 22748 34850 37645 40669 41583 44090 3329 7548 8092 11659 16832 35304 46738 46888 3510 5915 9603 30333 37198 42866 44361 46416 2575 5311 9421 13410 15375 34017 37136 43990 12468 14492 24417 26394 38565 38936 41899 45593 is Sending and receiving methods.

Images