Josephson junction fabrication method and system

Abstract

A method and system for fabricating Josephson junctions, related to the technical field of micro-nanomachining, is provided. The method includes the steps of: forming a circuit structure on a substrate using nanoimprinting (201), the circuit structure including a first lead, a second lead, and a peripheral circuit; forming an undercut structure on the substrate using photoresist (202), the undercut structure being a strip-shaped structure, with a first region and a second region having an upper photoresist layer and a lower photoresist layer, and the second region being an open region of the undercut structure; forming an oxide layer on the surface of the second lead not covered by the photoresist (203); obliquely evaporating a first superconducting layer from the first region to the second region to obtain a Josephson junction (204); and obliquely evaporating a second superconducting layer from the second region to the first region (205). This scheme can avoid the introduction of parasitic junctions, thereby improving the decoherence of quantum bit components and improving the performance of quantum computing devices.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application bearing application number 202210726039.6 and entitled "Method and system for preparing Josephson junctions," filed with the China Patent Office on June 23, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of micro-nano fabrication, and in particular to a method and system for fabricating Josephson junctions. [Background technology]

[0003] Josephson junctions are currently a commonly used qubit structure, and they can be fabricated (also called prepared) using pre-designed photoresist structures.

[0004] In the related technology, a Dranbridge photoresist structure pattern including an undercut is formed in a two-layer electron beam photoresist on the surface of a base by using an electron beam exposure method, and then a two-way oblique deposition method is adopted in which a superconducting metal film is first obliquely deposited, then oxidized to form an insulating layer, and then a superconducting metal film is vertically deposited to form a Josephson junction.

[0005] Subsequently, the above-mentioned Josephson junction fabrication scheme may introduce extra Josephson junctions (also called parasitic junctions) into the fabricated qubit component, which may affect the coherence of the qubit component. Summary of the Invention [Problem to be solved by the invention]

[0006] The present application aims to provide a method and system for fabricating Josephson junctions that can avoid the introduction of parasitic junctions and improve decoherence of quantum bit components. [Means for solving the problem]

[0007] According to one aspect, a method of making Josephson junctions is provided, the method being carried out by production line equipment, the method comprising: forming a circuit structure on a substrate by a nanoimprinting method, the circuit structure including a first lead, a second lead, and a peripheral circuit respectively connected to the first lead and the second lead, the first lead, the second lead, and the peripheral circuit being an integral structure; forming an undercut structure by photoresist on the substrate, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper photoresist layer and a lower photoresist layer, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a part of the second lead, and the third region being located between the first region and the second region; forming an oxide layer on a surface of the second lead that is not covered by the photoresist; Obliquely evaporating a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, the first superconducting layer covering an area of ​​the second lead not covered by photoresist, the first superconducting layer covering a portion of the substrate between the second lead and the first lead; and The method includes obliquely depositing a second superconducting layer in a direction from the second region to the first region, the second superconducting layer covering an area of ​​the first lead not covered by photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

[0008] According to another aspect, a Josephson junction fabrication system is provided, the system including a nanoimprint subsystem, a photolithography subsystem, an oxidation subsystem, and a deposition subsystem; the nanoimprint subsystem is used to form a circuit structure on a substrate by a nanoimprint method, the circuit structure includes a first lead, a second lead, and a peripheral circuit connected to the first lead and the second lead, respectively, the first lead, the second lead, and the peripheral circuit being an integral structure; The photolithography subsystem is used to form an undercut structure by photoresist on the substrate, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper photoresist layer and a lower photoresist layer, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a part of the second lead, and the third region being located between the first region and the second region; the oxidation subsystem is used to form an oxide layer on the surface of the second lead that is not covered by the photoresist; the deposition subsystem is used to obliquely deposit a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, the first superconducting layer covering an area of ​​the second lead that is not covered by photoresist, and the first superconducting layer covering a portion of the substrate between the second lead and the first lead; The deposition subsystem is further used to obliquely deposit a second superconducting layer according to a direction from the second region to the first region, the second superconducting layer covering an area of ​​the first lead not covered by photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

[0009] In one possible implementation, the undercut structure further includes a fourth region, the fourth region being an opening region of the undercut structure, and the second region is located between the third region and the fourth region.

[0010] In one possible implementation, the length of the second region is greater than the length of the first region, and the portion of the second lead covered by the second region is located on one side of the second region closer to the third region.

[0011] In one possible implementation, the oxidation subsystem is used to oxidize the substrate by placing it in an oxidation chamber with a pure oxygen atmosphere (environment).

[0012] The Josephson junction fabrication system further includes an etching subsystem, which is used to remove an oxide layer on a surface of the first lead that is not covered by photoresist by performing ion etching at an angle according to a direction from the second region to the first region.

[0013] In one possible implementation, the time length of the gradient ion etching from the second region to the first region is 2 minutes, and the etching power is 200 watts.

[0014] In one possible implementation, the pressure in the oxidation chamber is 4 Torr and the oxidation time length of the substrate in the oxidation chamber is 1000 to 2000 seconds.

[0015] In one possible implementation, the etching subsystem is further used to perform ion etching on the surfaces of the first lead and the second lead that are not covered by photoresist.

[0016] In one possible implementation, the etching subsystem is used to rotate the substrate while keeping the ion etch tilt angle constant.

[0017] In one possible implementation, the deposition ramp rate of the first superconducting layer is 1 nanometer per second and the thickness of the first superconducting layer is 100 nanometers.

[0018] In one possible implementation, an extension of the first lead crosses the second lead.

[0019] In one possible implementation, the first lead is perpendicular to the second lead, and the first lead is parallel to the undercut structure.

[0020] In one possible implementation, the nanoimprint subsystem is used to: forming a superconducting film layer on the substrate; spin-coating the superconducting film layer with a nanoimprint adhesive; imprinting a structural pattern of the circuit structure on the nanoimprint adhesive using a nanoimprint mask; Etching the superconducting film layer based on the structural pattern; and Cleaning the nanoimprint adhesive on the substrate to obtain the circuit structure located on the substrate.

[0021] In one possible realization, the thickness of the superconducting film layer is 100 nanometers.

[0022] In one possible implementation, the nanoimprint subsystem is used to perform etching in the superconducting film layer according to the structure pattern in the manner of dry etching.

[0023] In one possible implementation, the nanoimprint subsystem is further used to remove remaining nanoimprint adhesive in the imprint grooves of the nanoimprint adhesive. Effect of the Invention

[0024] The advantageous effects brought by the technical solutions provided in the embodiments of the present application are at least as follows:

[0025] When fabricating a quantum computing device, first, a Josephson junction peripheral circuit and a lead for connecting the Josephson junction to the peripheral circuit are formed by nanoimprinting, and the lead and the peripheral circuit are integral, so that the Josephson junction formed subsequently does not need to be additionally fabricated as a Josephson junction patch / Josephson junction bandage for connecting the Josephson junction to the peripheral circuit, and then, a first superconducting layer and a second superconducting layer are formed by depositing superconducting material in two oblique directions by undercut structures, in which the first superconducting layer forms a Josephson junction at the crossing with the second lead, and the second superconducting layer is connected to the first superconducting layer and the end of the first lead, thereby making a superconducting connection between the end of the first lead and the Josephson junction. When fabricating a Josephson junction in a quantum computing device by the above scheme, the introduction of a parasitic junction can be avoided, which can improve the decoherence of the quantum bit component and improve the performance of the quantum computing device. [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is a diagram showing the effect of creating a Josephson junction according to the present application. [Diagram 2] 1 is a flow chart of a method for fabricating a Josephson junction according to one exemplary embodiment of the present application. [Diagram 3] 3 is a diagram showing an undercut structure according to the embodiment shown in FIG. 2. [Figure 4] 1 is a flow chart for fabricating a Josephson junction as shown in one exemplary embodiment of the present application. [Diagram 5] 1 is a flow chart of a method for fabricating a Josephson junction according to one exemplary embodiment of the present application. [Figure 6] 6 is a diagram showing a circuit structure and an undercut structure according to the embodiment shown in FIG. 5. [Figure 7] 6 shows another circuit structure and an undercut structure according to the embodiment shown in FIG. 5. [Figure 8] FIG. 6 shows the results after oxidation according to the embodiment shown in FIG. 5. [Figure 9] FIG. 6 is a diagram showing the effect after aluminum coating according to the embodiment shown in FIG. 5. [Figure 10] FIG. 6 illustrates the removal of an oxide layer according to the embodiment shown in FIG. 5. [Figure 11] FIG. 6 is a diagram showing a Josephson junction region according to the embodiment shown in FIG. 5. [Figure 12] 1 is a flowchart of the creation of a quantum computing device according to one exemplary embodiment of the present application. [Figure 13] FIG. 2 illustrates a product application scenario provided in one embodiment of the present application. [Figure 14] FIG. 1 illustrates a Josephson junction fabrication system according to one exemplary embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] First, the meanings of some terms used in this application will be introduced.

[0028] Qubit: In quantum information science, a quantum bit is a unit of measurement for quantum information. Unlike a classical bit, which can only be in one of two states, 0 or 1, a qubit can be in both states 0 and 1 at the same time, i.e., in a quantum superposition of 0 and 1.

[0029] Josephson Junction: A sandwich structure consisting of a superconducting layer, an insulating layer, and another superconducting layer, also called a superconducting tunnel junction. A Josephson junction is generally a structure consisting of two superconductors sandwiching a very thin barrier layer (thickness ≦ coherence length of Cooper electron pairs), for example, an S (Superconductor)-I (Semiconductor or Insulator)-S (Superconductor) structure, abbreviated as SIS structure. In a Josephson junction, superconducting electrons can reach the other superconducting layer from one superconducting layer by passing through a thin semiconductor or insulator film due to the tunnel effect.

[0030] Parasitic junction: An additional Josephson junction that arises in the process of creating a Josephson junction.

[0031] Shadow evaporation: In evaporation, the material to be evaporated is incident on the surface of a base (also called a substrate) at a certain angle, and a photoresist pattern is defined in the incident path to provide a barrier of a certain shape, allowing the film layer to be selectively evaporated in some places on the surface of the base and preventing the film layer from being evaporated in other places.

[0032] Josephson junction patch: A part in a superconducting quantum chip that connects a Josephson junction to an external circuit.

[0033] Josephson junction bandage: A part in a superconducting quantum chip that connects a Josephson junction patch to an external circuit.

[0034] Ion milling: The oxide layer on a material surface is removed by irradiating the surface with an ion beam in a specific direction.

[0035] Oblique evaporation: The deposition of the material along a direction not parallel to the normal to the base to form a thin film.

[0036] Straight evaporation: The material is evaporated in a direction parallel to the normal to the base to form a thin film.

[0037] Liftoff: A process in which the photoresist is dissolved in an adhesive remover (stripper) and the metal layer on top of the photoresist is simultaneously removed from the base.

[0038] Decoherence time: The ability of qubits to maintain correlation between different quantum states.

[0039] Undercut: A pattern feature formed after development of photoresist where the size of the opening above it is smaller than the size of the opening below it.

[0040] In situ: A multi-step process carried out in a single vacuum chamber or multiple interconnected vacuum chambers, where the sample / product is not transferred to the atmosphere.

[0041] Quantum computers have attracted a lot of attention because they can handle some specific problems much faster than classical computers. At present, one possible way to realize a quantum computer is the superconducting quantum computer. A superconducting quantum computer relies on superconducting quantum chips to realize logic gate operations. A superconducting quantum chip can be simply regarded as consisting of an external circuit and a Josephson junction, among which the Josephson junction is the core device of a superconducting quantum chip.

[0042] One of the methods for fabricating a Josephson junction is the shadow deposition method, which is formed by in-situ ion milling, oblique incidence deposition, oxidation and straight incidence deposition to form a Josephson junction. Please refer to FIG. 1, which is a diagram of the fabrication effect of a Josephson junction according to the present application. In FIG. 1, two Josephson junctions 101 connected in parallel are shown, and the two Josephson junctions 101 are connected to an external circuit by a Josephson junction patch 102. As shown in FIG. 1, after in-situ ion milling, oblique incidence deposition, oxidation and straight incidence deposition, a parasitic junction 103 may be generated in the quantum bit component, which is shown in the dotted frame in FIG. 1.

[0043] As shown in FIG. 1, when creating a Josephson junction according to the above-described scheme, large-area parasitic junctions may be introduced into the quantum bit component that includes the Josephson junction, which may affect the decoherence of the quantum bit component and thus affect the performance of the quantum computing device.

[0044] To improve the performance of qubit components whose structures are Josephson junctions, a new Josephson junction fabrication scheme is provided in the following examples of this application.

[0045] Please refer to Figure 2, which is a flow chart of a method for fabricating Josephson junctions according to one exemplary embodiment of the present application. The method is performed by production line equipment, and as shown in Figure 2, the method may include the following steps:

[0046] Step 201: Form a circuit structure on a substrate by a nanoimprint method, the circuit structure including a first lead, a second lead, and a peripheral circuit respectively connected to the first lead and the second lead, and the first lead, the second lead, and the peripheral circuit are an integral structure.

[0047] In one possible implementation, an extension of the first lead crosses the second lead.

[0048] Nanoimprint technology refers to the technique of transferring micro-nano structures on a template to a material to be processed using photoresist.

[0049] Among these, nanoimprint technology can be divided into the following three steps:

[0050] The first step is the fabrication of the template, usually by using tools such as electron beam etching to fabricate the required structures in a silicon or other substrate. Because the diffraction limit of electrons is much smaller than that of photons, much higher resolution can be achieved than with photolithography.

[0051] The second step is pattern transfer: a photoresist is applied to the surface of the material to be processed, and then the template is pressed onto the surface to transfer the pattern to the photoresist by applying pressure.

[0052] The third step is the processing of the substrate: the photoresist is solidified (cured) by ultraviolet light, and after peeling off the template, the surface of the material to be processed is exposed, and then it is processed by etching method, and after completion, all the photoresist is removed, and finally a high-precision processed product is obtained.

[0053] Step 202: forming an undercut structure using photoresist on the substrate, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper photoresist layer and a lower photoresist layer, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a portion of the second lead, and the third region being located between the first region and the second region.

[0054] The above-mentioned open region refers to a region where no photoresist exists.

[0055] The above-mentioned first region covering the end of the first lead refers to the first region being located above the end of the first lead in a direction perpendicular to the substrate, and correspondingly, the second region covering a portion of the second lead refers to the second region being located above a portion of the second lead in a direction perpendicular to the substrate.

[0056] In the embodiment of the present application, the photoresist undercut structure is strip-shaped and simultaneously covers the first lead and the second lead, in which photoresist is present on both the first lead and the second lead on the portions covered by the undercut structure, and an opening area is present in the undercut structure in the portion located between the first lead and the second lead.

[0057] For example, refer to FIG. 3, which is a diagram showing an undercut structure according to an embodiment of the present application. Part (a) in FIG. 3 is a top view of a substrate after the undercut structure is formed, and part (b) in FIG. 3 is a cross-sectional view of the substrate after the undercut structure is formed along the extension direction of the undercut structure. As shown in FIG. 3, the first lead 31 does not intersect with the second lead 32, but the extension line of the first lead 31 intersects with the second lead 32. The strip-shaped undercut structure extends from the end 31a of the first lead 31 beyond the second lead 32, and includes a first region 33 (lower layer cavity), a third region 34 (opening), and a second region 35 (lower layer cavity), respectively, and the first region 33 covers the end 31a of the first lead 31, and the second region 35 covers a part of the second lead 32.

[0058] Step 203: Form an oxide layer on the surface of the second lead that is not covered by the photoresist.

[0059] In the embodiment of the present application, the oxide layer formed on the surface of the second lead not covered by the above-mentioned photoresist is then made into an insulating layer in the Josephson junction.

[0060] Step 204: Obliquely deposit a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, where the first superconducting layer covers an area of ​​the second lead that is not covered by the photoresist, and the first superconducting layer also covers a part of the substrate between the second lead and the first lead.

[0061] In the embodiment of the present application, since there is an opening between the first region and the second region in the above-mentioned undercut structure, when the superconducting material is obliquely evaporated according to the direction from the first region to the second region, the superconducting material is evaporated obliquely through the opening onto the surface of the second lead not covered by the photoresist, forming a first superconducting layer, which covers not only the surface of the second lead not covered by the photoresist but also a part of the substrate. Due to the surface of the second lead not covered by the photoresist and the pre-formed oxide layer, the first superconducting layer, the oxide layer, and the part of the second lead not covered by the photoresist can form a Josephson junction of "superconducting layer-insulating layer-superconducting layer".

[0062] Step 205: Obliquely deposit a second superconducting layer according to a direction from the second region to the first region, where the second superconducting layer covers the area of ​​the first lead not covered by the photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

[0063] In one possible implementation, the implementation process of steps 204 to 205 above can be performed in an in-situ environment.

[0064] The deposition direction in step 204 is a direction inclined from the direction from the first region to the second region, and the first lead is the first region of the undercut structure above, and the end of the first lead is not deposited with superconducting material because of the presence of photoresist blocking. That is, the first lead is not connected to the Josephson junction formed in step 204. At this time, by performing oblique deposition according to the direction from the second region to the first region, a second superconducting layer covering the end of the first lead can be obtained, and the second superconducting layer extends from the end of the first lead to the first superconducting layer, so that the Josephson junction is connected to the first lead, thereby allowing the above-mentioned Josephson junction to be connected to peripheral circuits, thereby forming one superconducting quantum bit in a quantum computing device.

[0065] In summary, in the scheme shown in the embodiment of the present application, when a quantum computing device is fabricated, the peripheral circuit of the Josephson junction and the lead for connecting the Josephson junction to the peripheral circuit are first formed by nanoimprinting, and the lead and the peripheral circuit are integral, so that the Josephson junction formed subsequently does not need to be additionally formed as a Josephson junction patch / Josephson junction bandage for connecting to the peripheral circuit, and then the first superconducting layer and the second superconducting layer are formed by respectively depositing superconducting material in two oblique directions by undercut structure, among which the first superconducting layer forms a Josephson junction at the intersection with the second lead, and the second superconducting layer is connected to the first superconducting layer and the end of the first lead, so that the end of the first lead can be superconductively connected to the Josephson junction. When the Josephson junction in the quantum computing device is fabricated by the above scheme, the introduction of parasitic junctions can be avoided, so that the decoherence of the qubit component can be improved, and the performance of the quantum computing device can be improved.

[0066] Based on the scheme shown in Figure 2, reference is made to Figure 4, which is a diagram illustrating the fabrication of a Josephson junction shown in one exemplary embodiment of the present application. As shown in Figure 4, the fabrication flow of the Josephson junction may be as follows.

[0067] S1: Form a circuit structure on a base using nanoimprinting.

[0068] As shown in part (a) of FIG. 4, the circuit structure includes a first lead 41, a second lead 42, and a peripheral circuit 43 connected to the first lead 41 and the second lead 42, respectively.

[0069] Wherein, the above-mentioned first lead 41 does not intersect with the second lead 42, but the extension line of the first lead 41 intersects with the second lead 42 (i.e., the above-mentioned first lead 41 is not parallel to the second lead 42). The above-mentioned first lead 41, second lead 42 and peripheral circuits are an integrated structure formed by nanoimprinting, and there is no Josephson junction patch or Josephson junction bandage.

[0070] S2: An undercut structure is formed on the substrate using a photoresist.

[0071] As shown in part (b) of Figure 4, the undercut structure is a strip-like structure, and the undercut structure includes a first region 44, a second region 45 and a third region 46 that are adjacent to each other, where the first region 44 covers the end of the first lead 41, the second region 45 covers a portion of the second lead 42, and the third region 46 is located between the first region 44 and the second region 45.

[0072] S3: An oxide layer is formed on the surface of the second lead that is not covered by the photoresist.

[0073] As shown in part (b) of FIG. 4, the oxide layer 47 may be generated by the superconducting material constituting the second lead being oxidized after coming into contact with pure oxygen, and since only the part of the second lead covered by the second region can come into contact with pure oxygen, the above-mentioned oxide layer 47 can also be limited to the surface of the second lead that is not covered by the photoresist.

[0074] S4: A first superconducting layer is obliquely deposited according to a direction from the first region to the second region.

[0075] As shown in part (c) of Figure 4, due to the undercut structure consisting of the first region 44, the second region 45 and the third region 46, when the superconducting material is obliquely evaporated in the direction from the first region to the second region, the superconducting material can be obliquely incident on the second lead through the opening at the third region 46 but cannot be incident on the first lead. Therefore, the first superconducting layer 48 can be formed only on the second lead and a part of the base between the second lead and the first lead, and among them, the second lead 42, the oxide layer 47 and the first superconducting layer 48 form a Josephson junction at the second lead 42.

[0076] S5: A second superconducting layer is obliquely deposited in a direction from the second region to the first region.

[0077] 4(d), the second superconducting layer 49 covers the area of ​​the first lead 41 not covered by the photoresist, a part of the substrate between the second lead 42 and the first lead 41, and a part of the first superconducting layer 48. The second superconducting layer 49 connects the first superconducting layer 48 and the superconductivity of the first lead 41, so that the Josephson junction formed at the second lead 42 by the second lead 42, the oxide layer 47, and the first superconducting layer 48 can be connected to a peripheral circuit.

[0078] In the schemes shown in Figures 2 and 4 above, in the process of forming an oxide layer on the surface of the second lead that is not covered by photoresist, an oxide layer may be formed first on the surfaces of the first lead and the second lead that are not covered by photoresist, and then the oxide layer on the surface of the first lead that is not covered by photoresist may be removed.

[0079] Please refer to Figure 5, which is a flow chart of a method for fabricating a Josephson junction according to one exemplary embodiment of the present application. As shown in Figure 5, the method may include the following steps:

[0080] Step 501: Form a circuit structure on a substrate by nanoimprinting.

[0081] Wherein, the above-mentioned circuit structure includes a first lead, a second lead, and a peripheral circuit connected to the first lead and the second lead respectively, and the first lead, the second lead and the peripheral circuit are an integral structure.

[0082] In one possible implementation, an extension of the first lead crosses the second lead.

[0083] In one possible implementation, forming a circuit structure on a substrate by the above-mentioned nanoimprint method includes: Forming a superconducting film layer on a substrate; Spin-coating a nanoimprint adhesive onto the superconducting film layer; imprinting a structural pattern of a circuit structure on the nanoimprint adhesive through a nanoimprint mask; Etching in the superconducting film layer based on the structure pattern; and Cleaning the nanoimprint adhesive on the substrate to obtain a circuit structure located on the substrate.

[0084] In the embodiments of the present application, the thickness of the above-mentioned superconducting film layer can be controlled to allow the superconducting film layer to meet the circuit requirements of a quantum computing device, for example, the thickness of the above-mentioned superconducting film layer can be set in the range of 80 nanometers (nm) to 120 nm.

[0085] For example, in one possible implementation of the embodiments of the present application, the thickness of the above-mentioned superconducting film layer may be 100 nanometers.

[0086] For example, in the embodiments of the present application, a deposition apparatus can be used to deposit a superconducting material (e.g., aluminum) onto a substrate, and by controlling factors such as deposition time and superconducting film layer growth rate, the thickness of the superconducting film layer can be made to be approximately 100 nm.

[0087] In one possible implementation, the process of etching in the superconducting film layer according to the above-mentioned structure pattern includes: The method may include etching the superconducting film layer according to the structure pattern by dry etching.

[0088] Alternatively, in another possible implementation, etching may be performed in the superconducting film layer according to the structure pattern in the manner of wet etching.

[0089] In one possible implementation, before etching in the superconducting film layer according to the structure pattern, the nanoimprint adhesive remaining in the imprint grooves of the nanoimprint adhesive may further be removed.

[0090] First, a high-quality aluminum film with a thickness of 100 nm is grown on a sapphire or silicon base using an electron beam evaporation or molecular beam epitaxy (MBE) device. Then, a nanoimprint adhesive is spin-coated on the aluminum film. Then, a nanoimprint device and a nanoimprint mask are used to imprint the circuit structure of the quantum chip, including the readout line, resonant cavity, capacitor, etc., and the bottom layer aluminum of the Josephson junction into the adhesive. Then, a plasma adhesive removal device is used to remove the photoresist remaining in the nanoimprint adhesive groove. Finally, a pattern is formed by etching the aluminum film by dry etching or wet etching, of which the size of the structure can be more accurately controlled when dry etching is used, and the characteristics of the aluminum film structure after etching are better. After the aluminum film structure is formed by etching, the nanoimprint adhesive can be washed, and finally the result of the part (a) in FIG. 4 can be obtained. Among them, the peripheral circuit 43 represents a large circuit structure, and the line width is generally several microns to several tens of microns, and this part can be connected to circuits other than the chip by the way of leads. The first lead 41 and the second lead 42 may represent the bottom aluminum layer of a Josephson junction and may have a line width of 200 nm or less.

[0091] Among them, the above-mentioned peripheral circuits may include micron-level circuits, such as read lines, resonating chambers, and capacitors, which are relatively large in size.

[0092] Step 502: Form a photoresist undercut structure in a substrate.

[0093] Wherein, the above-mentioned undercut structure is a strip-shaped structure, and the undercut structure includes a first region, a second region and a third region whose head and tail are adjacent to each other, the first region and the second region have an upper layer photoresist and a lower layer intervening space, the second region is an opening region of the undercut structure, the first region covers an end of the first lead, the second region covers a part of the second lead, and the third region is located between the first region and the second region.

[0094] Optionally, the portion of the second lead that is covered by the second region may be an end of the second lead or another portion of the second lead.

[0095] In one possible implementation, the first lead is perpendicular to the second lead, and the first lead is parallel to the undercut structure, where the first lead being parallel to the undercut structure may refer to the first lead being parallel to the extending direction (longitudinal direction) of the strip-shaped undercut structure.

[0096] In the embodiment of the present application, in order to ensure the quantum performance of the Josephson junction and reduce the difficulty of fabrication, the first lead and the second lead may be set to be perpendicular to each other.

[0097] Optionally, to meet various circuit wiring requirements, the first lead and the second lead may be non-perpendicular to each other, and correspondingly, the first lead and the undercut structure may be non-parallel to each other.

[0098] For example, refer to Fig. 6, which is a diagram showing a circuit structure and an undercut structure according to an embodiment of the present application. As shown in Fig. 6, the first lead 61 and the second lead 62 in the circuit structure form an angle of 45 degrees and do not cross each other, the undercut structure spans the first lead 61 and the second lead 62, the first region 63a (bottom cavity) and the second region 63b (bottom cavity) in the undercut structure cover the ends of the first lead 61 and the second lead 62, respectively, and there is a third region 63c between the first region 63a and the second region 63b that opens.

[0099] In one possible implementation, the undercut structure further includes a fourth region, the fourth region being an open region of the undercut structure, and the second region is located between the third region and the fourth region.

[0100] In one possible implementation, the length of the second region is greater than the length of the first region, and the portion of the second lead that is covered by the second region is located on one side of the second region closer to the third region.

[0101] For example, refer to FIG. 7, which is a diagram showing another circuit structure and undercut structure according to an embodiment of the present application. As shown in part (a) of FIG. 7, the first lead 71 and the second lead 72 in the circuit structure form a 90 degree angle, and the undercut structure includes a first region 73a (bottom hollow), a second region 73b (bottom hollow), a third region 73c (opening region) and a fourth region 73d (opening region), in which the first region 73a covers the end of the first lead 71, the second region 73b covers the end of the second lead 72, and continues to extend to the left side (the other side of the first region 73a), the third region 73c is located between the first region 73a and the second region 73b, and the fourth region 73d is located on the other side of the second region 73b. In which, the end of the second lead 72 is located on one side (the left side) of the second region 73b close to the first region 73a.

[0102] In the embodiment of the present application, after completing the etching of the bottom layer aluminum, an undercut structure can be formed in the Josephson junction region by the method of electron beam exposure using electron beam photoresist, which refers to a structure in which the upper layer is photoresist and the lower layer is a cavity, as shown in part (a) of Figure 7. In this step, photolithography can be carried out by the method of two-layer adhesive of MMA (Methyl Methacrylate) and PMMA (Poly Methyl Methacrylate), and the amount of exposure agent is 150 μC / cm2 respectively. 2 and 450 μC / cm 2 7, and then a mixture of MIBK (Methyl Isobutyl Ketone) and IPA (Isopropyl Alcohol) is used for development, and IPA is used for fixing. The third and fourth regions 73c and 73d in FIG. 7 represent the portions where the photoresist is removed by development to expose the base to the environment, and the first and second regions 73a and 73b represent the undercut structure, i.e., the upper layer is photoresist and the lower layer is hollow. The undercut structure in some regions of the first and second regions 73a and 73b overlaps with the bottom aluminum layer of the Josephson junction (i.e., the ends of the two leads). The portion (b) in FIG. 7 corresponds to the side view of the portion (a) along the dotted line in FIG. 7, and the region 74 represents the stop range (boundary range) of the undercut structure, i.e., the right side from here is the complete photoresist.

[0103] Step 503: Ion etching is performed on the surfaces of the first lead and the second lead that are not covered by the photoresist.

[0104] In the embodiment of the present application, after forming the above-mentioned circuit structure, the first lead and the second lead may be exposed to the atmosphere, so that the exposed surfaces of the first lead and the second lead may undergo an oxidation reaction with oxygen in the air to generate a natural oxide layer. The natural oxide layer is usually not dense and has a relatively low insulating performance, which may affect the insulating performance of the oxide layer formed subsequently. Therefore, in the embodiment of the present application, before forming the dense oxide layer, the natural oxide layer on the surfaces of the first lead and the second lead that are not covered by the photoresist can be removed first by ion etching.

[0105] In one possible implementation, performing ion etching on the surfaces of the first lead and the second lead that are not covered by the photoresist includes: This involves keeping the ion etch tilt angle constant and rotating the substrate.

[0106] In the embodiment of the present application, the ion etching tilt angle is kept constant while the substrate is rotated, so that the ion flow can penetrate sufficiently into the undercut structure, thereby improving the effect of removing the native oxide layer on the surfaces of the first lead and the second lead.

[0107] In an embodiment of the present application, after forming the undercut structure, plasma is used to irradiate regions such as the third region 73c and the fourth region 73d at a predetermined angle (for example, a left diagonal direction in FIG. 7), and the relatively large ion etching bevel angle is controlled as much as possible while the base is controlled to rotate horizontally at a predetermined rotation speed, so that the plasma can sufficiently penetrate into the third region 73c and the fourth region 73d, which may be selected as 10 rpm, thereby allowing the plasma to uniformly and completely remove the native oxide layer on the exposed portions on the first lead 71 and the second lead 72.

[0108] Step 504: The substrate is placed in an oxidation chamber with a pure oxygen atmosphere to be oxidized.

[0109] In this step, an oxide layer can be formed on the surface of the second lead that is not covered by the photoresist.

[0110] In one possible implementation, the pressure in the oxidation chamber is 4 Torr and the oxidation time length of the substrate in the oxidation chamber is 1000 to 2000 seconds.

[0111] In the embodiment of the present application, the substrate can be oxidized in an in-situ manner (while maintaining a vacuum environment) in an oxidation chamber in a pure oxygen environment. At this time, a denser oxide layer can be obtained by setting the pressure in the oxidation chamber to about 4 Torr and the oxidation time to 1000s to 2000s, and the required resistance of the Josephson junction can be obtained by precisely controlling the pressure in the chamber and the oxidation time during oxidation.

[0112] Step 505: Obliquely evaporate a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction.

[0113] The first superconducting layer covers the area of ​​the second lead not covered by the photoresist and a portion of the substrate between the second lead and the first lead.

[0114] In one possible implementation, the deposition ramp rate of the first superconducting layer is 1 nanometer per second and the thickness of the first superconducting layer is 100 nanometers.

[0115] Please refer to FIG. 8, which is a diagram showing the result after oxidation according to an embodiment of the present application. All the superconducting film (e.g., aluminum film) exposed to oxygen can be oxidized, of which, region 81 and region 82 represent the dense aluminum oxide layer obtained after oxidation in an oxidation chamber, which is one of the key steps in the fabrication of Josephson junctions. Then, along the left diagonal direction shown in FIG. 8, a layer of aluminum film is coated on the aluminum oxide film layer represented by region 81. Of which, the coating rate can be selected as 1 nm / s, and the thickness of the aluminum film can be selected as 100 nm.

[0116] Please refer to FIG. 9, which is an effect diagram after aluminum coating according to an embodiment of the present application. As shown in FIG. 9, the aluminum-aluminum oxide-aluminum structure shown in region 91 is the obtained Josephson junction. Since the coating direction is left diagonal in the step shown in FIG. 8, not only a Josephson junction is obtained, but also a new aluminum film is coated on the base, for example, the region 92 shown in FIG. 9. In addition, by precisely controlling the coating angle, the distance between the newly coated region 92 and the region 93 (i.e., the first lead end) can be relatively close, but the region 92 does not contact the region 93, and the distance between the region 92 and the region 93 can be controlled to be on the order of hundreds of nanometers.

[0117] Step 506: Perform ion etching at an angle according to a direction from the second region to the first region.

[0118] This step makes it possible to remove the oxide layer on the surface of the first lead that is not covered by the photoresist.

[0119] In one possible implementation, the time length of the gradient ion etching from the second region to the first region is 2 minutes, and the etching power is 200 watts.

[0120] In the oxidation step as shown in step 504, when oxidation is performed in the oxidation chamber, aluminum oxide can be formed on the surface of all exposed superconducting films (e.g., aluminum films), i.e., the parts represented by region 81 and region 82 in FIG. 8, of which region 81 is for forming Josephson junctions and is a necessary part for the scheme shown in the present application, and the region represented by region 82 needs to be connected to an external circuit, so the oxide layer in this region needs to be removed, otherwise it may form a parasitic junction and affect the bit performance. Refer to FIG. 10, which is a diagram showing the removal of the oxide layer according to an embodiment of the present application. As shown in the part (a) of FIG. 10, the aluminum oxide additionally formed on the end of the first lead is removed along the direction to the lower right, i.e., the oxide layer in the part of region 1001 is removed, at this time, the irradiation time of the aluminum oxide by the plasma may be selected as 2 min, and the power may be selected as 200 W. Also, because the undercut structure shown in region 1002 is larger than the undercut structure shown in region 1003, the tilt angle of the ion beam can be controlled to achieve removal of aluminum oxide in region 1001 while also ensuring that the plasma does not affect the Josephson junction region.

[0121] In an embodiment of the present application, the above-mentioned step 506 may be performed after step 505 because when the plasma is irradiated to the region 1001, impurities may be generated and fall into the oxide layer of the junction region of the Josephson junction, which may affect the bit performance.

[0122] Optionally, the above-mentioned step 506 may be performed before step 505, thus avoiding affecting the newly coated superconducting film layer in the area 92 in FIG. 9 when the plasma is irradiated to the oxide layer in the area 1001.

[0123] Step 507: Obliquely deposit a second superconducting layer according to a direction from the second region to the first region.

[0124] The second superconducting layer covers the area of ​​the first lead not covered by the photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

[0125] In the embodiment of the present application, after the deposition of the first superconducting layer and the removal of the oxide layer on the first lead, a superconducting film (aluminum film) can be coated along a diagonally downward direction as shown in part (b) of FIG. 10. Here, the purpose of coating the aluminum film is to connect the region 1004 (first superconducting layer) and the region 1005 (the end of the first lead), and since the undercut structure shown in the region 1002 is larger than the undercut structure shown in the region 1003, the inclination angle of the ion beam can be controlled to only connect the region 1004 and the region 1005 when the aluminum film is coated, and the aluminum film is not coated on the Josephson junction region. At this time, the connection between the Josephson junction and the external circuit is completed. The coating rate of the second superconducting layer can be selected as 1 nm / s, and the thickness of the aluminum film can be selected as 100 nm.

[0126] Please refer to Fig. 11, which is a diagram showing the Josephson junction region according to the embodiment of the present application. As shown in Fig. 11, the quantum computing device obtained by the scheme shown in the embodiment of the present application has an aluminum oxide film only in the Josephson junction, and no parasitic junction exists in other regions. In addition, since the plasma is irradiated only to the base of a very small region shown in the region 1101, the impact of damage to the base on bit performance can be greatly reduced.

[0127] In summary, in the scheme shown in the embodiment of the present application, when a quantum computing device is fabricated, the peripheral circuit of the Josephson junction and the lead connecting the Josephson junction and the peripheral circuit are first formed by nanoimprinting, and the lead and the peripheral circuit are integral, so that the Josephson junction formed subsequently does not need to be additionally formed as a Josephson junction patch / Josephson junction bandage for connecting to the peripheral circuit, and then the first superconducting layer and the second superconducting layer are formed by depositing superconducting material in two oblique directions by undercut structure, in which the first superconducting layer forms a Josephson junction at the crossing with the second lead, and the second superconducting layer connects the first superconducting layer and the end of the first lead, thereby making a superconducting connection between the end of the first lead and the Josephson junction. The above scheme can avoid the introduction of parasitic junctions when fabricating a Josephson junction in a quantum computing device, thereby improving the decoherence of the quantum bit component and improving the performance of the quantum computing device.

[0128] The basic idea of ​​this application is to use nanoimprinting to form large circuit structures and bottom aluminum structures of Josephson junctions at the same time. Nanoimprinting has a resolution of several nanometers and belongs to mechanical imprinting, so large area structures can be rapidly formed by imprinting. Therefore, micron-level circuit structures and nanometer-level Josephson junctions can be made on the same mask.

[0129] 12 is a flow chart of the fabrication of a quantum computing device according to one exemplary embodiment of the present application. As shown in FIG. 12, the basic flow of the fabrication of the quantum computing device may include the following steps:

[0130] S1201: First, a nanoimprint mask is formed according to the circuit structure of the quantum chip.

[0131] S1202: Next, a nanoimprint mask is used to implement a pattern in the photoresist, which includes the readout lines, resonator chambers, capacitors and junction areas.

[0132] Nanoimprinting uses mechanical pressure to imprint a groove structure into the photoresist, so there is obvious photoresist residue at the bottom of the groove, and then a plasma adhesive removal device is used to remove the residual photoresist at the bottom of the groove.

[0133] S1203: Form circuit structures in the aluminum film by etching, including relatively large micron-level circuits such as read lines, resonator chambers, and capacitors, and relatively small nanometer-level circuits such as the bottom aluminum layer of Josephson junctions, and this step can utilize dry etching or wet etching.

[0134] S1204: Then, remove the nanoimprint photoresist, and then use e-beam photoresist to form an undercut structure by exposure in the Josephson junction area.

[0135] S1205: Because the surface of the aluminum film is very susceptible to oxidation in air, after forming the undercut structure, the coating equipment can use plasma to remove the native oxide layer on the surface of the aluminum film, and in this step, the base can be controlled to rotate at a predetermined rotation speed, so that the oxide layer removal process can be more uniform and complete.

[0136] S1206: Then, the aluminum film is oxidized in the oxidation chamber of the coating device to obtain a dense oxide layer.

[0137] S1207: Then, a layer of aluminum film is obliquely evaporated on the oxide layer to obtain a Josephson junction.

[0138] S1208: On the other side, the oxide layer is removed using plasma and a film coating is performed, allowing the Josephson junction to conduct to an external circuit.

[0139] S1209: Finally, the photoresist is washed away to obtain the quantum computing device chip.

[0140] In the scheme shown in the examples of the present application, the formation of parasitic junctions in the quantum computing device fabrication process can be avoided by forming large circuit structures and the bottom aluminum layer of Josephson junctions at once using a nanoimprint method, thereby reducing the impact on bit performance.

[0141] At present, the commonly used method for forming the bottom aluminum layer of the Josephson junction is the peeling method, but the schemes shown in the examples of this application adopt the etching method to form the bottom aluminum layer structure of the Josephson junction, which can improve the quality of quantum computing devices.

[0142] Please refer to Figure 13, which is a diagram showing a product application scenario provided in one embodiment of the present application. As shown in Figure 13, the quantum computing device product (e.g., quantum computing chip) produced in the embodiment of the present application can be used in the application scenario as shown in Figure 13, which may be a superconducting quantum computing platform, and which includes a quantum computing device 131, a dilution refrigerator 132, a control device 133 and a computer 134.

[0143] The quantum computing device 131 is a circuit that operates on a physical quantum bit, and the quantum computing device 131 may be realized as a quantum chip, for example, a superconducting quantum chip that is near absolute zero. The dilution refrigerator 132 is used to provide an absolute zero environment for the superconducting quantum chip. Among them, the above-mentioned physical quantum bit may be a Josephson junction fabricated by the method shown in the above-mentioned embodiment of the present application.

[0144] Controller 133 is used to control quantum computing device 131, and computer 134 is used to control controller 133. For example, a written quantum program is compiled into instructions by software in computer 134, and the instructions are sent to controller 133 (e.g., an electronic / microwave control system). Controller 133 converts the above-mentioned instructions into electronic / microwave control signals to input to dilution refrigerator 132, thereby controlling superconducting qubits at temperatures below 10 mK. The readout process is reversed, and the readout waveform is transmitted to quantum computing device 131.

[0145] 14 is a diagram illustrating a Josephson junction fabrication system according to one exemplary embodiment of the present application. The Josephson junction fabrication system can be implemented as a production line device. As shown in FIG. 14, the Josephson junction fabrication system includes a nanoimprint subsystem 1401, a photolithography subsystem 1402, an oxidation subsystem 1403, and a deposition subsystem 1404.

[0146] The nanoimprint subsystem 1401 is used to form a circuit structure on a substrate by a nanoimprint method, the circuit structure including a first lead, a second lead, and a peripheral circuit connected to the first lead and the second lead respectively, and the first lead, the second lead, and the peripheral circuit are an integral structure.

[0147] In one possible implementation, an extension of the first lead crosses the second lead.

[0148] Among them, the above-mentioned nanoimprint subsystem 1401 may include a spin coating device (used for spin coating nanoimprint adhesive), a nanoimprint device (used for imprinting circuit patterns), an adhesive removal device (used for removing nanoimprint adhesive), an etching device (used for etching superconducting film layer), etc.

[0149] The photolithography subsystem 1402 is used to form a photoresist undercut structure on the substrate, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper layer photoresist and a lower layer intervening space, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a portion of the second lead, and the third region being located between the first region and the second region.

[0150] Among them, the above-mentioned photolithography subsystem 1402 may include a spin coater (used for spin coating photoresist), a photolithography device (used for performing photolithography on the photoresist), a developer (used for exposing and developing the photoresist after photolithography), a cleaner (used for cleaning the remaining exposed photoresist), etc.

[0151] The oxidation subsystem 1403 is used to form an oxide layer on the surface of the second lead that is not covered by photoresist.

[0152] The oxidation subsystem 1403 described above may include an oxidation chamber.

[0153] The deposition subsystem 1404 is used to obliquely deposit a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, the first superconducting layer covering an area of ​​the second lead that is not covered by photoresist, and the first superconducting layer covering a portion of the substrate between the second lead and the first lead.

[0154] The deposition subsystem 1404 is further used to obliquely deposit a second superconducting layer according to a direction from the second region to the first region, where the second superconducting layer covers the area of ​​the first lead not covered by photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

[0155] The deposition subsystem 1404 described above may include a deposition device (used to deposit the superconducting material).

[0156] In one possible implementation, the undercut structure further includes a fourth region, the fourth region being an opening region of the undercut structure, and the second region is located between the third region and the fourth region.

[0157] In one possible implementation, the length of the second region is greater than the length of the first region, and the portion of the second lead covered by the second region is located on one side of the second region closer to the third region.

[0158] In one possible implementation, the oxidation subsystem is used to oxidize the substrate by placing it in an oxidation chamber with a pure oxygen atmosphere.

[0159] The Josephson junction fabrication system further includes an etching subsystem, which is used to remove an oxide layer on a surface of the first lead that is not covered by photoresist by performing ion etching at an angle according to a direction from the second region to the first region.

[0160] In one possible implementation, the time length of the gradient ion etching from the second region to the first region is 2 minutes, and the etching power is 200 watts.

[0161] In one possible implementation, the pressure in the oxidation chamber is 4 Torr and the oxidation time length of the substrate in the oxidation chamber is 1000 to 2000 seconds.

[0162] In one possible implementation, the etching subsystem is further used to perform ion etching on the surfaces of the first lead and the second lead that are not covered by photoresist.

[0163] In one possible implementation, the etching subsystem is used to keep the ion etching tilt angle constant and to rotate the substrate.

[0164] In one possible implementation, the deposition ramp rate of the first superconducting layer is 1 nanometer per second and the thickness of the first superconducting layer is 100 nanometers.

[0165] In one possible implementation, the first lead is perpendicular to the second lead, and the first lead is parallel to the undercut structure.

[0166] In one possible implementation, the nanoimprint subsystem 1401 includes: forming a superconducting film layer on the substrate; spin-coating the superconducting film layer with a nanoimprint adhesive; imprinting a structural pattern of the circuit structure on the nanoimprint adhesive using a nanoimprint mask; Etching the superconducting film layer based on the structural pattern; and The nanoimprint adhesive on the substrate is washed away and used to obtain the circuit structure located on the substrate.

[0167] In one possible realization, the thickness of the superconducting film layer is 100 nanometers.

[0168] In one possible implementation, the nanoimprint subsystem 1401 is used to etch the superconducting film layer according to the structure pattern in a dry etching manner.

[0169] In one possible implementation, the nanoimprint subsystem 1401 is further used to remove the nanoimprint adhesive remaining in the imprint grooves of the nanoimprint adhesive.

[0170] Optionally, each subsystem and each device in the subsystem may be spatially connected via a conveyor belt, or the movement of the workpiece between each device may be completed by a robotic arm or the like.

[0171] Optionally, the Josephson junction fabrication system further includes a memory adapted to store at least one computer instruction, and the processor executes the at least one computer instruction to cause the Josephson junction fabrication system to realize the Josephson junction fabrication method described above.

[0172] In summary, in the scheme shown in the embodiment of the present application, when a quantum computing device is fabricated, the peripheral circuit of the Josephson junction and the lead for connecting the Josephson junction to the peripheral circuit are first formed by nanoimprinting, and the lead and the peripheral circuit are integral, so that the Josephson junction to be subsequently fabricated does not need to be additionally formed as a Josephson junction patch / Josephson junction bandage for connecting to the peripheral circuit, and then the first superconducting layer and the second superconducting layer are formed by respectively depositing superconducting material in two oblique directions by undercut structure, in which the first superconducting layer forms a Josephson junction at the crossing with the second lead, and the second superconducting layer is connected to the first superconducting layer and the end of the first lead, thereby making a superconducting connection between the end of the first lead and the Josephson junction. When the Josephson junction in the quantum computing device is fabricated by the above scheme, the introduction of parasitic junctions can be avoided, which can improve the decoherence of the quantum bit component and improve the performance of the quantum computing device.

[0173] In one exemplary embodiment, a computer-readable storage medium is further provided having at least one computer instruction stored thereon, which, when executed by a processor in the Josephson junction fabrication system, causes the Josephson junction fabrication system to perform the Josephson junction fabrication method described above.

[0174] In an exemplary embodiment, a computer program product or computer program is further provided, the computer program product or computer program including computer instructions stored on a computer readable storage medium, the computer instructions being read by a processor of a production line equipment from the computer readable storage medium, and the processor executing the computer instructions to cause a Josephson junction fabrication system to perform the Josephson junction fabrication method described above.

[0175] Although the preferred embodiment of the present application has been described above, the present application is not limited to this embodiment, and any modification to the present application falls within the technical scope of the present application as long as it does not depart from the spirit of the present application.

Claims

1. 1. A method for making Josephson junctions performed by production line equipment, comprising: forming a circuit structure on a substrate by a nanoimprinting method, the circuit structure including a first lead, a second lead, and a peripheral circuit connected to the first lead and the second lead respectively, the first lead, the second lead, and the peripheral circuit being an integral structure; forming an undercut structure on the substrate using photoresist, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper photoresist layer and a lower photoresist layer, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a part of the second lead, and the third region being located between the first region and the second region; forming an oxide layer on the surface of the second lead that is not covered with photoresist; Obliquely evaporating a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, the first superconducting layer covering the region of the second lead not covered by photoresist, the first superconducting layer covering the substrate in the portion between the second lead and the first lead; and 11. The method of claim 10, further comprising: obliquely depositing a second superconducting layer according to a direction from the second region to the first region, the second superconducting layer covering an area of ​​the first lead not covered by photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

2. 2. The method of claim 1, The method, wherein the undercut structure further comprises a fourth region, the fourth region being an open region of the undercut structure, and the second region being located between the third region and the fourth region.

3. 3. The method of claim 2, A method according to claim 1, wherein a length of the second region is greater than a length of the first region, and a portion of the second lead covered by the second region is located on one side of the second region closer to the third region.

4. A method according to any one of claims 1 to 3, comprising: The step of forming an oxide layer on the surface of the second lead not covered with the photoresist includes: placing the substrate in an oxidation chamber in a pure oxygen atmosphere to oxidize it; The method further comprises: before the step of obliquely depositing a second superconducting layer according to a direction from the second region to the first region to obtain a Josephson junction, removing an oxide layer on a surface of the first lead that is not covered by photoresist by performing ion etching at an angle according to a direction from the second region to the first region.

5. 5. The method of claim 4, The method wherein the time length for performing the gradient ion etching according to the direction from the second region to the first region is 2 minutes and the etching power is 200 Watts.

6. 5. The method of claim 4, The method, wherein the pressure in the oxidation chamber is 4 Torr and the oxidation time length of the substrate in the oxidation chamber is 1000 to 2000 seconds.

7. A method according to any one of claims 1 to 3, comprising: before the step of forming an oxide layer on the surface of the second lead not covered with the photoresist, The method further includes performing ion etching on surfaces of the first and second leads that are not covered by the photoresist.

8. 8. The method of claim 7, The step of performing ion etching on the surfaces of the first lead and the second lead that are not covered by the photoresist includes: The method includes rotating the substrate while keeping the ion etch tilt angle constant.

9. A method according to any one of claims 1 to 3, comprising: The method of claim 1, wherein the deposition ramp rate of the first superconducting layer is 1 nanometer per second and the thickness of the first superconducting layer is 100 nanometers.

10. A method according to any one of claims 1 to 3, comprising: The method wherein an extension of the first lead intersects with the second lead.

11. 11. The method of claim 10, The method, wherein the first lead is perpendicular to the second lead and the first lead is parallel to the undercut structure.

12. A method according to any one of claims 1 to 3, comprising: The step of forming a circuit structure on a substrate by nanoimprinting includes: forming a superconducting film layer on the substrate; spin-coating the superconducting film layer with a nanoimprint adhesive; imprinting a structural pattern of the circuit structure into the nanoimprint adhesive through a nanoimprint mask; Etching the superconducting film layer based on the structure pattern; and cleaning the nanoimprint adhesive on the substrate to obtain the circuit structure located on the substrate.

13. 13. The method of claim 12, The method of claim 1, wherein the superconducting film layer has a thickness of 100 nanometers.

14. 13. The method of claim 12, The step of etching the superconducting film layer based on the structure pattern includes: The method includes a step of etching the superconducting film layer based on the structural pattern in a dry etching manner.

15. 13. The method of claim 12, before etching the superconducting film layer based on the structure pattern, The method further comprising removing any nanoimprint adhesive remaining in the imprint grooves of the nanoimprint adhesive.

16. 1. A system for making a Josephson junction, comprising: the system includes a nanoimprint subsystem, a photolithography subsystem, an oxidation subsystem, and a deposition subsystem; the nanoimprint subsystem is used to form a circuit structure on a substrate by a nanoimprint method, the circuit structure includes a first lead, a second lead, and a peripheral circuit connected to the first lead and the second lead, respectively, the first lead, the second lead, and the peripheral circuit being an integral structure; The photolithography subsystem is used to form an undercut structure by photoresist on the substrate, the undercut structure being a strip-like structure, the undercut structure including a first region, a second region and a third region adjacent to each other, the first region and the second region having an upper photoresist layer and a lower photoresist layer, the second region being an opening region of the undercut structure, the first region covering an end of the first lead, the second region covering a part of the second lead, and the third region being located between the first region and the second region; the oxidation subsystem is used to form an oxide layer on the surface of the second lead that is not covered by the photoresist; the deposition subsystem is used to obliquely deposit a first superconducting layer according to a direction from the first region to the second region to obtain a Josephson junction, the first superconducting layer covering an area of ​​the second lead not covered by photoresist, the first superconducting layer covering a portion of the substrate between the second lead and the first lead; The deposition subsystem is further used to obliquely deposit a second superconducting layer according to a direction from the second region to the first region, the second superconducting layer covering an area of ​​the first lead not covered by photoresist, a portion of the substrate between the second lead and the first lead, and a portion of the first superconducting layer.

17. 17. The system of claim 16, the undercut structure further comprises a fourth region, the fourth region being an open region of the undercut structure, and the second region being located between the third region and the fourth region.

18. 18. The system of claim 17, A system, wherein a length of the second region is greater than a length of the first region, and a portion of the second lead covered by the second region is located on one side of the second region closer to the third region.

19. A system according to any one of claims 16 to 18, comprising: the oxidation subsystem is used to oxidize the substrate by placing it in an oxidation chamber in a pure oxygen atmosphere; The Josephson junction fabrication system further includes an etching subsystem, the etching subsystem being used to perform ion etching at an angle according to a direction from the second region to the first region to remove an oxide layer on a surface of the first lead that is not covered by photoresist.

20. 20. The system of claim 19, The system has a time length for performing gradient ion etching according to a direction from the second region to the first region of 2 minutes and an etching power of 200 watts.

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