Display device

Abstract

In this display device comprising an organic EL element OLED, a p-channel type switching transistor T8 having a conductive terminal connected to a channel region of a p-channel type driving transistor T4 is provided. Accordingly, when a white image is displayed on the display device, a hole trapped at a trap level of the channel region of the p-channel type driving transistor T4 is extracted through the switching transistor T8 to an initialization line Vini. As a result, since driving current corresponding to a data voltage flows through the driving transistor T4, a residual image would not be visually recognized even if a gray image is displayed in an immediately subsequent frame.

Description

[Technical field]

[0001] The following disclosure relates to a display device, and more specifically to a display device including a light-emitting display element such as an organic EL element that is driven by a current. [Background technology]

[0002] In recent years, organic electroluminescence (EL) display devices have been attracting attention as a display device with features such as a thin shape, high image quality, and low power consumption, replacing liquid crystal display devices, and their development is currently underway. On the display panel of an EL display device, multiple pixel circuits are arranged in a matrix. An image is displayed on the display panel by the organic EL elements contained in each pixel circuit turning on and off with a brightness corresponding to the input data signal.

[0003] However, for example, if an image with a large difference in brightness between light and dark, such as a checkerboard pattern, continues to be displayed on a display panel, the viewer may see the originally displayed image as an afterimage when the next screen is displayed. When the brightness of the image changes from white to gray, the current value flowing through the drive transistor in gray display becomes smaller than the current value that should flow due to carriers trapped in the trap level of the interface between the channel region and the gate insulating film of the drive transistor and the crystal grain boundary during white display. As a result, there is a problem that the brightness of the displayed image decreases, and the viewer sees it as an afterimage.

[0004] In the display device disclosed in Patent Document 1, when a data signal representing a high-luminance (white display) image is written to the pixel circuit in the immediately preceding frame, the driving transistor Driving TFT as Carriers flowing through the gate insulating film may be trapped in the gate insulating film, and the trapped carriers may cause the threshold voltage of the driving TFT to fluctuate. In this case, a current with a value different from the current value for displaying the image to be displayed in the next frame is supplied to the driving TFT. TFT This causes an afterimage.

[0005] Therefore, in Patent Document 1, before a data signal is written, the potential of the gate of the driving TFT is increased to pull the carriers trapped in the gate insulating film from the gate insulating film to the source or drain, thereby initializing the electrical characteristics of the driving TFT and suppressing the occurrence of afterimages. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2006-251455 Summary of the Invention [Problem to be solved by the invention]

[0007] However, the display device described in Patent Document 1 requires control of the precharge transistor and control for increasing the potential of the storage capacitance line, which results in a complex circuit configuration.

[0008] Therefore, an object of the present application is to provide a display device that suppresses the occurrence of afterimages by discharging carriers trapped in the trap level of a channel region during a light emission period in which an organic EL element emits light, without complicating the circuit configuration. [Means for solving the problem]

[0009] In one aspect, there is provided a display device including a plurality of data lines for providing a data signal representing an image to be displayed, a plurality of scanning lines intersecting the plurality of data lines, a plurality of pixel circuits respectively disposed at intersections of the plurality of data lines and the plurality of scanning lines, and a constant voltage supply line for supplying a predetermined voltage to each pixel circuit, Each pixel circuit is corresponding to any one of the plurality of data lines and any one of the plurality of scanning lines; a light-emitting display element that emits light with a luminance corresponding to an amount of current supplied thereto; a capacitance element; a drive transistor having a control terminal connected to one end of the capacitance element and controlling an amount of current supplied to the light-emitting display element in accordance with a voltage written to the capacitance element; and a switching transistor having a first conduction terminal connected to a channel region of the drive transistor and a second conduction terminal connected to the constant voltage supply line; When a corresponding scanning line is active, the voltage of the corresponding data line is applied to the control terminal of the drive transistor and written to the capacitive element, and the switching transistor is configured to be turned on at least when a voltage corresponding to the maximum or minimum display brightness is applied to the control terminal of the drive transistor. Effect of the Invention

[0010] According to one aspect, one conductive terminal of the switching transistor is connected to a channel region of the driving transistor that supplies a driving current to the light-emitting display element, and the other conductive terminal is connected to a voltage supply line. When a large current is passed through the driving transistor in order to display an image with high brightness in such a pixel circuit, carriers are trapped in the trap level of the channel region. At this time, if the switching transistor is also set to be turned on, the carriers trapped in the trap level of the driving transistor are released by the electric field of the voltage supply line. The released carriers are extracted to the voltage supply line through the switching transistor, so that the number of carriers trapped in the channel region decreases. Therefore, the driving current flowing through the driving transistor is no longer affected by the trapped carriers, and a current corresponding to the data signal is supplied to the light-emitting display element. As a result, when a data signal for displaying an image with lower brightness in the next frame is given to an area in which an image with high brightness was displayed in the current frame, an image with the original brightness corresponding to the data signal is displayed. As a result, an afterimage displayed as an image with lower or higher brightness than the brightness corresponding to the data signal is not visible. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a pixel circuit used in basic studies. [Diagram 2] 1 is a block diagram showing an overall configuration of an organic EL display device according to a first embodiment. [Diagram 3] 1 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a first embodiment. [Figure 4] 4 is a diagram showing a layout pattern of a driving transistor and a switching transistor of the pixel circuit shown in FIG. 3 and their vicinity. FIG. [Diagram 5] 5A and 5B are cross-sectional views of the layout pattern shown in FIG. 4, more specifically, (A) is a cross-sectional view of a drive transistor taken along the arrow line A-A' shown in FIG. 4, and (B) is a cross-sectional view of a switching transistor taken along the arrow line B-B' shown in FIG. 4. [Figure 6] 4 is a timing chart showing an operation of the pixel circuit shown in FIG. 3 when a white display voltage is written to the pixel circuit. [Figure 7] 4 is a timing chart showing an operation of the pixel circuit shown in FIG. 3 when a black display voltage is written to the pixel circuit. [Figure 8] 1 is a diagram showing a channel region of a drive transistor and a band of a switching transistor having an n-type source region connected to the channel region. [Figure 9] 1 is a diagram showing a channel region of a drive transistor and a band of a switching transistor having a p-type source region connected to the channel region. [Figure 10] FIG. 11 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a second embodiment. [Figure 11] 11 is a plan view showing a layout pattern of a driving transistor and a switching transistor of the pixel circuit shown in FIG. 10 and their vicinity. [Figure 12]12A and 12B are cross-sectional views of the layout pattern shown in FIG. 11, and more specifically, (A) is a cross-sectional view of a driving transistor along the arrow line A-A' shown in FIG. 11, and (B) is a cross-sectional view of a switching transistor along the arrow line C-C' shown in FIG. 11. [Figure 13] FIG. 11 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a third embodiment. [Figure 14] 14 is a plan view showing a layout pattern of a driving transistor, a switching transistor, and the switching transistors and their vicinities in the pixel circuit shown in FIG. 13. [Figure 15] These are cross-sectional views of the layout pattern shown in Figure 14, and more specifically, (A) is a cross-sectional view of the drive transistor T4 taken along the arrow line A-A' shown in Figure 14, (B) is a cross-sectional view of the switching transistor taken along the arrow line B-B' shown in Figure 14, and (C) is a cross-sectional view of the switching transistor taken along the arrow line C-C' shown in Figure 14. [Figure 16] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a fourth embodiment. [Figure 17] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a fifth embodiment. [Figure 18] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a sixth embodiment. [Figure 19] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to a seventh embodiment. [Figure 20] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit included in an organic EL display device according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Before describing each embodiment of the present invention, a basic study will be given on the configuration of a pixel circuit equipped with an internal compensation circuit and the reason why an afterimage occurs. In this specification, unless otherwise specified, "connection" means "electrically connected state" and includes not only direct connection but also indirect connection within the scope of the present invention.

[0013] <1. Basic study> <1.1 Pixel circuit configuration> The configuration of a pixel circuit 15 having an internal compensation circuit arranged in a display panel of a conventional organic EL display device will be described. FIG. 1 is a circuit diagram showing the configuration of a pixel circuit 15 arranged in a display panel 10. As shown in FIG. 1, the pixel circuit 15 includes one organic EL element OLED, seven p-channel transistors T1 to T7, and one storage capacitor Cst (also called a "capacitor"). More specifically, the pixel circuit 15 includes a first initialization transistor T1, a compensation transistor T2, a writing transistor T3, a driving transistor T4, a power supply transistor T5, a light emission control transistor T6, and a second initialization transistor T7.

[0014] The driving transistor T4 has a gate terminal (also called a "control terminal"), a first conduction terminal, and a second conduction terminal. The first conduction terminal of the driving transistor T4 is a conduction terminal connected to an H-level power supply line ELVDD (also called a "voltage supply line", "positive voltage supply line" or "high voltage supply line") via a power supply transistor T5, and the second conduction terminal is a conduction terminal connected to an organic EL element OLED via a light emission control transistor T6. In the driving transistor T4, when holes, which are carriers, flow from the first conduction terminal to the second conduction terminal, the first conduction terminal becomes a source terminal, and the second conduction terminal becomes a drain terminal.

[0015] The substrate on which the pixel circuits 15 are formed is provided with scanning lines Sj (an integer of 1≦j≦n), previous scanning lines Sj-1 (also called "discharge lines"), emission lines Ej, data lines Di (an integer of 1≦i≦m), H-level power lines ELVDD, L-level power lines ELVSS (also called "constant voltage supply lines", "negative voltage supply lines" or "low voltage supply lines"), and initialization lines Vini (also called "constant voltage supply lines"). The write transistor T3 has a gate terminal connected to the scanning lines Sj and a source terminal connected to the data lines Di, and supplies a data signal supplied to the data lines Di to the first conduction terminal of the drive transistor T4 in response to the selection of the scanning lines Sj.

[0016] A first conductive terminal of the driving transistor T4 is connected to a drain terminal of the writing transistor T3, and a gate terminal of the driving transistor T4 is connected to a node N_G. The node N_G is a node where a second conductive terminal of a compensation transistor T2 (described later) and a first terminal of a storage capacitor Cst are connected, and the storage capacitor Cst is charged by the voltage of a data signal applied to the node N_G. The driving transistor T4 supplies, to the organic EL element OLED, a driving current determined by a voltage (also called a "data voltage") corresponding to the data signal charged in the storage capacitor Cst. Note that charging the storage capacitor Cst with the data voltage as described above means "writing the data voltage to the storage capacitor Cst" or "writing the data voltage to the node N_G".

[0017] The compensation transistor T2 is provided between the gate terminal and the second conduction terminal of the driving transistor T4. The gate terminal of the compensation transistor T2 is connected to the scanning line Sj. When the scanning line Sj becomes active, the compensation transistor T2 is turned on and the driving transistor T4 is diode-connected. As a result, the potential Vng of the node N_G becomes lower than the data voltage by the absolute value |Vth| of the threshold voltage of the driving transistor T4, as shown in the following equation (1). The potential Vng of the node N_G is applied to the gate terminal of the driving transistor T4 as a gate voltage. Vng = Vdata - |Vth| … (1) Here, Vdata is the data voltage, Vth is the threshold voltage of the driving transistor T4, Vth<0 for a p-channel transistor, and Vth>0 for an n-channel transistor.

[0018] The first initialization transistor T1 has a gate terminal connected to the previous scanning line Sj-1 and is provided between the gate terminal of the driving transistor T4 and the initialization line Vini. When the previous scanning line Sj-1 becomes active, the first initialization transistor T1 becomes conductive and initializes the potential Vng of the node N_G by providing an initialization potential Vini to the node N_G. This provides the initialization potential Vini to the gate terminal of the driving transistor T4. The first initialization transistor T1 and the compensation transistor T2 adopt a dual gate structure to reduce leakage current.

[0019] The power supply transistor T5 has a gate terminal connected to the emission line Ej and is provided between the H-level power line ELVDD and the first conduction terminal of the drive transistor T4. When the emission line Ej becomes active, the power supply transistor T5 becomes conductive and supplies the H-level voltage ELVDD to the first conduction terminal of the drive transistor T4.

[0020] The light emission control transistor T6 has a gate terminal connected to the emission line Ej and is provided between the drive transistor T4 and the second initialization transistor T7. The light emission control transistor T6 conducts electricity between the second conduction terminal of the drive transistor T4 and the organic EL element OLED in response to the selection of the emission line Ej. As a result, a drive current whose current value is controlled by the drive transistor T4 is supplied from the drive transistor T4 to the organic EL element OLED.

[0021] The second initialization transistor T7 has a gate terminal connected to the scan line Sj and is provided between the anode of the organic EL element OLED and the initialization line Vini. When the scan line Sj is selected, the second initialization transistor T7 provides an initialization signal DIS to the anode of the organic EL element OLED to initialize the potential of the anode.

[0022] A first terminal of the storage capacitor Cst is connected to the node N_G, and a second terminal is connected to the H-level power supply line ELVDD. The storage capacitor Cst holds the potential Vng of the node N_G when the first initialization transistor T1 and the compensation transistor T2 are turned off.

[0023] The organic EL element OLED has an anode (one end of the organic EL element OLED) connected to the second conduction terminal of the drive transistor T4 via the light emission control transistor T6, and a cathode (the other end of the organic EL element OLED) connected to the L level power supply line ELVSS. When a drive current controlled by the drive transistor T4 is supplied, the organic EL element OLED emits light with a luminance according to the current value.

[0024] <1.2 Afterimage Phenomenon> When the driving transistor T4 is a P-channel type, a white box pattern is displayed for a certain period of time on a part of the screen that is displayed in black, and then the entire screen is displayed in gray. At this time, the brightness of the area where the white box pattern was displayed becomes lower than the brightness of the surrounding gray display area. This box pattern with reduced brightness is visually recognized by the viewer as an afterimage.

[0025] The longer the white box pattern is displayed, the longer the afterimage is perceived as. For example, if the white box pattern is displayed for 60 seconds, it takes about 30 seconds for the afterimage to disappear.

[0026] It is considered that such an afterimage occurs due to the following mechanism. In the current frame displaying a white box pattern, holes are trapped in trap levels formed at the interface between the channel region 42 of the p-channel driving transistor T4 and the gate insulating film and at the grain boundaries. Even if the white box pattern displayed in the current frame is switched to a gray display in the next frame, the trapped holes are not immediately released from the trap levels and remain in the trap levels for a while. Therefore, even if a data voltage for a gray display is applied to the gate terminal of the driving transistor T4 in the next frame, the current value of the current supplied to the organic EL element OLED through the driving transistor T4 becomes smaller than the current value determined by the data voltage. As a result, the brightness of the area where the white box pattern was displayed becomes lower than the brightness of the surrounding gray display. Such a low-brightness area is visually recognized by the viewer as an afterimage until all the holes trapped in the trap levels are released.

[0027] Therefore, if the holes trapped in the trap levels present at the interface between the channel region 42 of the driving transistor T4 and the gate insulating film and at the crystal grain boundaries can be quickly released when white is displayed, the afterimage can be quickly eliminated. Therefore, in each of the first to third embodiments described below, the configuration and operation of a pixel circuit that quickly eliminates the afterimage by releasing the holes trapped in the trap levels will be described.

[0028] 2. First embodiment <2.1 Structure of organic EL display device> Fig. 2 is a block diagram showing the overall configuration of an organic EL display device according to a first embodiment. As shown in Fig. 2, the organic EL display device (also simply referred to as a "display device") includes a display panel 10, a display control circuit 20, a data line driver 30, a scanning line driver 50, and an emission line driver 60. The organic EL display device shown in Fig. 2 directly supplies data signals to each data line from the data line driver 30. In this embodiment, the data line driver 30 realizes a data line driving circuit, the scanning line driver 50 realizes a scanning line driving circuit, and the emission line driver 60 realizes a light emission control line driving circuit.

[0029] The display panel 10 is provided with m (m is an integer of 2 or more) data lines D1 to Dm and n+1 (n is an integer of 2 or more) scanning lines S0 to Sn. The display panel 10 is also provided with m×n pixel circuits 11 corresponding to intersections of the m data lines D1 to Dm and the n scanning lines S1 to Sn. Therefore, each pixel circuit 11 corresponds to any one of the m data lines D1 to Dm and any one of the n scanning lines S1 to Sn. As shown in FIG. 3 described later, each pixel circuit 11 is connected to not only the corresponding scanning line Sj but also the scanning line Sj-1 immediately preceding the corresponding scanning line Sj (1≦j≦n). In each pixel circuit 11, the corresponding scanning line Sj is used to control writing of a data voltage, and the immediately preceding scanning line Sj-1 is used to control initialization of the data voltage (initialization of the potential of a node N_G described later) (details will be described later).

[0030] The display panel 10 further includes n emission lines E1-En arranged in parallel with the n scanning lines S1-Sn as light emission control lines. The m data lines D1-Dm are arranged to intersect with the n scanning lines S1-Sn and the n emission lines E1-En, respectively, and are connected to a data line driver 30. The n scanning lines S1-Sn are connected to a scanning line driver 50. The n emission lines E1-En are connected to an emission line driver 60. The n emission lines E1-En correspond to the n scanning lines S1-Sn, respectively, and each pixel circuit 11 corresponds to one of the n emission lines E1-En.

[0031] Further, the display panel 10 is provided with a power supply line (not shown) common to each pixel circuit 11. More specifically, a power supply line (hereinafter referred to as an "H-level power supply line" and represented by the symbol ELVDD like the H-level potential) for supplying an H-level voltage ELVDD for driving an organic EL element (also referred to as an "emissive display element") described below, and a power supply line (hereinafter referred to as an "L-level power supply line" and represented by the symbol ELVSS like the L-level potential) for supplying an L-level voltage ELVSS for driving the organic EL element are provided. Furthermore, an initialization line (represented by the symbol Vini like the initialization potential) for supplying an initialization potential Vini for an initialization operation described below is provided. These potentials are supplied from a power supply circuit (not shown).

[0032] The display control circuit 20 outputs various control signals to the data line driver 30, the scanning line driver 50, and the emission line driver 60. More specifically, the display control circuit 20 outputs a data start pulse DSP, a data clock DCK, display data DA, and a latch pulse LP to the data line driver 30. The display control circuit 20 also outputs a scan start pulse SSP and a scan clock SCK to the scanning line driver 50. The display control circuit 20 further outputs an emission start pulse ESP and an emission clock ECK to the emission line driver 60.

[0033] The data line driver 30 includes an m-bit shift register, a sampling circuit, a latch circuit, m D / A converters, and the like (not shown). The shift register has m bistable circuits connected in cascade, transfers a data start pulse DSP supplied to the first stage in synchronization with a data clock DCK, and outputs a sampling pulse from each stage. Display data DA is supplied to the sampling circuit in accordance with the output timing of the sampling pulse. The sampling circuit stores the display data DA in accordance with the sampling pulse. When one row of display data DA is stored in the sampling circuit, the display control circuit 20 outputs a latch pulse LP to the latch circuit. When the latch circuit receives the latch pulse LP, it holds the display data DA stored in the sampling circuit. The D / A converters are provided corresponding to the m data lines D1 to Dm connected to the m output terminals (not shown) of the data line driver 30, respectively, convert the display data DA held in the latch circuit into a data signal which is an analog signal voltage, and output the obtained data signal to each of the data lines D1 to Dm.

[0034] The scanning line driver 50 drives n scanning lines S1 to Sn. More specifically, the scanning line driver 50 includes a shift register and a buffer (not shown). The shift register sequentially transfers a scanning start pulse SSP in synchronization with a scanning clock SCK. Scanning signals output from each stage of the shift register are sequentially supplied to the corresponding scanning lines S1 to Sn via the buffer. An active (low level in this embodiment) scanning signal collectively selects pixels made up of m pixel circuits 11 connected to the scanning line Sj.

[0035] The emission line driver 60 drives n emission lines E1 to En. More specifically, the emission line driver 60 includes a shift register and a buffer (not shown). The shift register sequentially transfers an emission start pulse ESP in synchronization with an emission clock ECK. An emission signal, which is an output from each stage of the shift register, is supplied to a corresponding emission line Ej (j=1 to n) via a buffer.

[0036] FIG. 2 shows an organic EL display device in which the scanning line driver 50 is disposed on one end side of the display panel 10 (on the left side of the display panel 10 in FIG. 2) and the emission line driver 60 is disposed on the other end side of the display panel 10 (on the right side of the display panel 10 in FIG. 2) as an example, but the arrangement of the scanning line driver 50 and the emission line driver 60 is not limited to this. For example, the scanning line driver 50 and the emission line driver 60 may be disposed on both sides of the display panel 10 to have a double-sided input structure. In addition, in order to reduce the number of output terminals of the data line driver 30, a demultiplexer unit may be provided between the data line driver 30 and each pixel circuit 11. In this case, the data line driver 30 is driven by a driving method called SSD (Source Shared Driving) in which the data signal outputted is supplied to each data line via the demultiplexer unit.

[0037] 2.2 Pixel circuit configuration The configuration of the pixel circuit 11 formed in the display panel 10 will be described. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit 11. The pixel circuit 11 shown in FIG. 3 further includes a p-channel switching transistor T8 in addition to the pixel circuit 15 shown in FIG. 1. The source terminal of the switching transistor T8 is connected to the body terminal (also referred to as "body terminal N_body") which is the channel region of the drive transistor T4, the drain terminal is connected to the initialization line Vini of a negative potential, and the gate terminal is connected to a node N_G. The other configurations of the pixel circuit 11 are the same as those of the pixel circuit 15, so their description will be omitted.

[0038] <2.3 Layout patterns near switching transistors> 4 is a diagram showing a layout pattern of the driving transistor T4 and the switching transistor T8 and their vicinity in the pixel circuit 11. In the following explanation of the layout pattern and the cross-sectional view, the terms "gate terminal", "source terminal", "drain terminal", and "body terminal" used in the above circuit explanation will be replaced with "gate electrode", "source region", "drain region", and "channel region", respectively.

[0039] As shown in FIG. 4, the semiconductor layer 40 (also referred to as the "first semiconductor layer") constituting the driving transistor T4 includes a source region 41 (also referred to as the "first source region"), a channel region 42 (also referred to as the "first channel region"), and a drain region 43 (also referred to as the "first drain region"). The source region 41 is connected to the writing transistor T3 (not shown) and the power supply transistor T5 (not shown). The drain region 43 is connected to the compensation transistor T2 (not shown) and the emission control transistor T6 (not shown), and is further connected to the anode electrode (not shown) of the organic EL element OLED via the emission control transistor T6 (not shown).

[0040] 4 from the channel region 42 (also referred to as the "first channel region") of the driving transistor T4, a semiconductor layer 80 (also referred to as the "second semiconductor layer") constituting the switching transistor T8 extends, and in the semiconductor layer 80, a source region 81 (also referred to as the "second source region"), a channel region 82 (also referred to as the "second channel region"), and a drain region 83 (also referred to as the "second drain region") are arranged in this order from the side closest to the channel region 42 of the driving transistor T4. The source region 81 of the switching transistor T8 is connected to the channel region of the driving transistor T4, and the drain region 83 is connected to the initialization line Vini.

[0041] The node N_G functions as the gate electrode of the driving transistor T4, and also functions as the first terminal of the storage capacitor Cst for charging the data voltage. The node N_G is composed of a rectangular body part BY (also called a "node body part") that covers the channel region 42 of the driving transistor T4, and a protrusion part PR that branches off from the body part BY and extends onto the channel region 82 of the switching transistor T8. The body part BY functions as a gate electrode that controls the driving current flowing through the driving transistor T4, and the protrusion part PR functions as a gate electrode that controls the current flowing through the switching transistor T8.

[0042] Conventionally, a low temperature polysilicon (LTPS) film has been used for the semiconductor layer constituting the transistor. However, in recent years, a low temperature polycrystalline oxide (LTPO) technology has been developed, which has two semiconductor layers, a low temperature polysilicon film in the lower layer and an oxide semiconductor film such as IGZO (indium gallium zinc oxide) in the upper layer. Therefore, in each embodiment described in this specification, the LTPO technology may be used instead of the low temperature polysilicon film. As a result, for example, an IGZO film is used for transistors (T1, T2, T7, etc.) that require a small leakage current, and an LTPS film is used for transistors (T3, T4, T5, T6) that require a driving capability, thereby forming a pixel circuit that achieves both of these characteristics. The semiconductor layer of the above configuration constituting the transistor is also used in each embodiment described below.

[0043] Fig. 5 is a cross-sectional view of the layout pattern shown in Fig. 4, and more specifically, Fig. 5(A) is a cross-sectional view of the driving transistor T4 taken along the arrow line A-A' shown in Fig. 4, and Fig. 5(B) is a cross-sectional view of the switching transistor T8 taken along the arrow line B-B' shown in Fig. 4. Since the driving transistor T4 is a p-channel type, as shown in Fig. 5(A), the source region 41 and the drain region 43 are p+ regions doped with p-type impurities, and the channel region 42 is an n-type region. A main body portion BY functioning as a gate electrode is formed on the channel region 42 with a gate insulating film GI sandwiched therebetween.

[0044] The switching transistor T8 is also of a p-channel type, and the source region 81 and the drain region 83 are usually formed of p-type regions doped with p-type impurities, but as shown in FIG. 5(B), the source region 81 may be an n-type region doped with n-type impurities (which may be an n+ type or intrinsic type region), and the drain region 83 may be a p+ type region doped with p-type impurities. The channel region 82 is an n-type region. The source region 81 is connected to the channel region 42 of the driving transistor T4. A protrusion PR is formed on the channel region 82, which branches off from the main body portion BY and extends across the gate insulating film GI, and functions as a gate electrode. The drain region 83 is connected to the initialization line Vini.

[0045] 2.4 Operation of pixel circuit 6 and 7 are diagrams showing timing charts illustrating the operation of pixel circuit 11. As shown in Fig. 6 and Fig. 7, the timing chart is divided into a previous frame up to time t1, a current frame from time t1 to t7, and a next frame from time t7 onwards. The current frame is further divided into an initialization period from time t1 to t2, a data writing period from time t2 to t3, and a light emission period from time t3 to t7.

[0046] In the light emission period of the previous frame, the previous scanning line Sj-1 and the scanning line Sj are at H level (high level), and the emission line Ej is at L level (low level). The level of the data voltage applied to the data line Di can take values ​​ranging from H level (VGH) (also called "black display voltage") representing a black display voltage, which is a data voltage showing the minimum display luminance, to L level (VGL) (also called "white display voltage") representing a white display voltage, which is a data voltage showing the maximum display luminance (including an M level (VGM) (also called "gray display voltage") representing a gray display voltage, which is an intermediate level between them). In this application, for the sake of simple explanation, it is assumed that the data voltage level is expressed in three levels, and a voltage close to the black display voltage is included in the H level, a voltage close to the white display voltage is included in the L level, and a voltage between the voltage close to the black display voltage and the voltage close to the white display voltage is included in the M level.

[0047] At time t1 when the frame changes from the previous frame to the current frame, the potential of the emission line Ej changes from L level to H level. This turns off the power supply transistor T5 and the light emission control transistor T6, and current does not flow to the drive transistor T4. After that, during the period until time t2, when the potential of the previous scanning line Sj-1 changes from H level to L level, the first initialization transistor T1 turns on, and the potential Vng of the node N_G becomes the initialization potential Vini. Next, when the potential of the previous scanning line Sj-1 returns from L level to H level, the first initialization transistor T1 turns off, and the potential Vng of the node N_G maintains the initialization potential Vini.

[0048] <2.4.1 When the data voltage changes from H level, M level or L level to L level> In the following, as shown in FIG. 6, a case will be described in which the data voltage changes from H level, M level, or L level to L level at time t2. At time t2, the data voltage applied to the data line Di changes from H level, M level, or L level to L level. After that, during the period until time t3, the potential of the scanning line Sj changes from H level to L level. As a result, the writing transistor T3 and the compensation transistor T2 are turned on, and the data voltage of the L level is written to the node N_G, and the threshold compensation of the driving transistor T4 is performed. Next, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off, and the potential Vng of the node N_G is expressed by the following equation. Vng = Vdata - |Vth|

[0049] Here, when a white display voltage is applied to the gate electrode of the drive transistor T4, holes are trapped in the trap level of the channel region 42. An afterimage caused by the trapped holes is visually recognized by the viewer in the next frame. However, in this embodiment, the transistor T8 turns on when the data voltage written to the node N_G becomes the L level, and the holes trapped in the trap levels at the interface between the channel region 42 and the gate insulating film and at the grain boundaries are released to the initialization line Vini via the transistor T8. As a result, the occurrence of the afterimage phenomenon caused by the trapped holes is suppressed in the next frame.

[0050] At time t3, the potential of the emission line Ej changes from H level to L level. This causes the light emission control transistor T6 and the power supply transistor T5 to turn on, and a current is supplied from the H level power supply line ELVDD through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order to the organic EL element OLED. At this time, the driving transistor T4 controls the current flowing through the power supply transistor T5 by the white display voltage Vdata(W) written to the node N_G and supplies it to the organic EL element OLED. This causes the organic EL element OLED to emit light, and the pixel circuit 11 displays a white display image. Thereafter, a current continues to flow through the organic EL element OLED until time t7, and the pixel circuit 11 continues to display a white display image.

[0051] The next frame starts at time t7. At time t7, the potential of the emission line Ej changes from L level to H level. As a result, the light emission control transistor T6 and the power supply transistor T5 are turned off, and the current is no longer supplied to the organic EL element OLED, so that the organic EL element OLED goes out. After that, in the period until time t8, the potential of the previous scanning line Sj-1 changes from H level to L level, and the first initialization transistor T1 turns on. As a result, the potential Vng of the node N_G is initialized to the initialization potential Vini. Furthermore, the potential of the previous scanning line Sj-1 returns from L level to H level, and the first initialization transistor T1 turns off. As a result, the initialization potential Vini is held at the node N_G.

[0052] At time t8, the data voltage applied to the data line Di changes from L level to M level. Thereafter, until time t9, the potential of the scanning line Sj changes from H level to L level. This turns on the write transistor T3 and the compensation transistor T2, and the M level data voltage is written to the node N_G, and the threshold compensation of the drive transistor T4 is performed.

[0053] In the conventional pixel circuit 15 shown in FIG. 1, holes are trapped in the trap level of the channel region 42 during the period from time t2 to t3 of the current frame. Since there is no mechanism for actively releasing the trapped holes, the trapped holes are difficult to release (slowly released according to a time constant on the order of msec or more) and continue to remain after time t2. Therefore, the carriers (current) induced in the channel region 42 after time t8 of the next frame are less than the carriers (current) corresponding to the M-level data voltage written to the node N_G. As a result, the viewer sees an image with reduced brightness (an afterimage).

[0054] In contrast, in the pixel circuit 11 according to the present embodiment shown in FIG. 3, the switching transistor T8 is turned on from time t2 to t7, and the holes trapped in the trap level of the channel region 42 are discharged to the initialization line Vini through the switching transistor T8. At time t8 of the next frame, carriers (current) corresponding to the M-level data voltage written to the node N_G are induced in the channel region 42. This suppresses the occurrence of an afterimage caused by the trapped holes. Next, in the period until time t9, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0055] At time t9, the potential of the emission line Ej changes from H level to L level. This turns on the power supply transistor T5 and the light emission control transistor T6, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 controls the current flowing from the H level power supply line ELVDD through the power supply transistor T5 by the data voltage for gray display written to the node N_G.

[0056] As described above, when the data voltage changes from the H level, M level, or L level to the L level at time t2, in the pixel circuit 11, the switching transistor T8 is turned on during the period from time t3 to t7 of the current frame. As a result, the holes trapped in the trap level of the channel region 42 are discharged to the initialization line Vini through the switching transistor T8. As a result, after time t8, carriers (current) corresponding to the desired M-level data voltage are induced in the channel region 42. In this way, the afterimage phenomenon is suppressed, so that the organic EL element OLED emits light with a luminance corresponding to the data voltage, and the pixel circuit 11 displays an image with a desired gray display. Since the desired current continues to flow through the organic EL element OLED thereafter, the organic EL element OLED continues to emit light with a desired luminance corresponding to the data voltage, and the pixel circuit 11 displays a gray display.

[0057] <2.4.2 When the data voltage changes from H level, M level, or L level to H level> Next, as shown in FIG. 7, a case will be described where the data voltage changes from the H level, M level, or L level to the H level at time t2. At time t2, the data voltage applied to the data line Di changes from the H level, M level, or L level to the H level. After that, during the period until time t3, the potential of the scanning line Sj changes from the H level to the L level. As a result, the writing transistor T3 and the compensation transistor T2 are turned on, and the H level data voltage is written to the node N_G, and the threshold compensation of the driving transistor T4 is performed. Next, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0058] Here, when the black display voltage is applied to the gate electrode of the driving transistor T4, the data voltage written to the node N_G becomes H level, so that the switching transistor T8 is turned off. As a result, the channel region 42 of the driving transistor T4 is separated from the initialization line Vini. In addition, in the case of the black display voltage, since the number of holes trapped in the trap level is small, even if the trapped holes are not discharged to the initialization line Vini, the residual image (reduction in brightness) due to this is hardly visible, but on the other hand, since the electrons trapped in the trap level are more prominent, the residual image (increase in brightness) due to this becomes visible. In addition, if it is only for discharging holes when the black display voltage is applied, the switching transistor T8 may be either an n-channel type or a p-channel type.

[0059] The light emission period of the current frame starts from time t3, and the potential of the emission line Ej changes from H level to L level. This turns on the power supply transistor T5 and the light emission control transistor T6, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 controls the current flowing from the H level power supply line ELLVDD through the power supply transistor T5 by the data voltage for black display written to the node N_G. This causes the organic EL element OLED to continue emitting light with a luminance according to the data voltage, and the pixel circuit 11 displays black.

[0060] The next frame starts at time t7. At time t7, the potential of the emission line Ej changes from L level to H level. As a result, the light emission control transistor T6 and the power supply transistor T5 are turned off, and the current is no longer supplied to the organic EL element OLED, so that the organic EL element OLED goes out. After that, in the period until time t8, the potential of the previous scanning line Sj-1 changes from H level to L level, and the first initialization transistor T1 turns on. As a result, the potential Vng of the node N_G is initialized to the initialization potential Vini. Furthermore, the potential of the previous scanning line Sj-1 returns from L level to H level, and the first initialization transistor T1 turns off. As a result, the initialization potential Vini is held at the node N_G.

[0061] At time t8, the data voltage applied to the data line Di changes from H level to M level. Thereafter, until time t9, the potential of the scanning line Sj changes from H level to L level. This turns on the write transistor T3 and the compensation transistor T2, and the M level data voltage is written to the node N_G, and the threshold compensation of the drive transistor T4 is performed.

[0062] In the conventional pixel circuit 15 shown in FIG. 1, electrons are trapped in the trap level of the channel region 42 during the period from time t2 to t3 of the current frame. Since there is no mechanism for actively releasing the trapped electrons, the trapped electrons are difficult to release (slowly released according to a time constant on the order of msec or more) and continue to remain after time t2. For this reason, the carriers (current) induced in the channel region 42 after time t8 of the next frame are greater than the carriers (current) corresponding to the M-level data voltage written to the node N_G. As a result, the viewer sees an image with increased brightness (an afterimage).

[0063] On the other hand, in the pixel circuit 11 according to the present embodiment shown in FIG. 3, the switching transistor T8 is turned on from time t2 to t7, but since the power supply line connected to the initialization line Vini has a negative potential, the electrons trapped in the trap level of the channel region 42 remain without being discharged. Therefore, the carriers (current) induced in the channel region 42 after time t8 of the next frame are greater than the carriers (current) corresponding to the data voltage of the M level written to the node N_G. As a result, as in the conventional pixel circuit 15, the viewer will see an image (afterimage) with increased luminance. Next, in the period until time t9, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0064] At time t9, the potential of the emission line Ej changes from H level to L level. This turns on the power supply transistor T5 and the light emission control transistor T6, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 controls the current flowing from the H level power supply line ELVDD through the power supply transistor T5 by the data voltage for gray display written to the node N_G.

[0065] As described above, when the data voltage changes from the H level, M level, or L level to the H level at time t2, in the pixel circuit 11, the switching transistor T8 is turned on during the period from time t2 to t7 of the current frame, but since the connected power supply line is the initialization line Vini, which has a negative potential, the electrons trapped in the trap level of the channel region 42 continue to remain without being discharged. As a result, from time t8 of the next frame onwards, carriers (current) larger than the carriers (current) corresponding to the desired M level data voltage are induced in the channel region 42. Since the afterimage phenomenon is not suppressed, at the moment of switching to gray display, the organic EL element OLED emits light with a luminance equal to or higher than the data voltage, and the pixel circuit 11 displays an image brighter than the desired gray display. After that, the trapped electrons are gradually released (slowly according to the time constant), so that the organic EL element OLED gradually decreases to the desired luminance corresponding to the desired M level data voltage over several tens of seconds, and finally displays the desired gray display, and the afterimage disappears.

[0066] 2.5 Operation of switching transistors <2.5.1 When a low-level white display voltage is written to node N_G> In the current frame, when the threshold voltage of the driving transistor T4 is compensated for by writing the L-level white display voltage Vdata(W) to the node N_G, holes are trapped in the trap level in the channel region of the driving transistor T4. In order to discharge the trapped holes to the initialization line Vini via the p-channel switching transistor T8, it is necessary to turn on the switching transistor T8. The condition for turning on the p-channel switching transistor T8 is as follows: Vth(T8)>Vgs Here, Vgs is the gate-source voltage of the switching transistor T8 and is expressed by the following equation. Vgs = Vng - Vbody =Vdata(W)-|Vth(T4)|-Vbody =Vdata(W)+Vth(T4)-Vbody Therefore, the condition for turning on the switching transistor T8 is as follows: Vth(T8)>Vdata(W)+Vth(T4)-Vbody…(2)

[0067] In order to turn on the switching transistor T8, the threshold voltage Vth(T4) of the drive transistor T4, the threshold voltage Vth(T8) of the switching transistor T8, and the white display voltage Vdata(W) are set to satisfy the above formula (2). An example of voltage setting is: Vdata(W)= 2V ELVDD = 4V ELVSS = -4V Voltage = 3V Vbody ≒{(ELVDD-ELVSS)―Voled} / 2 = 2.5V Vini= -3V Vth(T4) = -4V Vth(T8) = -2V If we set it as above, the left side of equation (2) becomes Vth(T8) = -2V The right hand side of equation (2) is Vdata(W)+Vth(T4)-Vbody=2V+(-4V)-(2.5V) = -4.5V which satisfies formula (2). Therefore, the switching transistor T8 turns on, and the holes trapped in the trap level in the channel region of the drive transistor T4 are discharged to the initialization line Vini via the switching transistor T8. As a result, if the current frame is white, no afterimage (white display area appears dark) occurs when the next frame is gray. However, if the threshold voltage or power supply voltage is set to a value that does not satisfy formula (2), the switching transistor T8 does not turn on, and an afterimage may occur even when white is displayed.

[0068] <2.5.2 When a high-level black voltage is written to a node> In the current frame, when the H-level black display voltage Vdata(B) is written, electrons are trapped in the trap level in the channel region of the driving transistor T4. At this time, the condition for turning on the p-channel switching transistor T8 is expressed by the following equation, similar to equation (2). Vth(T8)>Vgs Where: Vgs = Vng - Vbody =Vdata(B)-|Vth(T4)|-Vbody =Vdata(B)+Vth(T4)-Vbody Therefore, the condition for the switching transistor T8 to be turned on is as follows: Vth(T8)>Vdata(B)+Vth(T4)-Vbody…(3) An example of voltage setting is: Vdata(B) = 5V ELVDD = 4V ELVSS = -4V Voltage = 3V Vbody ≒{(ELVDD-ELVSS)―Voled} / 2 = 2.5V Vini= -3V Vth(T4) = -4V Vth(T8) = -2V If we set it as above, the left side of equation (3) becomes Vth(T8) = -2V The right hand side of equation (3) is Vdata(B)+Vth(T4)-Vbody=5V+(-4V)-(2.5V) = -1.5V This does not satisfy equation (3). Therefore, the switching transistor T8 is not turned on, and the electrons trapped in the trap level in the channel region of the driving transistor T4 are not discharged to the initialization line Vini via the switching transistor T8, but remain in the channel region of the driving transistor T4. As a result, when the current frame is displayed in black, an afterimage (the black display area appears bright) occurs when the next frame is displayed in gray.

[0069] <2.6 Band diagram for discharging holes trapped in the channel region of the drive transistor to the initialization line> Using a band diagram, it will be explained that when the drive transistor T4 is turned on and a drive current flows, holes trapped in the channel region 42 are discharged to the initialization line Vini via the switching transistor T8. Figures 8 and 9 are diagrams showing the channel region 42 of the drive transistor T4 and the bands of the switching transistor T8 connected to the channel region 42. Figure 8 is a diagram when the source region 81 of T8 is n-type, and Figure 9 is a diagram when the source region 81 of T8 is p-type.

[0070] First, a description will be given of the state when the driving transistor T4 and the switching transistor T8 are off. As shown in FIG. 8 and FIG. 9, the channel region 42 of the driving transistor T4 and the channel region 82 of the switching transistor T8 are both n-type regions, and a voltage (Vng≧Vth(T8)+Vbody) that turns off T8 is applied. At this time, the channel region of T4 does not trap holes because its Fermi level Ef is above the intrinsic Fermi level Ei. The p+ type drain region 83 contacts the n-type channel region 82 and is also connected to the initialization line Vini, which is a negative potential. Therefore, the Fermi level Ef of the drain region 83 is higher than the Fermi level Ef of the channel region by the reverse bias voltage Vini. Since the holes themselves are not trapped in the channel region 42, regardless of whether the source region 81 of T8 is n-type or p-type (in either case of FIG. 8 or FIG. 9), the holes are not discharged to the initialization line Vini via the switching transistor T8.

[0071] Next, a case where the driving transistor T4 and the switching transistor T8 are on will be described.

[0072] Since node N_G functions as the gate electrodes of drive transistor T4 and switching transistor T8, when a voltage (Vng < Vth(T8) + Vbody) that turns on T8 is applied to the gate electrodes of transistors T4 and T8, the Fermi level Ef in channel region 42 and channel region 82 becomes smaller than the intrinsic Fermi level Ei, and the conduction type reverses from n-type to p-type. Along with the bending of the band (reversal of the conduction type) at this time, holes are trapped at the trap levels near channel region 42 of T4. As shown in FIG. 8, when the source region 81 of T8 is n-type, this region becomes a potential barrier for holes, so in terms of potential, it becomes difficult for holes to flow to Vini. On the other hand, it becomes easier for holes to recombine with electrons, which are the majority carriers in the valence band of source region 81, and the holes trapped near the channel region of T4 are likely to disappear. Also, as shown in FIG. 9, when the source region of T8 is p-type, this region does not become a potential barrier for holes, so the holes trapped near the channel region of T4 flow directly to Vini and are discharged.

[0073] <2.7 Effect> According to this embodiment, in order to compensate for the threshold of drive transistor T4, when writing the white display voltage of the L level as the data voltage to node N_G, holes are trapped at the trap levels in channel region 42 of drive transistor T4. Next, during the light emission period, when the white display data voltage is applied, drive transistor T4 supplies a drive current corresponding to the data voltage to organic EL element OLED. At this time, switching transistor T8 turns on. As a result, the holes trapped at the trap levels in channel region 42 of drive transistor T4 are discharged to initialization line Vini through switching transistor T8. As a result, since there are no holes trapped at the trap levels of drive transistor T4, even when the gray display voltage is written in the next frame, a current corresponding to the written gray display data voltage value is supplied from drive transistor T4 to organic EL element OLED through emission control transistor T6. As a result, an image without afterimages can be displayed.

[0074] 3. Second embodiment <3.1 Structure of organic EL display device> The overall configuration of the organic EL display device according to the second embodiment is the same as the overall configuration of the organic EL display device according to the first embodiment shown in FIG. 2, so a block diagram and description thereof will be omitted.

[0075] <3.2 Pixel circuit configuration> The configuration of the pixel circuit 12 formed in the display panel 10 of this embodiment will be described. FIG. 10 is a circuit diagram showing the configuration of the pixel circuit 12 included in the organic EL display device according to this embodiment. The pixel circuit 12 shown in FIG. 10 is different from the pixel circuit 11 shown in FIG. 3 in that an n-channel switching transistor T9 is provided as a switching transistor instead of the p-channel switching transistor T8. The source terminal of the switching transistor T9 is connected to the channel region of the drive transistor T4, as in the case of the switching transistor T8, and the gate terminal is connected to the node N_G. However, unlike the case of the switching transistor T8, the drain terminal of the switching transistor T9 is connected to the H-level power supply line ELVDD of a positive potential. Note that other configurations of the pixel circuit 12 are the same as those of the pixel circuit 11 shown in FIG. 3, and therefore description thereof will be omitted.

[0076] <3.3 Switching transistors and layout patterns in their vicinity> Fig. 11 is a plan view showing a layout pattern of the driving transistor T4 and the switching transistor T9 and their vicinity in the pixel circuit 12. As shown in Fig. 11, the connection destinations of the source region 41 and the drain region 43 of the semiconductor layer 40 (also called the "first semiconductor layer") constituting the driving transistor T4 are the same as those in the first embodiment, and therefore the description thereof will be omitted.

[0077] A semiconductor layer 90 (also referred to as a "second semiconductor layer") that constitutes the switching transistor T9 extends downward in FIG. 11 from the channel region 42 of the driving transistor T4. The semiconductor layer 90 includes a source region 91 (also referred to as a "second semiconductor layer") that is arranged in the order from the side closest to the channel region 42 of the driving transistor T4. Second A source region 91 of the switching transistor T9 is connected to the channel region 42 of the driving transistor T4, and a drain region 93 of the switching transistor T9 is connected to the H-level power supply line ELVDD.

[0078] The node N_G functions as the gate electrode of the driving transistor T4 and also serves as the storage capacitor Cst for charging the data voltage. The first terminal of The node N_G includes a rectangular body portion BY covering the channel region 42 of the driving transistor T4, and a protrusion portion PR branching from the body portion BY and extending onto the channel region 92 of the switching transistor T9. The body portion BY functions as a gate electrode that controls the driving current flowing through the driving transistor T4, and also functions as a first terminal of the storage capacitor Cst for charging the data voltage. The protrusion portion PR functions as a gate electrode that controls the current flowing through the switching transistor T9.

[0079] Fig. 12 is a cross-sectional view of the layout pattern shown in Fig. 11, and more specifically, Fig. 12(A) is a cross-sectional view of the driving transistor T4 taken along the arrow line A-A' shown in Fig. 11, and Fig. 12(B) is a cross-sectional view of the switching transistor T9 taken along the arrow line C-C' shown in Fig. 11. Since the driving transistor T4 is a p-channel type, the cross-sectional view shown in Fig. 12(A) is the same as the cross-sectional view shown in Fig. 5(A). Therefore, a description of the driving transistor T4 will be omitted.

[0080] Unlike the switching transistor T8, the switching transistor T9 is an n-channel type transistor, and the source region 91 and the drain region 93 are usually formed of n-type regions doped with n-type impurities, but as shown in Fig. 12(B), the source region 91 may be p-type (or may be p+ type or intrinsic type), the channel region 92 may be p-type, and the drain region 93 may be n+ type. A gate electrode consisting of a protrusion PR extending from the body portion BY of the node N_G is formed on the channel region 92 of the switching transistor T9, sandwiching a gate insulating film GI. The source region 91 is connected to the channel region 42 of the drive transistor T4, and the drain region 93 is connected to the H-level power supply line ELVDD.

[0081] 3.4 Operation of pixel circuit The timing chart showing the operation of the pixel circuit is the same as that of the first embodiment shown in Figures 6 and 7. For this reason, the operation of the pixel circuit 12 according to this embodiment will be described using Figures 6 and 7.

[0082] <3.4.1 When the data voltage changes from H level, M level, or L level to H level> In the following, as shown in FIG. 7, a case where the data voltage changes from any of the H level, M level, or L level to the H level, which is a black display voltage, will be described. The operation up to time t1 is the same as that of the first embodiment, and therefore the description thereof will be omitted. At time t2, the data voltage applied to the data line Di changes from any of the H level, M level, or L level to the H level. Thereafter, during the period until time t3, the potential of the scanning line Sj changes from the H level to the L level. As a result, the writing transistor T3 and the compensation transistor T2 are turned on, and the H level data voltage is written to the node N_G, and the threshold compensation of the driving transistor T4 is performed. Next, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off, and the node N_G is expressed by the following equation, similar to the equation (1) of the first embodiment. Vng = Vdata - |Vth|

[0083] Here, when a black display voltage is applied to the gate electrode of the driving transistor T4, electrons are trapped in the trap level of the channel region 42. An afterimage caused by the trapped electrons is visually recognized by the viewer in the next frame. However, in this embodiment, the transistor T9 turns on when the data voltage written to the node N_G becomes H level, and the electrons trapped in the trap levels at the interface between the channel region 42 and the gate insulating film and at the grain boundaries are released to the H level power supply line ELVDD via the transistor T9. As a result, the occurrence of the afterimage phenomenon caused by the trapped electrons is suppressed in the next frame.

[0084] At time t3, the potential of the emission line Ej changes from H level to L level. This causes the light emission control transistor T6 and the power supply transistor T5 to turn on, and a current is supplied from the H level power supply line ELVDD through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order to the organic EL element OLED. At this time, the driving transistor T4 controls the current flowing through the power supply transistor T5 by the black display voltage Vdata(B) written to the node N_G and supplies it to the organic EL element OLED. This causes the organic EL element OLED to emit light, and the pixel circuit 11 displays a black display image. Thereafter, a current continues to flow through the organic EL element OLED until time t7, and the pixel circuit 11 continues to display a black display image.

[0085] The next frame starts at time t7. At time t7, the potential of the emission line Ej changes from L level to H level. As a result, the light emission control transistor T6 and the power supply transistor T5 are turned off, and the current is no longer supplied to the organic EL element OLED, so that the organic EL element OLED goes out. After that, in the period until time t8, the potential of the previous scanning line Sj-1 changes from H level to L level, and the first initialization transistor T1 turns on. As a result, the potential Vng of the node N_G is initialized to the initialization potential Vini. Furthermore, the potential of the previous scanning line Sj-1 returns from L level to H level, and the first initialization transistor T1 turns off. As a result, the initialization potential Vini is held at the node N_G.

[0086] At time t8, the data voltage applied to the data line Di changes from H level to M level. Thereafter, until time t9, the potential of the scanning line Sj changes from H level to L level. This turns on the write transistor T3 and the compensation transistor T2, and the M level data voltage is written to the node N_G, and the threshold compensation of the drive transistor T4 is performed.

[0087] In the conventional pixel circuit 15 shown in FIG. 1, electrons are trapped in the trap level of the channel region 42 during the period from time t2 to t3 of the current frame. Since the conventional pixel circuit 15 does not have a mechanism for actively releasing trapped electrons, the trapped electrons are difficult to release after time t2 (since they are released slowly according to a time constant on the order of msec or more) and continue to remain in the next frame and thereafter. Therefore, the carriers (current) induced in the channel region 42 after time t8 become greater than the carriers (current) corresponding to the M-level data voltage written to the node N_G. As a result, the viewer sees an image with increased brightness (an afterimage).

[0088] In contrast, in the pixel circuit 12 according to the present embodiment shown in FIG. 10, in order to turn on the switching transistor T9 from time t2 to t7, the electrons trapped in the trap level of the channel region 42 are transferred to the switching transistor T9. T9 , and is discharged to the H-level power supply line ELVDD. At time t8 of the next frame, carriers (current) corresponding to the M-level data voltage written to the node N_G are induced in the channel region 42. This suppresses the occurrence of afterimages caused by trapped electrons. Next, during the period until time t9, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0089] At time t9, the potential of the emission line Ej changes from H level to L level. This turns on the power supply transistor T5 and the light emission control transistor T6, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 controls the current flowing from the H level power supply line ELVDD through the power supply transistor T5 by the data voltage for gray display written to the node N_G.

[0090] As described above, when the data voltage changes from the H level, M level, or L level to the H level at time t2, in the pixel circuit 12, the switching transistor T9 is turned on during the period from time t2 to t7 of the current frame. As a result, the electrons trapped in the trap level of the channel region 42 are discharged to the H level power supply line ELVDD through the switching transistor T9. As a result, from time t8 onwards, carriers (current) corresponding to the desired M level data voltage are induced in the channel region 42. In this way, the afterimage phenomenon is suppressed, so that the organic EL element OLED emits light with a luminance corresponding to the data voltage, and the pixel circuit 12 displays a desired gray image. Since the desired current continues to flow through the organic EL element OLED thereafter, the organic EL element OLED continues to emit light with a desired luminance corresponding to the data voltage, and the pixel circuit 12 will be displayed in gray.

[0091] <3.4.2 When the data voltage changes from H level, M level, or L level to L level> As shown in Fig. 6, at time t2, the data voltage applied to the data line Di changes from either the H level, M level, or L level to the L level. Thereafter, during the period until time t3, the potential of the scanning line Sj changes from the H level to the L level. As a result, the writing transistor T3 and the compensation transistor T2 are turned on, so that the L level data voltage is written to the node N_G and the threshold compensation of the driving transistor T4 is performed. Next, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0092] The light emission period of the current frame starts from time t3, and the potential of the emission line Ej changes from H level to L level. This causes the power supply transistor T5 and the light emission control transistor T6 to turn on, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 is connected to the H level power supply line ELVDDThe current flowing from the node N_G through the power supply transistor T5 is controlled by the data voltage for white display written to the node N_G, so that the organic EL element OLED emits light with a brightness according to the data voltage, and the pixel circuit displays white.

[0093] When a white display voltage is applied to the gate electrode of the driving transistor T4, the data voltage written to the node N_G becomes L level, and the switching transistor T9 is turned off. As a result, the channel region 42 of the driving transistor T4 is connected to the H level power supply line ELVDD In the case of a white display voltage, the number of electrons trapped in the trap level of the channel region 42 is small, so that the trapped electrons are separated from the H-level power supply line. ELVDD Even if the discharge is not observed, the residual image caused by the discharge is hardly noticeable. However, the holes trapped in the trap level become more noticeable, and the residual image (reduction in brightness) caused by the discharge becomes noticeable.

[0094] The next frame starts at time t7. At time t7, the potential of the emission line Ej changes from L level to H level. As a result, the light emission control transistor T6 and the power supply transistor T5 are turned off, and the current is no longer supplied to the organic EL element OLED, so that the organic EL element OLED goes out. After that, in the period until time t8, the potential of the previous scanning line Sj-1 changes from H level to L level, and the first initialization transistor T1 turns on. As a result, the potential Vng of the node N_G is initialized to the initialization potential Vini. Furthermore, the potential of the previous scanning line Sj-1 returns from L level to H level, and the first initialization transistor T1 turns off. As a result, the initialization potential Vini is held at the node N_G.

[0095] At time t8, the data voltage applied to the data line Di changes from L level to M level. Thereafter, until time t9, the potential of the scanning line Sj changes from H level to L level. This turns on the write transistor T3 and the compensation transistor T2, and the M level data voltage is written to the node N_G, and the threshold compensation of the drive transistor T4 is performed.

[0096] In the conventional pixel circuit 15 shown in FIG. 1, holes are trapped in the trap level of the channel region 42 during the period from time t2 to t3 of the current frame. Since the conventional pixel circuit 15 does not have a mechanism for actively releasing the trapped holes, the trapped holes are difficult to release (slowly released according to a time constant on the order of msec or more) and continue to remain after time t2. For this reason, the carriers (current) induced in the channel region 42 after time t8 of the next frame are less than the carriers (current) corresponding to the M-level data voltage written to the node N_G. As a result, the viewer sees an image with reduced brightness (an afterimage).

[0097] On the other hand, in the pixel circuit 12 according to the present embodiment shown in FIG. 10, the switching transistor T9 is turned on from time t2 to t7, but the holes trapped in the trap level of the channel region 42 remain without being discharged because the connected power supply line is the H-level power supply line ELVDD, which is a positive potential. Therefore, the carriers (current) induced in the channel region 42 after time t8 of the next frame are less than the carriers (current) corresponding to the M-level data voltage written to the node N_G. As a result, as in the conventional pixel circuit 15, the viewer will see an image (afterimage) with reduced luminance. Next, in the period until time t9, when the potential of the scanning line Sj returns from the L level to the H level, the writing transistor T3 and the compensation transistor T2 are turned off.

[0098] At time t9, the potential of the emission line Ej changes from H level to L level. This turns on the power supply transistor T5 and the light emission control transistor T6, and a current is supplied from the H level power supply line ELVDD to the organic EL element OLED through the power supply transistor T5, the driving transistor T4, and the light emission control transistor T6 in this order. At this time, the driving transistor T4 controls the current flowing from the H level power supply line ELVDD through the power supply transistor T5 by the data voltage for gray display written to the node N_G.

[0099] As described above, when the data voltage changes from the H level, M level, or L level to the L level at time t2, in the pixel circuit 12, the switching transistor T9 is turned on during the period from time t2 to t7 of the current frame, but the holes trapped in the trap level of the channel region 42 continue to remain without being discharged because the connected power supply line is the H level power supply line ELVDD, which has a positive potential. As a result, from time t8 of the next frame onwards, carriers (current) less than the carriers (current) corresponding to the desired M level data voltage are induced in the channel region 42. Since the afterimage phenomenon is not suppressed, at the moment of switching to gray display, the organic EL element OLED emits light with a luminance equal to or lower than the data voltage, and the pixel circuit 12 displays an image darker than the desired gray display. After that, the trapped holes are gradually released (slowly according to the time constant), so that the organic EL element OLED gradually decreases to the desired luminance corresponding to the desired M level data voltage over several tens of seconds, and finally displays the desired gray display, and the afterimage disappears.

[0100] <3.5 Operation of switching transistor> <3.5.1 When a high-level black voltage is written to node N_G> In the current frame, when the threshold voltage of the driving transistor T4 is compensated for by writing the H-level black display voltage Vdata(B) to the node N_G, electrons are trapped in the trap level in the channel region of the driving transistor T4. Therefore, in order to discharge the trapped electrons to the H-level power supply line ELLVDD via the n-channel switching transistor T9, it is necessary to turn on the switching transistor T9. The condition for turning on the n-channel switching transistor T9 is as follows: Vth(T9) <Vgs Here, Vgs is the gate-source voltage of the switching transistor T9 and is expressed by the following equation. Vgs = Vng - Vbody =Vdata(B)+Vth(T4)-Vbody Therefore, the condition for turning on the switching transistor T9 is as follows: Vth(T9) <Vdata(B)+Vth(T4)-Vbody…(4)

[0101] In order to turn on the switching transistor T9, the threshold voltage Vth(T4) of the drive transistor T4, the threshold voltage Vth(T9) of the switching transistor T9, and the black display voltage Vdata(B) are set to satisfy the above formula (4). An example of voltage setting is: Vdata(B) = 5V ELVDD = 4V ELVSS = -4V Voltage = 3V Vbody ≒{(ELVDD-ELVSS)―Voled} / 2 = 2.5V Vini= -3V Vth(T4) = -4V Vth(T9) = -2V If we set it as above, the left side of equation (4) becomes Vth(T9) = -2V The right hand side of equation (4) is Vdata(B)+Vth(T4)-Vbody=5V+(-4V)-(2.5V) = -1.5V This satisfies the formula (4). Therefore, the switching transistor T9 turns on, and the electrons trapped in the trap level of the channel region of the driving transistor T4 are discharged to the H-level power supply line ELLVDD via the switching transistor T9. As a result, in an area that is displayed in black in the current frame and grayed out in the next frame, no afterimage occurs in which the black display area appears bright. However, it should be noted that in the above voltage setting example, the switching transistor T9 is a depletion-type n-channel transistor, and its threshold voltage Vth(T9) is set to -2V. If the threshold voltage and power supply voltage are not set to satisfy the formula (4), the switching transistor T9 does not turn on, and an afterimage may occur even in the case of a black display.

[0102] <3.5.2 When a low-level white display voltage is written to node N_G> In the current frame, when a white display voltage of L level is written, holes are trapped in the trap level of the channel region of the driving transistor T4. At this time, the condition for turning on the n-channel switching transistor T9 is expressed by the following equation. Vth(T9) <Vgs Where: Vgs = Vng - Vbody =Vdata(W)+Vth(T4)-Vbody Therefore, the condition for turning on the switching transistor T9 is expressed by the following equation (5), similarly to equation (4). Vth(T9) <Vdata(W)+Vth(T4)-Vbody …(5)

[0103] An example of voltage setting is: Vdata(W)= 2V ELVDD = 4V ELVSS = -4V Voltage = 3V Vbody ≒{(ELVDD-ELVSS)―Voled} / 2 = 2.5V Vini= -3V Vth(T4) = -4V Vth(T9) = -2V If we set it as above, the left side of equation (5) becomes Vth(T9) = -2V The right hand side of equation (5) is Vdata(W)+Vth(T4)-Vbody=2V+(-4V)-(2.5V) = -4.5V which does not satisfy equation (5). Therefore, the switching transistor T9 is not turned on, and the holes trapped in the trap level in the channel region of the driving transistor T4 are not discharged to the H-level power supply line ELVDD, but remain in the channel region of the driving transistor T4. For this reason, if the current frame is displayed in white, an afterimage (the white display area appears dark) occurs when the next frame is displayed in gray. However, please note that in the above voltage setting example, the switching transistor T9 is a depletion-type n-channel transistor, and its threshold voltage Vth(T9) is set to -2V.

[0104] <3.6 Effects> According to this embodiment, when a black display voltage of H level is written to the node N_G in order to compensate the threshold voltage of the driving transistor T4, electrons are trapped in the trap level of the channel region of the driving transistor T4. When the driving transistor T4 is turned on and a driving current is supplied to the organic EL element OLED, the electrons trapped in the trap level of the channel region of the driving transistor T4 are released. The released electrons are discharged to the H level power supply line ELVDD via the switching transistor T9. As a result, the electrons trapped in the trap level of the driving transistor T4 are eliminated, so that even when a gray display voltage is written in the next frame, a current according to the written data voltage value of the gray display is supplied from the driving transistor T4 to the organic EL element OLED via the light emission control transistor T6. As a result, an image without an afterimage can be displayed in the next frame.

[0105] <4. Third embodiment> The overall configuration of the organic EL display device according to the third embodiment is the same as the overall configuration of the organic EL display device according to the first embodiment shown in FIG. 2, so a block diagram and description thereof will be omitted.

[0106] 4.1 Pixel circuit configuration The configuration of the pixel circuit 13 formed in the display panel 10 of this embodiment will be described. FIG. 13 is a circuit diagram showing the configuration of the pixel circuit 13 included in the organic EL display device according to this embodiment. As shown in FIG. 13, the pixel circuit 13 includes the p-channel switching transistor T8 described in the first embodiment and the n-channel switching transistor T9 described in the second embodiment. The source terminal of the switching transistor T8 and the source terminal of the switching transistor T9 are both connected to the body terminal N_body of the drive transistor T4. The drain terminal of the switching transistor T8 is connected to the initialization line Vini, and the drain terminal of the switching transistor T9 is connected to the H-level power supply line ELVDD. In addition, the gate terminals of the switching transistors T8 and T9 are both connected to a node N_G. The other configuration of the pixel circuit 13 is as follows. Figure 3 Since the configuration of the pixel circuit 11 is the same as that of the pixel circuit 11 shown in FIG.

[0107] <4.2 Switching transistors and layout patterns in their vicinity> 14 is a plan view showing the layout pattern of the driving transistor T4, the switching transistor T8, and the switching transistor T9 and their vicinity. The semiconductor layer 40 (also called the "first semiconductor layer") constituting the driving transistor T4 is the same as in the first and second embodiments, so its description is omitted. Two semiconductor layers 80, 90 (collectively called the "second semiconductor layer") are formed extending downward from the channel region 42 of the driving transistor T4.

[0108] The switching transistor T8 has the same configuration as the p-channel switching transistor T8 described in the first embodiment, and the switching transistor T9 has the same configuration as the n-channel switching transistor T9 described in the second embodiment. For this reason, the components of the switching transistors T8 and T9 are given the same reference characters as those given in Figures 4 and 11, respectively, and their descriptions are omitted.

[0109] The node N_G includes a rectangular body part BY covering the channel region of the drive transistor T4, and a protrusion part PR extending from the body part BY onto the channel regions 82, 92 of the switching transistors T8 and T9. The tip of the protrusion part PR branches in two directions, one of which extends onto the channel region 82 of the switching transistor T8, and the other of which extends onto the channel region 92 of the switching transistor T9. These function as gate electrodes for controlling the on / off of the switching transistors T8 and T9, respectively, and discharging holes or electrons trapped in the channel region of the drive transistor T4.

[0110] FIG. 15 is a cross-sectional view of the layout pattern shown in FIG. 14. More specifically, FIG. 15(A) is a cross-sectional view of the driving transistor T4 taken along the arrow A-A' shown in FIG. 14, FIG. 15(B) is a cross-sectional view of the switching transistor T8 taken along the arrow B-B' shown in FIG. 14, and FIG. 15(C) is a cross-sectional view of the switching transistor T9 taken along the arrow C-C' shown in FIG. 14. The cross-sectional view shown in FIG. 15(A) has the same structure as the cross-sectional view of the driving transistor T4 shown in FIG. 5(A). The cross-sectional view shown in FIG. 15(B) has the same structure as the cross-sectional view of the switching transistor T8 shown in FIG. 5(B), and the cross-sectional view shown in FIG. 15(C) has the same structure as the cross-sectional view of the switching transistor T9 shown in FIG. 12(B). For this reason, the description of the structures of these transistors T4, T8, and T9 will be omitted.

[0111] 4.3 Operation of pixel circuit The timing chart showing the operation of the pixel circuit 13 is the same as the timing chart shown in Figures 6 and 7 described in the first and second embodiments. Therefore, the detailed operation of the switching transistors T8 and T9 in this embodiment is the same as the operation described in the first and second embodiments, so the description will be omitted.

[0112] <4.4 Effects> According to this embodiment, when a white display voltage of an L level is written as a data voltage to the node N_G in order to compensate for the threshold voltage of the driving transistor T4, holes are trapped in the trap level of the channel region 42 of the driving transistor T4, and the switching transistor T8 is turned on. Similarly, when a black display voltage of an H level is written as a data voltage to the node N_G, electrons are trapped in the trap level of the channel region 42 of the driving transistor T4, and the switching transistor T9 is turned on.

[0113] In this way, either the switching transistor T8 or T9 is turned on according to the data voltage (H level or L level) corresponding to the white display or the black display. Therefore, when the carriers trapped in the trap level of the channel region 42 of the driving transistor T4 in the white display are holes, they are discharged to the initialization line Vini via the switching transistor T8, and when the carriers trapped in the black display are electrons, they are discharged to the H level power supply line ELVDD via the switching transistor T9. As a result, since there are no holes or electrons trapped in the trap level of the driving transistor T4, even when a gray display voltage is written in the next frame, a current according to the written data voltage value of the gray display is supplied to the organic EL element OLED. As a result, in the next frame, the influence of the carriers trapped in the trap level of the channel region 42 of the driving transistor T4 in the current frame disappears, so that when an image of the M level is displayed, an image with a luminance according to the data voltage without an afterimage can be displayed.

[0114] 5. Fourth embodiment (modification of the first embodiment) In the first to third embodiments, the gate terminals of the switching transistors T8 and T9 are both connected to the node N_G including the gate terminal of the drive transistor T4, but the p-channel switching transistor T8 is turned on when at least the lower of the data voltages (i.e., white display voltage or black display voltage) indicating the maximum or minimum display brightness is applied to the node N_G, and the n-channel switching transistor T9 is turned on when at least the higher of the data voltages (i.e., white display voltage or black display voltage) indicating the maximum or minimum display brightness is applied to the node N_G. Hereinafter, another example of an organic EL display device having such a configuration in which the p-channel switching transistor T8 is turned on when at least the lower of the data voltages indicating the maximum or minimum display brightness is applied to the node N_G will be described as a fourth embodiment.

[0115] This embodiment corresponds to a modified example of the first embodiment, and only the configuration of the pixel circuit is different from that of the first embodiment. FIG. 16 is a circuit diagram showing the configuration of a pixel circuit 14 in this embodiment. As shown in FIG. 16, the pixel circuit 14 in this embodiment has a gate terminal of a p-channel switching transistor T8 connected to a corresponding emission line Ej, and in this respect differs from the pixel circuit 11 (FIG. 3) in the first embodiment in which the gate terminal of the transistor T8 is connected to the gate terminal (node ​​N_G) of the driving transistor T4. Other configurations of the pixel circuit 14 in this embodiment are similar to those of the pixel circuit 11 in the first embodiment.

[0116] In the pixel circuit 14 in this embodiment, as shown in FIG. 6, during the light emission period, the data voltage (more precisely, the data voltage after threshold compensation) written in the storage capacitor Cst during the immediately preceding data write period, i.e., the data voltage corresponding to the luminance (display luminance) of the organic EL element OLED during the light emission period, is applied to the gate terminal (node ​​N_G) of the drive transistor T4, and the voltage of the emission line Ej connected to the gate terminal of the p-channel switching transistor T8 is at the L level. Therefore, when a voltage corresponding to the display luminance is applied to the gate terminal of the drive transistor T4, the p-channel switching transistor T8 is turned on. In this pixel circuit 14, the switching transistor T8 is turned on during the light emission period, not only when the lower voltage (white display voltage in this example) VGL of the data voltages indicating the maximum or minimum display luminance is applied to the gate terminal of the drive transistor T4, but also regardless of the value of the display luminance.

[0117] In this embodiment, similarly to the first embodiment described above, when a data voltage is written to N_G (or to the storage capacitor Cst connected to) of the driving transistor T4, the holes trapped in the trap level in the channel region of the driving transistor T4 can be discharged to the initialization line Vini via the switching transistor T8. Therefore, similarly to the first embodiment, an image without an afterimage can be displayed in the next frame.

[0118] 6. Fifth embodiment (modification of the second embodiment) Another example of an organic EL display device having the above-described configuration, including the organic EL display devices according to the first to third embodiments, in which the n-channel switching transistor T9 is turned on when at least the higher of the data voltages (i.e., the white display voltage or the black display voltage) indicating the maximum or minimum display brightness is applied to the node N_G, will be described as the fifth embodiment.

[0119] This embodiment corresponds to a modified example of the second embodiment, and only the configuration of the pixel circuit is different from that of the second embodiment. FIG. 17 is a circuit diagram showing the configuration of a pixel circuit 15 in this embodiment. As shown in FIG. 17, the pixel circuit 15 in this embodiment has a gate terminal of an n-channel switching transistor T9 connected to a corresponding scanning line Sj, and in this respect differs from the pixel circuit 12 (FIG. 10) in the second embodiment in which the gate terminal of the transistor T9 is connected to the gate terminal (node ​​N_G) of the driving transistor T4. Other configurations of the pixel circuit 15 in this embodiment are the same as those of the pixel circuit 12 in the second embodiment.

[0120] In the pixel circuit 15 in this embodiment, as shown in FIG. 7, during the light emission period, the data voltage (precisely, the data voltage after threshold compensation) written in the storage capacitor Cst during the immediately preceding data write period, i.e., the data voltage corresponding to the luminance (display luminance) of the organic EL element OLED during the light emission period, is applied to the gate terminal (node ​​N_G) of the drive transistor T4, and the voltage of the scanning line Sj connected to the gate terminal of the n-channel switching transistor T9 is at the L level. Therefore, when a voltage corresponding to the display luminance is applied to the gate terminal of the drive transistor T4, the n-channel switching transistor T9 is in the ON state. In this pixel circuit 16, the switching transistor T9 is in the ON state during the light emission period, not only when the higher voltage (black display voltage in this example) VGH of the data voltages indicating the maximum or minimum display luminance is applied to the gate terminal of the drive transistor T4, but also regardless of the value of the display luminance.

[0121] Therefore, in this embodiment, as in the above-described second embodiment, when a data voltage is written to N_G (or the storage capacitor Cst connected to) of the driving transistor T4, electrons trapped in the trap level in the channel region of the driving transistor T4 can be discharged to the H-level power supply line ELVDD via the switching transistor T9, so that an image without image retention can be displayed in the next frame, as in the second embodiment.

[0122] 7. Sixth embodiment (another modified example of the second embodiment) As a modification of the second embodiment, the gate electrode of the n-channel switching transistor T9 may be connected to the emission line instead of the protrusion PR extending from the body portion BY of the node N_G. An organic EL display device using a pixel circuit having such a configuration will be described as the sixth embodiment. Figure 18 1 is a circuit diagram showing a configuration of a pixel circuit 16 included in the organic EL display device.

[0123] In the pixel circuit 16 having the above configuration, the emission line Ej becomes H level and the switching transistor T9 is turned on in the period from time t1 to t3, as shown in the timing chart of Fig. 6 or 7. Therefore, when a data voltage is written to N_G of the driving transistor T4 in the period from time t2 to t3, the electrons trapped in the trap level of the channel region of the driving transistor T4 can be emitted to the H level power supply line ELVDD via the switching transistor T9, so that an image without an afterimage can be displayed in the next frame, as in the second embodiment.

[0124] 8. Seventh embodiment In the first to sixth embodiments, the drain terminals of the switching transistors T8 and T9 are connected to the L-level initialization line Vini and the H-level power supply line ELVDD, respectively. However, the wiring connecting these drain terminals is not limited to the above wiring, and may be any wiring that maintains H-level and L-level voltages during the light emission period or a period close to the light emission period. An example of an organic EL display device having such a configuration will be described below as the seventh embodiment.

[0125] FIG. 19 is a circuit diagram of a pixel circuit 17 according to this embodiment. The timing chart of the pixel circuit 17 is the same as the timing chart shown in FIG. 6 and FIG. 7 used in the description of the first to third embodiments, so the description will be omitted. As shown in FIG. 19, in order to sufficiently discharge carriers (holes) trapped in the driving transistor T4, it is desirable that each drain terminal is connected to a wiring functioning as a constant voltage supply line during the period from time t3, which is the start time of the light emission period, to time t7, which is the end time, or during a period close to that time. For this reason, the drain terminal of the p-channel switching transistor T8 is connected to an emission line Ej that is at an L level during the light emission period. This allows the holes trapped in the driving transistor T4 to be discharged to the emission line Ej via the switching transistor T8.

[0126] In this way, the holes trapped in the drive transistor T4 can be discharged by connecting the drain terminal of the p-channel switching transistor T8 to the emission line Ej. This makes it possible to suppress the occurrence of an afterimage even when a gray image is displayed after a white image is displayed.

[0127] <9. Eighth embodiment> Next, an example of an organic EL display device in which, instead of the H-level power supply line ELVDD, another wiring that maintains an H-level voltage during the light emission period or a period close to the light emission period is connected to the drain terminal of the n-channel switching transistor T9 will be described as the eighth embodiment.

[0128] Fig. 20 is a circuit diagram of a pixel circuit 18 according to this embodiment. The timing chart of the pixel circuit 18 is the same as the timing chart shown in Fig. 6 and Fig. 7 used in the description of the first to third embodiments, and therefore the description thereof will be omitted. As shown in Fig. 20, in order to sufficiently discharge carriers (electrons) trapped in the driving transistor T4, during the period from time t3, which is the start time of the light emission period, to time t7, which is the end time, or during a period close to that time, N-channel switching transistor T9It is preferable that the drain terminal of the n-channel switching transistor T9 is connected to a wiring that functions as a constant voltage supply line. Therefore, the drain terminal of the n-channel switching transistor T9 is connected to the scanning line Sj that is at H level during the light emission period. This allows the electrons trapped in the driving transistor T4 to be discharged to the scanning line Sj via the switching transistor T9.

[0129] In this way, the electrons trapped in the drive transistor T4 can be discharged by connecting the drain terminal of the n-channel switching transistor T9 to the scan line Sj as well, which makes it possible to suppress the occurrence of an afterimage even when a gray image is displayed after a black image is displayed.

[0130] <10.Other> In the above embodiments, the pixel circuit is described as being composed of p-channel transistors T1 to T7. However, the pixel circuit may be composed of n-channel transistors. In this case, at least one of p-channel and n-channel switching transistors is provided, as in the above embodiments. As a result, when a gray image is displayed in the next frame in an area that displayed a black or white image in the current frame, the displayed image has a luminance according to the data voltage, and no residual image is visible.

[0131] Hereinafter, a more detailed description will be given of a case where an n-channel transistor is used as the driving transistor T4 in a pixel circuit instead of a p-channel transistor. In a pixel circuit using an n-channel driving transistor T4, for example, as in the first embodiment (FIG. 3), a p-channel switching transistor T8 having a source terminal connected to the channel region of the driving transistor T4, a drain terminal connected to a negative voltage supply line such as the initialization line Vini, and a gate terminal connected to the gate terminal of the driving transistor T4 is provided, thereby obtaining the same effect as in the first embodiment. However, when the driving transistor T4 is an n-channel type, the L level of the data voltage corresponds to a black display voltage (a data voltage showing the minimum display brightness), and the H level corresponds to a white display voltage (a data voltage showing the maximum display brightness). Therefore, in this configuration, when a black display voltage of the L level is written to the pixel circuit, holes are trapped in the trap level of the channel region of the driving transistor T4, and the trapped holes are discharged to the negative voltage supply line via the switching transistor T8 during the light emission period. In addition, in a pixel circuit using an n-channel driving transistor T4, for example, in the same manner as in the second embodiment (FIG. 10), an n-channel switching transistor T9 having a source terminal connected to the channel region of the driving transistor T4, a drain terminal connected to a positive voltage supply line such as an H-level power supply line ELVDD, and a gate terminal connected to the gate terminal of the driving transistor T4 is provided, thereby obtaining the same effect as in the second embodiment. In this configuration, when an H-level white display voltage is written to the pixel circuit, electrons are trapped in the trap level of the channel region of the driving transistor T4, and the trapped electrons are discharged to the positive voltage supply line via the switching transistor T9 during the light emission period. Furthermore, in a pixel circuit using an n-channel driving transistor T4, a p-channel switching transistor T8 and an n-channel switching transistor T9 connected in the same manner as in the third embodiment are provided, thereby obtaining the same effect as in the third embodiment.

[0132] Furthermore, in each of the above embodiments, a pixel circuit of an internal compensation type is used, which is configured to write the data voltage of the data line Di to the node N_G (or to the storage capacitor Cst connected to the node N_G) via the drive transistor T4 in a diode-connected state. However, in pixel circuits of other internal compensation types or pixel circuits that do not perform internal compensation, the same effect as above can be obtained by providing a p-channel switching transistor T8 and / or an n-channel switching transistor T9 connected as in the pixel circuits of the above embodiments (see FIGS. 3, 10, 13, 18, and 19).

[0133] In addition, the features of the display device described above may be combined in any manner within the scope of the nature of the display device and the spirit of the present invention to form a display device having several features of the above embodiments and modified examples. [Explanation of symbols]

[0134] 10...Display panel 11~18…Pixel circuit T1: First initialization transistor T2: Compensation transistor T3: Write transistor T4: Drive transistor T5…Power supply transistor T6: Light-emitting control transistor T7: Second initialization transistor T8: p-channel switching transistor T9: n-channel switching transistor OLED: Organic EL element (light-emitting display element) N_G...node N_body: Body terminal (source region of switching transistor) ELVDD: High-level power supply line (voltage supply line, positive voltage supply line), High-level voltage ELVSS: L-level power supply line (voltage supply line, negative voltage supply line), L-level voltage Vini…Initialization line (negative voltage supply line) Sj...scan line (positive voltage supply line) Ej…Emission line (negative voltage supply line)

Claims

1. A display device comprising: a plurality of data lines for supplying data signals representing an image to be displayed; a plurality of scanning lines intersecting the plurality of data lines; a plurality of pixel circuits arranged to correspond to respective intersections of the plurality of data lines and the plurality of scanning lines; and a constant voltage supply line for supplying a predetermined voltage to each pixel circuit, Each pixel circuit is corresponding to any one of the plurality of data lines and any one of the plurality of scanning lines; a light-emitting display element that emits light with a luminance corresponding to an amount of current supplied thereto; a capacitance element; a drive transistor having a control terminal connected to one end of the capacitance element and controlling an amount of current supplied to the light-emitting display element in accordance with a voltage written to the capacitance element; and a switching transistor having a first conduction terminal connected to a channel region of the drive transistor and a second conduction terminal connected to the constant voltage supply line; A display device configured to apply a voltage of a corresponding data line to the control terminal of the driving transistor when a corresponding scanning line is active, to write the voltage to the capacitive element, and to turn on the switching transistor at least when a voltage corresponding to a maximum or minimum value of display brightness is applied to the control terminal of the driving transistor.

2. the driving transistor and the switching transistor are both p-channel transistors, each pixel circuit is configured to turn on the p-channel switching transistor when a voltage corresponding to a maximum value of display luminance is applied to the control terminal of the drive transistor; the constant voltage supply line is a negative voltage supply line that supplies a negative voltage, 2. The display device according to claim 1, wherein the channel region of the drive transistor is connected to the negative voltage supply line via the p-channel switching transistor.

3. the driving transistor is a p-channel transistor, and the switching transistor is an n-channel transistor; each pixel circuit is configured to turn on the n-channel switching transistor when a voltage corresponding to a minimum value of display luminance is applied to the control terminal of the drive transistor; the constant voltage supply line is a positive voltage supply line that supplies a positive voltage, 2. The display device according to claim 1, wherein the channel region of the drive transistor is connected to the positive voltage supply line via the n-channel switching transistor.

4. the driving transistor and the switching transistor are both n-channel transistors, each pixel circuit is configured to turn on the n-channel switching transistor when a voltage corresponding to a maximum value of display luminance is applied to the control terminal of the drive transistor; the constant voltage supply line is a positive voltage supply line that supplies a positive voltage, 2. The display device according to claim 1, wherein the channel region of the drive transistor is connected to the positive voltage supply line via the n-channel switching transistor.

5. the driving transistor is an n-channel transistor, and the switching transistor is a p-channel transistor; each pixel circuit is configured to turn on the p-channel switching transistor when a voltage corresponding to a minimum value of display luminance is applied to the control terminal of the drive transistor; the constant voltage supply line is a negative voltage supply line that supplies a negative voltage, 2. The display device according to claim 1, wherein the channel region of the drive transistor is connected to the negative voltage supply line via the p-channel switching transistor.

6. a positive voltage supply line that supplies a predetermined positive voltage to each pixel circuit; Each pixel circuit is a switching transistor of an n-channel type having a first conduction terminal connected to a channel region of the drive transistor and a second conduction terminal connected to the positive voltage supply line; 6. The display device according to claim 2 or 5, wherein the n-channel switching transistor is configured to be turned on when the control terminal of the drive transistor is supplied with a higher voltage of either a voltage corresponding to a maximum value or a voltage corresponding to a minimum value of display luminance.

7. 7. The display device according to claim 2, wherein holes trapped in the channel region of the drive transistor are discharged to the negative voltage supply line via the p-channel switching transistor connected to the channel region.

8. 7. The display device according to claim 3, wherein electrons trapped in the channel region of the drive transistor are discharged to the positive voltage supply line via the n-channel switching transistor connected to the channel region.

9. 7. The display device according to claim 2, wherein a control terminal of the p-channel switching transistor is connected to the control terminal of the drive transistor.

10. 7. The display device according to claim 3, wherein a control terminal of the n-channel switching transistor is connected to the control terminal of the drive transistor.

11. Further comprising a plurality of emission lines intersecting the plurality of data lines; Each emission line is active when a low-level voltage is applied, and inactive when a high-level voltage is applied. Each pixel circuit is Corresponding to any one of the plurality of emission lines, configured to allow current to be supplied to the light emitting display element when the corresponding emission line is active, and to cut off current to the light emitting display element when the corresponding emission line is inactive; 6. The display device according to claim 2, wherein a control terminal of the p-channel switching transistor is connected to the corresponding emission line.

12. Each scan line is active when it is given a low level voltage and is inactive when it is given a high level voltage.

5. The display device according to claim 3, wherein a control terminal of the n-channel switching transistor is connected to the corresponding scanning line.

13. Further comprising a plurality of emission lines intersecting the plurality of data lines; Each emission line is active when a low-level voltage is applied, and inactive when a high-level voltage is applied. Each pixel circuit is Corresponding to any one of the plurality of emission lines, configured to allow current to be supplied to the light emitting display element when the corresponding emission line is active, and to cut off current to the light emitting display element when the corresponding emission line is inactive; 5. The display device according to claim 3, wherein a control terminal of the n-channel switching transistor is connected to the corresponding emission line.

14. 7. The display device according to claim 3, wherein the positive voltage supply line is a power supply line for supplying a drive current to the light-emitting display element.

15. 7. The display device according to claim 2, wherein the negative voltage supply line is an initialization line for initializing a voltage of a control terminal of the drive transistor.

16. Each scan line is active when it is given a low level voltage and is inactive when it is given a high level voltage.

5. The display device according to claim 3, wherein in each pixel circuit, the positive voltage supply line is the corresponding scan line.

17. Further comprising a plurality of emission lines intersecting the plurality of data lines; Each emission line is active when a low-level voltage is applied, and inactive when a high-level voltage is applied. Each pixel circuit is Corresponding to any one of the plurality of emission lines, configured to allow current to be supplied to the light emitting display element when the corresponding emission line is active, and to block current supply to the light emitting display element when the corresponding emission line is inactive; 6. The display device according to claim 2, wherein in each pixel circuit, the negative voltage supply line is the corresponding emission line.

18. 18. The display device according to claim 1, wherein each pixel circuit is configured to, when the corresponding scanning line is active, put the driving transistor into a diode-connected state and to apply a voltage of the corresponding data line to the control terminal of the driving transistor via the driving transistor and write it into the capacitive element.

19. Further comprising a plurality of emission lines intersecting the plurality of data lines; Each emission line is active when a low-level voltage is applied, and inactive when a high-level voltage is applied. Each pixel circuit is Corresponding to any one of the plurality of emission lines, a first initialization transistor having a control terminal connected to the corresponding scanning line, a first conductive terminal connected to a node where the control terminal of the driving transistor and the one end of the capacitance element are connected, and a second conductive terminal connected to an initialization line that provides an initialization potential for initializing the node, the first initialization transistor being turned on during an initialization period provided before a data write period in which a voltage of the corresponding data line is written into the capacitance element to initialize the node; a write transistor having a control terminal connected to the corresponding scanning line, a first conduction terminal connected to the corresponding data line, and a second conduction terminal connected to the first conduction terminal of the drive transistor, the write transistor being turned on when the corresponding scanning line becomes active during the data write period to supply a voltage of the corresponding data line to the drive transistor; a compensation transistor having a control terminal connected to the corresponding scanning line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor, the compensation transistor being turned on when the corresponding scanning line becomes active during the data write period, causing the drive transistor to be in a diode-connected state; a power supply transistor having a control terminal connected to the corresponding emission line, a first conductive terminal connected to a power supply line for supplying a drive current to the light-emitting display element, and a second conductive terminal connected to the first conductive terminal of the drive transistor, the power supply transistor being turned off when the corresponding emission line becomes inactive during a non-light-emitting period provided to include the initialization period and the data write period, and being turned on when the corresponding emission line becomes active during a light-emitting period provided after the data write period; 2. The display device according to claim 1, further comprising: a light-emitting control transistor having a control terminal connected to the corresponding emission line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to an anode of the light-emitting display element, the light-emitting control transistor being turned off when the corresponding emission line becomes inactive during the non-light-emitting period, and being turned on when the corresponding emission line becomes active during the light-emitting period.

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