Pixel circuit, driving method thereof, and display device

Abstract

A pixel circuit and a driving method thereof are provided, which include: a light-emitting element having a first terminal and a second terminal; a driving circuit electrically connected to the first terminal of the light-emitting element and supplying power to the light-emitting element; a voltage comparator generating a pulse-width modulation signal having a duty ratio based on a data voltage and a reference voltage; an offset voltage detection circuit electrically connected to the output terminal of the voltage comparator and detecting an input offset voltage of the voltage comparator; and a data voltage compensation circuit electrically connected to the offset voltage detection circuit and compensating for the data voltage based on the detected input offset voltage.

Description

[Technical field]

[0001] The present disclosure relates to a pixel circuit, a driving method thereof, and a display device. [Background technology]

[0002] Micro light emitting diodes (LEDs) have higher efficiency, lower power consumption, and higher reliability than organic light emitting diodes (OLEDs), and are likely to become new display products in the future.

[0003] A micro LED is a type of current driving device, and its brightness is related to the current flowing through the micro LED and the illumination time or light emitting duration. The voltage comparator controls the duty ratio of a square wave signal (e.g., a pulse width modulation signal) output to the micro LED by adjusting the relative voltage relationship between the non-inverting input voltage and the inverting input voltage, thereby controlling the light emitting duration of the micro LED. The input offset voltage is an important parameter of the voltage comparator. When an input offset voltage exists (i.e., the input offset voltage is not zero), if the non-inverting input voltage of the voltage comparator deviates from the inverting input voltage of the voltage comparator by a certain value (not 0), the voltage comparator output changes from one logic level to the other logic level. Due to the existence or variation of the input offset voltage in the voltage comparator, when the same gray scale is displayed, the light emitting duration of each pixel circuit at different positions of the display panel is different, which may cause a problem of poor brightness uniformity of the display panel and affect the display. Here, the non-inverting input voltage refers to a voltage input to a non-inverting input terminal of a voltage comparator, and the inverting input voltage refers to a voltage input to an inverting input terminal of the voltage comparator. Summary of the Invention [Means for solving the problem]

[0004] The embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device.

[0005] According to a first aspect of the present disclosure, there is provided a pixel circuit including: a light-emitting element having a first terminal and a second terminal; a drive circuit electrically connected to the first terminal of the light-emitting element and supplying power to the light-emitting element; a voltage comparator generating a pulse-width modulation signal having a duty ratio based on a data voltage and a reference voltage; an offset voltage detection circuit electrically connected to an output terminal of the voltage comparator and detecting an input offset voltage of the voltage comparator; and a data voltage compensation circuit electrically connected to the offset voltage detection circuit and compensating for the data voltage based on the detected input offset voltage.

[0006] According to a second aspect of the present disclosure, there is provided a method for driving a pixel circuit including a light-emitting element having a first terminal and a second terminal, a drive circuit electrically connected to the first terminal of the light-emitting element and supplying power to the light-emitting element, a voltage comparator generating a pulse-width modulation signal having a duty ratio based on a data voltage and a reference voltage, an offset voltage detection circuit electrically connected to an output terminal of the voltage comparator and detecting an input offset voltage of the voltage comparator, and a data voltage compensation circuit electrically connected to the offset voltage detection circuit and compensating for the data voltage based on the detected input offset voltage, the method including detecting the input offset voltage of the voltage comparator during a detection period, and compensating the data voltage based on the input offset voltage during a display period to obtain a compensated data voltage. [Brief description of the drawings]

[0007] The embodiments will now be described more particularly with reference to specific embodiments illustrated in the accompanying drawings, which should be understood as merely illustrating some embodiments and not limiting the scope thereof. The embodiments will be described and interpreted with additional features and details using the accompanying drawings.

[0008] [Figure 1] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0009] [Diagram 2] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0010] [Diagram 3] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0011] [Figure 4] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0012] [Diagram 5] FIG. 4 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0013] [Figure 6] FIG. 1 is a schematic diagram of a voltage comparator VC.

[0014] [Figure 7] 7 is a diagram showing the input / output relationship of a voltage comparator VC in FIG. 6.

[0015] [Figure 8a] 1 is a voltage transfer curve of a voltage comparator at one position on a glass substrate.

[0016] [Figure 8b] 4 is a voltage transfer curve of a voltage comparator at another position on the same glass substrate.

[0017] [Figure 9a] FIG. 8a is a schematic diagram showing the input offset voltage of a voltage comparator, the voltage transfer curve of which is shown in FIG. 8a.

[0018] [Figure 9b] FIG. 8b is a schematic diagram showing the input offset voltage of the voltage comparator, the voltage transfer curve of which is shown in FIG.

[0019] [Figure 10a] FIG. 8a is an operation timing diagram when a voltage comparator is used to perform data voltage compensation, and the voltage transfer curve of the voltage comparator is shown in FIG. 8a.

[0020] [Figure 10b] FIG. 8b is an operation timing diagram when a voltage comparator is used to perform data voltage compensation, and the voltage transfer curve of the voltage comparator is shown in FIG.

[0021] [Figure 11] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0022] [Figure 12] FIG. 2 is a configuration diagram of a pixel circuit according to an embodiment of the present disclosure.

[0023] [Figure 13] 1 is a flowchart showing a method for driving a pixel circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present disclosure will be described below with reference to the drawings showing embodiments of the present disclosure. Note that these embodiments are not all embodiments, but are merely illustrative of the present disclosure. Based on the embodiments in the present disclosure, a person skilled in the art can derive other variations without creative effort, and all such variations are within the scope of the present disclosure.

[0025] As used throughout this disclosure, the terms "in one embodiment," "one embodiment," "one example," "some embodiments," or similar expressions mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, in this disclosure, the appearance of "in one embodiment," "in one embodiment," "in some embodiments," and similar expressions may refer to the same embodiment, but not necessarily all to the same embodiment, and may refer to "one or more embodiments." These may or may not include all of the embodiments disclosed. Thus, unless otherwise specified, features or elements of some embodiments can be used in several other embodiments.

[0026] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should be interpreted in their ordinary meaning as understood by those of ordinary skill in the art.

[0027] The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity, or importance. They are used merely as references to related devices, components, processes, steps, etc. Unless otherwise specified, these terms do not imply any spatial or temporal order. For example, a "first device" and a "second device" may refer to two separately formed devices or two parts or components of the same device. In some cases, for example, a "first device" and a "second device" may be the same and may be arbitrarily named. Similarly, a "first step" of a method or process may be performed before, after, or simultaneously with a "second step".

[0028] Unless otherwise expressly stated, the terms "comprises," "includes," "has," and variations thereof mean "including, but not limited to."

[0029] Unless otherwise stated, an enumerated list of items does not imply that any or all items are mutually exclusive. Unless otherwise stated, the terms "a," "one," and "the" also mean "one or more."

[0030] Terms such as "connect" or "conduct" are not restricted to a physical or mechanical connection, and may include a direct or indirect electrical connection.

[0031] The steps illustrated in the flowcharts in the figures may be executed by a computer system, such as a set of computer-executable instructions. Although a logical sequence is shown in the flowcharts, in some cases the steps shown or described may be executed in an order different from the order described herein.

[0032] The drawings in the present disclosure only relate to structures according to the present disclosure, and other structures may refer to conventional designs.

[0033] Each of the transistors used in the embodiments of the present disclosure may be a triode, a thin film transistor, a field effect transistor, or other devices having the same characteristics. In the embodiments, in order to distinguish between the two electrodes other than the control electrode of the transistor, one electrode is called a first electrode and the other electrode is called a second electrode.

[0034] In actual operation, if the transistor is triode, the control electrode may be the base, the first electrode may be the collector and the second electrode may be the emitter, or the control electrode may be the base, the first electrode may be the emitter and the second electrode may be the collector.

[0035] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source, or the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0036] A pixel circuit according to an embodiment of the present disclosure includes a light-emitting element, a drive circuit that supplies power to the light-emitting element, a voltage comparator that generates a pulse-width modulation signal having a duty ratio based on a data voltage and a reference voltage, an offset voltage detection circuit that detects an input offset voltage of the voltage comparator, and a data voltage compensation circuit that compensates for the data voltage based on the detected input offset voltage.

[0037] The pixel circuit according to an embodiment of the present disclosure may further include a data writing circuit, a switch control circuit, and a light emission control circuit.

[0038] The data write circuit is configured to control the writing of a data voltage supplied from the data line to a control terminal of the drive circuit by controlling a gate drive signal input from the gate line, and to control the potential of the control terminal of the drive circuit.

[0039] The light emission control circuit is configured to control the conduction between the second terminal of the switch control circuit and the light emitting element by controlling a light emission control signal input from the light emission control line, and to control the conduction between the control terminal of the drive circuit and a first input terminal (e.g., a non-inverting input terminal) of the voltage comparator.

[0040] The switch control circuit is configured to control conduction between a first terminal of the switch control circuit and a second terminal of the switch control circuit by controlling the potential of the control terminal of the switch control circuit.

[0041] The drive circuit is configured to control conduction between the power supply voltage terminal and the first terminal of the switch control circuit by controlling the potential of the control terminal of the drive circuit.

[0042] A second input terminal (e.g., an inverting input terminal) of the voltage comparator is electrically connected to the reference voltage terminal, and an output terminal of the voltage comparator is electrically connected to a control terminal of the switch control circuit, and the voltage comparator is configured to output a control voltage signal (e.g., a pulse width modulated signal) based on the voltage input to the first input terminal and the reference voltage input to the second input terminal.

[0043] In the pixel circuit according to an embodiment of the present disclosure, a detection period is set before a display period, and the display period includes a data writing phase. In the detection period, the offset voltage detection circuit detects an input offset voltage of the voltage comparator. In the data writing phase, the data voltage compensation circuit compensates the data voltage based on the input offset voltage to obtain a compensated data voltage. Thus, the pixel circuit according to the embodiment of the present disclosure can accurately control the on / off of the switch control circuit via the voltage comparator, and accurately adjust the light emitting time of the light emitting element.

[0044] In the embodiment of the present disclosure, after detecting the input offset voltage of the voltage comparator included in each of the pixel circuits and performing data voltage compensation for each of the pixel circuits according to the corresponding input offset voltage, when displaying the same gray scale, the light emission duration of each of the pixel circuits at different positions is the same, thereby improving the luminance uniformity of the display panel and improving the display effect.

[0045] The light emitting element may be a micro light emitting diode (micro LED).

[0046] In one embodiment of the present disclosure, the first input terminal of the voltage comparator may be a non-inverting input terminal and the second input terminal of the voltage comparator may be an inverting input terminal, or the first input terminal of the voltage comparator may be an inverting input terminal and the second input terminal of the voltage comparator may be a non-inverting input terminal.

[0047] 1, a pixel circuit according to an embodiment of the present disclosure includes a light emitting device or light emitting element EL, a drive circuit 12 that supplies power to the light emitting element, a voltage comparator VC that controls the light emitting time of the light emitting element by generating a pulse width modulation signal based on a data voltage and a reference voltage, an offset voltage detection circuit 15 that detects an input offset voltage of the voltage comparator, and a data voltage compensation circuit 16 that compensates for the data voltage based on the detected input offset voltage. The pixel circuit further includes a data writing circuit 11, a switch control circuit 13, and a light emission control circuit 14.

[0048] The data write circuit 11 is electrically connected to the gate line Gate, the data line Data, and a control terminal of the drive circuit 12. The data write circuit 11 is configured to control the writing of a data voltage supplied by the data line Data to the control terminal of the drive circuit 12 by controlling a gate drive signal input from the gate line Gate, and to control the potential of the control terminal of the drive circuit 12.

[0049] The drive circuit 12 is electrically connected to a power supply voltage terminal and a first terminal of the switch control circuit 13, and controls the conduction between the power supply voltage terminal and the first terminal of the switch control circuit 13 by controlling the potential of the control terminal of the drive circuit 12. The power supply voltage terminal is for inputting a power supply voltage VDD.

[0050] The light emission control circuit 14 is electrically connected to the light emission control line EM, the second terminal of the switch control circuit 13, the light emitting element EL, the control terminal of the drive circuit 12, and a first input terminal (e.g., non-inverting input terminal) of the voltage comparator VC. The light emission control circuit 14 is configured to control the conduction between the second terminal of the switch control circuit 13 and the light emitting element EL and to control the conduction between the control terminal of the drive circuit 12 and the first input terminal of the voltage comparator VC by controlling a light emission control signal input from the light emission control line EM.

[0051] The switch control circuit 13 is configured to control the conduction between a first terminal of the switch control circuit 13 and a second terminal of the switch control circuit 13 by controlling the potential of the control terminal thereof.

[0052] A second input terminal (e.g., an inverting input terminal) of the voltage comparator VC is electrically connected to a reference voltage terminal, and an output terminal of the voltage comparator VC is electrically connected to a control terminal of the switch control circuit 13. The voltage comparator VC outputs a control voltage signal based on the voltage of the first input terminal and a reference voltage Vref of the second input terminal. The reference voltage terminal is for inputting the reference voltage Vref.

[0053] The offset voltage detection circuit 15 is electrically connected to a first input terminal (eg, a non-inverting input terminal) of the voltage comparator VC and an output terminal of the voltage comparator VC, thereby detecting the input offset voltage of the voltage comparator VC.

[0054] The data voltage compensation circuit 16 is electrically connected to the offset voltage detection circuit 15 and the data line Data, and obtains a compensated data voltage by compensating the data voltage based on the input offset voltage, and supplies the compensated data voltage to the data line Data. For example, the data voltage compensation circuit 16 may be an application specific integrated circuit, or may include a programmable logic array, or a properly programmed microcontroller, or other hardware device that obtains a compensated data voltage based on the input offset voltage, and supplies the compensated data voltage to the data line.

[0055] In the pixel circuit shown in FIG. 1, the first input terminal of the voltage comparator VC is a non-inverting input terminal, and the second input terminal of the voltage comparator VC is an inverting input terminal, but the present disclosure is not limited thereto.

[0056] In an embodiment, the pixel circuit shown in FIG. 1 has a detection period set before a display period, and the display period includes a data writing stage and a light emitting stage which are set sequentially.

[0057] During the detection period, the offset voltage detection circuit 15 detects the input offset voltage of the voltage comparator VC. The data write circuit 11 controls the gate drive signal to disconnect the data line Data from the control terminal of the drive circuit 12. The light emission control circuit 14 controls the light emission control signal to disconnect the second terminal of the switch control circuit 13 from the light emitting element EL, and to disconnect the control terminal of the drive circuit 12 from the first input terminal of the voltage comparator VC.

[0058] In the data write stage, the data voltage compensation circuit 16 compensates the data voltage based on the input offset voltage to obtain a compensated data voltage. The data write circuit 11 writes the compensated data voltage to the control terminal of the drive circuit 12 under the control of the gate drive signal, and controls the potential of the control terminal of the drive circuit 12.

[0059] In the light emission stage, the offset voltage detection circuit 15 stops detecting the input offset voltage of the voltage comparator VC. The reference voltage terminal inputs a reference voltage Vref, and the drive circuit 12 controls the conduction between the power supply voltage terminal and the first terminal of the switch control circuit 13 by controlling the potential of the control terminal of the drive circuit 12. The light emission control circuit 14 controls the conduction between the second terminal of the switch control circuit 13 and the light emitting element EL by controlling the light emission control signal input from the light emission control line EM, and controls the conduction between the control terminal of the drive circuit 12 and the first input terminal of the voltage comparator VC. The voltage comparator VC outputs a control voltage signal based on the voltage of the first input terminal and the reference voltage Vref. The switch control circuit 13 controls the conduction between the first terminal of the switch control circuit 13 and the second terminal of the switch control circuit 13 by controlling the control voltage signal output from the voltage comparator VC, thereby controlling the light emission time of the light emitting element EL.

[0060] In the embodiment, in the light emitting step, the value of the current flowing through the light emitting element EL is related to the compensated data voltage, and the light emitting time of the light emitting element EL is Reference Voltage Related to Vref and the compensated data voltage.

[0061] In a display device including a plurality of pixel circuits according to an embodiment, after detecting the input offset voltage of the voltage comparator included in each of the pixel circuits and performing data voltage compensation for each of the pixel circuits according to the corresponding input offset voltage, when displaying the same gray scale, the light emission duration of each of the pixel circuits at different positions of the display device is the same, thereby improving the luminance uniformity of the display panel and improving the display effect.

[0062] In one embodiment, the offset voltage detection circuit may include a test voltage supply circuit and a detection circuit.

[0063] The test voltage supply circuit is configured to supply a DC test voltage to a first input terminal of the voltage comparator, and the detection circuit is configured to detect an output voltage output from an output terminal of the voltage comparator when the test voltage supply circuit supplies the DC test voltage to the first input terminal and supplies a reference voltage to the second input terminal, and obtain an input offset voltage of the voltage comparator.

[0064] In the pixel circuit shown in FIG. 2, the offset voltage detection circuit may include a test voltage supply circuit 151 and a detection circuit 152.

[0065] The test voltage supply circuit 151 is electrically connected to the non-inverting input terminal of the voltage comparator VC, and supplies a DC test voltage to the non-inverting input terminal of the voltage comparator VC.

[0066] The detection circuit 152 is electrically connected to the output terminal of the voltage comparator VC and the data voltage compensation circuit 16, and when the test voltage supply circuit 151 supplies a DC test voltage to the non-inverting input terminal and a reference voltage to the inverting input terminal, detects the output voltage output from the output terminal of the voltage comparator VC to obtain the input offset voltage of the voltage comparator, and supplies the input offset voltage to the data voltage compensation circuit 16.

[0067] The offset voltage detection circuit 15 determines the input offset voltage of the voltage comparator VC based on the output voltage of the voltage comparator VC as follows. When the output voltage of the voltage comparator VC is a predetermined voltage, the detection circuit 152 determines the voltage difference between the first input terminal of the voltage comparator VC and the second input terminal of the voltage comparator VC as the input offset voltage of the voltage comparator VC. The predetermined voltage may be (VH+VL) / 2, where VH is the high voltage output by the voltage comparator VC and VL is the low voltage output by the voltage comparator VC.

[0068] In one embodiment, the first input terminal of the voltage comparator may be a non-inverting input terminal, and the second input terminal of the voltage comparator may be an inverting input terminal, and a voltage difference between the DC test voltage (e.g., the voltage at the non-inverting input terminal) and the reference voltage (e.g., the voltage at the inverting input terminal) is within a first predetermined voltage difference range.

[0069] In one embodiment, the first input terminal of the voltage comparator may be an inverting input terminal, and the second input terminal of the voltage comparator may be a non-inverting input terminal. A voltage difference between the reference voltage and the DC test voltage is within a second predetermined voltage difference range.

[0070] In one example, the first predetermined voltage difference range and the second predetermined voltage difference range may be in the range of −2V to 2V, although the present disclosure is not limited thereto.

[0071] In one embodiment, the test voltage supply circuit may include a voltage supply switching subcircuit configured to control conduction between the test voltage terminal and the first input terminal of the voltage comparator under control of a test control signal input from the test control terminal.

[0072] The voltage supply switching subcircuit controls whether or not a DC test voltage is output to the first input terminal of the voltage comparator.

[0073] The voltage supply switching subcircuit may include a voltage supply switching transistor having a control electrode electrically connected to the test control terminal, a first electrode of the voltage supply switching transistor electrically connected to the test voltage terminal, and a second electrode of the voltage supply switching transistor electrically connected to the first input terminal of the voltage comparator.

[0074] In one embodiment, the test voltage supply circuit may further include a voltage supply sub-circuit for supplying a DC test voltage to the test voltage terminal.

[0075] In one embodiment, the detection circuit may include a detection switching subcircuit that controls conduction between the output terminal of the voltage comparator and the readout line under control of a detection switching control signal input from a detection switching control terminal.

[0076] The sense switching sub-circuit may include a sense switching transistor, a control electrode of the sense switching transistor electrically connected to the sense switching control terminal, a first electrode of the sense switching transistor electrically connected to the readout line, and a second electrode of the sense switching transistor electrically connected to the output terminal of the voltage comparator.

[0077] In one embodiment, the detection circuit may further include a detection sub-circuit electrically connected to the read line for obtaining an input offset voltage of the voltage comparator based on an output voltage output from an output terminal of the voltage comparator.

[0078] The detection switching subcircuit controls whether the voltage comparator outputs a voltage to the detection subcircuit.

[0079] In one embodiment, the data voltage compensation circuit is configured to add an input offset voltage and a data voltage to obtain a compensated data voltage, and provide the compensated data voltage to the data line. The data voltage compensation circuit compensates the data voltage by adding an offset voltage to the original data voltage.

[0080] 3, the test voltage supply circuit may include a voltage supply switching subcircuit 31 and a voltage supply subcircuit 32. The voltage supply switching subcircuit 31 is electrically connected to the test control terminal Gtest, the test voltage terminal Tst, and the non-inverting input terminal of the voltage comparator VC, and controls conduction between the test voltage terminal Tst and the non-inverting input terminal of the voltage comparator VC under control of a test control signal input from the test control terminal Gtest. The voltage supply subcircuit 32 is electrically connected to the test voltage terminal Tst, and supplies a DC test voltage to the test voltage terminal Tst.

[0081] The detection circuit may have a detection switching subcircuit 33 and a detection subcircuit 34. The detection switching subcircuit 33 is electrically connected to a detection switching control terminal S_Readout, an output terminal of a voltage comparator VC, and a readout line Readout, and controls conduction between the output terminal of the voltage comparator VC and the readout line Readout by controlling a detection switching control signal input from the detection switching control terminal S_Readout.

[0082] The detection subcircuit 34 is electrically connected to the readout line Readout and the data voltage compensation circuit 16, and obtains the input offset voltage of the voltage comparator VC based on the voltage output from the output terminal of the voltage comparator VC, and supplies the input offset voltage to the data voltage compensation circuit 16.

[0083] In an embodiment, the switch control circuit may include a switch control transistor, and the light emission control circuit may include a first light emission control transistor and a second light emission control transistor.

[0084] A control electrode of the switch control transistor is electrically connected to the output terminal of the voltage comparator, a first electrode of the switch control transistor is electrically connected to the driving circuit, and a second electrode of the switch control transistor is electrically connected to the first electrode of the second light-emitting control transistor.

[0085] A control electrode of the first light-emitting control transistor is electrically connected to the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected to a control terminal of the drive circuit, and a second electrode of the first light-emitting control transistor is electrically connected to a first input terminal of the voltage comparator.

[0086] A control electrode of the second light-emitting control transistor is electrically connected to the light-emitting control line, and a second electrode of the second light-emitting control transistor is electrically connected to the light-emitting element.

[0087] In one embodiment, the data write circuit may include a data write transistor and a storage capacitor, and the drive circuit may include a drive transistor.

[0088] A control electrode of the data write transistor is electrically connected to the gate line, a first electrode of the data write transistor is electrically connected to the data line, and a second electrode of the data write transistor is electrically connected to the control electrode of the drive transistor.

[0089] A first terminal of the storage capacitor is electrically connected to the control electrode of the drive transistor, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal.

[0090] The control electrode of the drive transistor is a control terminal of the drive circuit, a first electrode of the drive transistor is electrically connected to a power supply voltage terminal, and a second electrode of the drive transistor is electrically connected to a first terminal of the switch control circuit.

[0091] As an example, but not limited to, the first voltage terminal may be a low voltage terminal or a ground terminal.

[0092] In the embodiment shown in FIG. 4, the pixel circuit includes a micro light emitting diode MLED, a data writing circuit 11, a driving circuit 12, a voltage comparator VC, a switch control circuit 13, a light emission control circuit, an offset voltage detection circuit, and a data voltage compensation circuit 16.

[0093] The inverting input terminal of the voltage comparator VC is electrically connected to a reference voltage terminal for inputting a reference voltage Vref.

[0094] The offset voltage detection circuit includes a test voltage supply circuit and a detection circuit.

[0095] The test voltage supply circuit includes a voltage supply switching subcircuit 31 and a voltage supply subcircuit 32, and the voltage supply switching subcircuit 31 includes a voltage supply switching transistor T6. A gate of the voltage supply switching transistor T6 is electrically connected to a test control terminal Gtest, a drain of the voltage supply switching transistor T6 is electrically connected to a test voltage terminal Tst, and a source of the voltage supply switching transistor T6 is electrically connected to a non-inverting input terminal of a voltage comparator VC. The voltage supply subcircuit 32 is electrically connected to the test voltage terminal Tst and supplies a DC test voltage to the test voltage terminal Tst.

[0096] The detection circuit includes a detection switching subcircuit 33 and a detection subcircuit 34. The detection switching subcircuit 33 includes a detection switching transistor T7. The gate of the detection switching transistor T7 is electrically connected to the detection switching control terminal S_Readout, the drain of the detection switching transistor T7 is electrically connected to the readout line Readout, and the source of the detection switching transistor T7 is electrically connected to the output terminal of the voltage comparator VC. The detection subcircuit 34 is electrically connected to the readout line Readout and the data voltage compensation circuit 16, respectively, and obtains an input offset voltage of the voltage comparator VC based on the output voltage output from the output terminal of the voltage comparator, and supplies the input offset voltage to the data voltage compensation circuit 16.

[0097] The switch control circuit 13 includes a switch control transistor T4. The light emission control circuit includes a first light emission control transistor T2 and a second light emission control transistor T5. The data write circuit 11 includes a data write transistor T1 and a storage capacitor C1. The drive circuit 12 includes a drive transistor T3.

[0098] The gate of the switch control transistor T4 is electrically connected to the output terminal of the voltage comparator VC, the source of the switch control transistor T4 is electrically connected to the drain of the driving transistor T3, and the drain of the switch control transistor T4 is electrically connected to the source of the second emission control transistor T5.

[0099] The gate of the first light-emitting control transistor T2 is electrically connected to the light-emitting control line EM, the source of the first light-emitting control transistor T2 is electrically connected to the gate of the driving transistor T3, and the drain of the first light-emitting control transistor T2 is electrically connected to the non-inverting input terminal of the voltage comparator VC.

[0100] The gate of the second light emission control transistor T5 is electrically connected to the light emission control line EM, and the drain of the second light emission control transistor T5 is Micro Light Emitting Diode Electrically connected to the anode of the MLED, Micro Light Emitting Diode The cathode of the MLED is connected to a low voltage VSS.

[0101] The gate of the data write transistor T1 is electrically connected to a gate line Gate, the source of the data write transistor T1 is electrically connected to a data line Data, and the drain of the data write transistor T1 is electrically connected to the gate of the drive transistor T3.

[0102] A first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T3, and a second end of the storage capacitor C1 is electrically connected to the low voltage VSS.

[0103] The source of the driving transistor T3 is electrically connected to a power supply voltage terminal, the drain of the driving transistor T3 is electrically connected to the source of the switch control transistor T4, and the power supply voltage terminal is for inputting a power supply voltage VDD.

[0104] The data voltage compensation circuit 16 is electrically connected to the offset voltage detection circuit 15 and the data line Data, and compensates for the data voltage based on the input offset voltage to obtain a compensated data voltage to be supplied to the data line Data.

[0105] In the above embodiment shown in FIG. 4, all transistors are p-type transistors, however, the present disclosure is not limited in this respect.

[0106] 5 is an operation timing diagram of the pixel circuit shown in FIG. 4. In a detection period td, Test Control Terminal Gtest and Detection switching control terminal Both S_Readout and S_Readout are input at a low level, and both the voltage supply switching transistor T6 and the detection switching transistor T7 are turned on. A corresponding DC test voltage Vtest is input to the test voltage terminal Tst, and is supplied to the non-inverting input terminal of the voltage comparator VC via the voltage supply switching transistor T6. The voltage comparator VC is DC Test Voltage Vtest and Reference Voltage Vref is compared, and the output terminal is connected to the detection switching transistor T7, which is turned on. Read Line The input offset voltage of the voltage comparator VC is obtained from the output voltage of the voltage comparator VC. During the detection period td, the test voltage Vtest is changed multiple times to generate multiple sets of output voltages from the voltage comparator VC. output The voltage Vout is obtained and the input offset voltage is obtained by plotting the voltage transfer curve.

[0107] When the difference between the potential of the non-inverting input terminal of the voltage comparator VC and the potential of the inverting input terminal of the voltage comparator VC is greater than the input offset voltage of the voltage comparator VC, the voltage comparator VC outputs a high voltage VH, and when the difference between the potential of the non-inverting input terminal and the potential of the inverting input terminal is smaller than the input offset voltage, the voltage comparator VC outputs a low voltage VL. Therefore, theoretically, when it is determined that the voltage comparator VC outputs a voltage of (VH+VL) / 2, the difference between the potential of the non-inverting input terminal and the potential of the inverting input terminal becomes the input offset voltage of the voltage comparator VC.

[0108] In the detection period td, the transistors T1, T3, T2 and T5 in FIG. 4 are all turned off.

[0109] Also, Detection switching control terminal The duration that the low level is input to S_readout is Test Control TerminalIf the duration of the low level input to Gtest is longer than the time it lasts, the input offset voltage can be obtained more accurately.

[0110] When the pixel circuit shown in FIG. 4 is in operation, after a detection period, the pixel circuit performs normal display, and the display period may include a data writing stage and a light emitting stage which are set sequentially.

[0111] In the data write stage, the data voltage compensation circuit 16 compensates for the data voltage based on the input offset voltage (for example, adding the detected input offset voltage to the data voltage supplied from the source driver to obtain the compensated data voltage), and supplies the compensated data voltage to the data line Data. By controlling the gate drive signal input from the gate line Gate, the data write transistor T1 is turned on, the compensated data voltage is written to the gate of the drive transistor T3, the storage capacitance C1 is charged, and the potential of the gate of the drive transistor T3 is controlled.

[0112] In the light emission stage, the data write transistor T1 is turned off by the control of the gate drive signal input from the gate line Gate. Light Emitting Control Line Under the control of a light emission control signal input from EM, the first light emission control transistor T2 and the second light emission control transistor T5 are turned on, and the gate of the drive transistor T3 is connected to the non-inverting input terminal of the voltage comparator VC. Reference Voltage By changing Vref and controlling the voltage comparator VC to output a different voltage signal, the switch control transistor T4 is turned on and off. Micro Light Emitting Diode The light emission time of the MLED can be controlled.

[0113] In view of the input offset voltage in the voltage comparator, a pixel circuit according to an embodiment of the present disclosure is provided to improve the luminance uniformity of a display panel and improve the display effect.

[0114] FIG. 6 is a schematic diagram of a voltage comparator VC with a non-inverting input terminal Pa, an inverting input terminal Pb, and an output terminal Out.

[0115] FIG. 7 is a diagram showing the input / output relationship of the voltage comparator VC in FIG. 6, where the vertical axis indicates voltage and the horizontal axis indicates time t.

[0116] As shown in Figure 7, the input offset voltage of the voltage comparator VC is assumed to be 0. Va is the potential of the non-inverting input terminal of the voltage comparator VC, Vb is the potential of the inverting input terminal of the voltage comparator VC, and Vout is the voltage that the voltage comparator VC outputs from its output terminal.

[0117] In the first period S1, a first DC voltage Va1 is input to the non-inverting input terminal Pa, and a first triangular wave signal Vb1 is input to the inverting input terminal Pb. In the first period S1, First Triangle Wave Signal When Vb1 rises from the minimum voltage value to the maximum voltage value, from the first time point t1 to the second time point t2, First DC Voltage Va1 First Triangle Wave Signal Vb1, and the voltage comparator VC outputs a high voltage VH from its output terminal Out, i.e., Vout is VH. First DC Voltage Va1 First Triangle Wave Signal Vb1 becomes smaller than Vb1, and the voltage comparator VC outputs a low voltage VL from its output terminal Out, ie, Vout is VL.

[0118] In the second period S2, a second DC voltage Va2 is input to the non-inverting input terminal Pa, and a second triangular wave signal Vb2 is input to the inverting input terminal Pb. Second Triangle Wave Signal When Vb2 rises from the minimum voltage value to the maximum voltage value, from the third time point t3 to the fourth time point t4, Second DC Voltage Va2 Second Triangle Wave Signal Vb2, and the voltage comparator VC outputs a high voltage VH from its output terminal Out, i.e., Vout is VH. Second DC Voltage Va2 Second Triangle Wave Signal Vb2 becomes smaller, and the voltage comparator VC outputs a low voltage VL from its output terminal Out, ie, Vout is VL.

[0119] In actual operation, the duty ratio of the pulse width modulation signal (i.e., square wave signal) output from the voltage comparator can be adjusted by adjusting Va and / or Vb, thereby adjusting the light emission time of the micro LED.

[0120] Due to the non-uniformity of the semiconductor manufacturing process, there are differences in the element performance (especially the input offset voltage) of the voltage comparator in each pixel circuit at different positions on the display panel. If the output voltage of the voltage comparator is the average value of VH and VL (i.e., average value=(VH+VL) / 2), the input offset voltage is Non-inverting input terminal Voltage in Pa and Inverting Input Terminal The input offset voltage of a voltage comparator can be obtained by plotting the voltage transfer curve of the voltage comparator.

[0121] 8a and 8b are voltage transfer curves of voltage comparators at two positions on the same glass substrate. The horizontal axis represents Va-Vb in V (volts), and the vertical axis represents Vout in V (volts). It can be seen that the input offset voltages of the two voltage comparators are different, and the input offset voltage VOS1 corresponding to the voltage comparator corresponding to FIG. 8a (i.e., sample 1) has a positive value, and the input offset voltage VOS2 corresponding to the voltage comparator corresponding to FIG. 8b (i.e., sample 2) has a negative value.

[0122] The voltage transfer curve in Fig. 8a shows that when Va-Vb is greater than VOS1, the output voltage Vout of the voltage comparator as sample 1 is high, and the voltage transfer curve in Fig. 8b shows that when Va-Vb is greater than Vos2, the output voltage Vout of the voltage comparator as sample 2 is high, where Va is the potential of the non-inverting input terminal of the voltage comparator, and Vb is the potential of the inverting input terminal of the voltage comparator.

[0123] As shown in Fig. 9a, in the voltage comparator corresponding to Fig. 8a (i.e., sample 1), VOS1 is greater than 0. Therefore, when Va-Vb is greater than VOS1, Vout is a high voltage VH, and when Va-Vb is less than VOS1, Vout is a low voltage VL. Compared with a voltage comparator whose input offset voltage is 0, the time during which the voltage comparator outputs a high voltage VH is shortened by Δt1, and in the voltage comparator corresponding to Fig. 8a, the time during which the voltage comparator outputs a low voltage VL is lengthened by Δt1.

[0124] As shown in Figure 9b, in the voltage comparator corresponding to Figure 8b (i.e., sample 2), VOS2 is less than 0. Therefore, when Va-Vb is greater than VOS2, Vout is a high voltage VH, and when Va-Vb is less than VOS2, Vout is a low voltage VL. Compared with a voltage comparator whose input offset voltage is 0, the time during which the voltage comparator outputs a high voltage VH is longer by Δt2, and in the voltage comparator corresponding to Figure 8b, the time during which the voltage comparator outputs a low voltage VL is shorter by Δt2.

[0125] 9a and 9b, the horizontal axis represents time t.

[0126] It can be seen that the time when the voltage comparator corresponding to Figure 8a (i.e., sample 1) outputs a low voltage is different from the time when the voltage comparator corresponding to Figure 8b (i.e., sample 2) outputs a low voltage. Therefore, the difference in the on-time of the switch control transistors controlled by the output terminals of the two voltage comparators is Δt1+Δt2, that is, the difference in the light-emitting time of the two corresponding light-emitting elements is Δt1+Δt2, which deteriorates the display quality. For this reason, it is necessary to detect the input offset voltages of each voltage comparator at different positions on the glass substrate and compensate for them with the data line Data.

[0127] After obtaining the input offset voltage, the data voltage of each pixel circuit at different positions on the glass substrate can be adjusted to adjust the voltage input to the non-inverting input terminal of the voltage comparator, thereby compensating for the input offset voltage.

[0128] 10a and 10b show data voltage compensation performed by two voltage comparators (ie, sample 1 and sample 2), where the horizontal axis represents time t.

[0129] As shown in FIG. 10a, for sample 1, VOS1 is greater than 0, and the data voltage increases from Vdata to the first compensated data voltage Vdata_c1, and ideally, Vdata_c1-Vdata=VOS1.

[0130] In FIG. 10a, Vout1 is the voltage output from the voltage comparator before data voltage compensation, and Vout2 is the voltage output from the voltage comparator after data voltage compensation.

[0131] As shown in FIG. 10b, for sample 2, VOS2 is less than 0, and the data voltage decreases from Vdata to the second compensated data voltage Vdata_c2, and ideally, Vdata_c2-Vdata=VOS2.

[0132] In FIG. 10b, Vout1 is the voltage output from the voltage comparator before data voltage compensation, and Vout2 is the voltage output from the voltage comparator after data voltage compensation.

[0133] After data voltage compensation, two voltage comparators Low voltage The time for outputting VL is the same, and therefore the on-time of the switch control transistors controlled by the output terminals of the two voltage comparators is the same, which makes the light-emitting time of the corresponding two light-emitting elements the same, thereby achieving uniform luminance.

[0134] Based on the pixel circuit shown in FIG. 2, in the pixel circuit shown in FIG. 11, the test voltage supply circuit may include a voltage supply switching sub-circuit 31 that is electrically connected to the test control terminal Gtest, the test voltage terminal Tst, and the non-inverting input terminal of the voltage comparator VC, and controls the conduction between the test voltage terminal Tst and the non-inverting input terminal of the voltage comparator VC by controlling a test control signal input from the test control terminal Gtest.

[0135] 11, during the detection period, the voltage supply switching subcircuit 31 controls the test voltage terminal Tst to be conductive to the non-inverting input terminal of the voltage comparator VC under the control of the test control signal input from the test control terminal Gtest, and inputs the corresponding DC test voltage Vtest to the test voltage terminal Tst. DC Test Voltage Vtest is supplied to the voltage comparator VC, which compares the DC test voltage Vtest with the reference voltage Vref. The input offset voltage of the voltage comparator VC is obtained from the voltage output from the voltage comparator VC. During this detection period, the DC test voltage Vtest is changed multiple times to obtain multiple sets of voltages output from the voltage comparator VC, and the input offset voltage of the voltage comparator VC can be obtained by plotting a voltage transfer curve.

[0136] Based on the pixel circuit shown in FIG. 2, in the pixel circuit shown in FIG. 12, the detection circuit may have a detection switching subcircuit 33. The detection switching subcircuit 33 is electrically connected to a detection switching control terminal S_Readout, an output terminal of the voltage comparator VC, and a readout line Readout, respectively, and controls conduction between the output terminal of the voltage comparator VC and the readout line Readout by controlling a detection switching control signal input from the detection switching control terminal S_Readout. For example, by controlling a detection switching control signal input from the detection switching control terminal S_Readout, a voltage output from the voltage comparator VC is supplied to the readout line Readout via the output terminal of the voltage comparator VC, and the voltage output from the voltage comparator VC is supplied to a detection subcircuit 34 (not shown in FIG. 12) via the readout line Readout, thereby obtaining an input offset voltage of the voltage comparator VC. When the input offset voltage of the voltage comparator VC is obtained, it is supplied to a data voltage compensation circuit 16 to obtain a compensated data voltage. The data voltage compensation circuit 16 may be, for example, an application specific integrated circuit, or may include a programmable logic array, or a suitably programmed microcontroller, or other hardware device that derives a compensated data voltage based on an input offset voltage and provides the compensated data voltage to the data lines.

[0137] 12, during a detection period, under the control of a detection switching control signal input from a detection switching control terminal S_Readout, the detection switching sub-circuit 33 controls the output terminal of the voltage comparator VC so as to be conductive to the readout line Readout, and supplies the voltage output from the voltage comparator VC to the readout line Readout via its output terminal and the detection switching sub-circuit 33. Based on the voltage output from the voltage comparator VC, an input offset voltage of the voltage comparator VC is obtained. After the input offset voltage is obtained, it is supplied to the data voltage compensation circuit 16. The data voltage compensation circuit 16 compensates for the data voltage based on the input offset voltage to obtain a compensated data voltage and supplies it to the data line Data.

[0138] According to an embodiment of the present disclosure, a driving method applied to a pixel circuit is provided, the driving method includes: detecting an input offset voltage of a voltage comparator in a detection period; and compensating a data voltage based on the input offset voltage in a display period to obtain a compensated data voltage. The detection period is set before a display period, and the display period may include a data writing phase.

[0139] 13, in the detection period, the offset voltage detection circuit detects the input offset voltage of the voltage comparator (1302), and in the display period, particularly in the data writing stage, the data voltage compensation circuit compensates the data voltage based on the input offset voltage to obtain a compensated data voltage (1304). Therefore, the pixel circuit according to the embodiment of the present disclosure can accurately control the on / off of the switch control circuit through the voltage comparator, thereby accurately adjusting the light emitting time of the light emitting element.

[0140] In the embodiment of the present disclosure, the input offset voltage of the voltage comparator included in each pixel circuit is detected, and data voltage compensation is performed for each pixel circuit according to the corresponding input offset voltage, so that the light emission duration of each pixel circuit at different positions on the display panel is the same when displaying the same gray scale, thereby improving the luminance uniformity of the display panel and improving the display effect.

[0141] During the detection period, the step of detecting the input offset voltage of the voltage comparator includes: supplying a test voltage to a first input terminal of the voltage comparator, supplying a reference voltage to a second input terminal of the voltage comparator, detecting an output voltage of the voltage comparator, and obtaining the input offset voltage of the voltage comparator based on the output voltage.

[0142] The step of detecting the input offset voltage of the voltage comparator may further include determining a voltage difference between the first input terminal of the voltage comparator and the second input terminal of the voltage comparator as the input offset voltage of the voltage comparator when the output voltage of the voltage comparator is a predetermined voltage, where the predetermined voltage is (VH+VL) / 2, VH is a high voltage output from the voltage comparator, and VL is a low voltage output from the voltage comparator.

[0143] In one example, the offset voltage detection circuit of the pixel circuit may include a test voltage supply circuit and a detection circuit. The test voltage supply circuit supplies a corresponding DC test voltage to a non-inverting output of a voltage comparator. input The detection circuit detects a voltage output from the output terminal of the voltage comparator when the test voltage supply circuit supplies a DC test voltage to the non-inverting input terminal, and detects a voltage output from the output terminal of the voltage comparator when the output voltage of the voltage comparator is a predetermined voltage. input Inverting terminals and voltage comparators input The voltage difference between the terminals is determined as the input offset voltage of the voltage comparator, where the predetermined voltage may be (VH+VL) / 2, where VH is the high voltage output from the voltage comparator and VL is the low voltage output from the voltage comparator.

[0144] In the display period, compensating the data voltage based on the input offset voltage may include adding the input offset voltage to the data voltage to obtain a compensated data voltage.

[0145] In one embodiment, the driving method may further include, during the detection period, controlling the data writing circuit to disconnect the data line from the control terminal of the driving circuit by controlling a gate driving signal, and controlling the light emission control circuit to disconnect the second terminal of the switch control circuit from the light emitting element and to disconnect the control terminal of the driving circuit from the first input terminal of the voltage comparator by controlling a light emission control signal.

[0146] In one embodiment, the display period may further include a light emitting phase after the data writing phase, and the driving method may further include: in the data writing phase, the data writing circuit writes the compensated data voltage into a control terminal of the driving circuit under control of a gate driving signal, and controls the potential of the control terminal of the driving circuit; in the light emitting phase (light emitting phase or illumination phase), the reference voltage terminal inputs a reference voltage, and the driving circuit controls conduction between the power supply voltage terminal and a first terminal of the switch control circuit under control of the potential of the control terminal of the driving circuit; controlling the conduction between the second terminal of the switch control circuit and the light emitting element under control of a light emitting control signal input from a light emitting control line, and controlling the conduction between the control terminal of the driving circuit and a first input terminal of the voltage comparator; the voltage comparator outputs a control voltage signal based on the voltage of the first input terminal and the reference voltage; and the switch control circuit controls the connection and disconnection between the first terminal of the switch control circuit and the second terminal of the switch control circuit under control of the control voltage signal.

[0147] In one example, in the light emission stage, the offset voltage detection circuit stops detecting the offset voltage of the voltage comparator. The reference voltage terminal inputs a reference voltage, and the drive circuit controls the conduction between the power supply voltage terminal and the first terminal of the switch control circuit by controlling the potential of its control terminal. The light emission control circuit controls the conduction between the second terminal of the switch control circuit and the light emitting element by controlling a light emission control signal input from a light emission control line, and controls the conduction between the control terminal of the drive circuit and the non-inverting input terminal of the voltage comparator. The voltage comparator outputs a control voltage signal based on the voltage of the non-inverting input terminal and the reference voltage. The switch control circuit controls the connection and disconnection between the first terminal of the switch control circuit and the second terminal of the switch control circuit by controlling the control voltage signal, thereby controlling the light emission time of the light emitting element.

[0148] In the light emitting stage, the value of the current flowing through the light emitting device is related to the compensated data voltage, and the light emitting time of the light emitting device is related to the reference voltage and the compensated data voltage.

[0149] In the embodiment, the input offset voltage of the voltage comparator included in each pixel circuit is detected, and the data voltage compensation is performed for each pixel circuit according to the input offset voltage, so that the light emission duration of each pixel circuit at different positions on the display panel is the same when displaying the same gray scale, thereby improving the luminance uniformity of the display panel and improving the display effect.

[0150] According to an embodiment of the present disclosure, there is provided a display panel or a display device including the pixel circuit.

[0151] The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.

[0152] Various embodiments and / or examples are disclosed to provide exemplary and explanatory information to enable one skilled in the art to practice the present disclosure. A feature or component disclosed with reference to one embodiment or example is applicable to all embodiments or examples, unless expressly stated otherwise.

[0153] Although the present disclosure has been described in relation to specific embodiments, it will be understood by those skilled in the art that many changes and modifications may be made and equivalent substitutions may be made in components without departing from the scope of the present disclosure. The embodiments may be embodied in other specific forms. The embodiments disclosed herein should be considered as illustrative and not restrictive in all respects.

[0154] This application is based on and claims priority to a Chinese patent application bearing application number 201910522133.8, filed with the State Intellectual Property Office of the People's Republic of China on June 17, 2019, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. A pixel circuit, a light emitting element having a first terminal and a second terminal; a drive circuit electrically connected to a first terminal of the light-emitting element and configured to supply power to the light-emitting element, the drive circuit being configured to control conduction between a power supply voltage terminal and a first terminal of a switch control circuit by controlling a potential of a control terminal of the drive circuit; a voltage comparator, a second input terminal of the voltage comparator electrically connected to a reference voltage terminal supplying a reference voltage, an output terminal of the voltage comparator electrically connected to a control terminal of the switch control circuit, the voltage comparator generating a pulse width modulation signal based on a data voltage supplied to a first input terminal of the voltage comparator and the reference voltage; an offset voltage detection circuit electrically connected to an output terminal of the voltage comparator, the offset voltage detection circuit detecting an input offset voltage of the voltage comparator; a switch control circuit configured to control conduction between a first terminal of the switch control circuit and a second terminal of the switch control circuit by controlling a potential of a control terminal of the switch control circuit; a light emission control circuit electrically connected to the light emitting element, the light emission control circuit being configured to control conduction between a second terminal of the switch control circuit and the light emitting element and to control conduction between a control terminal of the drive circuit and a first input terminal of the voltage comparator by controlling a light emission control signal input from a light emission control line; The offset voltage detection circuit of the pixel circuit is electrically connected to a data voltage compensation circuit, and the data voltage compensation circuit compensates the data voltage based on the detected input offset voltage. Pixel circuit.

2. The offset voltage detection circuit includes: a test voltage supply circuit electrically connected to a first input terminal of the voltage comparator and configured to supply a test voltage to the first input terminal of the voltage comparator; a detection circuit electrically connected to an output terminal of the voltage comparator, the detection circuit detecting an output voltage of the voltage comparator when the test voltage is supplied to a first input terminal of the voltage comparator and the reference voltage is supplied to a second input terminal of the voltage comparator, to obtain an input offset voltage of the voltage comparator. The pixel circuit of claim 1 .

3. the test voltage supply circuit includes a voltage supply switching subcircuit that controls conduction between a test voltage terminal and a first input terminal of the voltage comparator under control of a test control signal input from a test control terminal; The pixel circuit of claim 2 .

4. the voltage supply switching subcircuit having a voltage supply switching transistor, a control electrode of the voltage supply switching transistor electrically connected to the test control terminal, a first electrode of the voltage supply switching transistor electrically connected to the test voltage terminal, and a second electrode of the voltage supply switching transistor electrically connected to the first input terminal of the voltage comparator; The pixel circuit of claim 3 .

5. the test voltage supply circuit further comprises a voltage supply sub-circuit for supplying a test voltage to the test voltage terminal; The pixel circuit of claim 3 .

6. the detection circuit has a detection switching subcircuit that controls conduction between the output terminal of the voltage comparator and a read line under control of a detection switching control signal input from a detection switching control terminal; The pixel circuit of claim 2 .

7. the sense switching subcircuit having a sense switching transistor, a control electrode of the sense switching transistor electrically connected to the sense switching control terminal, a first electrode of the sense switching transistor electrically connected to the readout line, and a second electrode of the sense switching transistor electrically connected to the output terminal of the voltage comparator; The pixel circuit of claim 6.

8. the detection circuit further includes a detection subcircuit connected to the read line and configured to obtain an input offset voltage of the voltage comparator based on an output voltage of the voltage comparator; The pixel circuit of claim 6.

9. the data voltage compensation circuit is configured to obtain a compensated data voltage by adding the input offset voltage and the data voltage. The pixel circuit according to any one of claims 1 to 8.

10. a data write circuit electrically connected to the data lines and the drive circuit; the data write circuit is configured to control writing of the data voltage supplied from the data line to a control terminal of the drive circuit by controlling a gate drive signal input from a gate line, and to control a potential of the control terminal of the drive circuit. The pixel circuit of claim 1 .

11. the switch control circuit has a switch control transistor, the light emission control circuit has a first light emission control transistor and a second light emission control transistor, a control electrode of the switch control transistor is electrically connected to an output terminal of the voltage comparator, a first electrode of the switch control transistor is electrically connected to the driving circuit, and a second electrode of the switch control transistor is electrically connected to a first electrode of the second light-emitting control transistor; a control electrode of the first light-emitting control transistor is electrically connected to the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected to a control terminal of the drive circuit, and a second electrode of the first light-emitting control transistor is electrically connected to a first input terminal of the voltage comparator; a control electrode of the second light-emitting control transistor is electrically connected to the light-emitting control line, and a second electrode of the second light-emitting control transistor is electrically connected to the light-emitting element; The pixel circuit of claim 10.

12. the data write circuit includes a data write transistor and a storage capacitor, the drive circuit includes a drive transistor, a control electrode of the data write transistor is electrically connected to the gate line, a first electrode of the data write transistor is electrically connected to the data line, and a second electrode of the data write transistor is electrically connected to a control electrode of the drive transistor; a first terminal of the storage capacitor electrically connected to a control electrode of the drive transistor, and a second terminal of the storage capacitor electrically connected to a first voltage terminal; a control electrode of the driving transistor is a control terminal of the driving circuit, a first electrode of the driving transistor is electrically connected to a power supply voltage terminal, and a second electrode of the driving transistor is electrically connected to a first terminal of the switch control circuit; 12. A pixel circuit according to claim 10 or 11.

13. a light-emitting element having a first terminal and a second terminal; a drive circuit electrically connected to the first terminal of the light-emitting element and supplying power to the light-emitting element, the drive circuit being configured to control conduction between a power supply voltage terminal and a first terminal of a switch control circuit by controlling a potential of a control terminal of the drive circuit; a voltage comparator, a second input terminal of the voltage comparator being electrically connected to a reference voltage terminal supplying a reference voltage, an output terminal of the voltage comparator being electrically connected to a control terminal of the switch control circuit, the voltage comparator generating a pulse width modulated signal based on a data voltage supplied to the first input terminal of the voltage comparator and the reference voltage; and an offset voltage detector electrically connected to the output terminal of the voltage comparator and detecting an input offset voltage of the voltage comparator. a light emission control circuit configured to control conduction between a first terminal of the switch control circuit and a second terminal of the switch control circuit by controlling a potential of a control terminal of the switch control circuit; and a light emission control circuit electrically connected to the light emitting element, the light emission control circuit configured to control conduction between the second terminal of the switch control circuit and the light emitting element by controlling a light emission control signal input from a light emission control line, and to control conduction between a control terminal of the drive circuit and a first input terminal of the voltage comparator, the offset voltage detection circuit of the pixel circuit being electrically connected to a data voltage compensation circuit, and the data voltage compensation circuit compensating for the data voltage based on a detected input offset voltage, Detecting an input offset voltage of the voltage comparator during a detection period; and compensating the data voltage based on the input offset voltage during a display period to obtain a compensated data voltage. A method for driving a pixel circuit.

14. During the detection period, detecting the input offset voltage of the voltage comparator includes: supplying a test voltage to a first input terminal of the voltage comparator; providing the reference voltage to a second input terminal of the voltage comparator; detecting an output voltage of the voltage comparator; and obtaining the input offset voltage of the voltage comparator based on the output voltage. The driving method according to claim 13.

15. Detecting the input offset voltage of the voltage comparator during the detection period includes: determining a voltage difference between a first input terminal of the voltage comparator and a second input terminal of the voltage comparator as the input offset voltage of the voltage comparator when the output voltage of the voltage comparator is a predetermined voltage; Here, the predetermined voltage is (VH+VL) / 2, where VH is the high voltage output from the voltage comparator, and VL is the low voltage output from the voltage comparator. The driving method according to claim 14.

16. In the display period, compensating the data voltage based on the input offset voltage includes: adding the input offset voltage and the data voltage to obtain the compensated data voltage. The driving method according to claim 13.

17. Detecting an input offset voltage of the voltage comparator during a detection period; during a display period, compensating the data voltage based on the input offset voltage to obtain a compensated data voltage; During a detection period, the data line is disconnected from the control terminal of the drive circuit under control of the gate drive signal, the second terminal of the switch control circuit is disconnected from the light emitting element under control of the light emission control signal, and the control terminal of the drive circuit is disconnected from the first input terminal of the voltage comparator under control of the light emission control signal. A method for driving a pixel circuit according to claim 10.

18. A display panel comprising the pixel circuit according to any one of claims 1 to 12.

19. A display device comprising the display panel according to claim 18.

Images