Display Device and Driving Method Thereof

Abstract

To provide a display device and driving method thereof, which enable detection of defects such as panel burn-in while the display device is being driven to display an image.SOLUTION: Embodiments relate to a display device 100 and driving method thereof, the display device comprising a display panel 110 having sub-pixels to display an image in units of frames, a data driver 120 including a driving circuit configured to apply data voltage to the sub-pixels during an active period for displaying an image within each frame and a sensing circuit configured to sense the sub-pixels during the active period, and a timing controller 140 configured to detect a defect of the display panel based on a sensing result of the sensing circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a display device and a driving method thereof.

[0002] Recently, display devices, which have been in the limelight as display devices, have advantages such as a fast response speed, a large light emitting efficiency, a large brightness, and a large viewing angle, because they use organic light emitting diodes (OLEDs) that emit light by themselves.

[0003] Such a display device arranges sub-pixels, each of which has an organic light-emitting diode and a driving transistor for driving the sub-pixel, in a matrix on a display panel, and controls the brightness of the sub-pixel selected by a scan signal according to the gray scale of the data.

[0004] Such a display device has various signal lines and signal transmission structures for driving.

[0005] If there is an open or short circuit in a signal line, or a problem with the connection or bonding of a signal transmission structure, the display device may not operate normally, causing a panel burn-in phenomenon in which the display panel burns in. Eventually, the display device may break down, and in the worst case, it may even cause a fire.

[0006] Therefore, it is possible to detect defects that may cause panel burn-in before the panel burn-in phenomenon occurs. Moreover, after detecting defects that may cause panel burn-in, it is useful to accurately grasp the detected defects and manage them efficiently. Such management makes it possible to take immediate and appropriate measures when defects occur. Summary of the Invention Problem to be solved

[0007] The embodiment provides a display device and a driving method thereof that can detect defects such as panel burn-in during a display driving period in which an image is displayed.

[0008] The embodiments provide a display device and a driving method thereof that can reduce the time of a real-time sensing process.

[0009] The embodiment provides a display device and a driving method thereof that can detect a phenomenon of a display panel within an active period of one frame during display driving.

[0010] A display device according to an embodiment may include a display panel including subpixels and displaying images in frame units, a data driver having a driving circuit unit that applies a data voltage to the subpixels during an active period in which an image is displayed within one frame and a sensing circuit unit that senses the subpixels during the active period, and a timing control unit that detects defects in the display panel based on a sensing result of the sensing circuit unit.

[0011] The sensing circuit may include a sampling switch that controls a connection between the subpixel and the sensing circuit, and the timing control unit may turn on the sampling switch at least once during the active period.

[0012] The sensing circuit unit may include a sampling circuit configured to sample an electrical signal sensed when the sampling switch is turned on as a sensing voltage, and an analog-to-digital converter configured to convert the sensing voltage into digital data and output the digital data.

[0013] The sensing circuit unit may further include a line capacitor for storing the sensing voltage sampled during the active period, and the analog-to-digital converter may convert the sensing voltage stored in the line capacitor into the digital data during a blank period after the active period.

[0014] The display device may further include a comparator that compares the sensing voltage with a preset or selected target voltage.

[0015] The target voltage may be determined corresponding to a data voltage applied during the active period.

[0016] The comparison unit may be provided in the timing control unit or the sensing circuit unit.

[0017] The comparison unit may compare the sensing voltage with the preset or selected target voltage, and output a lock signal when a difference between the sensing voltage and the preset or selected target voltage is greater than a threshold value.

[0018] The sensing circuit unit may further include an OR gate configured to receive the comparator, the lock signal output from the comparator, and a second lock signal generated based on a defect detected in the display device.

[0019] The timing controller may compensate image data based on a characteristic value of the sub-pixel sensed during a blank period after the active period, and provide the compensated image data to the driving circuit unit.

[0020] The display device may further include a power supply controller that applies a reference voltage to the sub-pixel, and a gate driver that applies a scanning signal and a sensing signal to the sub-pixel.

[0021] The active period may include a first period during which a scan signal and a sensing signal of a turn-on level, the data voltage, and a display reference voltage are applied to the sub-pixel, a second period during which application of the display reference voltage is interrupted, and a third period during which a scan signal and a sensing signal of a turn-off level are applied to the sub-pixel and the sampling switch is turned on.

[0022] A method for driving a display device according to one embodiment drives a display device including a display panel including subpixels, a data driver having a driving circuit unit that applies data voltages to the subpixels and a sensing circuit unit that senses electrical signals output from the subpixels, and a sampling switch that switches a connection between the subpixels and the sensing circuit unit.

[0023] The method may include programming the data voltage to the sub-pixel during an active period of a frame, and turning on the sampling switch during the active period to sample an electrical signal output from the sub-pixel to a sensing voltage.

[0024] The method may further include sensing a characteristic value of the sub-pixel during a blank period after the active period, compensating image data based on the characteristic value, and providing the compensated image data to the driving circuit unit.

[0025] The method may further include a step of storing the sampled sensing voltage in a line capacitor of the sensing circuit unit during the active period, and a step of converting the sampled sensing voltage stored in the sensing circuit unit into digital data during a blank period after the active period.

[0026] The method may further include the steps of comparing the sensing voltage with a preset or selected target voltage, and outputting a lock signal when a difference between the sensing voltage and the preset target voltage is greater than a threshold value.

[0027] The target voltage may be determined corresponding to a data voltage applied during the active period. Effect of the Invention

[0028] The display device and the driving method thereof according to the embodiment detects a burn-in defect of the display panel during display driving for displaying an image, thereby shortening the detection time for the burn-in defect of the display panel and reducing the blank period.

[0029] The display device and driving method thereof according to the embodiment can increase the driving frequency of the display device by reducing the blank period within one frame, and as a result, enables rapid driving of a high-luminance display device.

[0030] The display device and the driving method thereof according to the embodiment can detect burn-in defects in real time during display driving, so that a quick response is possible and further damage can be prevented. [Brief description of the drawings]

[0031] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment. [Diagram 2] 1 is a diagram illustrating a sub-pixel structure of a display device according to an embodiment; [Diagram 3] 11 is a diagram illustrating another sub-pixel structure and a compensation circuit of a display device according to an embodiment. [Figure 4] 4 is a diagram illustrating sensing timing of a display device according to an embodiment. [Diagram 5] 1 is a diagram for explaining a panel burn-in phenomenon in a display device according to an embodiment; [Figure 6] 4 illustrates a connection relationship between a data driver, a timing controller, a power controller, and a display panel according to an embodiment. [Figure 7] 1 is a diagram for explaining a burn-in detection operation according to an embodiment. [Figure 8] FIG. 13 is a diagram showing a driving state of a sub-pixel in an active period. [Figure 9] FIG. 13 is a diagram showing a driving state of a sub-pixel in an active period. [Figure 10] FIG. 13 is a diagram showing a driving state of a sub-pixel in an active period. [Figure 11] FIG. 2 is a block diagram showing the structure of a data driver according to an embodiment. [Figure 12] FIG. 13 is a block diagram showing a structure of a data driver according to another embodiment. Specific details for carrying out the invention

[0032] Hereinafter, examples will be described with reference to the drawings. In this specification, when a component (or a region, layer, portion, etc.) is referred to as being "on," "connected," or "coupled" to another component, it means that it may be directly connected / coupled to the other component, or that a third component may be disposed therebetween.

[0033] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, ratios, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all one or more combinations that can define the related configuration.

[0034] Terms such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another. For example, the first component may be named the second component, and the second component may be named the first component, without departing from the scope of the present embodiment. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0035] Terms such as "under", "below", "up" and "above" are used to describe the relative relationships of features shown in the drawings. The above terms are relative concepts and are described with reference to the directions shown in the drawings.

[0036] Terms such as "comprise" or "have" are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof set forth in the specification, but are to be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0037] FIG. 1 is a system configuration diagram of a display device (100) according to an embodiment.

[0038] Referring to FIG. 1, a display device (100) according to one embodiment includes a display panel (110) on which a plurality of data lines (DL1 to DLm) and a plurality of gate lines (GL1 to GLn) are arranged, and in which a plurality of sub-pixels (SP) defined by the plurality of data lines (DL1 to DLm) and the plurality of gate lines (GL1 to GLn) are arranged in a matrix shape, a data driver (120) for driving the plurality of data lines (DL1 to DLm), a gate driver (130) for driving the plurality of gate lines (GL1 to GLn), and a timing control unit (140) for controlling the data driver (120) and the gate driver (130).

[0039] The timing control unit 140 controls the data driver 120 and the gate driver 130 by supplying various control signals to the data driver 120 and the gate driver 130.

[0040] The timing control unit 140 starts scanning according to the timing implemented in each frame, converts input image data input from the outside into a data signal format used by the data driver 120, outputs the converted image data, and controls data driving at an appropriate time according to the scan.

[0041] The data driver 120 drives the data lines DL1 to DLm by supplying data voltages to the data lines DL1 to DLm. Here, the data driver 120 is also called a "source driver." The data driver 120 includes at least one source driver integrated circuit (hereinafter, SDIC) and can drive the data lines DL1 to DLm.

[0042] The gate driver (130) sequentially drives the multiple gate lines (GL1 to GLn) by sequentially supplying scan signals to the multiple gate lines (GL1 to GLn). Here, the gate driver (130) is also called a "scan driver." The gate driver (130) includes at least one gate driver integrated circuit (GDIC) and can drive the multiple gate lines (GL1 to GLn).

[0043] The gate driver 130 sequentially supplies a scan signal of an on voltage or an off voltage to the gate lines GL1 to GLn under the control of the timing control unit 140.

[0044] When a specific gate line is opened by the gate driver 130, the data driver 120 converts image data received from the timing control unit 140 into an analog data voltage and supplies the analog data voltage to the plurality of data lines DL1 to DLm.

[0045] In FIG. 1, the data driver 120 is located only on one side (e.g., the upper or lower side) of the display panel 110, but it may also be located on both sides (e.g., the upper and lower sides) of the display panel 110 depending on the driving method, panel design method, etc.

[0046] In FIG. 1, the gate driver 130 is located on only one side (e.g., the left or right side) of the display panel 110, but it may also be located on both sides (e.g., the left and right sides) of the display panel 110 depending on the driving method, panel design method, etc.

[0047] The timing control unit 140 described above receives various timing signals, including a vertical sync signal, a horizontal sync signal, an input data enable signal, and a clock signal, along with input video data from an external source (eg, a host system).

[0048] The timing control unit 140 receives timing signals, such as a vertical sync signal, a horizontal sync signal, an input DE signal, and a clock signal, and generates and outputs various control signals to the data driver 120 and the gate driver 130 in order to control the data driver 120 and the gate driver 130.

[0049] For example, the timing control unit 140 outputs various gate control signals (GCS) including a gate start pulse, a gate shift clock, a gate output enable signal, etc., to control the gate driver 130.

[0050] In addition, the timing control unit 140 outputs various data control signals (DCS) including a source start pulse, a source sampling clock, and a source output enable signal to control the data driver 120.

[0051] Each sub-pixel (SP) arranged in the display panel 110 may be configured to include a circuit element such as a transistor. As an example, each sub-pixel (SP) may be configured to include an organic light emitting diode (OLED) and a circuit element such as a driving transistor for driving the OLED. The type and number of circuit elements constituting each sub-pixel (SP) may be determined in various ways depending on the provided function and design method.

[0052] FIG. 2 is a diagram illustrating a structure of a sub-pixel (SP) of a display device (100) according to an embodiment.

[0053] Referring to Fig. 2, in the display device 100 according to an embodiment, each sub-pixel SP may include an organic light emitting diode (OLED), a driving transistor (DRT) for controlling a driving current applied to the organic light emitting diode (OLED), a switching transistor (SWT) for transmitting a data voltage to a gate node of the driving transistor (DRT), and a storage capacitor (Cstg) for maintaining a data voltage corresponding to an image signal voltage or a voltage corresponding thereto during one frame time. Some elements of the sub-pixel may be omitted in Fig. 1. For ease of explanation, they are shown in Fig. 2.

[0054] An organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode), an organic layer, and a second electrode (eg, a cathode electrode).

[0055] The driving transistor (DRT) drives the organic light emitting diode (OLED) by supplying a driving current to the organic light emitting diode (OLED). In the driving transistor (DRT), the first node (N1) may be electrically connected to a first electrode of the organic light emitting diode (OLED) and may be a source node or a drain node of the driving transistor (DRT). The second node (N2) may be electrically connected to a source node or a drain node of the switching transistor (SWT) and may be a gate node of the driving transistor (DRT). The third node (N3) may be electrically connected to a driving voltage line (DVL) that supplies a high potential driving voltage (EVDD) and may be a drain node or a source node of the driving transistor (DRT).

[0056] The switching transistor (SWT) may be electrically connected between the data line (DL) and the second node (N2) of the driving transistor (DRT), and may be controlled by applying a scan signal (SCAN) to the gate node via a gate line. The switching transistor (SWT) may be turned on by the scan signal (SCAN) and transfer a data voltage (Vdata) supplied from the data line (DL) to the second node (N2) of the driving transistor (DRT).

[0057] The storage capacitor (Cstg) may be electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT). Such a storage capacitor (Cstg) is not a parasitic capacitor, which is an internal capacitor, present between the first node (N1) and the second node (N2) of the driving transistor (DRT), but an external capacitor intentionally designed outside the driving transistor (DRT).

[0058] Meanwhile, in the display device 100 according to an embodiment, as the driving time of each sub-pixel SP accumulates (e.g., over the lifetime of the display device 100), degradation of circuit elements such as an organic light emitting diode (OLED) and a driving transistor (DRT) may progress. This may cause a change in inherent characteristic values ​​of the circuit elements. Here, the characteristic values ​​of the circuit elements may include the threshold voltage and mobility of the driving transistor (DRT) and the threshold voltage of the organic light emitting diode (OLED). Such a change in the characteristic value of the circuit elements causes a change in luminance in the corresponding sub-pixel, degrading the luminance uniformity of the display panel 110 and degrading the image quality.

[0059] The display device (100) according to one embodiment can provide a sensing function for sensing characteristic values ​​or changes in characteristic values ​​of circuit elements, and a compensation function for compensating for characteristic value deviations between circuit elements using the sensing results.

[0060] FIG. 3 is a diagram illustrating another sub-pixel structure and a compensation circuit of a display device according to an embodiment.

[0061] Referring to FIG. 3, each sub-pixel arranged in a display panel (110) according to an embodiment may further include, for example, a sensing transistor (SENT) in addition to an organic light emitting diode (OLED), a driving transistor (DRT), a switching transistor (SWT), and a storage capacitor (Cstg).

[0062] The sensing transistor (SENT) may be electrically connected between the first node (N1) of the driving transistor (DRT) and the reference voltage line (RVL), and may be controlled by applying a sensing signal (SENSE), which is a type of scan signal, to a gate node. The sensing transistor (SENT) is turned on by the sensing signal (SENSE) and applies the reference voltages (VpreR, VpreS) supplied via the reference voltage line (RVL) to the first node (N1) of the driving transistor (DRT). The sensing transistor (SENT) may be used as one of the voltage sensing paths for the first node (N1) of the driving transistor (DRT).

[0063] In one embodiment, the reference voltage line (RVL) may be arranged for each subpixel column, or may be arranged for each two or more subpixel columns, for example, when one pixel is composed of four subpixels (a red subpixel, a white subpixel, a green subpixel, and a blue subpixel), the reference voltage line (RVL) may be arranged for each pixel column including the four subpixel columns (a red subpixel column, a white subpixel column, a green subpixel column, and a blue subpixel column).

[0064] Meanwhile, the scan signal (SCAN) and the sensing signal (SENSE) may be separate gate signals. In this case, the scan signal (SCAN) and the sensing signal (SENSE) may be applied to the gate node of the switching transistor (SWT) and the gate node of the sensing transistor (SENT), respectively, through different gate lines. In another embodiment, the scan signal (SCAN) and the sensing signal (SENSE) may be the same gate signal. In this case, the scan signal (SCAN) and the sensing signal (SENSE) may be commonly applied to the gate node of the switching transistor (SWT) and the gate node of the sensing transistor (SENT) through the same gate line.

[0065] The driving transistor (DRT), the switching transistor (SWT), and the sensing transistor (SENT) may be implemented as an n-type or a p-type.

[0066] 3, the data driver 120 according to an embodiment may include a driving circuit unit 200 for driving the sub-pixels SP and a sensing circuit unit 300 for sensing the sub-pixels SP. The driving circuit unit 200 may be connected to a data line DL, and the sensing circuit unit 300 may be connected to a reference voltage line RVL.

[0067] The driving circuit unit 200 may output a data voltage for driving the sub-pixels SP. The sensing circuit unit 300 may sense a characteristic value of the sub-pixel (a characteristic value of the driving transistor DRT or a characteristic value of the organic light emitting diode OLED) or an electrical signal (e.g., a voltage) reflecting a change therein, outputted from the reference voltage line RVL, and convert the sensed electrical signal into a digital value to output as sensing data Vsen.

[0068] The sensing circuit unit 300 may include at least one analog to digital converter (ADC) for converting the sensed electrical signal into digital data. Each ADC may be included in an SDIC. The sensing data (Vsen) converted and output by the ADC may have an LVDS (Low Voltage Differential Signaling) data format, for example. The ADC will be described in more detail with reference to FIGS. 11 and 12.

[0069] In one embodiment, the display device (100) may include a first switch (RPRE) for controlling whether or not a display reference voltage (VpreR or initialization voltage) is supplied to the reference voltage line (RVL) in order to control sensing driving, a second switch (SPRE) for controlling whether or not a sensing reference voltage (VpreS) is supplied to the reference voltage line (RVL), and a sampling switch (SAMP) for switching the connection between the reference voltage line (RVL) and the sensing circuit unit (300).

[0070] The first switch (RPRE) controls a connection between a power supply controller outputting a display reference voltage (VpreR) during display driving and a reference voltage line (RVL). The first switch (RPRE) is turned on at least once during an active period of the display driving, and supplies the display reference voltage (VpreR) to the reference voltage line (RVL) during display driving. The reference voltage (VpreR) supplied to the reference voltage line (RVL) may be applied to a first node (N1) of the driving transistor (DRT) through the turned-on sensing transistor (SENT). At this time, when a data voltage (Vdata) applied to the data line (DL) is applied to the second node (N2) through the switching transistor (SWT), a voltage corresponding to the data voltage (Vdata) may be charged to the sub-pixel (SP).

[0071] The second switch (SPRE) controls a connection between the power supply controller outputting the sensing reference voltage (VpreS) during sensing driving and the reference voltage line (RVL). The second switch (SPRE) is turned on at least once during sensing driving to supply the sensing reference voltage (VpreR) to the reference voltage line (RVL). The sensing reference voltage (VpreS) supplied to the reference voltage line (RVL) may be applied to the first node (N1) of the driving transistor (DRT) via the turned-on sensing transistor (SENT).

[0072] Meanwhile, when the voltage of the first node (N1) of the driving transistor (DRT) becomes a voltage state reflecting the characteristic value of the sub-pixel, the voltage of the reference voltage line (RVL), which may be at the same potential as the first node (N1) of the driving transistor (DRT), may also become a voltage state reflecting the characteristic value of the sub-pixel. At this time, a voltage reflecting the characteristic value of the sub-pixel may be charged in a line capacitor (Csl) formed on the reference voltage line (RVL). That is, when the sensing transistor (SENT) is turned on, the voltage of the first node (N1) of the driving transistor (DRT) may be the same as the voltage of the reference voltage line (RVL) and the voltage charged in the line capacitor (Csl) formed on the reference voltage line (RVL).

[0073] When the voltage of the first node (N1) of the driving transistor (DRT) becomes a voltage state reflecting the characteristic value of the sub-pixel, the sampling switch (SAMP) is turned on, and the sensing circuit unit (300) and the reference voltage line (RVL) can be connected. As a result, the sensing circuit unit (300) senses the voltage of the reference voltage line (RVL), which is a voltage state reflecting the characteristic value of the sub-pixel. Here, the reference voltage line (RVL) is also referred to as a sensing line. That is, the sensing circuit unit (300) senses the voltage of the first node (N1) of the driving transistor (DRT).

[0074] The sensing circuit unit 300 may also sense a potential difference (voltage) formed across the line capacitor Csl connected to the reference voltage line RVL. In this manner, the sensing circuit unit 300 sensing a potential difference (voltage) formed across the line capacitor Csl may be the same as sensing the voltage of the first node N1. In some embodiments, the line capacitor Csl may be formed on the reference voltage line RVL (e.g., a parasitic capacitor) or connected to the reference voltage line RVL (e.g., an integrated capacitor).

[0075] The voltage sensed by the sensing circuit unit 300 may be a voltage value (Vdata-Vth or Vdata-ΔVth) including the threshold voltage (Vth) or a change in threshold voltage (ΔVth) of the driving transistor (DRT) in the case of sensing the threshold voltage of the driving transistor (DRT). Also, the voltage sensed by the sensing circuit unit 300 may be a voltage value for sensing the mobility of the driving transistor (DRT) in the case of mobility sensing of the driving transistor (DRT).

[0076] The sensing circuit unit 300 converts the sensed voltage into a digital value, generates and outputs sensing data including the converted digital value (sensing value). The sensing data (Vsen) output from the sensing circuit unit 300 may be stored in the memory 150 or provided to the timing control unit 140.

[0077] The timing control unit 140 may perform a compensation process to compensate for the characteristic value or characteristic value deviation of the sub-pixel using the sensing data Vsen, and may store the sensing data Vsen and / or the compensation value generated thereby in the memory 150.

[0078] Here, the change in the characteristic value of the driving transistor (DRT) may mean that the current sensing data (Vsen) has changed based on the previous sensing data (Vsen), or may mean that the current sensing data (Vsen) has changed based on the reference sensing data (Vsen).

[0079] Here, by comparing the characteristic values ​​or changes in the characteristic values ​​between the driving transistors (DRT), the compensation unit or circuit 330 can determine the deviation of the characteristic values ​​between the driving transistors (DRT). If the change in the characteristic value of the driving transistor (DRT) means that the current sensing data (Vsen) has changed based on the reference sensing data (Vsen), the characteristic value deviation between the driving transistors (DRT) (i.e., the brightness deviation of the subpixel) can be obtained from the change in the characteristic value of the driving transistor (DRT).

[0080] The characteristic value compensation process may include a threshold voltage compensation process for compensating for a threshold voltage of the driving transistor (DRT) and a mobility compensation process for compensating for a mobility of the driving transistor (DRT). The timing controller 140 may change the image data (Data) through the threshold voltage compensation process or the mobility compensation process and supply the changed data to a corresponding source driver integrated circuit (SDIC) in the data driver 120. The corresponding source driver integrated circuit (SDIC) may then convert the data changed by the timing controller 140 into a data voltage and supply it to a corresponding sub-pixel, thereby actually performing characteristic value compensation of the sub-pixel. By performing such characteristic value compensation of the sub-pixel, it is possible to reduce or prevent a luminance deviation between the sub-pixels, thereby improving the luminance uniformity of the display panel 110 and improving image quality.

[0081] FIG. 4 is a diagram showing sensing timing of the display device (100) according to an embodiment.

[0082] 4, the display device 100 according to an embodiment may sense characteristic values ​​of circuit elements in each sub-pixel disposed in the display panel 110 after a power-off signal is generated by a user input, etc. Sensing performed after the power-off signal is generated in this manner is called "off sensing."

[0083] In addition, the display device 100 according to an embodiment may sense characteristic values ​​of circuit elements in each sub-pixel disposed in the display panel 110 before display driving is started after a power-on signal is generated by a user input, etc. Sensing performed after the power-on signal is generated and before display driving is started is referred to as "on sensing."

[0084] In addition, the display device 100 according to an embodiment can sense characteristic values ​​of circuit elements in each sub-pixel arranged on the display panel 110 during display driving. Sensing performed during display driving in this manner is called "real time sensing (RT sensing)". Real time sensing can be performed for each blank time during an active time based on a vertical synchronization signal.

[0085] FIG. 5 is a diagram for explaining the panel burnt phenomenon in the display device according to one embodiment.

[0086] Referring to FIG. 5, the data driver 120 includes at least one source driver integrated circuit (SDIC) and can drive a plurality of data lines DL1 to DLm.

[0087] Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 by a tape automated bonding method or a chip on glass method, or may be directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. Also, each source driver integrated circuit (SDIC) may be embodied in a chip on film method mounted on a source side film (FS) connected to the display panel 110, as shown in FIG. 5.

[0088] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter, an output buffer, etc. Each source driver integrated circuit (SDIC) may further include an analog to digital converter, if necessary.

[0089] The gate driver 130 includes at least one gate driver integrated circuit (GDIC) and can drive a plurality of gate lines GL1 to GLn. Each gate driver integrated circuit (GDIC) may be connected to a bonding pad of the display panel 110 using a tape automated bonding method or a chip on glass method, or may be implemented as a GIP (Gate In Panel) type and directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. Also, as shown in FIG. 5, each gate driver integrated circuit (GDIC) may be implemented as a chip on film type mounted on a gate side film (FG) connected to the display panel 110. Each gate driver integrated circuit (GDIC) may include a shift register, a level shifter, etc.

[0090] The display device 100 according to an embodiment may include at least one source printed circuit board (S-PCB) required for circuit connection to at least one source driver integrated circuit (SDIC), and a control printed circuit board (C-PCB) for mounting control components and various electric devices. At least one source driver integrated circuit (SDIC) may be mounted on the at least one source printed circuit board (S-PCB), or a source side film (FS) on which at least one source driver integrated circuit (SDIC) is mounted may be connected. A timing control unit 140 for controlling the operation of the data driver 120 and the gate driver 130, etc., and a power supply controller for supplying various voltages or currents to the display panel 110, the data driver 120, the gate driver 130, etc., or for controlling the various voltages or currents to be supplied, etc. may be mounted on the control printed circuit board (C-PCB). At least one source printed circuit board (S-PCB) and a control printed circuit board (C-PCB) may be circuit-connected via at least one flexible flat cable (FFC1).

[0091] The display device 100 may further include a main printed circuit board (M-PCB) on which a main controller (M-CON) and the like are mounted, in addition to at least one source printed circuit board (S-PCB) and control printed circuit board (C-PCB). The main printed circuit board (M-PCB) may be connected to the control printed circuit board (C-PCB) via at least one flexible flat cable (FFC2). At least two of the at least one source printed circuit board (S-PCB), the control printed circuit board (C-PCB), and the main printed circuit board (M-PCB) may be integrated into one printed circuit board.

[0092] In one embodiment, the display panel 110 may suffer from a panel burn-in phenomenon, which is a phenomenon where the display panel 110 burns in due to various types of defects. Defects that may cause the panel burn-in phenomenon include a short circuit or open circuit in signal lines (DL, GL, DVL, RVL, gate voltage wiring, etc.) arranged in the display panel 110, a bonding error between the display panel 110 and the gate side film (FG) or the source side film (FS), an electrical connection problem between the source printed circuit board (S-PCB) and the control printed circuit board (C-PCB) due to an unconnected flexible flat cable (FFC1), and an electrical connection problem between the control printed circuit board (C-PCB) and the main printed circuit board (M-PCB) due to an unconnected flexible flat cable (FFC2), etc.

[0093] If such a defect occurs, the display panel 110 may burn in, causing a panel burn-in phenomenon, which may cause the display device 100 to malfunction, or the display device 100 may break down, or in the worst case, cause a fire.

[0094] Therefore, it is useful to detect defects that cause panel burn-in before the panel burn-in phenomenon occurs, which makes it possible to take immediate and appropriate measures when the defect occurs.

[0095] In one embodiment, the burn-in detection may be performed during an on-sensing process, an off-sensing process, and / or a real-time sensing process. In another embodiment, the burn-in detection may be performed during an active period in one frame during display driving.

[0096] In the following, a method for detecting panel burn-in during the active period will be described in more detail.

[0097] FIG. 6 illustrates a connection relationship between a data driver, a timing controller, a power controller, and a display panel according to an embodiment.

[0098] Referring to FIG. 6, a display device (100) according to an embodiment includes a timing control unit (140), a power controller (900), a data driver (120), and a display panel (110).

[0099] The data driver 120 may perform sensing to detect burn-in of the display panel 110 based on a control signal received from the timing control unit 140. In one embodiment, the data driver 120 may detect defects such as panel burn-in during the active period shown in FIG. 4. If the coupling detection is performed during the active period, the length of the blank period in one frame may be minimized or shortened. A method of detecting burn-in to minimize or shorten the length of the blank period will be described with reference to FIGS. 7 to 10.

[0100] The timing control unit 140 can determine whether or not there is a defect in the panel based on the sensing data Vsen received from the data driver 120. Furthermore, if it is determined that a panel defect has occurred, the timing control unit 140 can proceed with a burn-in countermeasure sequence corresponding thereto.

[0101] For example, the timing control unit 140 may generate and output a BDP signal (BDP). In one embodiment, the timing control unit 140 may output the BDP signal (BDP) to the power supply controller 900, etc. Also, the timing control unit 140 may stop outputting control signals to the data driver 120, the gate driver 130, etc. to stop operation.

[0102] The power controller 900 may perform a power-off process when the BDP signal BDP is received from the timing control unit 140. For example, the power controller 900 may stop generating driving voltages applied to the display panel 110, the data driver 120, the gate driver 130, etc. The power controller 900 may also output a power-off signal to an external host, etc., so that a power-off sequence is performed by the host.

[0103] Fig. 7 is a diagram for explaining the operation of detecting burn-in according to an embodiment. Fig. 8 to Fig. 10 are diagrams showing the driving states of sub-pixels in an active period.

[0104] 7, display driving may be performed in frame units, and one frame may include an active time for displaying an image and a blank time after the active time. The active time is a time during which the data driver 120 outputs a data voltage Vdata through a plurality of data lines DL1 to DLm while the gate driver 130 sequentially drives a plurality of gate lines GL1 to GLN, GLN+1 to GLn. During the blank time, real-time sensing may be performed to sense a characteristic value of the sub-pixel SP.

[0105] The active period includes a first period (t1) for programming a data voltage (Vdata) to the subpixel (SP), a second period (t2) for tracking the voltage of the second node (N2) of the driving transistor (DRT), and a third period (t3) for sensing the voltage of the reference voltage line (RVL).

[0106] 8, in a first period (t1), a scan signal (SCAN) of a turn-on level is applied to the switching transistor (SWT), and a sensing signal (SENSE) of a turn-on level is applied to the sensing transistor (SENT). In addition, in the first period (t1), a data voltage (Vdata) for displaying an image may be applied through the data line (DL), the first switch (RPRE) may be turned on, and a reference voltage (VpreR) for display may be applied through the reference voltage line (RVL).

[0107] As a result, the switching transistor (SWT) is turned on, the data voltage (Vdata) is applied to the second node (N2), and the sensing transistor (SENT) is turned on, and the display reference voltage (VpreR) is applied to the first node (N1). A voltage corresponding to the difference between the data voltage (Vdata) and the display reference voltage (VpreR) may be stored in the storage capacitor (Cstg). As a result, the organic light emitting diode (OLED) may emit light with a brightness corresponding to the voltage stored in the storage capacitor (Cstg) during the remaining active period, including the third period (t3) in which the switching transistor (SWT) and the sensing transistor (SENT) are turned off after the first period (t1).

[0108] 9, when the application of the display reference voltage VpreR is stopped during the second period t2, the reference voltage line RVL is floated. During the second period t2, the switching transistor SWT and the sensing transistor SENT are maintained in the turned-on state.

[0109] The voltage of the first node (N1) in a floating state gradually increases and then saturates. The saturated voltage of the first node (N1) of the drive transistor (DRT) may correspond to the magnitude of the data voltage (Vdata). That is, once the data voltage (Vdata) is determined, a target value (target voltage) of the saturation voltage is set or selected. For example, the saturation voltage of the first node (N1) may correspond to the difference between the data voltage (Vdata) and the threshold voltage (Vth) of the drive transistor (DRT).

[0110] Here, the voltage of the first node (N1) is the same as the voltage (Vrvl) of the reference voltage line (RVL), and the increased voltage (Vrvl) of the reference voltage line (RVL) may be similarly stored in the line capacitor (Csl).

[0111] When the voltage of the second node is saturated, sampling can be performed. Referring also to FIG. 10, the sampling switch (SAMP) may be turned on at least once during a third period (t3) to connect the sensing circuit unit (300) and the reference voltage line (RVL). Thus, the voltage (Vrvl) of the reference voltage line (RVL) can be transmitted to the sensing circuit unit (300).

[0112] The sensing circuit unit 300 can detect the presence or absence of a defect in the panel based on the sensed electrical signal, for example, the voltage (Vrvl), of the reference voltage line RVL. If there is no defect such as burn-in in the corresponding subpixel SP, the sensed voltage (Vrvl) of the reference voltage line RVL may be substantially equal to the above-mentioned preset or selected target voltage. Meanwhile, if burn-in occurs in the corresponding subpixel SP, the sensing voltage (Vrvl) may be lower than the target voltage since a current leaks from the reference voltage line RVL. Thus, the sensing circuit unit 300 can compare the sensing voltage (Vrvl) with the target voltage of the saturation voltage and determine that a defect such as panel burn-in has occurred in the corresponding subpixel SP if the difference between the sensing voltage (Vrvl) and the target voltage of the saturation voltage is equal to or greater than a predetermined threshold value.

[0113] The burn-in detection may be performed on a sub-pixel line basis. For example, one sensing circuit unit 300 may determine that a burn-in defect has occurred in the display panel 110 when a predetermined or selected number of sub-pixels SP in one sub-pixel line have a difference between the sensing voltage of the target saturation voltage and a threshold value or more.

[0114] Also, the burn-in detection may be performed only for a predetermined pre-set or selected sub-pixel line. In general, since panel burn-in frequently occurs in an edge region of a panel, particularly at the top and bottom edges, the burn-in detection may be performed only for the first and last sub-pixel lines among the plurality of sub-pixel lines. However, the present embodiment is not limited thereto.

[0115] In one embodiment, the sensing circuit unit 300 may sample the voltage (Vrvl) of the reference voltage line (RVL) in real time during an active period and determine whether a defect has occurred based on the sampled sensing voltage (Vrvl).

[0116] 7, the sensing circuit unit 300 may sample and store the sensed voltage (Vrvl) during the active period, and then compare the sampled sensing voltage stored during the blank period with a target voltage of the saturation voltage to detect defects. In such an embodiment, the sampled sensing voltage may be stored in a line capacitor and / or a DAC capacitor of the sensing circuit unit 300.

[0117] Meanwhile, the blank period includes a fourth period (t4) for initializing the voltages of the first node (N1) and the second node (N2) of the driving transistor (DRT), a fifth period (t5) for tracking the voltage of the second node (N2), and a sixth period (t6) for sensing the voltage of the reference voltage line (RVL).

[0118] In a fourth period (t4), a scan signal (SCAN) of a turn-on level is applied to the switching transistor (SWT) in the first period (t1), and a sensing signal (SENSE) of a turn-on level is applied to the sensing transistor (SENT). Also, in the fourth period (t4), a data voltage (Vdata) for sensing may be applied through the data line (DL), the second switch (SPRE) may be turned on, and a reference voltage (VpreS) for sensing may be applied through the reference voltage line (RVL).

[0119] In a fifth period t5, the application of the sensing reference voltage VpreS is stopped, and the first node N1 of the driving transistor DRT is floated, so that the voltage of the first node N1 of the driving transistor DRT rises.

[0120] The voltage of the first node N1 of the driving transistor DRT rises and then gradually decreases until it saturates. The saturated voltage of the first node N1 of the driving transistor DRT may correspond to the difference between the sensing data voltage Vdata and the threshold voltage Vth.

[0121] When the voltage of the first node (N1) of the driving transistor (DRT) is saturated, the sampling switch (SAMP) may be turned on at least once during a sixth period (t6) to sense the saturated voltage of the first node (N1) of the driving transistor (DRT).

[0122] The sensing circuit unit 300 converts the sensed voltage into sensing data (Vsen) and transmits it to the timing control unit 140, and the timing control unit 140 can perform a compensation process based on the sensing data (Vsen).

[0123] As described above, in the present embodiment, during display driving in which an image is displayed, voltage sensing and sensing voltage sampling for detecting burn-in defects are performed during an active period, not during a blank period, thereby enabling the blank period to be relatively shortened and the active period to be increased, enabling rapid driving of a high brightness display device.

[0124] FIG. 11 is a block diagram illustrating the structure of a data driver according to one embodiment.

[0125] Referring to FIG. 11, the data driver 120 includes a driving circuit unit 200 and a sensing circuit unit 300.

[0126] The driving circuit unit (200) includes a receiving unit (211), a shift register (212), a first latch (213), a second latch (214), a digital-analog converter (DAC) (215), and an output buffer (216).

[0127] The receiver 211 receives signals provided from the timing controller 140 through various interface technologies such as an LVDS interface, an EPI, a DP, or an eDP interface, and can restore and output image data (Data) and source control signals (SSP, SSC, SOE) from the received signals. In one embodiment, the image data (MDATA) received through the receiver 211 may be image data (Data') whose gain value is compensated by sensing a sub-pixel. The source control signals (SSP, SSC, SOE) may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The source start pulse (SSP) controls a data sampling start point of the source drive IC. The source sampling clock (SSC) is a clock signal that controls a data sampling operation in the source drive IC based on a rising or polling edge. The source output enable signal (SOE) controls the output of the source drive IC.

[0128] The receiver 211 may be configured to include a serial-parallel converter, etc. In one embodiment, the receiver 211 may receive a control packet from the timing controller 140 via an EPI interface, etc., and obtain control information for driving the overdriving sensing from the control packet.

[0129] The shift register 212 outputs a sampling signal in response to a source start pulse (SSP) and a source sampling clock (SSC) provided from the timing control unit 140.

[0130] The first latch 213 sequentially latches the digital image data (Data) in response to the sampling signal sequentially input from the shift register 212, and then latches and outputs the data in parallel. The first latch 213 simultaneously outputs one horizontal line of sampled image data (Data) in response to the source output enable signal (SOE).

[0131] The second latch 214 latches the data input from the first latch 213, and then outputs the latched image data (Data) simultaneously with the second latch 214 of the other DIC during the logic low period of the source output enable signal (SOE). In various embodiments, only one latch may be provided.

[0132] The DAC (215) receives the gamma gray scale voltage (GV) and converts the image data (MDATA) of one horizontal line into a data voltage (Vdata) using the gamma gray scale voltage (GV). That is, the DAC (215) can convert the image data (MDATA), which is digital data, into an analog data voltage (Vdata). The output buffer (216) supplies the data voltage (Vdata) output from the DAC (215) to the data line (DL) through the data channel (DCH) in response to a source output enable signal (SOE).

[0133] The sensing circuit unit (300) includes a current-voltage conversion unit (311), a noise removal unit (312), and an ADC (313).

[0134] The current-voltage converter 311 converts an input current from the display panel 110 or the current source 400 through the sensing channel SIO into a voltage by current integration and samples it into a voltage sensing value. The noise eliminator 312 eliminates noise flowing in through an adjacent channel from the sampled sensing value and outputs the result. Here, the current-voltage converter 311, or the current-voltage converter 311 and the noise eliminator 312, may be called a sampling unit or circuit for sampling the sensing voltage of the reference voltage line RVL.

[0135] The ADC (313) converts the sampled sensing value supplied from the noise elimination unit (312) or the sampled sensing value supplied from the current-voltage conversion unit (311) bypassing the noise elimination unit (312) into digital data and outputs the digital data to the timing control unit (140) as sensing data (Vsen).

[0136] The sensing circuit unit 300 may be provided with a line capacitor Csl. The line capacitor Csl may be provided at an input terminal of the ADC 313 or inside the ADC 313. The line capacitor Csl may temporarily store a sensing value sampled by the current-voltage converter 311, and input the stored sampled sensing value to the ADC 313 when the ADC 313 is driven. For example, when the sampling switch SAMP is turned on during an active period in one frame (e.g., during a period when the sampling switch SAMP is on), the sensing circuit unit 300 may sample a voltage of the reference voltage line RVL, and then convert the voltage sampled by the ADC 313 into a digital value during a blank period after the active period.

[0137] Meanwhile, although the current source 400 is provided outside the data driver 120 in the illustrated embodiment, the present embodiment is not limited thereto, that is, in other embodiments, the current source 400 may be a current source provided inside the data driver 120.

[0138] The timing control unit 140 can detect defects such as panel burn-in based on the sensing data Vsen output from the ADC 313. To this end, the timing control unit 140 can include a comparison unit 141. The comparison unit 141 can compare the voltage of the reference voltage line RVL sensed during the active period with a preset or selected target voltage. The target voltage can be determined based on a data voltage Vdata for displaying an image applied to the sub-pixel SP during the active period and a predetermined or selected threshold voltage Vth, and can be stored in advance in the memory 150, etc.

[0139] The comparator 141 may output a lock signal of a first level (e.g., a high level) if a difference between a sensing voltage acquired from the sensing data Vsen and a preset or selected target voltage is less than a preset or selected threshold, and may output a lock signal of a second level (e.g., a low level) if the difference is greater than the preset or selected threshold. The timing controller 140 may proceed with the above-mentioned burn-in countermeasure sequence in response to the lock signal (e.g., a low level lock signal) generated by the comparator 141.

[0140] FIG. 12 is a block diagram showing the structure of a data driver according to another embodiment.

[0141] 12, a comparator 314 may be provided in the sensing circuit 300 of the data driver 120. The comparator 314 is configured with analog hardware and receives the analog sampling voltage before it is digitally converted by the ADC 313.

[0142] The comparator 314 may receive a sensed voltage of the reference voltage line RVL sensed during an active period and a preset or selected target voltage, and may output a lock signal of a first level (e.g., a high level) if a difference between the sensed voltage and the preset or selected target voltage is less than a preset or selected threshold, and may output a lock signal of a second level (e.g., a low level) if the difference is greater than the preset or selected threshold.

[0143] An OR gate may be connected to the output terminal of the comparator 314. The OR gate is configured to receive a lock signal (lock) input from the outside and the lock signal (lock) output from the comparator 314. The lock signal (lock) input from the outside may be input to a second level (e.g., low level) when a defect such as an overcurrent occurs in another component, for example, the gate driver 130, or a defect such as a crack occurring at an edge of the display panel 110 is sensed.

[0144] When a second level lock signal (lock) is input from the outside due to the above-mentioned defect, or when a second level lock signal (lock) is input by the comparator (314) due to detection of a burn-in defect, the OR gate outputs a second level lock signal (lock) to the timing controller (140) via an EPI interface, etc. The OR gate can transmit a lock signal (e.g., a low level lock signal) to the timing controller (140) via an EPI interface, etc.

[0145] When a lock signal (eg, a low-level lock signal) is detected, the timing control unit 140 determines that panel burn-in has occurred and can proceed with the above-described burn-in countermeasure sequence.

[0146] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains will understand that the technical configuration of the present invention described above can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not limiting. At the same time, the scope of the present invention is defined by the claims below rather than the above detailed description. Furthermore, all modifications or alterations derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0147] 100:Display device 110: Display panel 120: Data Driver 130: Gate Driver 140: Timing control section

Claims

1. A display panel including sub-pixels for displaying images frame by frame; a data driver including a driving circuit unit that applies a data voltage to the sub-pixel during an active period in which the image is displayed within one frame, and a sensing circuit unit that senses the sub-pixel during the active period; a timing control unit that detects a defect in the display panel based on a sensing result of the sensing circuit unit; a power supply controller for applying a reference voltage to the subpixel; and a gate driver that applies a scanning signal and a sensing signal to the sub-pixel; The sensing circuit unit includes: a sampling switch for controlling a connection between the subpixel and the sensing circuitry; The timing control unit is turning on the sampling switch at least once during the active period; The active period is: a first period during which the scan signal, the sensing signal, the data voltage, and the display reference voltage are applied to the subpixel at a turn-on level; a second period during which application of the display reference voltage is interrupted; and the scanning signal and the sensing signal are applied to the sub-pixel at a turn-off level, and the sampling switch is turned on in a third period.

2. The sensing circuit unit includes: a sampling unit that samples an electrical signal sensed when the sampling switch is turned on as a sensing voltage; and The display device according to claim 1 , further comprising an analog-to-digital converter that converts the sensing voltage into digital data and outputs the digital data.

3. The sensing circuit unit includes: a line capacitor for storing the sensing voltage sampled during the active period; The analog-to-digital converter includes: The display device of claim 2 , further comprising: converting the sensing voltage stored in the line capacitor into the digital data during a blank period after the active period.

4. The display device of claim 2 , further comprising a comparator that compares the sensing voltage with a preset target voltage.

5. The target voltage is The display device according to claim 4 , wherein the data voltage is determined in response to a data voltage applied during the active period.

6. The comparison unit is The display device according to claim 4 , wherein the timing control unit or the sensing circuit unit is provided therein.

7. The comparison unit is The display device according to claim 4 , further comprising: a lock signal output unit configured to output a lock signal when the difference between the sensing voltage and the target voltage is greater than a threshold value by comparing the sensing voltage with the target voltage.

8. The sensing circuit unit includes: the comparison unit; and The display device according to claim 7 , further comprising an OR gate configured to receive the lock signal output from the comparator and a second lock signal generated based on a defect detected in the display device.

9. The timing control unit is The display device of claim 1 , further comprising: a compensation circuit for compensation of image data based on a characteristic value of the sub-pixel sensed during a blank period after the active period, the compensation being provided to the driving circuit unit.

10. 1. A method comprising: Providing a display device according to claim 1; applying, by the driving circuitry, the data voltages to the sub-pixels, the data voltages being programmed to the sub-pixels during the active period of a frame; and sensing an electrical signal output from the subpixel by the sensing circuitry, the electrical signal output being sampled as a sensing voltage by turning on the sampling switch during the active period, the sampling switch being configured to switch a connection between the subpixel and the sensing circuitry.

11. sensing a characteristic value of the sub-pixel during a blank period after the active period; and The method of claim 10 , further comprising the step of compensating video data based on the characteristic value and providing the compensated video data to the driving circuit unit.

12. During the active period, the sensing circuit stores the sampled sensing voltage in a line capacitor of the sensing circuit; and The method of claim 10 , further comprising the step of the sensing circuitry converting the sampled sensing voltage into digital data stored in the sensing circuitry during a blank period after the active period.

13. Comparing the sensed voltage with a preset target voltage; and The method of claim 10 , further comprising: outputting a lock signal when a difference between the sensing voltage and the target voltage is greater than a threshold.

14. The target voltage is The method of claim 13 , wherein the data voltage is determined corresponding to the data voltage applied during the active period.

15. a display panel having sub-pixels, the display panel displaying images in frames during operation, each frame including an active period followed by a blank period; a reference voltage line associated with said subpixel; A data driver, drive circuitry that, in operation, outputs data voltages to data lines coupled to the subpixels; and a data driver including a sensing circuitry that, during operation, generates sensing data by sampling an electrical signal on the reference voltage line during a third time period when the reference voltage line is electrically floating; a power controller that, during operation, generates a first reference voltage during the active period and generates a second reference voltage during the blank period; a timing controller configured to detect defects in the display panel based on the sensing data during operation; a power supply controller for applying a reference voltage to the subpixel; and a gate driver that applies a scanning signal and a sensing signal to the sub-pixel; The sensing circuit unit includes: a sampling switch for controlling a connection between the subpixel and the sensing circuitry; The timing control unit is turning on the sampling switch at least once during the active period; The active period is: a first period during which the scan signal, the sensing signal, the data voltage, and the display reference voltage are applied to the subpixel at a turn-on level; a second period during which application of the display reference voltage is interrupted; and the third period in which the scanning signal and the sensing signal at a turn-off level are applied to the sub-pixel and the sampling switch is turned on.

16. The sub-pixel is Organic light-emitting diodes; a drive transistor coupled to the organic light emitting diode; a switching transistor connected to the data line and to the gate of the driving transistor; and a sensing transistor connected to the reference voltage line and to a source of the driving transistor; The display device further comprises a gate driver configured to generate, during operation, the scanning signal applied to the switching transistor and the sensing signal applied to the sensing transistor; The data driver, during operation, electrically connecting the data line and the driving transistor by turning on the switching transistor during the first period and the second period prior to the third period of the active period; By turning on the sensing transistor during the first period and the second period, the reference voltage line and the drive transistor are electrically connected to each other; applying the first reference voltage generated by the power controller to the reference voltage line during the first time period; The display device of claim 15 , wherein the reference voltage line is electrically isolated from the power controller during the second period.

17. The sensing circuit unit includes an analog-to-digital converter (ADC), the sensing circuitry, during operation, stores the electrical signal sampled during the third period as a sensing voltage; The display device according to claim 16 , wherein the analog-to-digital converter converts the sensing voltage into the sensing data during a fourth period of the blank period following the third period of the active period.

Images