Driving / scanning circuit and display panel

Abstract

A driving scanning circuit and a display panel, the driving scanning circuit including an even number of signal lines configured to be divided into an odd set of signal lines and an even set of signal lines, and an assembly connected between the odd set of signal lines and the even set of signal lines, the assembly including a register section and a pull-down section, and a multi-stage scanning sub-circuit in which a load is connected between the register section and the pull-down section, the register section and the pull-down section provided on the same side of the load are arranged alternately, and any two of the register sections separated by N stages on one side of the load are cascaded to each other, N being half the total number of the even number of signal lines.

Description

[Technical field]

[0001] The present invention relates to the technical field of displays, and in particular to driving and scanning circuits and display panels. [Background technology]

[0002] In a typical display panel, the horizontal scanning lines are commonly driven by the GOA (gate driver on array) units on both the left and right sides, multiple pixels are connected in series to the scanning lines, and a resistive and capacitive load exists on the scanning lines. For example, in a double-sided driving architecture, in order to drive all the GOAs, the same number of clock (CK) wirings are symmetrically arranged on both sides of the circuit, and an even number (e.g., 2N) of clock wirings must be arranged on one side of the frame, which increases the wiring area required for the frame on one side and does not meet the requirements of a narrow frame panel. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a driving and scanning circuit and a display panel to improve the problem of realizing a narrow frame panel in the prior art. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a driving scanning circuit including an even number of signal lines divided into an odd set of signal lines and an even set of signal lines, and an assembly connected between the odd set of signal lines and the even set of signal lines, the assembly including a register unit and a pull-down unit, and a multi-stage scanning sub-circuit in which a load is connected between the register unit and the pull-down unit, the register unit and the pull-down unit provided on the same side of the load are alternately arranged, any two of the register units separated by N stages on one side of the load are cascaded to each other, N is half the total number of the even number of signal lines, the register unit and the pull-down unit adjacent to one side of the load are connected to different signal lines of the same set of signal lines, and the register unit and the pull-down unit adjacent to the same side of the load are integrally arranged. Therefore, the wiring area occupied by the register unit and the pull-down unit adjacent to one side of the load can be reduced, and the frame width can be significantly reduced. Furthermore, by drawing the register unit and the pull-down unit in a mixed layout, the frame width can be significantly reduced. By mixing and layouting the register unit, the width of the register unit can be reduced. In addition to reducing the number of signal wirings on one side, the width of the register unit after reduction can be saved to 30% of the original width of the register unit, which can be applied to a liquid crystal display panel. Furthermore, by providing the register unit and the pull-down unit alternately at a distance from each other, the signal lines can be efficiently distributed to both sides of the load, and the number of signal lines on one side can be reduced by half. The frame width can be significantly reduced, and a driving scanning circuit can be realized by a one-sided driving arrangement.

[0005] According to one embodiment of the present invention, in the same assembly, one of the register unit and the pull-down unit is connected between the load and one of the odd-numbered set of signal lines, and the other of the register unit and the pull-down unit is connected between the load and one of the even-numbered set of signal lines. Thus, the signal lines are efficiently distributed on both sides of the load, and the register unit and the pull-down unit in the same assembly are connected to the odd-numbered set of signal lines and the even-numbered set of signal lines located on different sides, and the frame width can be significantly reduced.

[0006] According to an embodiment of the present invention, the number of the even number of signal lines is 2N (N is a positive integer), the multi-stage scanning sub-circuit includes an n-th stage (n is a positive integer) scanning sub-circuit, the register unit in the n-th stage scanning sub-circuit is connected to the i-th signal line, the pull-down unit in the n-th stage scanning sub-circuit is connected to the j-th signal line, if n is an integer multiple of 2N, i=2N, otherwise i=mod(n,2N), if (n+N-1) is an integer multiple of 2N, j=2N, otherwise j=mod(n+N-1,2N). Therefore, it is advantageous to apply to different driving scanning circuits, and realizes the improvement of the driving scanning circuit without affecting the charging of the panel pixels.

[0007] According to an embodiment of the present invention, the number of the even-numbered signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer), and when n≦N, a preset start signal is input to the register unit in the n-th stage scanning sub-circuit, and when n>N, the register unit in the n-th stage scanning sub-circuit outputs a start signal to the register unit in the (n+N)th stage scanning sub-circuit. Therefore, it is advantageous to be applied to different driving scanning circuits, and realizes the improvement of the driving scanning circuits without affecting the charging of panel pixels.

[0008] According to one embodiment of the present invention, the number of transistors included in the register unit is greater than the number of transistors included in the pull-down unit, and therefore the number of transistors included in the pull-down unit is less than the number of transistors included in the register unit, which effectively simplifies the circuit configuration of the pull-down unit and realizes an improvement in the driving and scanning circuit without affecting the charging of the panel pixels.

[0009] According to an embodiment of the present invention, the pull-down unit includes a pull-down transistor, a control terminal of the pull-down transistor is connected to a pulse port, a first terminal of the pull-down transistor is connected to a scan input port, a second terminal of the pull-down transistor is connected to a lower port, and the load is connected between the scan input port of the pull-down unit and the scan output port of the register unit. Thus, the circuit configuration of the pull-down unit is efficiently simplified, and the load is commonly driven using the scan output port of the register unit and the scan input port of the pull-down unit, thereby realizing an improvement in the driving and scanning circuit without affecting the charging of the panel pixels.

[0010] According to one embodiment of the present invention, the number of the even number of signal lines is 2N (N is a positive integer), the even number of signal lines transmit an even number of pulse signals, and in the transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, and each of the pulse signals is configured as a pulse width modulated signal with a duty ratio of (N-1) / 2N. Therefore, in accordance with such signal timing, the register units cascaded with the pull-down are all odd or even stages, so that the register units cascaded with each other can be arranged on the same side of the load, and half the number of signal lines can be arranged on the same side of the panel, which is advantageous for realizing a narrow frame panel.

[0011] In order to solve the above problem, the second aspect of the present invention provides a driving and scanning circuit including an even number of signal lines divided into an odd number of signal lines and an even number of signal lines, an assembly connected between the odd number of signal lines and the even number of signal lines, the assembly including a register unit and a pull-down unit, a multi-stage scanning sub-circuit with a load connected between the register unit and the pull-down unit, the register unit and the pull-down unit provided on the same side of the load are alternately arranged, and any two of the register units separated by N stages on one side of the load are cascaded to each other, where N is half the total number of the even number of signal lines. Therefore, the register units and pull-down units provided alternately at a distance from each other can efficiently distribute the signal lines to both sides of the load, halving the number of signal lines on one side, significantly reducing the frame width, and realizing a driving and scanning circuit by a one-sided driving arrangement.

[0012] According to one embodiment of the present invention, in the same assembly, one of the register unit and the pull-down unit is connected between the load and one of the odd-numbered set of signal lines, and the other of the register unit and the pull-down unit is connected between the load and one of the even-numbered set of signal lines. Thus, the signal lines are efficiently distributed on both sides of the load, and the register unit and the pull-down unit in the same assembly are connected to the odd-numbered set of signal lines and the even-numbered set of signal lines located on different sides, and the frame width can be significantly reduced.

[0013] According to an embodiment of the present invention, the register unit and the pull-down unit adjacent to one side of the load are connected to different signal lines of the same set of signal lines, thereby reducing the wiring area occupied by the register unit and the pull-down unit adjacent to one side of the load and significantly reducing the frame width.

[0014] According to an embodiment of the present invention, the number of the even number of signal lines is 2N (N is a positive integer), the multi-stage scanning sub-circuit includes an n-th stage (n is a positive integer) scanning sub-circuit, the register unit in the n-th stage scanning sub-circuit is connected to the i-th signal line, the pull-down unit in the n-th stage scanning sub-circuit is connected to the j-th signal line, if n is an integer multiple of 2N, i=2N, otherwise i=mod(n,2N), if (n+N-1) is an integer multiple of 2N, j=2N, otherwise j=mod(n+N-1,2N). Therefore, it is advantageous to apply to different driving scanning circuits, and realizes the improvement of the driving scanning circuit without affecting the charging of the panel pixels.

[0015] According to an embodiment of the present invention, the number of the even-numbered signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer), and when n≦N, a preset start signal is input to the register unit in the n-th stage scanning sub-circuit, and when n>N, the register unit in the n-th stage scanning sub-circuit outputs a start signal to the register unit in the (n+N)th stage scanning sub-circuit. Therefore, it is advantageous to be applied to different driving scanning circuits, and realizes the improvement of the driving scanning circuits without affecting the charging of panel pixels.

[0016] According to one embodiment of the present invention, the number of transistors included in the register unit is greater than the number of transistors included in the pull-down unit, and therefore the number of transistors included in the pull-down unit is less than the number of transistors included in the register unit, which effectively simplifies the circuit configuration of the pull-down unit and realizes an improvement in the driving and scanning circuit without affecting the charging of the panel pixels.

[0017] According to an embodiment of the present invention, the pull-down unit includes a pull-down transistor, a control terminal of the pull-down transistor is connected to a pulse port, a first terminal of the pull-down transistor is connected to a scan input port, a second terminal of the pull-down transistor is connected to a lower port, and the load is connected between the scan input port of the pull-down unit and the scan output port of the register unit. Thus, the circuit configuration of the pull-down unit is efficiently simplified, and the load is commonly driven using the scan output port of the register unit and the scan input port of the pull-down unit, thereby realizing an improvement in the driving and scanning circuit without affecting the charging of the panel pixels.

[0018] According to one embodiment of the present invention, the number of the even number of signal lines is 2N (N is a positive integer), the even number of signal lines transmit an even number of pulse signals, and in the transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, and each of the pulse signals is configured as a pulse width modulated signal with a duty ratio of (N-1) / 2N. Therefore, since the register units cascaded to the pull-down in accordance with such signal timing are all odd or even stages, the register units cascaded to each other can be arranged on the same side of the load, and half the number of signal lines can be arranged on the same side of the panel, which is advantageous for realizing a narrow frame panel.

[0019] According to one embodiment of the present invention, the adjacent register section and pull-down section are integrally arranged on the same side of the load. Therefore, by drawing the register section and the pull-down section together in the layout, the frame width can be significantly reduced, and by laying them out together, the width of the register section can be reduced, and in addition to reducing the number of signal wirings on one side, the width of the register section after reduction can be reduced to 30% of the original width of the register section, which can be applied to liquid crystal display panels.

[0020] In order to solve the above problems, a third aspect of the present invention provides a display panel including the above-mentioned driving and scanning circuit. Effect of the Invention

[0021] The driving and scanning circuit and display panel of the present invention include the assembly in which each stage of scanning sub-circuits is connected between the odd set of signal lines and the even set of signal lines, the assembly includes the register unit and the pull-down unit, the load is connected between the register unit and the pull-down unit, the register unit and the pull-down unit provided on the same side of the load are alternately arranged, and any two of the register units separated by N stages are cascaded to one side of the load, where N is half the total number of the even number of signal lines. Thus, the signal lines are efficiently distributed to both sides of the load, the number of signal lines on one side is halved, the area required for wiring on one side is reduced, the frame width is greatly reduced, the power consumption and delay are reduced, the driving and scanning circuit is realized by a one-sided driving arrangement, and the circuit improvement is realized without affecting the charging of the panel pixels.

[0022] In the following, in order to more clearly describe the technical means in the embodiments of the present invention, the drawings necessary to be used in the description of the embodiments will be briefly introduced. The drawings in the following description are only some embodiments of the present invention, and it is obvious that those skilled in the art can also derive other drawings from these drawings without creative efforts. [Brief description of the drawings]

[0023] [Figure 1] FIG. 2 is a circuit schematic diagram of a driving and scanning circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit schematic diagram of a register unit according to an embodiment of the present invention. [Diagram 3] FIG. 4 is a circuit schematic diagram of a pull-down section according to an embodiment of the present invention. [Figure 4] 13 is a timing chart showing the pulse waveform of an 8CK configuration and the cascade connection relationship. [Diagram 5] FIG. 2 is a block diagram showing an example of a shift register. [Figure 6] FIG. 1 is a waveform diagram showing the start and reset of a single stage of a shift register. [Figure 7] FIG. 13 is a diagram showing space saving of a mixed layout of a register section and a pull-down section on the same side in an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The technical means in the embodiments of the present invention will be described below clearly and completely with reference to the drawings in the embodiments of the present invention. It is clear that the described embodiments are only some of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments that can be obtained by those skilled in the art without creative labor fall within the scope of protection of the present invention.

[0025] In the description herein, the orientations or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientations or positional relationships shown in the drawings. These terms are merely for ease of and simplicity of description of the invention, and are not intended to indicate or imply that the devices or components referred to have a particular orientation and must be constructed and operated in a particular orientation, and therefore should not be understood as limiting the invention.

[0026] In the present description, the terms "first" and "second" are merely for illustrative purposes and should not be understood to indicate or suggest the relative importance or number of technical features shown. Thus, a feature qualified by "first" or "second" may expressly or imply the inclusion of one or more of said features. In the present description, unless otherwise clearly and specifically stated, "plurality" means two or more.

[0027] In this specification, many different embodiments or examples are provided for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, specific example components and configurations are described below. Of course, these are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numbers and / or reference alphabets in different examples for brevity and clarity, and as such, do not indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, although examples of various specific processes and materials are provided in this specification, those skilled in the art may recognize the application of other processes and / or the use of other materials.

[0028] Finding better narrow-bezel solutions for liquid crystal and light-emitting diode (LED) display panels has always been a research and development focus, as illustrated by, but not limited to, the following examples.

[0029] A first aspect of the present invention provides a drive scanning circuit that is applicable to liquid crystal display panels such as a narrow-frame liquid crystal display panel, but is not limited to this.

[0030] The following description will be given taking the above-mentioned embodiments of the driving and scanning circuit as examples, but the present invention is not limited to these.

[0031] For example, as shown in Fig. 1, the driving scanning circuit includes an even number of signal (CK) lines and a multi-stage scanning sub-circuit D for driving a plurality of horizontal scanning lines in a display panel, and the scanning lines can be regarded as a series connection of a plurality of pixels (e.g., a plurality of pixels arranged in a horizontal direction in a display panel), and a resistive-capacitive load exists in the scanning lines. For example, the number of the even number of signal lines is 2N (N is a positive integer), for example, 2N=2 or 4 or 6 (e.g., 4CK or 6CK is used for small electronic sports screens), or 2N=8 (e.g., 8CK is used for medium-sized televisions, etc.), or 2N=12 or 16 (e.g., 12CK or 16CK is used for high-resolution 8K displays).

[0032] It should be understood that if the number of CK lines is too small, the charging rate may be poor in the panel, and if the number of CK lines is too large, the frame of the panel will be large (not applicable to narrow frame panels). For example, in an 8K display, it is sufficient to adopt a charging rate of 12CK or 16CK, and there is no need to increase the number of CK lines any further. The following will be described using an example in which 10 scan lines adopt 8CK, but the remaining number of CK lines and the number of scan lines can also be applied, but will not be described in detail. In this specification, in order to facilitate the description and prevent the symbols from becoming too complicated, CKn (n is a positive integer) is used to indicate different signal lines and signals to be transmitted, for example, CK1 is used to indicate signal line CK1 or signal CK1 in the paragraph.

[0033] For example, as shown in FIG. 1, taking 8CK as an example, that is, 2N=8, the even number of signal lines (e.g., CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8) are configured to be divided into an odd set of signal lines (e.g., CK1, CK3, CK5, CK7) and an even set of signal lines (e.g., CK2, CK4, CK6, CK8).

[0034] In this example, 10 rows of scanning lines are taken as an example, that is, n=1, 2, 3, ..., 10, and the multiple-stage scanning sub-circuit D includes 10 stages of scanning sub-circuits D, and each stage of scanning sub-circuit D includes an assembly A connected between the odd-numbered set of signal lines (e.g., CK1, CK3, CK5, CK7) and the even-numbered set of signal lines (e.g., CK2, CK4, CK6, CK8), and the assembly A includes a register unit 1 and a pull-down unit 2, and the register unit 1 may be configured as a shift register (also written as GOA) or the like, and the pull-down unit 2 may be configured as a pull-down unit (also written as PDU) or the like, and a load B is connected between the register unit 1 and the pull-down unit 2, and for example, the load B may be configured to include a plurality of pixels connected in series, and the load B has a resistive and capacitive load.

[0035] For ease of explanation, in this example, the assembly A of the first-stage scanning subcircuit D includes a register unit 1 (e.g., GOA1) and a pull-down unit 2 (e.g., PDU1), the assembly A of the second-stage scanning subcircuit D includes a register unit 1 (e.g., GOA2) and a pull-down unit 2 (e.g., PDU2), the assembly A of the third-stage scanning subcircuit D includes a register unit 1 (e.g., GOA3) and a pull-down unit 2 (e.g., PDU3), the assembly A of the fourth-stage scanning subcircuit D includes a register unit 1 (e.g., GOA4) and a pull-down unit 2 (e.g., PDU4), and the assembly A of the fifth-stage scanning subcircuit D includes a register unit 1 (e.g., GOA5) and a pull-down unit 2 (e.g., PDU5). The assembly A of the scanning sub-circuit D in the 6th stage includes a register unit 1 (e.g., GOA 6) and a pull-down unit 2 (e.g., PDU 6), the assembly A of the scanning sub-circuit D in the 7th stage includes a register unit 1 (e.g., GOA 7) and a pull-down unit 2 (e.g., PDU 7), the assembly A of the scanning sub-circuit D in the 8th stage includes a register unit 1 (e.g., GOA 8) and a pull-down unit 2 (e.g., PDU 8), the assembly A of the scanning sub-circuit D in the 9th stage includes a register unit 1 (e.g., GOA 9) and a pull-down unit 2 (e.g., PDU 9), and the assembly A of the scanning sub-circuit D in the 10th stage includes a register unit 1 (e.g., GOA 10) and a pull-down unit 2 (e.g., PDU 10).

[0036] As shown in FIG. 1, the register unit 1 and the pull-down unit 2 in the multiple stages of scanning sub-circuits D may be configured to be arranged alternately in stages on both sides of the load B. For example, the register unit 1 (e.g., GOA1) of the first stage scanning sub-circuit D is on one side (e.g., the left side) of the load B, the pull-down unit 2 (e.g., PDU1) of the first stage scanning sub-circuit D is on the other side (e.g., the right side) of the load B, the pull-down unit 2 (e.g., PDU2) of the second stage scanning sub-circuit D is on one side (e.g., the left side) of the load B, and the pull-down unit 3 (e.g., PDU3) of the second stage scanning sub-circuit D is on the other side (e.g., the right side) of the load B. The register unit 1 (e.g., GOA2) of the first scanning sub-circuit D is on the other side (e.g., the right side) of the load B, the register unit 1 (e.g., GOA3) of the third scanning sub-circuit D is on one side (e.g., the left side) of the load B, the pull-down unit 2 (e.g., PDU3) of the third scanning sub-circuit D is on the other side (e.g., the right side) of the load B, and so on; the pull-down unit 2 (e.g., PDU10) of the tenth scanning sub-circuit D is on one side (e.g., the left side) of the load B, and the register unit 1 (e.g., GOA10) of the tenth scanning sub-circuit D is on the other side (e.g., the right side) of the load B.

[0037] For example, as shown in FIG. 1, the register units 1 and the pull-down units 2 provided on the same side of the load B are arranged alternately. For example, the register units 1 (e.g., GOA1, GOA3, GOA5, GOA7, GOA9) of the odd-numbered scanning sub-circuits D and the pull-down units 2 (e.g., PDU2, PDU4, PDU6, PDU8, PDU10) of the even-numbered scanning sub-circuits D are arranged alternately in stages on one side (e.g., the left side) of the load B. For example, from top to bottom, the register units 1 and the pull-down units 2 are arranged alternately in stages on one side (e.g., the left side) of the load B. The pull-down units 2 (e.g., PDU1, PDU3, PDU5, PDU7, PDU9) of the odd-numbered scanning sub-circuits D and the register units 1 (e.g., GOA2, GOA4, GOA6, GOA8, GOA10) of the even-numbered scanning sub-circuits D are arranged alternately in stages on the other side (e.g., the right side) of the load B, for example, arranged from top to bottom as PDU1, GOA2, PDU3, GOA4, PDU5, GOA6, PDU7, GOA8, PDU9, GOA10, etc.

[0038] For example, as shown in FIG. 1, in the same assembly A, one of the register unit 1 and the pull-down unit 2 is connected between the load B and any one of the signal lines of the odd set of signal lines (e.g., CK1, CK3, CK5, CK7), and the other of the register unit 1 and the pull-down unit 2 is connected between the load B and any one of the signal lines of the even set of signal lines (e.g., CK2, CK4, CK6, CK8), and the register unit 1 and the pull-down unit 2 adjacent to one side of the load B are connected to different signal lines of the same set of signal lines (e.g., the odd set of signal lines CK1, CK3, CK5, CK7 or the even set of signal lines CK2, CK4, CK6, CK8).

[0039] For ease of explanation, in this example, an 8CK that is adapted to eight stages of scanning sub-circuits is taken as the module M, but a single driving scanning circuit may have a plurality of modules M.

[0040] For example, as shown in FIG. 1, in a single module M, the register units 1 (e.g., GOA1, GOA3, GOA5, GOA7) of the scanning sub-circuits D in odd stages (e.g., 1st, 3rd, 5th, 7th stages) are respectively connected to odd sets of signal lines (e.g., CK1, CK3, CK5, CK7), and the register units 1 (e.g., GOA2, GOA4, GOA6, GOA8) of the scanning sub-circuits D in even stages (e.g., 2nd, 4th, 6th, 8th stages) are respectively connected to even sets of signal lines (e.g., CK2, CK4, CK6, CK8). Furthermore, for different modules of the same driving and scanning circuit, the signal line numbers are used cyclically in increasing order from 1 to 8, such as CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK1, CK2, CK3, ..., CK7, CK8, CK1, CK2, CK3, ..., CK7, CK8, etc., so that, for example, in the same assembly A, the signal line of the pull-down unit 2 and the signal line of the register unit 1 can maintain a number difference of (N-1).

[0041] For example, as shown in FIG. 1, taking 2N=8 (N=4) as an example, the signal line of the pull-down unit 2 and the signal line of the register unit 1 can maintain a number difference of (N-1=3). For example, the register unit 1 (e.g., GOA1) of the first-stage scanning sub-circuit D is connected to a signal line CK1, the pull-down unit 2 (e.g., PDU1) of the first-stage scanning sub-circuit D is connected to a signal line CK4, the register unit 1 (e.g., GOA2) of the second-stage scanning sub-circuit D is connected to a signal line CK2, and the pull-down unit 2 (e.g., PDU2) of the second-stage scanning sub-circuit D is connected to a signal line CK3. 5, a register unit 1 (e.g., GOA3) of the third-stage scanning subcircuit D is connected to a signal line CK3, a pull-down unit 2 (e.g., PDU3) of the third-stage scanning subcircuit D is connected to a signal line CK6, a register unit 1 (e.g., GOA4) of the fourth-stage scanning subcircuit D is connected to a signal line CK4, a pull-down unit 2 (e.g., PDU4) of the fourth-stage scanning subcircuit D is connected to a signal line CK7, a register unit 1 (e.g., GOA5) of the fifth-stage scanning subcircuit D is connected to a signal line CK5, and a pull-down unit 2 (e.g., PDU5) of the fifth-stage scanning subcircuit D is connected to a signal line CK6. ) is connected to signal line CK8, the register unit 1 (e.g., GOA6) of the 6th-stage scanning subcircuit D is connected to signal line CK6, the pull-down unit 2 (e.g., PDU6) of the 6th-stage scanning subcircuit D is connected to signal line CK1 (6+3=9, and CK1 is used based on CK1 to CK8), the register unit 1 (e.g., GOA7) of the 7th-stage scanning subcircuit D is connected to signal line CK7, and the pull-down unit 2 (e.g., PDU7) of the 7th-stage scanning subcircuit D is connected to signal line CK2 (7+3=10, and CK2 is used based on CK1 to CK8). the register unit 1 (e.g., GOA8) of the 8th-stage scanning subcircuit D is connected to a signal line CK8, the pull-down unit 2 (e.g., PDU8) of the 8th-stage scanning subcircuit D is connected to a signal line CK3 (8+3=11, and CK3 is used based on CK1 to CK8), the register unit 1 (e.g., GOA9) of the 9th-stage scanning subcircuit D is connected to a signal line CK1, the pull-down unit 2 (e.g., PDU8) of the 9th-stage scanning subcircuit D is connected to a signal line CK4, ..., the register unit (not shown) of the 13th-stage scanning subcircuit is connected to a signal line CK5,The pull-down section (not shown) of the 13th stage scanning subcircuit is connected to signal line CK8, ..., the register section (not shown) of the 16th stage scanning subcircuit is connected to signal line CK8, and the pull-down section (not shown) of the 16th stage scanning subcircuit is connected to signal line CK3, and other connection configurations can be understood based on this explanation.

[0042] For example, as shown in FIG. 1, in an exemplary configuration, the numbers of the signal lines connected to the register unit 1 and the pull-down 2 may be configured based on a rule, for example. For example, the number of the even number of signal lines is 2N (N is a positive integer), the multiple stages of scan subcircuits include an n-th stage (n is a positive integer) scan subcircuit, the register unit in the n-th stage scan subcircuit is connected to the i-th signal line, and the pull-down in the n-th stage scan subcircuit is connected to the i-th signal line. When the down unit is connected to the jth signal line and n is an integer multiple of 2N (for example, n=2N, 4N, 6N, ..., i.e., mod(n, 2N)=0), then i=2N; otherwise, i=mod(n, 2N); and when (n+N-1) is an integer multiple of 2N (for example, (n+N-1)=2N, 4N, 6N, ..., i.e., mod((n+N-1), 2N)=0), then j=2N; otherwise, j=mod(n+N-1, 2N).

[0043] In this example, as shown in FIG. 1, for ease of explanation, the register unit 1 may include, but is not limited to, a first pulse (Sync) port 11, a start input (Start1) port 12, a reset (Reset) port 13 and a scan output (Output1) port 14, and in other configurations, the register unit 1 may include other start input ports and / or scan output ports, and the pull-down unit 2 may include, but is not limited to, a second pulse port 21 and a scan input port 22, and in other configurations, the pull-down unit 2 may include other ports, such as a lower port, and the load B is connected between the scan output port 14 and the scan input port 22.

[0044] For example, as shown in FIG. 2, the register unit 1 may be configured as, for example, a gate driver on array (GOA) circuit, and includes a plurality of transistors including a control terminal, a first terminal and a second terminal, and a capacitor, and the transistor may be, for example, a thin film transistor (TFT) having a gate, a source and a drain, and the register unit 1 includes, for example, an input unit 1A, an output unit 1B, a sustain unit 1C, a first control unit 1D, a second control unit 1E and a reset unit 1F.

[0045] For example, as shown in FIG. 2, the input unit 1A includes a first transistor T11, a control terminal of the first transistor T11 is connected to the start input port 12 for inputting an initial start signal STV or a previous-stage start signal ST(nN), and a first terminal of the first transistor T11 is connected to a previous-stage scanning port 15 for inputting a previous-stage scanning signal G(nN).

[0046] For example, as shown in FIG. 2, the output unit 1B includes a second transistor T21, a third transistor T22, and a capacitor Cbt, in which the control terminal of the second transistor T21 and the control terminal of the third transistor T22 are connected to the second terminal of the first transistor T11 to form a first contact Q, the first terminal of the second transistor T21 and the first terminal of the third transistor T22 are connected to a pulse port, such as a first pulse port 11 for inputting a first pulse signal CK(i), the second terminal of the second transistor T21 is connected to the scanning output port 14 for outputting the n-th stage scanning signal G(n), the second terminal of the third transistor T22 is connected to a reset port 13 for outputting the n-th stage start signal ST(n), and the capacitor Cbt is connected between the control terminal and the second terminal of the second transistor T21.

[0047] For example, as shown in FIG. 2, the sustain unit 1C includes a fourth transistor T31 and a fifth transistor T41, a control terminal of the fourth transistor T31 and a control terminal of the fifth transistor T41 are connected to a subsequent scanning port 16 for inputting a subsequent scanning signal G(n+N), a first terminal of the fourth transistor T31 is connected to the scanning output port 14, a second terminal of the fourth transistor T31 is connected to a first lower port 19 for inputting a first lower signal VSSG, a first terminal of the fifth transistor T41 is connected to the first contact Q, and a second terminal of the fifth transistor T41 is connected to a second lower port 1a for inputting a second lower signal VSSQ.

[0048] For example, as shown in FIG. 2, the first control unit 1D includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, a ninth transistor T54, a tenth transistor T32 and an eleventh transistor T42, in which a control terminal and a first terminal of the sixth transistor T51 and a first terminal of the eighth transistor T53 are connected to a first control port 17 for inputting a first control signal LC1, a second terminal of the sixth transistor T51 is connected to a first terminal of the seventh transistor T52 and a control terminal of the eighth transistor T53, and a control terminal of the seventh transistor T52 and a control terminal of the ninth transistor T54 are connected to a first control port 17 for inputting a first control signal LC1. a terminal connected to the second terminal of the first transistor T11, a second terminal of the seventh transistor T52, a second terminal of the ninth transistor T54, a second terminal of the tenth transistor T32 and a second terminal of the eleventh transistor T42 connected to the second lower port 1a, a second terminal of the eighth transistor T53 connected to the first terminal of the ninth transistor T54, a control terminal of the tenth transistor T32 and a control terminal of the eleventh transistor T42, a first terminal of the tenth transistor T32 connected to the scanning output port 14, and a first terminal of the eleventh transistor T42 connected to the first contact Q.

[0049] For example, as shown in FIG. 2, the second control unit 1E includes a twelfth transistor T61, a thirteenth transistor T62, a fourteenth transistor T63, a fifteenth transistor T64, a sixteenth transistor T33 and a seventeenth transistor T43, in which a control terminal and a first terminal of the twelfth transistor T61 and a first terminal of the fourteenth transistor T63 are connected to a second control port 18 for inputting a second control signal LC2, a second terminal of the twelfth transistor T61 is connected to a first terminal of the thirteenth transistor T62 and a control terminal of the fourteenth transistor T63, and a control terminal of the thirteenth transistor T62 and a seventeenth transistor T43 are connected to a second control port 18 for inputting a second control signal LC2. The fourth control terminal is connected to the second terminal of the first transistor T11, the second terminal of the thirteenth transistor T62, the second terminal of the fifteenth transistor T64, the second terminal of the sixteenth transistor T33 and the second terminal of the seventeenth transistor T43 are connected to the second lower port 1a, the second terminal of the fourteenth transistor T63 is connected to the first terminal of the fifteenth transistor T64, the control terminal of the sixteenth transistor T33 and the control terminal of the seventeenth transistor T43, the first terminal of the sixteenth transistor T33 is connected to the scanning output port 14, and the first terminal of the seventeenth transistor T43 is connected to the first contact Q.

[0050] For example, as shown in FIG. 2, the reset unit 1F includes an 18th transistor T44, a control terminal of the 18th transistor T44 is connected to a reset (Re-setup) port 10 for inputting a reset signal RST, a first terminal of the 18th transistor T44 is connected to the first contact Q, and a second terminal of the 18th transistor T44 is connected to the second lower port 1a.

[0051] In this example, as shown in FIG. 1 and FIG. 2, taking N=4 as an example, the first pulse port 11 may be configured to input the first pulse signal CK(i), for example, a pulse signal from one of the even number of signal lines (for example, CK1 to CK8); the start input port 12 of the register unit 1 of the 1st to 4th stage scanning sub-circuits D may input the initial start signal STV; the start input port 12 of the register unit 1 of the nth (n>4) stage scanning sub-circuit D may input the (n-4) stage start signal ST(n-4), i.e., the start signal from the register unit 1 of the (n-4) stage scanning sub-circuit D; the reset port 13 may output the nth stage start signal ST(n); the scanning output port 14 may output the nth stage scanning signal G(n); and the nth stage scanning signal G(n) is output to a load B of the nth stage scanning sub-circuit D, for example, the load B for driving a plurality of serially connected pixels in the nth row scanning line.

[0052] For example, as shown in FIG. 1, in the driving scanning circuit, any two of the register units 1 (for example, GOA1, GOA5, GOA9, ..., not limited thereto) on one side of the load B are cascade-connected to each other, for example, the number of the even number of signal lines is 2N (N is a positive integer) (in this example, N=4), the multiple-stage scanning subcircuit D includes an n-th stage (n is a positive integer) scanning subcircuit D, and when n≦N, the register unit 1 in the n-th stage scanning subcircuit D inputs the preset start signal STV, and when n>N, the register unit 1 in the n-th stage scanning subcircuit D outputs the start signal ST(n) to the start input port 12 of the register unit 1 in the (n+N)th stage scanning subcircuit D.

[0053] For example, as shown in Fig. 1 and Fig. 3, the pull-down unit 2 includes a pull-down transistor T, but is not limited thereto, and the pull-down unit 2 may further include other members (e.g., other transistors, etc.), and a control terminal of the pull-down transistor T is connected to a pulse port such as a second pulse port 21 for inputting a second pulse signal CK(j) such as a pulse signal from one of the even number of signal lines CK1 to CK8, a first terminal of the pull-down transistor T is connected to a scan input port 22 for inputting an n-th stage scanning signal G(n) passing through a load B of an n-th stage scanning sub-circuit D, and a second terminal of the pull-down transistor T is connected to a lower port 23 for inputting the first lower signal VSSG. In this example, the second pulse signal CK(j) can guide the n-th stage scanning signal G(n) passing through the load B of the n-th stage scanning sub-circuit D to the lower port 23.

[0054] The operation of the driving and scanning circuit according to the embodiment of the present invention will be described below by taking as an example the driving and scanning circuit belongs to a pull-down GOA architecture with one-sided driving, as shown in Fig. 1, taking 2N=8 as an example, the odd-numbered set of signal lines CK1, CK3, CK5, CK7 are arranged on one side of the load B, and the even-numbered set of signal lines CK2, CK4, CK6, CK8 are arranged on the other side of the load B, so as to halve the number of signal lines on one side, which is advantageous for application to a narrow frame panel. In addition, on both sides of the load B, the register unit 1 and the pull-down unit 2 of the assembly A are arranged alternately for each row in the horizontal direction, and the register unit 1 can output the scanning signal for driving the scanning line, and in this example, the pull-down unit 2 is a single thin film transistor, which is controlled by a periodic square wave signal that is a pulse signal, and when the pulse signal is at a high level, the drain and source are conducted to pull down the potential of the scanning line. In addition, the register section 1 and the pull-down section 2 are arranged alternately in the vertical direction on one side of the load B, and for a square wave signal of one stage of gate, the rising edge is driven only by the register section 1, and the falling edge is driven commonly by the register section 1 and the pull-down section 2, and for the precharge gate waveform, the speed of the falling edge is a key factor affecting in-plane charging.

[0055] As shown in FIG. 4, the operation principle of the above-mentioned architecture is explained by taking 2N=8 as an example, and the timing of the 8CK architecture. For simplicity, G1, G2, G3, ..., G27 indicate the gate timing of the register unit in the 1st, 2nd, 3rd, ..., 27th stage scanning sub-circuits, and GOA1, GOA2, ... are used to indicate the register unit 1 in different scanning sub-circuits in FIG. 1. All pulse signals CK (for example, CK1 to CK8) are square wave signals with periodic waveforms, and the high level voltage of the square wave pulse signal is CKH and the low level voltage is CKL. For 2N CK systems, the duty ratio of the pulse signal CK is (N-1) / 2N.

[0056] In the timing diagram shown in FIG. 4, the high-level periods of CK are indicated by elongated boxes (e.g., G1, G2, G3, ..., G5, ..., G9, ..., G26, G27, ..., but not limited to these), and the timing of their rising edges is indicated by the digital scale in the numbered boxes above. During scanning operation, the gate signal of each stage synchronizes with the high-level square wave of CK and then maintains a low-level state. For example, for G1 driven by signal line CK1, the signal synchronized with G1 is shown by the G1 waveform in the figure. For simplicity, the high-level pulse synchronized with each gate signal is shown in the high-level box of CK. In this architecture, the cascade connection of start is shown by the same type of box.

[0057] For example, in Fig. 1 and Fig. 4, the start signal STV starts the register units 1 of the first stage to the nth stage (for example, GOA1 to GOA(n)), and in the case of an 8CK system, the register units 1 of the first four stages (for example, GOA1 to GOA4) use the start signal STV as a start signal. Then, as shown in the box, GOA1 supplies a start signal to GOA5 (for example, in Fig. 4, the frames of G1 and G5 are both thin lines), and GOA5 supplies a start signal to GOA9 (for example, in Fig. 4, the frames of G5 and G9 are both thin lines), and further, the order is GOA13, GOA17, GOA21, and GOA25 (for example, in Fig. 4, the frames of G13, G17, G21, and G25 are all thin lines), and the same applies to the remaining signals having the same frame lines, so their description will be omitted. However, the pull-down action of the gate of each stage is initiated by the pull-down section 2 on the opposite side of the register 1, i.e., it provides a pull-down reset, and the cascaded relationship is shown by the vertical lines in the figure. For example, PDU1 on the opposite side of GOA1 is driven by a square wave pulse provided to GOA4 from signal line CK4, so that GOA1 becomes out of sync with signal CK1 at time 4. The other pull-down relationships correspond to it.

[0058] As can be seen from FIG. 4, in the transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, for example, the high level period (e.g., G2) of pulse signal CK2 is delayed by one time unit from the high level period (e.g., G1) of pulse signal CK1, the high level period (e.g., G3) of pulse signal CK3 is delayed by one time unit from the high level period (e.g., G2) of pulse signal CK2, and the remaining signals are similar, and each of the pulse signals is configured as a pulse width modulated signal with a duty ratio of (N-1) / 2N.

[0059] In addition, the duty ratio of (N-1) / (2N) is a key factor for realizing the driving function of this single-sided driving GOA-PDU, so that the GOAs cascaded to the pulldown are all odd or even stages according to such timing, and it is only necessary to arrange the cascaded GOAs on one side of the load (e.g., the pixels of the panel) and arrange half the number of CK signal lines on the same side of the panel, which is advantageous for realizing a narrow frame panel. The number of CKs required for the pulldown PDU of each stage causes odd-even conversion, for example, the CK connected to the PDU of the odd stage GOA is an even CK, and the even CK is on the opposite side of the odd CK. For example, as shown in FIG. 1, the odd CK on one side (e.g., the left side) provides the driving of the odd stage GOA and the driving of the even stage PDU, while the even CK on the other side (e.g., the right side) drives the even stage GOA and provides the pulldown driving to the odd stage PDU. Therefore, the CK wiring on each side is saved by half compared to the conventional panel. Method embodiments of the present invention are also applicable to architectures with other numbers of CKs, such as 2N=12 and 2N=16.

[0060] In a specific example, as shown in FIG. 5, for example, an exemplary shift register 1′ includes a plurality of ports 11′, 12′, 13′, 14′, 15′, 16′, 17′, 18′, 19′ and 1a′, where the port 11′ is for inputting signals CK(1) to CK(2N) as a sync signal, the ports 12′ and 15′ are for inputting signals ST(nN) and G(nN) as two start signals, the port 13′ is for outputting a signal ST(n), the port 14′ is for outputting a signal G(n), the port 15′ is for inputting a signal G(nN), the port 16′ is for inputting a signal G(n+N) as a reset signal, the ports 17′ and 18′ are for inputting signals LC1 and LC2, and the ports 19′ and 1a′ are for inputting signals VSSG and VSSQ.

[0061] Signals LC1 and LC2 are high level signals, signals VSSG and VSSQ are low level DC signals, these two signals are pull-down holding power signal lines of the shift register, signals LC1, LC2 and signals VSSG, VSSQ can be simplified as signals LC and VSS, the two start signals are synchronous start signals, when the two start signals are both high level, the shift register 1' is activated, at this time ports 13', 14' start to synchronize the signal connected to port 11', the GOA circuit is driven by 2N CK lines, signals G(nN) and ST(nN) are two start connection signals of the nth stage shift register 1', and signal G(n+N) or ST(n+N) is the reset signal of the shift register 1'.

[0062] In the first stage shift register 1', when there is no output from the previous stage as a start signal, a start signal can be supplied to ports 12' and 15' through an independent start (STV) line. Figure 6 shows the GOA timing driven by 8CK, where ST(n-4) and G(n-4) are square wave pulse signals advanced by half a CK period, and G(N+4) is a square wave pulse signal delayed by half a period, the nth stage shift register synchronizes the CK signal starting from the rising timing of ST(n-4) (STV(n-4) shown in the figure) and G(n-4), and the timing at which it becomes out of sync is the rising timing of G(n+4), the output signals of the shift register 1' are ST(n) and G(n), and the signal of the first contact in the shift register 1' is Q(n).

[0063] In the comparative example, for example, one scanning subcircuit of a double-sided driving scanning circuit includes two shift registers 1' on both sides of a load, and has one shift register 1' on each side of the load, and for example, the shift register 1' includes the GOA circuits from the first transistor to the 18th transistor described above, and in the comparative example, the shift register 1' includes 18 transistors and a capacitor, whereas one scanning subcircuit D of a single-sided driving scanning circuit of the above-mentioned embodiment includes the register unit 1 and the pull-down unit 2 on both sides of the load B, and has only the register unit 1 or the pull-down unit 2 on one side of the load B, and the pull-down unit 2 has only one transistor. Comparing the two, the number of elements (e.g., transistors) of the pull-down unit 2 on one side of the load and the shift register 1' on the other side is significantly different. In the pull-down units on the same side, the cascade connection relationship of the plurality of pull-down units coincides with the cascade connection relationship of the plurality of register units, for example, the reset signal of the pull-down unit 2 (e.g., PDU1) is the output signal of the pull-down unit 2 (e.g., PDU5), and the reset signal of another pull-down unit 2 (e.g., PDU3) is the output signal of the pull-down unit (e.g., PDU7), and the like. When adjacent register units and pull-down units on the same side are arranged integrally, for example, by drawing them mixed together in the layout, as shown in FIG. 7, the left side shows the width W1 of the GOA in which the adjacent register units and pull-down units on the same side are not arranged integrally, and the right side shows the width W2 of the GOA in which the adjacent register units and pull-down units on the same side are arranged integrally. From the figure, it can be seen that the width of the GOA can be reduced from W1 to W2 by arranging the adjacent register units and pull-down units on the same side integrally, and in addition to the reduction in the number of CK wirings on one side, the reduction amount of the GOA width after reduction is 30% of the original GOA width.

[0064] As shown below, Table 1 is data for comparing the waveforms of the shift register 1' of the comparative example and the assembly A of the embodiment using a liquid crystal panel. The high and low levels of the signal CK are 30V and -10V, and by measuring the rising edge (rising, abbreviated as rising) and falling edge (falling, abbreviated as falling) times of the gate square wave of 9 points (left-center-right-upper-middle-lower), it can be seen that the rising and falling times of the right-down are the longest and the maximum load point. The width W2 of the GOA in FIG. 7 (where the pull-down section and the register section adjacent to each other are integrally arranged on the same side) is larger in rise time than the width W1 of the GOA in FIG. 7 (where the pull-down section and the register section adjacent to each other are not integrally arranged on the same side), which is about twice as long, but the fall time (which is an important index that affects the charging of in-plane pixels) is not significantly different. Therefore, the original fall time can be realized by optimizing the size of the thin film transistors of the register section and the pull-down section in the assembly.

[0065] Table 1 Comparison of load waveforms for different architectures [Table 1]

[0066] Several examples of the driving and scanning circuit are given below, but the present invention is not limited to these.

[0067] One aspect of the present invention provides a driving and scanning circuit including an even number of signal lines divided into an odd number of signal lines and an even number of signal lines, an assembly connected between the odd number of signal lines and the even number of signal lines, the assembly including a register unit and a pull-down unit, a multi-stage scanning sub-circuit with a load connected between the register unit and the pull-down unit, the register unit and the pull-down unit provided on the same side of the load are alternately arranged, and any two of the register units separated by N stages on one side of the load are cascaded to each other, where N is half the total number of the even number of signal lines. Thus, the register units and pull-down units provided alternately at a distance from each other can efficiently distribute the signal lines to both sides of the load, halving the number of signal lines on one side, significantly reducing the frame width, and realizing a driving and scanning circuit by a one-sided driving arrangement.

[0068] Optionally, in one embodiment, in the same assembly, one of the resistor unit and the pull-down unit is connected between the load and one of the odd set of signal lines, and the other of the resistor unit and the pull-down unit is connected between the load and one of the even set of signal lines, so that the resistor unit and the pull-down unit in the same assembly are connected to the odd set of signal lines and the even set of signal lines located on different sides of the load by effectively distributing signal lines on both sides of the load, and the frame width can be significantly reduced.

[0069] Optionally, in one embodiment, the resistor unit and the pull-down unit adjacent to one side of the load are connected to different signal lines of a same set of signal lines, thereby reducing the wiring area occupied by the resistor unit and the pull-down unit adjacent to one side of the load and significantly reducing the frame width.

[0070] Optionally, in one embodiment, the number of the even number of signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer) of scanning sub-circuits, the register unit in the n-th stage of scanning sub-circuit is connected to the i-th signal line, the pull-down unit in the n-th stage of scanning sub-circuit is connected to the j-th signal line, if n is an integer multiple of 2N, i=2N, otherwise, i=mod(n,2N), if (n+N-1) is an integer multiple of 2N, j=2N, otherwise, j=mod(n+N-1,2N). Thus, it is advantageous to apply to different driving and scanning circuits, and realizes the improvement of the driving and scanning circuits without affecting the charging of panel pixels.

[0071] Optionally, in one embodiment, the number of the even-numbered signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer) scanning sub-circuit, and if n≦N, a preset start signal is input to the register unit in the n-th stage scanning sub-circuit, and if n>N, the register unit in the n-th stage scanning sub-circuit outputs a start signal to the register unit in the (n+N)th stage scanning sub-circuit. Thus, it is advantageous to be applied to different driving scanning circuits, and realizes an improvement of the driving scanning circuits without affecting the charging of panel pixels.

[0072] Optionally, in one embodiment, the number of transistors included in the register section is greater than the number of transistors included in the pull-down section, so that the number of transistors included in the pull-down section is less than the number of transistors included in the register section, effectively simplifying the circuit configuration of the pull-down section and realizing an improvement in the driving and scanning circuit without affecting the charging of panel pixels.

[0073] Optionally, in one embodiment, the pull-down unit includes a pull-down transistor, a control terminal of the pull-down transistor is connected to a pulse port, a first terminal of the pull-down transistor is connected to a scan input port, a second terminal of the pull-down transistor is connected to a lower port, and the load is connected between the scan input port of the pull-down unit and the scan output port of the register unit, thus efficiently simplifying the circuit configuration of the pull-down unit and achieving an improvement in the driving and scanning circuit by commonly driving the load using the scan output port of the register unit and the scan input port of the pull-down unit without affecting the charging of panel pixels.

[0074] Optionally, in one embodiment, the number of the even number of signal lines is 2N (N is a positive integer), the even number of signal lines transmit an even number of pulse signals, and in a transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, and each of the pulse signals is configured as a pulse width modulated signal having a duty ratio of (N-1) / 2N. Therefore, in accordance with such signal timing, the register units cascaded to the pull-down are all odd or even stages, so that the register units cascaded to each other can be arranged on the same side of the load, and half the number of signal lines can be arranged on the same side of the panel, which is advantageous for realizing a narrow frame panel.

[0075] Optionally, in one embodiment, the adjacent resistor unit and pull-down unit on the same side of the load are integrally arranged. Therefore, by drawing the resistor unit and the pull-down unit in a mixed manner in the layout, the frame width can be significantly reduced, and by laying them out in a mixed manner, the width of the resistor unit can be reduced, and in addition to reducing the number of signal lines on one side, the width saving of the resistor unit after reduction can be 30% of the width of the original resistor unit, which can be applied to liquid crystal display panels.

[0076] Another aspect of the present invention provides a display panel, such as a liquid crystal display panel, comprising the above-mentioned driving and scanning circuit, the implementation and beneficial effects of which have been described above and will not be described in further detail.

[0077] The driving and scanning circuit and display panel of the above-mentioned embodiment of the present invention includes the assembly in which each stage of scanning sub-circuits is connected between the odd set of signal lines and the even set of signal lines, the assembly includes the register unit and the pull-down unit, the load is connected between the register unit and the pull-down unit, the register unit and the pull-down unit provided on the same side of the load are arranged alternately, and any two of the register units separated by N stages are cascaded to one side of the load, where N is half the total number of the even number of signal lines. Thus, the signal lines are efficiently distributed to both sides of the load, the number of signal lines on one side is halved, the area required for wiring on one side is reduced, the frame width is greatly reduced, the power consumption and delay are reduced, the driving and scanning circuit is realized by a one-sided driving arrangement, and the circuit improvement is realized without affecting the charging of the panel pixels.

[0078] The above describes the embodiments of the present invention in detail. Although the principles and embodiments of the present invention have been described using specific examples, the description of the above embodiments is merely intended to aid in the understanding of the technical means and meaning of the present invention. Those skilled in the art should understand that the technical means described in each of the above embodiments can still be modified or some of the technical features can be replaced with equivalents, as long as the meaning of the corresponding technical means does not deviate from the scope of the technical means of each of the embodiments of the present invention.

Claims

1. an even number of signal lines divided into an odd number of signal lines CK 2M-1 (M is a positive integer) and an even number of signal lines CK 2M (M is a positive integer); each of the odd-numbered sets of signal lines and the even-numbered sets of signal lines, the assembly including a register section and a pull-down section, a load connected between the register section and the pull-down section, the load including a plurality of stages of scanning sub-circuits which are pixels of a display panel; the resistor units and the pull-down units provided on the same side of the load are alternately arranged, and any two resistor units separated by N stages are cascaded to one side of the load, N being half the total number of the even number of signal lines; The resistor unit and the pull-down unit adjacent to one side of the load are connected to different signal lines of a same set of signal lines, and the resistor unit and the pull-down unit adjacent to the same side of the load are integrally arranged; a driving scanning circuit in which the number of the even number of signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer) scanning sub-circuit, the register unit in the n-th stage scanning sub-circuit is connected to a signal line CK i, the pull-down unit in the n-th stage scanning sub-circuit is connected to a signal line CK j, if n is an integer multiple of 2N, then i=2N, otherwise, i=mod(n, 2N), if (n+N-1) is an integer multiple of 2N, then j=2N, otherwise, j=mod(n+N-1, 2N).

2. 2. The driving and scanning circuit according to claim 1, wherein in the same assembly, one of the register unit and the pull-down unit is connected between the load and one of the odd-numbered set of signal lines, and the other of the register unit and the pull-down unit is connected between the load and one of the even-numbered set of signal lines.

3. 2. The driving scanning circuit according to claim 1, wherein the number of the even-numbered signal lines is 2N (N is a positive integer), the multiple stages of scanning subcircuits include an n-th stage (n is a positive integer), and when n≦N, a preset start signal is input to the register unit in the n-th stage scanning subcircuit, and when n>N, the register unit in the n-th stage scanning subcircuit outputs a start signal to the register unit in the (n+N)th stage scanning subcircuit.

4. 2. The driving and scanning circuit according to claim 1, wherein the number of transistors included in the register section is greater than the number of transistors included in the pull-down section.

5. 2. The driving and scanning circuit of claim 1, wherein the pull-down section includes a pull-down transistor, a control terminal of the pull-down transistor is connected to a pulse port, a first terminal of the pull-down transistor is connected to a scan input port, a second terminal of the pull-down transistor is connected to a lower port, and the load is connected between the scan input port of the pull-down section and the scan output port of the register section.

6. 2. The driving and scanning circuit according to claim 1, wherein the number of the even number of signal lines is 2N (N is a positive integer), the even number of signal lines transmit an even number of pulse signals, and in a transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, and each of the pulse signals is configured as a pulse width modulation signal having a duty ratio of (N-1) / 2N.

7. an even number of signal lines divided into an odd number of signal lines CK 2M-1 (M is a positive integer) and an even number of signal lines CK 2M (M is a positive integer); a plurality of stages of scanning sub-circuits each including an assembly connected between the odd set of signal lines and the even set of signal lines, the assembly including a register section and a pull-down section, a load connected between the register section and the pull-down section, the load being a pixel of a display panel; the resistor units and the pull-down units provided on the same side of the load are alternately arranged, and any two resistor units separated by N stages are cascaded to one side of the load, N being half the total number of the even number of signal lines; a driving scanning circuit in which the number of the even number of signal lines is 2N (N is a positive integer), the multiple stages of scanning sub-circuits include an n-th stage (n is a positive integer) scanning sub-circuit, the register unit in the n-th stage scanning sub-circuit is connected to a signal line CK i, the pull-down unit in the n-th stage scanning sub-circuit is connected to a signal line CK j, if n is an integer multiple of 2N, then i=2N, otherwise, i=mod(n, 2N), if (n+N-1) is an integer multiple of 2N, then j=2N, otherwise, j=mod(n+N-1, 2N).

8. 8. The driving and scanning circuit according to claim 7, wherein, in the same assembly, one of the register unit and the pull-down unit is connected between the load and one of the odd-numbered set of signal lines, and the other of the register unit and the pull-down unit is connected between the load and one of the even-numbered set of signal lines.

9. The driving and scanning circuit of claim 7 , wherein the register unit and the pull-down unit adjacent to one side of the load are connected to different signal lines of a same set of signal lines.

10. 8. The driving scanning circuit according to claim 7, wherein the number of the even-numbered signal lines is 2N (N is a positive integer), the multiple stages of scanning subcircuits include an n-th stage (n is a positive integer), and when n≦N, a preset start signal is input to the register unit in the n-th stage scanning subcircuit, and when n>N, the register unit in the n-th stage scanning subcircuit outputs a start signal to the register unit in the (n+N)th stage scanning subcircuit.

11. 8. The driving and scanning circuit according to claim 7, wherein the number of transistors included in the register section is greater than the number of transistors included in the pull-down section.

12. 8. The driving and scanning circuit of claim 7, wherein the pull-down section includes a pull-down transistor, a control terminal of the pull-down transistor is connected to a pulse port, a first terminal of the pull-down transistor is connected to a scan input port, a second terminal of the pull-down transistor is connected to a lower port, and the load is connected between the scan input port of the pull-down section and the scan output port of the register section.

13. 8. The driving and scanning circuit according to claim 7, wherein the number of the even number of signal lines is 2N (N is a positive integer), the even number of signal lines transmit an even number of pulse signals, and in a transmission configuration, of two successively adjacent pulse signals, the next pulse signal is delayed by one time unit from the previous pulse signal, and each of the pulse signals is configured as a pulse width modulation signal having a duty ratio of (N-1) / 2N.

14. 8. The driving and scanning circuit according to claim 7, wherein the resistor section and the pull-down section adjacent to the same side of the load are integrally disposed.

15. A display panel comprising the drive scanning circuit according to claim 7.

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