CIRCUIT DEVICE AND ELECTRO-OPTICAL DEVICE

Abstract

To provide a circuit device and the like that can increase a demultiplexing number through a reduction of writing errors due to leakage current.SOLUTION: A circuit device 100 includes: a selection signal output circuit 130 that outputs selection signals SEL1-SEL4 to a switch circuit 210 based on first to fourth driving orders of demultiplex drive; and a data line driving circuit 110 that outputs first to fourth data signals to a data signal supply line SL1 according to the first to fourth driving orders. In the first driving order, the selection signal output circuit 130 activates the i-th selection signal SELi, and the data line driving circuit 110 outputs the i-th data signal to the i-th data line DLi. In this case, after the first to fourth driving orders, the circuit device performs a rewriting operation in which the selection signal output circuit 130 activates the i-th selection signal SELi and the data line driving circuit 110 outputs the i-th data signal to the i-th data line DLi.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit device, an electro-optical device, and the like. [Background technology]

[0002] Demultiplex driving is known as a driving method for electro-optical devices. When the number of data lines to be demultiplexed is X, a demultiplexer consisting of X switches is provided between a data signal supply line and the X data lines. The electro-optical device first precharges the X data lines by turning on all of the X switches and outputting a precharge voltage to the data signal supply line. Next, the electro-optical device selects the X data lines one by one by turning on the X switches one by one, and writes a data signal to the pixel of each data line by outputting a data signal corresponding to the pixel of each data line to the data signal supply line.

[0003] A conventional technique for demultiplex driving is disclosed in Patent Document 1. In the electro-optical device of Patent Document 1, when X data lines are selected one by one, the first data line selected in a horizontal scanning period is selected twice in succession, and the same data signal is written twice to the data line, thereby preventing insufficient writing to pixel electrodes in common inversion driving. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-178525 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the above demultiplex drive, when the first switch is turned on after precharge and a data signal is written to the pixel of the first data line, the remaining X-1 switches are off and the precharge voltage is held in the X-1 data lines connected to it. At this time, one end of the X-1 switches is a data signal and the other end is the precharge voltage, so the data signal of the data signal supply line is affected by the leak current of the X-1 switches. Since this data signal is the data signal written to the pixel of the first data line, the data signal generates an error with respect to the target voltage. As the data lines are selected one by one, the number of switches that generate a leak decreases from X-1 to X-2, ..., to 1, so the data line selected first in the demultiplex drive is most affected by the leak current. In other words, the target voltage differs between the first data line and the last data line, which may be visually recognized as unevenness in the image.

[0006] It is considered that the writing error of the data signal due to such leakage current becomes larger as the demultiplexing number increases. It is possible to increase the demultiplexing number for the purpose of reducing the number of driving amplifiers to reduce power consumption or increasing the pixel count of an electro-optical panel, but there is a problem that the writing error due to the leakage current becomes an obstacle when increasing the demultiplexing number. [Means for solving the problem]

[0007] One aspect of the present disclosure is a circuit device for driving an electro-optical panel including a switch circuit provided between first to nth data lines (n is an integer of 3 or more) and a data signal supply line, the circuit device including: a selection signal output circuit that outputs first to nth selection signals to the switch circuit, the first to nth selection signals controlling connections between the first to nth data lines and the data signal supply line based on a first to nth drive order of a demultiplex drive; and a data line drive circuit that outputs first to nth data signals corresponding to the first to nth data lines to the data signal supply line in the first to nth drive order; This relates to a circuit device that performs a rewrite operation in which, in a first driving order of the 1st to nth driving orders, the selection signal output circuit activates the ith selection signal (i is an integer greater than or equal to 1 and less than or equal to n) of the 1st to nth selection signals and the data line driving circuit outputs the ith data signal of the 1st to nth data signals to the ith data line of the 1st to nth data lines, after the 1st to nth driving orders, the selection signal output circuit activates the ith selection signal and the data line driving circuit outputs the ith data signal to the ith data line.

[0008] Another aspect of the present disclosure relates to an electro-optical device including the circuit device described above and the electro-optical panel. [Brief description of the drawings]

[0009] [Figure 1] An example of the configuration of an electro-optical panel. [Diagram 2] 1 shows an example of the configuration of a circuit device. [Diagram 3] 11A and 11B are diagrams for explaining a write error caused by a leakage current in the conventional demultiplex driving. [Figure 4] 11A and 11B are diagrams for explaining a write error caused by a leakage current in the conventional demultiplex driving. [Diagram 5] 11A and 11B are diagrams for explaining a write error caused by a leakage current in the conventional demultiplex driving. [Figure 6] FIG. 4 is a waveform diagram illustrating a first driving technique in the present embodiment. [Figure 7] 5A to 5C are diagrams for explaining the relationship between the reduction of writing errors and display in the first operation example. [Figure 8] 3 shows a first detailed configuration example of a display control circuit. [Figure 9] An example of the operation of the multiplexing circuit. [Figure 10] FIG. 4 is a waveform diagram illustrating a second driving technique in the present embodiment. [Figure 11] 13A to 13C are diagrams for explaining the relationship between the reduction of writing errors and display in the second operation example. [Figure 12] 13A to 13C are diagrams for explaining the relationship between the reduction of writing errors and display in the second operation example. [Figure 13] 13 shows a second detailed configuration example of a display control circuit. [Figure 14] FIG. 11 is a waveform diagram illustrating the operation of the second detailed configuration example. [Figure 15] 1 shows an example of the configuration of an electro-optical device and an example of the configuration of a system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0011] 1. Circuit devices, electro-optical panels Fig. 1 shows a configuration example of an electro-optical panel 200 driven by a circuit device 100 of this embodiment, and Fig. 2 shows a configuration example of the circuit device 100 of this embodiment. Note that, although the number of demultiplexes is 4 in the following, the number of demultiplexes may be n, where n is an integer equal to or greater than 3.

[0012] First, the electro-optical panel 200 of Fig. 1 will be described. The electro-optical panel 200 is an active matrix type display panel driven by a demultiplex driving method, such as a liquid crystal display panel or an EL display panel. EL is an abbreviation for Electro Luminescence. The electro-optical panel 200 includes data signal input terminals TDI1 to TDIp, data signal supply lines SL1 to SLp, selection signal input terminals TSI1 to TSI4, selection signal lines LL1 to LL4, a switch circuit 210, data lines DL1 to DLm, scanning signal lines GL1 to GLk, and a plurality of pixels PX. p is an integer of 2 or more. m is an integer obtained by multiplying p by the number of demultiplexes. k is an integer of 2 or more.

[0013] One end of the selection signal line LL1 is connected to the selection signal input terminal TSI1. Similarly, one ends of the selection signal lines LL2 to LL4 are connected to the selection signal input terminals TSI2 to TSI4. One end of the data signal supply line SL1 is connected to the data signal input terminal TDI1. Similarly, one ends of the data signal supply lines SL2 to SLp are connected to the data signal input terminals TDI2 to TDIp.

[0014] The switch circuit 210 includes transistors SD1 to SDm. The transistors SD1 to SDm operate as switches and are, for example, N-type transistors formed of TFTs (Thin Film Transistors). Either the source or the drain of the transistors SD1 to SD4 is commonly connected to the other end of the data signal supply line SL1. The other of the source or the drain of the transistor SD1 is connected to one end of the data line DL1. Similarly, the other of the source or the drain of the transistors SD2 to SD4 is connected to one end of the data lines DL2 to DL4. The gate of the transistor SD1 is connected to a selection signal line LL1. Similarly, the gates of the transistors SD2 to SD4 are connected to selection signal lines LL2 to LL4. The same configuration as that of the transistors SD2 to SD4 is repeated in the transistors SD5 to SDm.

[0015] The pixels PX are m×k pixels. One pixel PX is connected to one of the data lines DL1 to DLm and one of the scanning signal lines GL1 to GLk. The electro-optical panel 200 may include a scanning driver (not shown) that outputs scanning signals to the scanning signal lines GL1 to GLk. Alternatively, the scanning driver may be provided in the circuit device 100.

[0016] Next, the circuit device 100 of Fig. 2 will be described. The circuit device 100 is a display driver that drives an electro-optical panel 200, and is an integrated circuit device in which circuit elements are configured on a substrate by a semiconductor process. The circuit device 100 includes a data line driving circuit 110, a processing circuit 120, a selection signal output circuit 130, an interface circuit 140, selection signal output terminals TSQ1 to TSQ4, data signal output terminals TDQ1 to TDQp, and interface terminals THY and TSE. Each terminal is a pad provided on the substrate of the integrated circuit device, or a terminal provided on the package of the integrated circuit device. Note that although Fig. 2 shows only one interface terminal THY and one interface terminal TSE, in reality, the number of terminals provided corresponds to the number of input signals.

[0017] The interface circuit 140 performs communication between an external processing device and the circuit device 100. The interface circuit 140 includes a display interface 141 and a setting interface 142.

[0018] Various image data interfaces such as an RGB interface or an LVDS (Low Voltage Differential Signal) interface are adopted as the display interface 141. The display interface 141 receives display data and a display control signal input via an interface terminal THY. The display control signal is a clock signal, a synchronization signal, etc.

[0019] Various serial interfaces such as the SPI (Serial Peripheral Interface) system or the I2C (Inter Integrated Circuit) system are adopted as the setting interface 142. For example, when the SPI system is adopted, the setting interface 142 receives a chip select signal, a clock signal, and a serial data signal input via an interface terminal TSE.

[0020] The processing circuit 120 performs signal processing on image data, control of display timing, and operation setting processing for the circuit device 100. The processing circuit 120 includes a register 121 and a display control circuit 123. The processing circuit 120 is a logic circuit, such as a gate array configured by automatic placement and wiring, or a standard cell array configured by automatic wiring. Note that the processing circuit 120, part or all of the interface circuit 140, and part or all of the selection signal output circuit 130 may be configured as an integrated gate array or standard cell array.

[0021] The display control circuit 123 performs display timing control based on the display data and display control signals received by the display interface 141. Specifically, the display control circuit 123 controls the timing of demultiplex driving by outputting selection control signals CTS1 to CTS4, and outputs the display data PD1 to PDp to the data line driving circuit 110 at a timing synchronized therewith. In this embodiment, the data line driving circuit 110 drives the data lines driven in the first driving order of the demultiplex driving again after the nth driving order. The display control circuit 123 performs timing control of this rewrite operation. The rewrite operation will be described in detail later.

[0022] Operation setting data is written to the register 121 based on a signal received by the setting interface 142. The processing circuit 120 sets the operation of each part of the circuit device 100 based on the operation setting data stored in the register 121. For example, an enable signal ENB, which will be described later, is written to the register 121 via the setting interface 142. The display control circuit 123 changes the display timing based on the enable signal ENB stored in the register 121.

[0023] The data line driving circuit 110 drives the electro-optical panel 200 by supplying data signals to the pixels PX of the electro-optical panel 200. The data line driving circuit 110 includes D / A conversion circuits DA1 to DAp and amplifier circuits AM1 to AMp. The D / A conversion circuit DA1 is a circuit that performs D / A conversion on the display data PD1, and is, for example, a switch circuit that selects a reference voltage corresponding to the display data PD1 from among a plurality of reference voltages. Similarly, the D / A conversion circuits DA2 to DAp are circuits that perform D / A conversion on the display data PD2 to PDp. The amplifier circuit AM1 is a circuit that outputs a data signal VQ1 to a data signal output terminal TDQ1 by amplifying or buffering the output voltage of the D / A conversion circuit DA1. Similarly, the amplifier circuits AM2 to AMp are circuits that amplify or buffer the output voltage of the D / A conversion circuits DA2 to DAp. The amplifier circuits AM1 to AMp can include, for example, an operational amplifier, a resistor, a capacitor, and the like. The data signal output terminals TDQ1 to TDQp are connected to the data signal input terminals TDI1 to TDIp of the electro-optical panel 200.

[0024] The selection signal output circuit 130 outputs selection signals SEL1-SEL4 to selection signal output terminals TSQ1-TSQ4 based on selection control signals CTS1-CTS4. The selection signals SEL1-SEL4 control the connection between the data lines and the data signal supply lines. Taking the data signal supply line SL1 as an example, the selection signals SEL1-SEL4 control the connection between the data lines DL1-DL4 and the data signal supply line SL1. The selection signal output terminals TSQ1-TSQ4 are connected to selection signal input terminals TSI1-TSI4 of the electro-optical panel 200.

[0025] 2. Write errors due to leakage current A write error caused by a leak current in conventional demultiplex driving will be described with reference to Figures 3 to 5. Here, a case will be described in which the data lines DL1 to DL4 shown in Figure 1 are demultiplex-driven in that order without considering rotation, but a similar write error will occur when rotation is performed.

[0026] 3 shows voltage waveforms of the data signal supply line SL1 and the data lines DL1 to DL4 during one horizontal scanning period in conventional demultiplex driving, and a schematic diagram of a leakage current flowing through the switch of the switch circuit 210. The transistors shown in the lower part of FIG.

[0027] In the precharge period TPR, the selection signal output circuit 130 outputs high-level selection signals SEL1 to SEL4, and the data line drive circuit 110 outputs a precharge voltage to the data signal supply line SL1. Since all the switches of the switch circuit 210 are turned on, the precharge voltage is applied to all of the data lines DL1 to DL4.

[0028] The drive periods of the demultiplex drive are designated as GS1 to GS4. In the drive period GS1, the selection signal output circuit 130 outputs a high-level selection signal SEL1 and low-level selection signals SEL2 to SEL4, and the data line drive circuit 110 outputs a data signal corresponding to the pixel of the data line DL1 to the data signal supply line SL1. Since the switch connected to the data line DL1 is turned on, the data signal is written to the pixel of the data line DL1. The data lines DL2 to DL4 remain at the precharge voltage.

[0029] In this embodiment, the circuit device 100 performs polarity inversion driving. That is, the driving polarity is inverted every one or more frames or every one or more scan lines. The precharge voltage belongs to a negative grayscale voltage range lower than the common voltage. FIG. 3 shows a waveform of positive driving. That is, the data signal belongs to a positive grayscale voltage range higher than the common voltage. At this time, in the driving period GS1, the voltage of the data signal supply line SL1 is a positive data signal, and the voltage of the data lines DL2 to DL4 is a negative precharge voltage. Therefore, a leak current flows from the data signal supply line SL1 to the data lines DL2 to DL4 via the switch.

[0030] In the drive periods GS2, GS3, and GS4, the switches are turned on one by one, so the number of data lines holding the precharge voltage is reduced by one. Therefore, in the drive periods GS2, GS3, and GS4, the number of switches through which the leakage current flows is reduced from 2 to 1 to 0, and the leakage current is also reduced. In other words, the effect of the leakage current is maximum in the drive period GS1 and minimum in the drive period GS4.

[0031] FIG. 4 shows simulation waveforms of the voltages of the data lines DL1 to DL4.

[0032] In the electro-optical panel 200, there is an input resistor between the data signal input terminal TDI1 and the switch circuit 210. The leakage current flowing through the switch flows through the input resistor, causing a voltage drop in the data signal supply line. Therefore, the voltage written from the data signal supply line to each data line is lower than the target voltage of the data signal output by the data line driving circuit 110 by the amount of the voltage drop.

[0033] As shown in Fig. 4, the data signals written to the data lines DL1 to DL3 are at a lower voltage than the target voltage. In Fig. 4, the write error in the data line DL1 is designated as Verr. The write error is maximum in the data line DL1, and decreases in the order of the data lines DL2 and DL3. Since the leakage current in the data line DL4 is almost zero, the write error in the data line DL4 is almost zero.

[0034] FIG. 5 is a diagram explaining the relationship between the write error due to leakage current and the display. The numbers shown with the arrows indicate the drive order in demultiplex drive. That is, "1" to "4" correspond to the drive periods GS1 to GS4. "Brightness" indicates the brightness of the pixel to which the data signal is written. "Display" is a schematic representation of how the pixel appears. One rectangle represents one pixel, and pixels with low brightness are marked with darker hatching.

[0035] Here, it is assumed that data signals of the same target voltage are written to all pixels. In other words, if there is no writing error, all pixels will have the same luminance. However, due to the above-mentioned writing error, the luminance of pixels decreases in the order of driving orders 4, 3, 2, and 1. Since the data line DL5 driven in driving order 1 is arranged next to the data line DL4 driven in driving order 4, the luminance difference between the data lines DL4 and DL5 becomes large. In other words, the luminance difference becomes large at the boundary of the blocks driven in a demultiplexed manner. This luminance difference is visually recognized as display unevenness, resulting in a decrease in display quality.

[0036] A specific example will be given below to show the extent to which a write error occurs due to a leakage current.

[0037] When the input resistance of the electro-optic panel 200 is Rin and the leakage current per switch is Ileak, the write error in the data line DL1 is Verr=Rin×(n-1)×Ileak. Since n=4 here, Verr=Rin×3×Ileak, but the larger the demultiplexing number n, the larger the write error Verr becomes.

[0038] For example, the main cause of the leak current is light leakage, and Ileak=100nA is assumed. The input resistance of the electro-optical panel is assumed to be Rin=2kΩ. If the demultiplex number n=8, then Verr=2kΩ×(8-1)×100nA=1.4mV. If the gradation voltage range of one polarity is 5V and the number of gradations is 2 to the power of 12, the voltage step per gradation is ΔV=1.2mV. In other words, Verr>ΔV. For example, it is conceivable to increase the demultiplex number n in order to reduce the number of driving amplifiers for low power consumption or to increase the pixel count of the electro-optical panel. However, the more the demultiplex number n is increased, the larger the writing error Verr becomes, and the more easily the resulting luminance difference becomes visible. There is also a method of dispersing display unevenness by performing rotation in demultiplex driving, thereby reducing the visibility of the display unevenness. However, as the demultiplexing number n increases, the rotation period becomes longer and writing errors also become larger, increasing the possibility that display unevenness will be visible.

[0039] As described above, in the conventional demultiplex drive, the writing error of the data signal due to the leakage current deteriorates the display quality, and the writing error due to the leakage current becomes an obstacle when increasing the number of demultiplexes.

[0040] 3. Driving method of this embodiment 6 is a waveform diagram for explaining the first driving method in this embodiment. Here, an example is shown in which the demultiplexing number is n=4 and rotation is not performed. In addition, the block of the data signal supply line SL1 and the data lines DL1 to DL4 is explained as an example, but the other blocks operate in the same way.

[0041] As shown in Fig. 6, the period between one rising edge and the next rising edge of the horizontal synchronization signal HSYNC is defined as a horizontal scanning period TH. The horizontal scanning period TH is divided into a precharge period TPR and drive periods GS1 to GS5. The length of the precharge period TPR may be different from the length of one drive period.

[0042] In the precharge period TPR, the selection signal output circuit 130 outputs high-level selection signals SEL1 to SEL4, and the data line drive circuit 110 outputs a precharge voltage to the data signal supply line SL1. Since all the switches of the switch circuit 210 are turned on, the precharge voltage is applied to all of the data lines DL1 to DL4.

[0043] During the driving period GS1, the selection signal output circuit 130 outputs a high-level selection signal SEL1 and low-level selection signals SEL2 to SEL4, and the data line driving circuit 110 outputs data signals corresponding to the pixels of the data line DL1 to the data signal supply line SL1. Since the switch connected to the data line DL1 is turned on, the data signals are written to the pixels of the data line DL1. Similarly, during the driving periods GS2 to GS4, the selection signal output circuit 130 outputs high-level selection signals SEL2 to SEL4, and the data line driving circuit 110 outputs data signals corresponding to the pixels of the data lines DL2 to DL4 to the data signal supply line SL1. Since the switch connected to the data lines DL2 to DL4 is turned on, the data signals are written to the pixels of the data lines DL2 to DL4.

[0044] The driving period GS5 corresponds to the driving period GSn+1 when the demultiplex number is n. That is, in this embodiment, n+1 driving periods are provided for the demultiplex number n. In the driving period GS5, the selection signal output circuit 130 outputs a high-level selection signal SEL1 and low-level selection signals SEL2 to SEL4, and the data line driving circuit 110 outputs the same data signal as the data signal in the driving period GS1 to the data signal supply line SL1. As a result, the data signal is written to the pixel of the data line DL1 again.

[0045] 7 is a diagram for explaining the relationship between the reduction of writing errors and display in the first operation example. "1" to "5" correspond to the driving periods GS1 to GS5. Here, it is assumed that data signals of the same target voltage are written to all pixels.

[0046] As explained in FIG. 6, the data line DL1 is rewritten in the drive period GS5. At this time, since data signals have already been written to the data lines DL2 to DL4, the leakage current is almost zero, similar to the leakage current in the drive period GS4. Therefore, the luminance of the data lines DL1 and DL4 becomes approximately the same, and the luminance of the data lines DL2 and DL3 becomes slightly lower. Compared to FIG. 5, there is almost no difference in luminance at the boundary of the blocks driven in a demultiplexed manner, so that display unevenness is less noticeable and the display quality is improved.

[0047] 8 shows a first detailed configuration example of the display control circuit 123 that controls the above operations. The display control circuit 123 includes a line latch circuit 125, a selector 126, a precharge control circuit 127, and a multiplexing circuit 150. Here, the control related to the display data PD1 will be described as an example, but similar processing is performed on each of the display data PD1 to PDp.

[0048] The line latch circuit 125 receives display data from the display interface 141 and stores the display data for one scan line. Each of the pixel data DT1-DT4 is data for one pixel and indicates a gradation value to be written to the pixel on the data line DL1. In particular, the pixel data DT1 indicates a gradation value to be written to the pixel on the data line DL1. Similarly, the pixel data DT2-DT4 indicate a gradation value to be written to the pixels on the data lines DL2-DL4.

[0049] The multiplexing circuit 150 performs multiplexing processing of the pixel data DT1 to DT4 and controls the timing of the selection signals SEL1 to SEL4. The multiplexing circuit 150 includes a rotation counter 151, a decoder 152, and a selector 153.

[0050] The rotation counter 151 outputs a count value RCQ for determining the drive order of the data lines DL1 to DL4. The rotation counter 151 outputs one count value RCQ in each of the drive periods GS1 to GS5.

[0051] The decoder 152 determines the rotation drive order by decoding the count value RCQ. That is, the drive order is rotated by changing the correspondence between the count value RCQ and the drive order for each horizontal scanning period.

[0052] Specifically, the decoder 152 activates the selection control signal CTS1-CTS4 that corresponds to the count value RCQ, and deactivates the other selection control signals. The selection signal output circuit 130 outputs the selection signals SEL1-SEL4 by buffering the selection control signals CTS1-CTS4. For example, when the selection control signal CTS1 is active, the selection signal output circuit 130 outputs an active selection signal SEL1.

[0053] Furthermore, the decoder 152 activates the selector control signal DCQ1-DCQ4 that corresponds to the count value RCQ, and deactivates the other selector control signals. The selector 153 selects the pixel data that corresponds to the active selector control signal from the pixel data DT1-DT4. For example, when the selector control signal DCQ1 is active, the selector 153 selects the pixel data DT1. The selector 153 outputs the selected pixel data as the output data DTQ.

[0054] The precharge control circuit 127 controls switching between the precharge period TPR and the drive periods GS1 to GS5, and controls the precharge voltage. Specifically, the precharge control circuit 127 outputs a precharge selection signal SLPR that is active in the precharge period TPR and inactive in the drive periods GS1 to GS5. The precharge control circuit 127 also outputs precharge data DPR indicating the grayscale value of the precharge voltage. The selector 126 selects the precharge data DPR when the precharge selection signal SLPR is active, and selects the output data DTQ of the selector 153 when the precharge selection signal SLPR is inactive. The selector 126 outputs the selected data as display data PD1.

[0055] 9 shows an example of the operation of the multiplexing circuit 150. The upper diagram shows an example of the operation when rotation is not taken into consideration, and the lower diagram shows an example of the operation when rotation is taken into consideration.

[0056] As shown in the upper diagram, the rotation counter 151 outputs a 2-bit count value. Specifically, the rotation counter 151 outputs count values ​​00, 01, 10, 11, and 00 during the driving periods GS1, GS2, GS3, GS4, and GS5. When the count value is 00, 01, 10, and 11, the decoder 152 activates the selection signals SEL1, SEL2, SEL3, and SEL4. Since the count value is 00 during the driving period GS5, the selection signal SEL1 becomes active. That is, the selection signal SEL1 becomes active during both the driving periods GS1 and GS5, and a data signal is written to the pixel of the data line DL1. The number of bits of the count value may be set to a number of bits according to the demultiplexing number n. For example, when n=8, the number of bits of the count value is 3.

[0057] As shown in the lower diagram, the rotation counter 151 outputs count values ​​00, 01, 10, 11, and 00 during the drive periods GS1, GS2, GS3, GS4, and GS5. When the count value is 00, 01, 10, and 11, the decoder 152 activates the selection signals SEL3, SEL4, SEL1, and SEL2. Since the count value is 00 during the drive period GS5, the selection signal SEL3 becomes active. That is, the selection signal SEL3 becomes active during both drive periods GS1 and GS5, and a data signal is written to the pixel of the data line DL3. In the lower diagram, the correspondence between the count value and the selection signal is different from that in the upper diagram, and this correspondence is changed for each horizontal scanning period to control the rotation drive order.

[0058] In the above embodiment, the circuit device 100 drives the electro-optical panel 200. The electro-optical panel 200 includes a switch circuit 210 provided between the first to fourth data lines DL1 to DL4 and the data signal supply line SL1. The circuit device 100 includes a selection signal output circuit 130 and a data line driving circuit 110. The selection signal output circuit 130 outputs to the switch circuit 210 first to fourth selection signals SEL1 to SEL4 that control the connection between the first to fourth data lines DL1 to DL4 and the data signal supply line SL1 based on the first to fourth driving orders of the demultiplex driving. The data line driving circuit 110 outputs first to fourth data signals corresponding to the first to fourth data lines DL1 to DL4 to the data signal supply line SL1 in the first to fourth driving orders. It is assumed that i is an integer between 1 and n. In the first driving sequence, the selection signal output circuit 130 activates the ith selection signal SELi, and the data line driving circuit 110 outputs the ith data signal to the ith data line DLi. At this time, after the first to fourth driving sequences, a rewrite operation is performed in which the selection signal output circuit 130 activates the ith selection signal SELi, and the data line driving circuit 110 outputs the ith data signal to the ith data line DLi.

[0059] According to this embodiment, after normal demultiplex driving is performed in the first to fourth driving orders, the i-th data signal is rewritten to the i-th data line DLi driven in the first driving order. As described above, the writing error of the i-th data line DLi written in the first driving order is the largest, but by rewriting the i-th data signal to the i-th data line DLi, the writing error of the i-th data signal is reduced. This reduces display unevenness caused by the writing error. In addition, it is possible to reduce the number of driving amplifiers to reduce power consumption, or to increase the number of demultiplexes for the purpose of increasing the pixel count of the electro-optical panel, etc.

[0060] The first to fourth driving orders refer to the order in which the data lines DL1 to DL4 are driven in the driving periods GS1 to GS4. When no rotation is performed, the driving order is DL1, DL2, DL3, DL4. When rotation is performed, any one of the data lines DL1 to DL4 is driven in each driving period, and each data line is driven once. The i-th data line and the i-th selection signal are the first data line DL1 and the first selection signal SEL1 in the upper part of FIG. 6 and FIG. 9, and are the third data line DL3 and the third selection signal SEL3 in the lower part of FIG. 9. "After the first to fourth driving orders" is the driving period GS5 in FIG. 6 and FIG. 9, that is, the fifth driving order. However, when rewriting is performed on two data lines as described later, "after the first to fourth driving orders" may be the driving period GS6, that is, the sixth driving order. The above first to fourth may be rephrased as first to nth. n is an integer of 3 or more.

[0061] Furthermore, in this embodiment, in the precharge period TPR before the first to fourth driving sequences, the selection signal output circuit 130 activates the first to fourth selection signals SEL1 to SEL4, and the data line driving circuit 110 outputs a precharge voltage to the first to fourth data lines DL1 to DL4.

[0062] According to this embodiment, in the first to fourth driving orders, data signals are written to the first to fourth data lines one by one, but the data lines to which no data signal is written are held at a precharge voltage. Therefore, a leak current occurs in the switch due to a voltage difference between the data signal of the data signal supply line SL1 and the precharge voltage held in the data line. As described above, the write error of the data signal due to the leak current is maximum in the first driving order, but the write error is reduced by performing a rewrite operation.

[0063] In this embodiment, the precharge voltage is a negative voltage in the polarity inversion driving. The selection signal output circuit 130 and the data line driving circuit 110 perform a rewrite operation during a positive polarity driving period in the polarity inversion driving.

[0064] According to this embodiment, a leak current occurs in the switch due to a voltage difference between the positive data signal of the data signal supply line SL1 and the negative precharge voltage held in the data line. Compared to when the data signal is negative, the voltage difference across the switch is larger, so the leak current is larger. In this embodiment, a rewrite operation is performed, so that write errors are reduced even during the positive drive period when the leak current is large.

[0065] The rewrite operation may be performed during the negative drive period, or, as described later, the rewrite operation may be performed during the positive drive period and not during the negative drive period. In this case, the rewrite operation during the negative drive period may be disabled by the enable control described later.

[0066] In this embodiment, the circuit device 100 includes a multiplexing circuit 150. The multiplexing circuit 150 multiplexes the first to fourth pixel data DT1 to DT4 corresponding to the first to fourth data signals in the first to fourth driving orders, and further multiplexes the i-th pixel data DTi after the first to fourth driving orders. The data line driving circuit 110 includes a D / A conversion circuit DA1 that performs D / A conversion on the output data of the multiplexing circuit 150, and an amplifier circuit AM1 that buffers or amplifies the output signal of the D / A conversion circuit DA1 and outputs the result to a data signal supply line SL1.

[0067] According to this embodiment, the multiplexing circuit 150 further multiplexes the i-th pixel data DTi after the first to fourth driving sequences, thereby realizing a rewrite operation in which the data line driving circuit 110 outputs the i-th data signal to the i-th data line DLi.

[0068] Furthermore, in this embodiment, when the input resistance value of the data signal supply line SL1 is Rin, the leakage current per data line in the switch circuit 210 is Ileak, and the voltage step per gradation of the first to nth data signals is ΔV, Rin×(n-1)×Ileak>ΔV.

[0069] As described above, the leakage current in the first driving sequence, i.e., the driving period GS1, is (n-1)×Ileak, and the voltage drop caused by the leakage current flowing through the input resistor is Rin×(n-1)×Ileak. This voltage drop becomes a writing error due to the leakage current, but since it is larger than the voltage step ΔV per gradation, it is highly likely that it will be visually recognized as display unevenness. In this embodiment, the writing error is reduced by the rewrite operation, so that the possibility of visually recognizing display unevenness is reduced.

[0070] 10 is a waveform diagram illustrating the second driving method in this embodiment. Here, an example is shown in which the demultiplexing number is an integer n equal to or greater than 3 and rotation is not performed. In addition, the block including the data signal supply line SL1 and the data lines DL1 to DL4 is used as an example for explanation, but the other blocks operate in the same manner.

[0071] In this embodiment, n+2 driving periods are provided for the demultiplex number n. That is, the horizontal scanning period TH is divided into a precharge period TPR and driving periods GS1 to GSn+2. The operation in the precharge period TPR is the same as that in Fig. 6. Moreover, the operation in the driving periods GS1 to GSn is also the same as that in the driving periods GS1 to GS4 in Fig. 6, except that the demultiplex number is n.

[0072] In the driving period GSn+1, the selection signal output circuit 130 outputs a high-level selection signal SEL2 and low-level selection signals SEL1, SEL3 to SELn, and the data line driving circuit 110 outputs the same data signal as that in the driving period GS2 to the data signal supply line SL1. As a result, the data signal is written to the pixels of the data line DL2 again.

[0073] In the driving period GSn+2, the selection signal output circuit 130 outputs a high-level selection signal SEL1 and low-level selection signals SEL2 to SELn, and the data line driving circuit 110 outputs the same data signal as that in the driving period GS1 to the data signal supply line SL1. As a result, the data signal is written to the pixels of the data line DL1 again.

[0074] In this embodiment, the data lines DL1 and DL2 are selected in this order during the drive periods GS1 and GS2, and the data lines DL2 and DL1 are selected in this order during the drive periods GSn+1 and GSn+2. That is, the drive order when the data lines DL1 and DL2 are driven for the first time is reversed to the drive order during rewriting.

[0075] 11 and 12 are diagrams for explaining the relationship between the reduction of writing errors and display in the second operation example. Here, the demultiplexing number n=8, and data signals of the same target voltage are written to all pixels. "1" to "10" correspond to the driving periods GS1 to GS10.

[0076] FIG. 11 shows a case where the driving order in rewriting is not reversed, that is, the data lines DL1 and DL2 are driven in the order of driving periods GS9 and GS10. As a writing error due to leakage current, the influence of leakage current during writing has been described above, but the influence of leakage current also exists after the switch is turned off. That is, when the switch is turned off, the data signal is held in the data line, but the held data signal is slightly lowered due to the leakage current of the switch, which becomes a writing error. This error becomes smaller as the elapsed time after the switch is turned off becomes shorter. That is, the data signal written to the data line DL1 in the driving period GS9 is slightly lower than the data signal written to the data line DL2 in the subsequent driving period GS10. In this case, the luminance difference between the pixel of the data line DT2 and the pixel of the data line DT3 is ΔVA.

[0077] FIG. 12 shows a case where the driving order in rewriting is reversed, that is, the data lines DL2 and DL1 are driven in the order of driving periods GS9 and GS10. As described above, the shorter the time that has elapsed since the switch was turned off, the smaller the write error, so the data signal written to the data line DL2 in the driving period GS9 is slightly lower than the data signal written to the data line DL1 in the subsequent driving period GS10. Therefore, the luminance difference ΔVB between the pixel of the data line DT2 and the pixel of the data line DT3 in FIG. 12 is smaller than the luminance difference ΔVA in FIG. 11. Since the smaller the luminance difference between adjacent pixels is, the less likely the luminance difference is to be visible, it can be seen that reversing the driving order in rewriting reduces the possibility of the luminance difference being visible.

[0078] In the above embodiment, when j is an integer between 1 and n and j≠i, in the second driving order, the selection signal output circuit 130 activates the j-th selection signal SELj and the data line driving circuit 110 writes the j-th data signal to the j-th data line DLj. After the first to n-th driving orders, the selection signal output circuit 130 activates the j-th selection signal SELj and the data line driving circuit 110 performs a re-write operation to output the j-th data signal to the j-th data line DLj.

[0079] According to this embodiment, after normal demultiplex driving is performed in the first to nth driving orders, the jth data signal is rewritten to the jth data line DLj driven in the second driving order. The jth data line DLj written in the second driving order has the second largest write error, but by rewriting the jth data signal to the jth data line DLj, the write error of the jth data signal is reduced. This further reduces display unevenness caused by the write error.

[0080] In this embodiment, the rewrite operation includes a rewrite operation in the (n+1)th drive order after the 1st to nth drive orders, and a rewrite operation in the (n+2)th drive order. In the (n+1)th drive order, the selection signal output circuit 130 activates the jth selection signal SELj, and the data line drive circuit 110 rewrites the jth data signal to the jth data line DLj. In the (n+2)th drive order, the selection signal output circuit 130 activates the i-th selection signal SELi, and the data line drive circuit 110 rewrites the i-th data signal to the i-th data line DLi.

[0081] According to this embodiment, rewriting is performed on two data lines driven in the first and second drive orders. At this time, in the n+1th and n+2nd drive orders, the data lines are rewritten in the reverse order of the first and second drive orders. That is, the i-th data line DLi driven in the first drive order is rewritten last. As a result, as described in FIG. 11 and FIG. 12, the luminance difference caused by the writing error due to the leakage current is smaller than when the rewriting is not performed in the reverse order, and the possibility of visually recognizing display unevenness is reduced.

[0082] 10 and 12, the jth data line, the jth selection signal, the ith data line, and the ith selection signal are the second data line DL2, the second selection signal SEL2, the first data line DL1, and the first selection signal SEL1. The n+1th and n+2th driving orders correspond to the driving periods GSn+1 and GSn+2 in Fig. 10, and correspond to the driving periods GS9 and GS10 when n=8 shown in Fig. 12.

[0083] Fig. 13 shows a second detailed configuration example of the display control circuit 123. In the second detailed configuration example, an enable signal ENB is input from the register 121 to the rotation counter 151. Note that only parts different from the first detailed configuration example of Fig. 8 will be explained, and explanations of parts similar to the first detailed configuration example will be omitted as appropriate.

[0084] The enable signal ENB is a signal for enabling or disabling the rewrite operation. That is, the display control circuit 123 performs the rewrite operation when the enable signal ENB is active, and does not perform the rewrite operation when the enable signal ENB is inactive.

[0085] Specifically, when the enable signal ENB is active, the rotation counter 151 outputs a count value RCQ corresponding to the drive periods GS1 to GSn+1 or the drive periods GS1 to GSn+2 in one horizontal scanning period. For example, when n=4 and the drive periods GS1 to GS5 are set, the rotation counter 151 outputs 00, 01, 10, 11, and 00 corresponding to the drive periods GS1 to GS5, as described in FIG.

[0086] When the enable signal ENB is inactive, the rotation counter 151 outputs a count value RCQ corresponding to the drive periods GS1 to GSn in one horizontal scanning period. For example, when n=4, the rotation counter 151 outputs 00, 01, 10, and 11 corresponding to the drive periods GS1 to GS4.

[0087] 14 is a waveform diagram for explaining the operation of the second detailed configuration example, where the demultiplexing number n=4 and the active level of the enable signal ENB is set to a high level.

[0088] When ENB=L, that is, when the enable signal ENB is inactive, the horizontal scanning period TH includes the precharge period TPR and the drive periods GS1 to GS4, but does not include the drive period GS5. In the drive periods GS1 to GS4, the selection signal output circuit 130 activates the selection signals SEL1 to SEL4, and the data line drive circuit 110 outputs data signals corresponding to the data lines DL1 to DL4.

[0089] When ENB=H, that is, when the enable signal ENB is active, the horizontal scanning period TH includes a precharge period TPR and driving periods GS1 to GS5. In the driving periods GS1 to GS4, the selection signal output circuit 130 activates the selection signals SEL1 to SEL4, and the data line driving circuit 110 outputs data signals corresponding to the data lines DL1 to DL4. In the driving period GS5, the selection signal output circuit 130 activates the selection signal SEL1, and the data line driving circuit 110 outputs the same data signal as the data signal in the driving period GS1.

[0090] When ENB=H, the horizontal scanning period TH may include a precharge period TPR and driving periods GS1 to GS6. In the driving periods GS5 and GS6, the selection signal output circuit 130 may activate the selection signals SEL2 and SEL1, and the data line driving circuit 110 may output the same data signals as those in the driving periods GS2 and GS1.

[0091] In the above embodiment, the circuit device 100 includes a register 121 that stores an enable signal ENB for a rewrite operation. When the enable signal ENB stored in the register 121 indicates enable, the selection signal output circuit 130 and the data line driving circuit 110 perform a rewrite operation.

[0092] According to this embodiment, the rewrite operation can be switched between enabled and disabled. By enabling the rewrite operation, write errors due to leakage currents are reduced. Furthermore, by disabling the rewrite operation, the number of drive periods in demultiplex driving is reduced compared to when the rewrite operation is enabled. This lengthens the length of one drive period, thereby reducing insufficient writing of data signals. For example, as will be described later in FIG. 15, the rewrite operation may be enabled in intermediate gradations where display unevenness is easily visible, and disabled in low and high gradations.

[0093] In this embodiment, the rewrite operation may be disabled during the negative polarity drive period in the polarity inversion drive. For example, the display control circuit 123 may generate an enable signal ENB based on a polarity signal that controls the drive polarity, and write the enable signal ENB to the register 121. The display control circuit 123 may activate the enable signal ENB when the polarity signal indicates positive polarity drive, and may deactivate the enable signal ENB when the polarity signal indicates negative polarity drive.

[0094] As described above, the leakage current is larger in the positive drive period than in the negative drive period, and therefore the write error is also larger. According to this embodiment, the rewrite operation is enabled in the positive drive period in which the write error due to the leakage current is large, thereby reducing the write error due to the leakage current. In addition, the rewrite operation is disabled in the negative drive period in which the write error due to the leakage current is small, thereby lengthening the length of one drive period, thereby reducing the insufficient writing of the data signal.

[0095] 4. Electro-optical devices and systems 15 shows a configuration example of an electro-optical device 350 and a configuration example of a system 500 including the electro-optical device 350. The system 500 includes a processing device 300, a camera 310, and the electro-optical device 350. The electro-optical device 350 includes a circuit device 100 and an electro-optical panel 200. Note that when enable control using the camera 310 is not performed, the camera 310 may be omitted.

[0096] The system 500 is, for example, a projector, a mobile information terminal, or an information processing device, but is not limited to these, and may be any device that displays an image. The processing device 300 is a CPU, a microcomputer, or the like, and transmits display data to the circuit device 100. The circuit device 100 drives the electro-optical panel 200 based on the received display data, thereby causing the electro-optical panel 200 to display an image. The camera 310 captures the image displayed on the electro-optical panel 200. Note that, when the system 500 is a projector, the image displayed on the electro-optical panel 200 is projected onto a screen by a light source and a projection optical system, and the camera 310 captures the image projected onto the screen.

[0097] The camera 310 transmits image data to the processing device 300. The processing device 300 analyzes the brightness of the image displayed on the electro-optical panel 200 from the received image data. When the brightness of the image is an intermediate gradation, the processing device 300 writes an active enable signal ENB to the register 121 of the circuit device 100, and when the brightness of the image is a low gradation or a high gradation, the processing device 300 writes an inactive enable signal ENB to the register 121. As a result, when the brightness of the image is an intermediate gradation, the display unevenness is reduced by the rewrite operation, and when the brightness of the image is a low gradation or a high gradation, the rewrite operation is not performed, and the writing time of the pixel is extended. Display unevenness is more easily visible in an intermediate gradation than in a low gradation or a high gradation. Therefore, the display quality is improved by performing the rewrite operation in an intermediate gradation.

[0098] Note that the enable control is not limited to the above. For example, the processing device 300 may write an enable signal ENB to the register 121 of the circuit device 100 in advance, and the circuit device 100 may enable or disable the rewrite operation based on the preset enable signal ENB, regardless of the display gradation.

[0099] The circuit device of the present embodiment described above drives an electro-optical panel including a switch circuit provided between the first to n-th data lines and a data signal supply line, where n is an integer of 3 or more. The circuit device includes a selection signal output circuit that outputs to the switch circuit first to n-th selection signals that control connections between the first to n-th data lines and a data signal supply line based on the first to n-th driving orders of the demultiplex drive, and a data line drive circuit that outputs the first to n-th data signals corresponding to the first to n-th data lines to the data signal supply line in the first to n-th driving orders. In the first driving order of the first to n-th driving orders, the selection signal output circuit activates the ith selection signal of the first to n-th selection signals, and the data line drive circuit outputs the ith data signal of the first to n-th data signals to the ith data line of the first to n-th data lines. i is an integer of 1 to n. At this time, after the first to nth driving sequences, the selection signal output circuit activates the ith selection signal and the data line driving circuit performs a rewrite operation to output the ith data signal to the ith data line.

[0100] According to this embodiment, after normal demultiplex driving is performed in the first to nth driving orders, the i-th data signal is rewritten to the i-th data line driven in the first driving order. The writing error of the i-th data line written in the first driving order is the largest, but by rewriting the i-th data signal to the i-th data line, the writing error of the i-th data signal is reduced. This reduces display unevenness caused by the writing error. In addition, it is possible to reduce the number of driving amplifiers to reduce power consumption, or to increase the number of demultiplexes for the purpose of increasing the pixel count of the electro-optical panel, etc.

[0101] Furthermore, in this embodiment, in the second driving order of the 1st to nth driving orders, the selection signal output circuit may activate the jth selection signal of the 1st to nth selection signals, and the data line driving circuit may write the jth data signal of the 1st to nth data signals to the jth data line of the 1st to nth data lines, where j is an integer between 1 and n and j≠i. In this case, after the 1st to nth driving orders, a rewrite operation may be performed in which the selection signal output circuit activates the jth selection signal, and the data line driving circuit outputs the jth data signal to the jth data line.

[0102] According to this embodiment, after normal demultiplex driving is performed in the first to nth driving orders, the jth data signal is rewritten to the jth data line driven in the second driving order. The jth data line written in the second driving order has the second largest write error, but by rewriting the jth data signal to the jth data line, the write error of the jth data signal is reduced. This further reduces display unevenness caused by the write error.

[0103] In this embodiment, the rewrite operation may include a rewrite operation in the (n+1)th drive order after the 1st to nth drive orders, and a rewrite operation in the (n+2)th drive order. In the (n+1)th drive order, the selection signal output circuit may activate the jth selection signal and the data line drive circuit may rewrite the jth data signal to the jth data line. In the (n+2)th drive order, the selection signal output circuit may activate the ith selection signal and the data line drive circuit may rewrite the ith data signal to the ith data line.

[0104] According to this embodiment, rewriting is performed on two data lines driven in the first and second drive orders. At this time, in the n+1th and n+2nd drive orders, the data lines are rewritten in the reverse order of the first and second drive orders. That is, the i-th data line driven in the first drive order is rewritten last. As a result, the luminance difference caused by the writing error due to the leakage current is smaller than when the rewriting is not performed in the reverse order, and the possibility of visually recognizing display unevenness is reduced.

[0105] In addition, in this embodiment, in a precharge period before the first to nth drive sequences, the selection signal output circuit may make the first to nth selection signals active, and the data line drive circuit may output a precharge voltage to the first to nth data lines.

[0106] According to this embodiment, data signals are written to the first to nth data lines one by one in the first to nth driving orders, but the data lines to which no data signals are written are held at a precharge voltage. Therefore, a leak current occurs in the switch due to a voltage difference between the data signal on the data signal supply line and the precharge voltage held on the data line. The write error of the data signal due to the leak current is maximum in the first driving order, but the write error is reduced by performing a rewrite operation.

[0107] In this embodiment, the precharge voltage may be a voltage of negative polarity in the polarity inversion driving. The selection signal output circuit and the data line driving circuit may perform a rewrite operation during a positive polarity driving period in the polarity inversion driving.

[0108] According to this embodiment, a leakage current occurs in the switch due to a voltage difference between the positive data signal of the data signal supply line and the negative precharge voltage held in the data line. Compared to when the data signal is negative, the voltage difference across the switch is larger, so the leakage current is larger. In this embodiment, a rewrite operation is performed, so that writing errors are reduced even during a positive drive period when the leakage current is large.

[0109] In this embodiment, the rewrite operation may be set to be disabled during the negative polarity drive period in the polarity inversion drive.

[0110] Since the leakage current is larger in the positive drive period than in the negative drive period, the write error is also larger. According to this embodiment, the rewrite operation is enabled in the positive drive period where the write error due to the leakage current is large, thereby reducing the write error due to the leakage current. In addition, the rewrite operation is disabled in the negative drive period where the write error due to the leakage current is small, thereby lengthening the length of one drive period, thereby reducing the insufficient writing of the data signal.

[0111] In the present embodiment, the circuit device may further include a register for storing an enable signal for the rewrite operation. When the enable signal stored in the register indicates enable, the selection signal output circuit and the data line driving circuit may perform the rewrite operation.

[0112] According to this embodiment, the rewrite operation can be switched between enabled and disabled. By enabling the rewrite operation, write errors due to leakage currents are reduced. Furthermore, by disabling the rewrite operation, the number of drive periods in the demultiplex drive is reduced compared to when the rewrite operation is enabled. This lengthens the length of one drive period, thereby reducing insufficient writing of data signals.

[0113] In the present embodiment, the circuit device may include a multiplexing circuit. The multiplexing circuit may multiplex the first to n-th pixel data corresponding to the first to n-th data signals in the first to n-th driving orders, and may further multiplex the i-th pixel data of the first to n-th pixel data after the first to n-th driving orders. The data line driving circuit may include a D / A conversion circuit that performs D / A conversion on the output data of the multiplexing circuit, and an amplifier circuit that buffers or amplifies the output signal of the D / A conversion circuit and outputs the result to a data signal supply line.

[0114] According to this embodiment, the multiplexing circuit further multiplexes the i-th pixel data after the first to n-th driving sequences, thereby realizing a rewrite operation in which the data line driving circuit outputs the i-th data signal to the i-th data line.

[0115] An electro-optical device according to the present embodiment includes any one of the circuit devices described above and an electro-optical panel.

[0116] In this embodiment, the input resistance value of the data signal supply line may be Rin, the leakage current per data line in the switch circuit may be Ileak, and the voltage step per gradation of the first to nth data signals may be ΔV. In this case, Rin×(n-1)×Ileak>ΔV may be satisfied.

[0117] The leakage current in the first driving order is (n-1)×Ileak, and the voltage drop caused by the leakage current flowing through the input resistor is Rin×(n-1)×Ileak. This voltage drop becomes a writing error due to the leakage current, but since it is larger than the voltage step ΔV per gradation, it is highly likely to be recognized as display unevenness. In this embodiment, the writing error is reduced by the rewrite operation, so the possibility of the display unevenness being recognized is reduced.

[0118] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the circuit device, electro-optical panel, electro-optical device, and system are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0119] 100...circuit device, 110...data line driving circuit, 120...processing circuit, 121...register, 123...display control circuit, 125...line latch circuit, 126...selector, 127...precharge control circuit, 130...selection signal output circuit, 140...interface circuit, 141...display interface, 142...setting interface, 150...multiplexing circuit, 151...rotation counter, 152...decoder, 153...selector, 200...electro-optical panel, 210...switch circuit, 30 0...processing device, 310...camera, 350...electro-optical device, 500...system, AM1 to AMp...amplifier circuit, DA1 to DAp...D / A conversion circuit, DL1 to DLm...data line, DT1 to DT4...pixel data, ENB...enable signal, GL1 to GLk...scanning signal line, GS1 to GS10, GSn, GSn+1, GSn+2...drive period, HSYNC...horizontal synchronization signal, PX...pixel, SEL1 to SEL4...selection signal, SL1 to SLp...data signal supply line, TH...horizontal scanning period, TPR...precharge period

Claims

1. A circuit device for driving an electro-optical panel, the circuit device including a switch circuit provided between first to n-th data lines (n is an integer of 3 or more) and a data signal supply line, a selection signal output circuit that outputs first to n-th selection signals to the switch circuit, the first to n-th selection signals controlling connections between the first to n-th data lines and the data signal supply lines based on first to n-th drive orders of demultiplex driving; a data line driving circuit that outputs first to n-th data signals corresponding to the first to n-th data lines to the data signal supply lines in the first to n-th driving orders; Including, In a first driving order of the first to nth driving orders, when the selection signal output circuit activates an ith selection signal (i is an integer between 1 and n) of the first to nth selection signals and the data line driving circuit outputs the ith data signal of the first to nth data signals to the ith data line of the first to nth data lines, after the first to nth driving orders, a rewrite operation is performed in which the selection signal output circuit activates the ith selection signal and the data line driving circuit outputs the ith data signal to the ith data line; In a precharge period before the first to nth driving sequences, the selection signal output circuit activates the first to nth selection signals, and the data line driving circuit outputs a precharge voltage, which is a negative polarity voltage in polarity inversion driving, to the first to nth data lines; During a positive polarity driving period in the polarity inversion driving, the selection signal output circuit and the data line driving circuit perform the rewrite operation, The circuit device according to claim 1, wherein the rewrite operation is disabled during a negative polarity drive period in the polarity reversal drive.

2. A circuit device for driving an electro-optical panel, the circuit device including a switch circuit provided between first to n-th data lines (n is an integer of 3 or more) and a data signal supply line, a selection signal output circuit that outputs first to n-th selection signals to the switch circuit, the first to n-th selection signals controlling connections between the first to n-th data lines and the data signal supply lines based on first to n-th drive orders of demultiplex driving; a data line driving circuit that outputs first to n-th data signals corresponding to the first to n-th data lines to the data signal supply lines in the first to n-th driving orders; The register and Including, In a first driving order of the first to nth driving orders, when the selection signal output circuit activates an ith selection signal (i is an integer between 1 and n) of the first to nth selection signals and the data line driving circuit outputs the ith data signal of the first to nth data signals to the ith data line of the first to nth data lines, after the first to nth driving orders, a rewrite operation is performed in which the selection signal output circuit activates the ith selection signal and the data line driving circuit outputs the ith data signal to the ith data line; the register stores an enable signal for the rewrite operation; When the enable signal stored in the register indicates enable, the selection signal output circuit and the data line driving circuit perform the rewrite operation.

3. 3. The circuit device according to claim 1, In the second driving order of the first to n-th driving orders, when the selection signal output circuit activates a j-th selection signal (j is an integer between 1 and n, and j≠i) of the first to n-th selection signals and the data line driving circuit writes the j-th data signal of the first to n-th data signals to the j-th data line of the first to n-th data lines, A circuit device characterized in that, after the first to nth driving sequences, the selection signal output circuit activates the jth selection signal and the data line driving circuit outputs the jth data signal to the jth data line, thereby performing the rewrite operation.

4. 4. The circuit device according to claim 3, The rewrite operation includes a rewrite operation in an (n+1)th drive order after the first to nth drive orders and a rewrite operation in an (n+2)th drive order; In the n+1 driving sequence, the selection signal output circuit activates the j selection signal and the data line driving circuit rewrites the j data signal to the j data line; In the n+2 driving sequence, the selection signal output circuit activates the i-th selection signal and the data line driving circuit rewrites the i-th data signal to the i-th data line.

5. 5. The circuit device according to claim 1, a multiplexing circuit that multiplexes first to n-th pixel data corresponding to the first to n-th data signals in the first to n-th driving sequences, and further multiplexes the i-th pixel data of the first to n-th pixel data after the first to n-th driving sequences; The data line driving circuit includes: a D / A conversion circuit for D / A converting output data of the multiplexing circuit; an amplifier circuit that buffers or amplifies an output signal of the D / A conversion circuit and outputs the resultant signal to the data signal supply line; A circuit device comprising:

6. A circuit device according to any one of claims 1 to 5; The electro-optical panel; 1. An electro-optical device comprising:

7. 7. The electro-optical device according to claim 6, When the input resistance value of the data signal supply line is Rin, the leakage current per data line in the switch circuit is Ileak, and the voltage step per gradation of the first to n-th data signals is ΔV, Rin×(n-1)×Ileak>ΔV 13. An electro-optical device comprising:

Images